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1 /*****************************************************************************
2 * Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
3 *
4 * Unless you and Broadcom execute a separate written software license
5 * agreement governing use of this software, this software is licensed to you
6 * under the terms of the GNU General Public License version 2, available at
7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8 *
9 * Notwithstanding the above, under no circumstances may you combine this
10 * software in any way with any other Broadcom software provided under a
11 * license other than the GPL, without Broadcom's express prior written
12 * consent.
13 *****************************************************************************/
14
15 #ifndef CHIPC_INLINE_H
16 #define CHIPC_INLINE_H
17
18 /* ---- Include Files ----------------------------------------------------- */
19
20 #include <linux/errno.h>
21 #include <mach/csp/reg.h>
22 #include <mach/csp/chipcHw_reg.h>
23 #include <mach/csp/chipcHw_def.h>
24
25 /* ---- Private Constants and Types --------------------------------------- */
26 typedef enum {
27         chipcHw_OPTYPE_BYPASS,  /* Bypass operation */
28         chipcHw_OPTYPE_OUTPUT   /* Output operation */
29 } chipcHw_OPTYPE_e;
30
31 /* ---- Public Constants and Types ---------------------------------------- */
32 /* ---- Public Variable Externs ------------------------------------------- */
33 /* ---- Public Function Prototypes ---------------------------------------- */
34 /* ---- Private Function Prototypes --------------------------------------- */
35 static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
36                                     chipcHw_OPTYPE_e type, int mode);
37
38 /****************************************************************************/
39 /**
40 *  @brief   Get Numeric Chip ID
41 *
42 *  This function returns Chip ID that includes the revison number
43 *
44 *  @return  Complete numeric Chip ID
45 *
46 */
47 /****************************************************************************/
48 static inline uint32_t chipcHw_getChipId(void)
49 {
50         return readl(&pChipcHw->ChipId);
51 }
52
53 /****************************************************************************/
54 /**
55 *  @brief   Enable Spread Spectrum
56 *
57 *  @note chipcHw_Init() must be called earlier
58 */
59 /****************************************************************************/
60 static inline void chipcHw_enableSpreadSpectrum(void)
61 {
62         if ((readl(&pChipcHw->
63              PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
64             chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
65                 writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
66                     (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
67                      ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
68                      &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
69                 writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
70                     ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
71                     &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
72         }
73 }
74
75 /****************************************************************************/
76 /**
77 *  @brief   Disable Spread Spectrum
78 *
79 */
80 /****************************************************************************/
81 static inline void chipcHw_disableSpreadSpectrum(void)
82 {
83         ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
84 }
85
86 /****************************************************************************/
87 /**
88 *  @brief   Get Chip Product ID
89 *
90 *  This function returns Chip Product ID
91 *
92 *  @return  Chip Product ID
93 */
94 /****************************************************************************/
95 static inline uint32_t chipcHw_getChipProductId(void)
96 {
97         return (readl(&pChipcHw->
98                  ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
99                 chipcHw_REG_CHIPID_BASE_SHIFT;
100 }
101
102 /****************************************************************************/
103 /**
104 *  @brief   Get revision number
105 *
106 *  This function returns revision number of the chip
107 *
108 *  @return  Revision number
109 */
110 /****************************************************************************/
111 static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
112 {
113         return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
114 }
115
116 /****************************************************************************/
117 /**
118 *  @brief   Enables bus interface clock
119 *
120 *  Enables  bus interface clock of various device
121 *
122 *  @return  void
123 *
124 *  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
125 */
126 /****************************************************************************/
127 static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
128 {
129         reg32_modify_or(&pChipcHw->BusIntfClock, mask);
130 }
131
132 /****************************************************************************/
133 /**
134 *  @brief   Disables bus interface clock
135 *
136 *  Disables  bus interface clock of various device
137 *
138 *  @return  void
139 *
140 *  @note    use chipcHw_REG_BUS_CLOCK_XXXX
141 */
142 /****************************************************************************/
143 static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
144 {
145         reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
146 }
147
148 /****************************************************************************/
149 /**
150 *  @brief   Get status (enabled/disabled) of bus interface clock
151 *
152 *  This function returns the status of devices' bus interface clock
153 *
154 *  @return  Bus interface clock
155 *
156 */
157 /****************************************************************************/
158 static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
159 {
160         return readl(&pChipcHw->BusIntfClock);
161 }
162
163 /****************************************************************************/
164 /**
165 *  @brief   Enables various audio channels
166 *
167 *  Enables audio channel
168 *
169 *  @return  void
170 *
171 *  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
172 */
173 /****************************************************************************/
174 static inline void chipcHw_audioChannelEnable(uint32_t mask)
175 {
176         reg32_modify_or(&pChipcHw->AudioEnable, mask);
177 }
178
179 /****************************************************************************/
180 /**
181 *  @brief   Disables various audio channels
182 *
183 *  Disables audio channel
184 *
185 *  @return  void
186 *
187 *  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
188 */
189 /****************************************************************************/
190 static inline void chipcHw_audioChannelDisable(uint32_t mask)
191 {
192         reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
193 }
194
195 /****************************************************************************/
196 /**
197 *  @brief    Soft resets devices
198 *
199 *  Soft resets various devices
200 *
201 *  @return   void
202 *
203 *  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
204 */
205 /****************************************************************************/
206 static inline void chipcHw_softReset(uint64_t mask)
207 {
208         chipcHw_softResetEnable(mask);
209         chipcHw_softResetDisable(mask);
210 }
211
212 static inline void chipcHw_softResetDisable(uint64_t mask)
213 {
214         uint32_t ctrl1 = (uint32_t) mask;
215         uint32_t ctrl2 = (uint32_t) (mask >> 32);
216
217         /* Deassert module soft reset */
218         REG_LOCAL_IRQ_SAVE;
219         writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
220         writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
221                 (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
222         REG_LOCAL_IRQ_RESTORE;
223 }
224
225 static inline void chipcHw_softResetEnable(uint64_t mask)
226 {
227         uint32_t ctrl1 = (uint32_t) mask;
228         uint32_t ctrl2 = (uint32_t) (mask >> 32);
229         uint32_t unhold = 0;
230
231         REG_LOCAL_IRQ_SAVE;
232         writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
233         /* Mask out unhold request bits */
234         writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
235                 (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
236
237         /* Process unhold requests */
238         if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
239                 unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
240         }
241
242         if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
243                 unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
244         }
245
246         if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
247                 unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
248         }
249
250         if (unhold) {
251                 /* Make sure unhold request is effective */
252                 writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
253         }
254         REG_LOCAL_IRQ_RESTORE;
255 }
256
257 /****************************************************************************/
258 /**
259 *  @brief    Configures misc CHIP functionality
260 *
261 *  Configures CHIP functionality
262 *
263 *  @return   void
264 *
265 *  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
266 */
267 /****************************************************************************/
268 static inline void chipcHw_miscControl(uint32_t mask)
269 {
270         reg32_write(&pChipcHw->MiscCtrl, mask);
271 }
272
273 static inline void chipcHw_miscControlDisable(uint32_t mask)
274 {
275         reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
276 }
277
278 static inline void chipcHw_miscControlEnable(uint32_t mask)
279 {
280         reg32_modify_or(&pChipcHw->MiscCtrl, mask);
281 }
282
283 /****************************************************************************/
284 /**
285 *  @brief    Set OTP options
286 *
287 *  Set OTP options
288 *
289 *  @return   void
290 *
291 *  @note     use chipcHw_REG_OTP_XXXXXX
292 */
293 /****************************************************************************/
294 static inline void chipcHw_setOTPOption(uint64_t mask)
295 {
296         uint32_t ctrl1 = (uint32_t) mask;
297         uint32_t ctrl2 = (uint32_t) (mask >> 32);
298
299         reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
300         reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
301 }
302
303 /****************************************************************************/
304 /**
305 *  @brief    Get sticky bits
306 *
307 *  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
308 *
309 */
310 /****************************************************************************/
311 static inline uint32_t chipcHw_getStickyBits(void)
312 {
313         return readl(&pChipcHw->Sticky);
314 }
315
316 /****************************************************************************/
317 /**
318 *  @brief    Set sticky bits
319 *
320 *  @return   void
321 *
322 *  @note     use chipcHw_REG_STICKY_XXXXXX
323 */
324 /****************************************************************************/
325 static inline void chipcHw_setStickyBits(uint32_t mask)
326 {
327         uint32_t bits = 0;
328
329         REG_LOCAL_IRQ_SAVE;
330         if (mask & chipcHw_REG_STICKY_POR_BROM) {
331                 bits |= chipcHw_REG_STICKY_POR_BROM;
332         } else {
333                 uint32_t sticky;
334                 sticky = readl(pChipcHw->Sticky);
335
336                 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
337                     && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
338                         bits |= chipcHw_REG_STICKY_BOOT_DONE;
339                 }
340                 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
341                     && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
342                         bits |= chipcHw_REG_STICKY_GENERAL_1;
343                 }
344                 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
345                     && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
346                         bits |= chipcHw_REG_STICKY_GENERAL_2;
347                 }
348                 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
349                     && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
350                         bits |= chipcHw_REG_STICKY_GENERAL_3;
351                 }
352                 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
353                     && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
354                         bits |= chipcHw_REG_STICKY_GENERAL_4;
355                 }
356                 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
357                     && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
358                         bits |= chipcHw_REG_STICKY_GENERAL_5;
359                 }
360         }
361         writel(bits, pChipcHw->Sticky);
362         REG_LOCAL_IRQ_RESTORE;
363 }
364
365 /****************************************************************************/
366 /**
367 *  @brief    Clear sticky bits
368 *
369 *  @return   void
370 *
371 *  @note     use chipcHw_REG_STICKY_XXXXXX
372 */
373 /****************************************************************************/
374 static inline void chipcHw_clearStickyBits(uint32_t mask)
375 {
376         uint32_t bits = 0;
377
378         REG_LOCAL_IRQ_SAVE;
379         if (mask &
380             (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
381              chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
382              chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
383                 uint32_t sticky = readl(&pChipcHw->Sticky);
384
385                 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
386                     && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
387                         bits = chipcHw_REG_STICKY_BOOT_DONE;
388                         mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
389                 }
390                 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
391                     && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
392                         bits |= chipcHw_REG_STICKY_GENERAL_1;
393                         mask &= ~chipcHw_REG_STICKY_GENERAL_1;
394                 }
395                 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
396                     && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
397                         bits |= chipcHw_REG_STICKY_GENERAL_2;
398                         mask &= ~chipcHw_REG_STICKY_GENERAL_2;
399                 }
400                 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
401                     && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
402                         bits |= chipcHw_REG_STICKY_GENERAL_3;
403                         mask &= ~chipcHw_REG_STICKY_GENERAL_3;
404                 }
405                 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
406                     && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
407                         bits |= chipcHw_REG_STICKY_GENERAL_4;
408                         mask &= ~chipcHw_REG_STICKY_GENERAL_4;
409                 }
410                 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
411                     && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
412                         bits |= chipcHw_REG_STICKY_GENERAL_5;
413                         mask &= ~chipcHw_REG_STICKY_GENERAL_5;
414                 }
415         }
416         writel(bits | mask, &pChipcHw->Sticky);
417         REG_LOCAL_IRQ_RESTORE;
418 }
419
420 /****************************************************************************/
421 /**
422 *  @brief    Get software strap value
423 *
424 *  Retrieves software strap value
425 *
426 *  @return   Software strap value
427 *
428 */
429 /****************************************************************************/
430 static inline uint32_t chipcHw_getSoftStraps(void)
431 {
432         return readl(&pChipcHw->SoftStraps);
433 }
434
435 /****************************************************************************/
436 /**
437 *  @brief    Set software override strap options
438 *
439 *  set software override strap options
440 *
441 *  @return   nothing
442 *
443 */
444 /****************************************************************************/
445 static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
446 {
447         reg32_write(&pChipcHw->SoftStraps, strapOptions);
448 }
449
450 /****************************************************************************/
451 /**
452 *  @brief   Get Pin Strap Options
453 *
454 *  This function returns the raw boot strap options
455 *
456 *  @return  strap options
457 *
458 */
459 /****************************************************************************/
460 static inline uint32_t chipcHw_getPinStraps(void)
461 {
462         return readl(&pChipcHw->PinStraps);
463 }
464
465 /****************************************************************************/
466 /**
467 *  @brief   Get Valid Strap Options
468 *
469 *  This function returns the valid raw boot strap options
470 *
471 *  @return  strap options
472 *
473 */
474 /****************************************************************************/
475 static inline uint32_t chipcHw_getValidStraps(void)
476 {
477         uint32_t softStraps;
478
479         /*
480          ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
481          ** which copies HW straps to soft straps if there is no override
482          */
483         softStraps = chipcHw_getSoftStraps();
484
485         return softStraps;
486 }
487
488 /****************************************************************************/
489 /**
490 *  @brief    Initialize valid pin strap options
491 *
492 *  Retrieves valid pin strap options by copying HW strap options to soft register
493 *  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
494 *
495 *  @return   nothing
496 *
497 */
498 /****************************************************************************/
499 static inline void chipcHw_initValidStraps(void)
500 {
501         uint32_t softStraps;
502
503         REG_LOCAL_IRQ_SAVE;
504         softStraps = chipcHw_getSoftStraps();
505
506         if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
507                 /* Copy HW straps to software straps */
508                 chipcHw_setSoftStraps(chipcHw_getPinStraps());
509         }
510         REG_LOCAL_IRQ_RESTORE;
511 }
512
513 /****************************************************************************/
514 /**
515 *  @brief   Get boot device
516 *
517 *  This function returns the device type used in booting the system
518 *
519 *  @return  Boot device of type chipcHw_BOOT_DEVICE
520 *
521 */
522 /****************************************************************************/
523 static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
524 {
525         return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
526 }
527
528 /****************************************************************************/
529 /**
530 *  @brief   Get boot mode
531 *
532 *  This function returns the way the system was booted
533 *
534 *  @return  Boot mode of type chipcHw_BOOT_MODE
535 *
536 */
537 /****************************************************************************/
538 static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
539 {
540         return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
541 }
542
543 /****************************************************************************/
544 /**
545 *  @brief   Get NAND flash page size
546 *
547 *  This function returns the NAND device page size
548 *
549 *  @return  Boot NAND device page size
550 *
551 */
552 /****************************************************************************/
553 static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
554 {
555         return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
556 }
557
558 /****************************************************************************/
559 /**
560 *  @brief   Get NAND flash address cycle configuration
561 *
562 *  This function returns the NAND flash address cycle configuration
563 *
564 *  @return  0 = Do not extra address cycle, 1 = Add extra cycle
565 *
566 */
567 /****************************************************************************/
568 static inline int chipcHw_getNandExtraCycle(void)
569 {
570         if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
571                 return 1;
572         } else {
573                 return 0;
574         }
575 }
576
577 /****************************************************************************/
578 /**
579 *  @brief   Activates PIF interface
580 *
581 *  This function activates PIF interface by taking control of LCD pins
582 *
583 *  @note
584 *       When activated, LCD pins will be defined as follows for PIF operation
585 *
586 *       CLD[17:0]  = pif_data[17:0]
587 *       CLD[23:18] = pif_address[5:0]
588 *       CLPOWER    = pif_wr_str
589 *       CLCP       = pif_rd_str
590 *       CLAC       = pif_hat1
591 *       CLFP       = pif_hrdy1
592 *       CLLP       = pif_hat2
593 *       GPIO[42]   = pif_hrdy2
594 *
595 *       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
596 *
597 */
598 /****************************************************************************/
599 static inline void chipcHw_activatePifInterface(void)
600 {
601         reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
602 }
603
604 /****************************************************************************/
605 /**
606 *  @brief   Activates LCD interface
607 *
608 *  This function activates LCD interface
609 *
610 *  @note
611 *       When activated, LCD pins will be defined as follows
612 *
613 *       CLD[17:0]  = LCD data
614 *       CLD[23:18] = LCD data
615 *       CLPOWER    = LCD power
616 *       CLCP       =
617 *       CLAC       = LCD ack
618 *       CLFP       =
619 *       CLLP       =
620 */
621 /****************************************************************************/
622 static inline void chipcHw_activateLcdInterface(void)
623 {
624         reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
625 }
626
627 /****************************************************************************/
628 /**
629 *  @brief   Deactivates PIF/LCD interface
630 *
631 *  This function deactivates PIF/LCD interface
632 *
633 *  @note
634 *       When deactivated LCD pins will be in rti-stated
635 *
636 */
637 /****************************************************************************/
638 static inline void chipcHw_deactivatePifLcdInterface(void)
639 {
640         reg32_write(&pChipcHw->LcdPifMode, 0);
641 }
642
643 /****************************************************************************/
644 /**
645 *  @brief   Select GE2
646 *
647 *  This function select GE2 as the graphic engine
648 *
649 */
650 /****************************************************************************/
651 static inline void chipcHw_selectGE2(void)
652 {
653         reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
654 }
655
656 /****************************************************************************/
657 /**
658 *  @brief   Select GE3
659 *
660 *  This function select GE3 as the graphic engine
661 *
662 */
663 /****************************************************************************/
664 static inline void chipcHw_selectGE3(void)
665 {
666         reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
667 }
668
669 /****************************************************************************/
670 /**
671 *  @brief   Get to know the configuration of GPIO pin
672 *
673 */
674 /****************************************************************************/
675 static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
676 {
677         return (readl(chipcHw_REG_GPIO_MUX(pin))) &
678                 (chipcHw_REG_GPIO_MUX_MASK <<
679                  chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
680             chipcHw_REG_GPIO_MUX_POSITION(pin);
681 }
682
683 /****************************************************************************/
684 /**
685 *  @brief   Configure GPIO pin function
686 *
687 */
688 /****************************************************************************/
689 static inline void chipcHw_setGpioPinFunction(int pin,
690                                               chipcHw_GPIO_FUNCTION_e func)
691 {
692         REG_LOCAL_IRQ_SAVE;
693         *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
694             ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
695         *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
696             func << chipcHw_REG_GPIO_MUX_POSITION(pin);
697         REG_LOCAL_IRQ_RESTORE;
698 }
699
700 /****************************************************************************/
701 /**
702 *  @brief   Set Pin slew rate
703 *
704 *  This function sets the slew of individual pin
705 *
706 */
707 /****************************************************************************/
708 static inline void chipcHw_setPinSlewRate(uint32_t pin,
709                                           chipcHw_PIN_SLEW_RATE_e slewRate)
710 {
711         REG_LOCAL_IRQ_SAVE;
712         *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
713             ~(chipcHw_REG_SLEW_RATE_MASK <<
714               chipcHw_REG_SLEW_RATE_POSITION(pin));
715         *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
716             (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
717         REG_LOCAL_IRQ_RESTORE;
718 }
719
720 /****************************************************************************/
721 /**
722 *  @brief   Set Pin output drive current
723 *
724 *  This function sets output drive current of individual pin
725 *
726 *  Note: Avoid the use of the word 'current' since linux headers define this
727 *        to be the current task.
728 */
729 /****************************************************************************/
730 static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
731                                                chipcHw_PIN_CURRENT_STRENGTH_e
732                                                curr)
733 {
734         REG_LOCAL_IRQ_SAVE;
735         *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
736             ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
737         *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
738             (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
739         REG_LOCAL_IRQ_RESTORE;
740 }
741
742 /****************************************************************************/
743 /**
744 *  @brief   Set Pin pullup register
745 *
746 *  This function sets pullup register of individual pin
747 *
748 */
749 /****************************************************************************/
750 static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
751 {
752         REG_LOCAL_IRQ_SAVE;
753         *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
754             ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
755         *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
756             (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
757         REG_LOCAL_IRQ_RESTORE;
758 }
759
760 /****************************************************************************/
761 /**
762 *  @brief   Set Pin input type
763 *
764 *  This function sets input type of individual pin
765 *
766 */
767 /****************************************************************************/
768 static inline void chipcHw_setPinInputType(uint32_t pin,
769                                            chipcHw_PIN_INPUTTYPE_e inputType)
770 {
771         REG_LOCAL_IRQ_SAVE;
772         *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
773             ~(chipcHw_REG_INPUTTYPE_MASK <<
774               chipcHw_REG_INPUTTYPE_POSITION(pin));
775         *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
776             (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
777         REG_LOCAL_IRQ_RESTORE;
778 }
779
780 /****************************************************************************/
781 /**
782 *  @brief   Power up the USB PHY
783 *
784 *  This function powers up the USB PHY
785 *
786 */
787 /****************************************************************************/
788 static inline void chipcHw_powerUpUsbPhy(void)
789 {
790         reg32_modify_and(&pChipcHw->MiscCtrl,
791                          chipcHw_REG_MISC_CTRL_USB_POWERON);
792 }
793
794 /****************************************************************************/
795 /**
796 *  @brief   Power down the USB PHY
797 *
798 *  This function powers down the USB PHY
799 *
800 */
801 /****************************************************************************/
802 static inline void chipcHw_powerDownUsbPhy(void)
803 {
804         reg32_modify_or(&pChipcHw->MiscCtrl,
805                         chipcHw_REG_MISC_CTRL_USB_POWEROFF);
806 }
807
808 /****************************************************************************/
809 /**
810 *  @brief   Set the 2nd USB as host
811 *
812 *  This function sets the 2nd USB as host
813 *
814 */
815 /****************************************************************************/
816 static inline void chipcHw_setUsbHost(void)
817 {
818         reg32_modify_or(&pChipcHw->MiscCtrl,
819                         chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
820 }
821
822 /****************************************************************************/
823 /**
824 *  @brief   Set the 2nd USB as device
825 *
826 *  This function sets the 2nd USB as device
827 *
828 */
829 /****************************************************************************/
830 static inline void chipcHw_setUsbDevice(void)
831 {
832         reg32_modify_and(&pChipcHw->MiscCtrl,
833                          chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
834 }
835
836 /****************************************************************************/
837 /**
838 *  @brief   Lower layer function to enable/disable a clock of a certain device
839 *
840 *  This function enables/disables a core clock
841 *
842 */
843 /****************************************************************************/
844 static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
845                                     chipcHw_OPTYPE_e type, int mode)
846 {
847         uint32_t __iomem *pPLLReg = NULL;
848         uint32_t __iomem *pClockCtrl = NULL;
849
850         switch (clock) {
851         case chipcHw_CLOCK_DDR:
852                 pPLLReg = &pChipcHw->DDRClock;
853                 break;
854         case chipcHw_CLOCK_ARM:
855                 pPLLReg = &pChipcHw->ARMClock;
856                 break;
857         case chipcHw_CLOCK_ESW:
858                 pPLLReg = &pChipcHw->ESWClock;
859                 break;
860         case chipcHw_CLOCK_VPM:
861                 pPLLReg = &pChipcHw->VPMClock;
862                 break;
863         case chipcHw_CLOCK_ESW125:
864                 pPLLReg = &pChipcHw->ESW125Clock;
865                 break;
866         case chipcHw_CLOCK_UART:
867                 pPLLReg = &pChipcHw->UARTClock;
868                 break;
869         case chipcHw_CLOCK_SDIO0:
870                 pPLLReg = &pChipcHw->SDIO0Clock;
871                 break;
872         case chipcHw_CLOCK_SDIO1:
873                 pPLLReg = &pChipcHw->SDIO1Clock;
874                 break;
875         case chipcHw_CLOCK_SPI:
876                 pPLLReg = &pChipcHw->SPIClock;
877                 break;
878         case chipcHw_CLOCK_ETM:
879                 pPLLReg = &pChipcHw->ETMClock;
880                 break;
881         case chipcHw_CLOCK_USB:
882                 pPLLReg = &pChipcHw->USBClock;
883                 if (type == chipcHw_OPTYPE_OUTPUT) {
884                         if (mode) {
885                                 reg32_modify_and(pPLLReg,
886                                                  ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
887                         } else {
888                                 reg32_modify_or(pPLLReg,
889                                                 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
890                         }
891                 }
892                 break;
893         case chipcHw_CLOCK_LCD:
894                 pPLLReg = &pChipcHw->LCDClock;
895                 if (type == chipcHw_OPTYPE_OUTPUT) {
896                         if (mode) {
897                                 reg32_modify_and(pPLLReg,
898                                                  ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
899                         } else {
900                                 reg32_modify_or(pPLLReg,
901                                                 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
902                         }
903                 }
904                 break;
905         case chipcHw_CLOCK_APM:
906                 pPLLReg = &pChipcHw->APMClock;
907                 if (type == chipcHw_OPTYPE_OUTPUT) {
908                         if (mode) {
909                                 reg32_modify_and(pPLLReg,
910                                                  ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
911                         } else {
912                                 reg32_modify_or(pPLLReg,
913                                                 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
914                         }
915                 }
916                 break;
917         case chipcHw_CLOCK_BUS:
918                 pClockCtrl = &pChipcHw->ACLKClock;
919                 break;
920         case chipcHw_CLOCK_OTP:
921                 pClockCtrl = &pChipcHw->OTPClock;
922                 break;
923         case chipcHw_CLOCK_I2C:
924                 pClockCtrl = &pChipcHw->I2CClock;
925                 break;
926         case chipcHw_CLOCK_I2S0:
927                 pClockCtrl = &pChipcHw->I2S0Clock;
928                 break;
929         case chipcHw_CLOCK_RTBUS:
930                 pClockCtrl = &pChipcHw->RTBUSClock;
931                 break;
932         case chipcHw_CLOCK_APM100:
933                 pClockCtrl = &pChipcHw->APM100Clock;
934                 break;
935         case chipcHw_CLOCK_TSC:
936                 pClockCtrl = &pChipcHw->TSCClock;
937                 break;
938         case chipcHw_CLOCK_LED:
939                 pClockCtrl = &pChipcHw->LEDClock;
940                 break;
941         case chipcHw_CLOCK_I2S1:
942                 pClockCtrl = &pChipcHw->I2S1Clock;
943                 break;
944         }
945
946         if (pPLLReg) {
947                 switch (type) {
948                 case chipcHw_OPTYPE_OUTPUT:
949                         /* PLL clock output enable/disable */
950                         if (mode) {
951                                 if (clock == chipcHw_CLOCK_DDR) {
952                                         /* DDR clock enable is inverted */
953                                         reg32_modify_and(pPLLReg,
954                                                          ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
955                                 } else {
956                                         reg32_modify_or(pPLLReg,
957                                                         chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
958                                 }
959                         } else {
960                                 if (clock == chipcHw_CLOCK_DDR) {
961                                         /* DDR clock disable is inverted */
962                                         reg32_modify_or(pPLLReg,
963                                                         chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
964                                 } else {
965                                         reg32_modify_and(pPLLReg,
966                                                          ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
967                                 }
968                         }
969                         break;
970                 case chipcHw_OPTYPE_BYPASS:
971                         /* PLL clock bypass enable/disable */
972                         if (mode) {
973                                 reg32_modify_or(pPLLReg,
974                                                 chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
975                         } else {
976                                 reg32_modify_and(pPLLReg,
977                                                  ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
978                         }
979                         break;
980                 }
981         } else if (pClockCtrl) {
982                 switch (type) {
983                 case chipcHw_OPTYPE_OUTPUT:
984                         if (mode) {
985                                 reg32_modify_or(pClockCtrl,
986                                                 chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
987                         } else {
988                                 reg32_modify_and(pClockCtrl,
989                                                  ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
990                         }
991                         break;
992                 case chipcHw_OPTYPE_BYPASS:
993                         if (mode) {
994                                 reg32_modify_or(pClockCtrl,
995                                                 chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
996                         } else {
997                                 reg32_modify_and(pClockCtrl,
998                                                  ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
999                         }
1000                         break;
1001                 }
1002         }
1003 }
1004
1005 /****************************************************************************/
1006 /**
1007 *  @brief   Disables a core clock of a certain device
1008 *
1009 *  This function disables a core clock
1010 *
1011 *  @note    no change in power consumption
1012 */
1013 /****************************************************************************/
1014 static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
1015 {
1016
1017         /* Disable output of the clock */
1018         chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
1019 }
1020
1021 /****************************************************************************/
1022 /**
1023 *  @brief   Enable a core clock of a certain device
1024 *
1025 *  This function enables a core clock
1026 *
1027 *  @note    no change in power consumption
1028 */
1029 /****************************************************************************/
1030 static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
1031 {
1032
1033         /* Enable output of the clock */
1034         chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
1035 }
1036
1037 /****************************************************************************/
1038 /**
1039 *  @brief   Enables bypass clock of a certain device
1040 *
1041 *  This function enables bypass clock
1042 *
1043 *  @note    Doesnot affect the bus interface clock
1044 */
1045 /****************************************************************************/
1046 static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
1047 {
1048         /* Enable bypass clock */
1049         chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
1050 }
1051
1052 /****************************************************************************/
1053 /**
1054 *  @brief   Disabled bypass clock of a certain device
1055 *
1056 *  This function disables bypass clock
1057 *
1058 *  @note    Doesnot affect the bus interface clock
1059 */
1060 /****************************************************************************/
1061 static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
1062 {
1063         /* Disable bypass clock */
1064         chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
1065
1066 }
1067
1068 /****************************************************************************/
1069 /**  @brief Checks if software strap is enabled
1070  *
1071  *   @return 1 : When enable
1072  *           0 : When disable
1073  */
1074 /****************************************************************************/
1075 static inline int chipcHw_isSoftwareStrapsEnable(void)
1076 {
1077         return readl(&pChipcHw->SoftStraps) & 0x00000001;
1078 }
1079
1080 /****************************************************************************/
1081 /**  @brief Enable software strap
1082  */
1083 /****************************************************************************/
1084 static inline void chipcHw_softwareStrapsEnable(void)
1085 {
1086         reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
1087 }
1088
1089 /****************************************************************************/
1090 /**  @brief Disable software strap
1091  */
1092 /****************************************************************************/
1093 static inline void chipcHw_softwareStrapsDisable(void)
1094 {
1095         reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
1096 }
1097
1098 /****************************************************************************/
1099 /**  @brief PLL test enable
1100  */
1101 /****************************************************************************/
1102 static inline void chipcHw_pllTestEnable(void)
1103 {
1104         reg32_modify_or(&pChipcHw->PLLConfig,
1105                         chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1106 }
1107
1108 /****************************************************************************/
1109 /**  @brief PLL2 test enable
1110  */
1111 /****************************************************************************/
1112 static inline void chipcHw_pll2TestEnable(void)
1113 {
1114         reg32_modify_or(&pChipcHw->PLLConfig2,
1115                         chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1116 }
1117
1118 /****************************************************************************/
1119 /**  @brief PLL test disable
1120  */
1121 /****************************************************************************/
1122 static inline void chipcHw_pllTestDisable(void)
1123 {
1124         reg32_modify_and(&pChipcHw->PLLConfig,
1125                          ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1126 }
1127
1128 /****************************************************************************/
1129 /**  @brief PLL2 test disable
1130  */
1131 /****************************************************************************/
1132 static inline void chipcHw_pll2TestDisable(void)
1133 {
1134         reg32_modify_and(&pChipcHw->PLLConfig2,
1135                          ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1136 }
1137
1138 /****************************************************************************/
1139 /**  @brief Get PLL test status
1140  */
1141 /****************************************************************************/
1142 static inline int chipcHw_isPllTestEnable(void)
1143 {
1144         return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1145 }
1146
1147 /****************************************************************************/
1148 /**  @brief Get PLL2 test status
1149  */
1150 /****************************************************************************/
1151 static inline int chipcHw_isPll2TestEnable(void)
1152 {
1153         return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1154 }
1155
1156 /****************************************************************************/
1157 /**  @brief PLL test select
1158  */
1159 /****************************************************************************/
1160 static inline void chipcHw_pllTestSelect(uint32_t val)
1161 {
1162         REG_LOCAL_IRQ_SAVE;
1163         pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1164         pChipcHw->PLLConfig |=
1165             (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1166         REG_LOCAL_IRQ_RESTORE;
1167 }
1168
1169 /****************************************************************************/
1170 /**  @brief PLL2 test select
1171  */
1172 /****************************************************************************/
1173 static inline void chipcHw_pll2TestSelect(uint32_t val)
1174 {
1175
1176         REG_LOCAL_IRQ_SAVE;
1177         pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1178         pChipcHw->PLLConfig2 |=
1179             (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1180         REG_LOCAL_IRQ_RESTORE;
1181 }
1182
1183 /****************************************************************************/
1184 /**  @brief Get PLL test selected option
1185  */
1186 /****************************************************************************/
1187 static inline uint8_t chipcHw_getPllTestSelected(void)
1188 {
1189         return (uint8_t) ((readl(&pChipcHw->
1190                            PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1191                           >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1192 }
1193
1194 /****************************************************************************/
1195 /**  @brief Get PLL2 test selected option
1196  */
1197 /****************************************************************************/
1198 static inline uint8_t chipcHw_getPll2TestSelected(void)
1199 {
1200         return (uint8_t) ((readl(&pChipcHw->
1201                            PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1202                           >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1203 }
1204
1205 /****************************************************************************/
1206 /**
1207 *  @brief  Disable the PLL1
1208 *
1209 */
1210 /****************************************************************************/
1211 static inline void chipcHw_pll1Disable(void)
1212 {
1213         REG_LOCAL_IRQ_SAVE;
1214         writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
1215                 &pChipcHw->PLLConfig);
1216         REG_LOCAL_IRQ_RESTORE;
1217 }
1218
1219 /****************************************************************************/
1220 /**
1221 *  @brief  Disable the PLL2
1222 *
1223 */
1224 /****************************************************************************/
1225 static inline void chipcHw_pll2Disable(void)
1226 {
1227         REG_LOCAL_IRQ_SAVE;
1228         writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
1229                 &pChipcHw->PLLConfig2);
1230         REG_LOCAL_IRQ_RESTORE;
1231 }
1232
1233 /****************************************************************************/
1234 /**
1235 *  @brief   Enables DDR SW phase alignment interrupt
1236 */
1237 /****************************************************************************/
1238 static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
1239 {
1240         REG_LOCAL_IRQ_SAVE;
1241         writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
1242                 &pChipcHw->Spare1);
1243         REG_LOCAL_IRQ_RESTORE;
1244 }
1245
1246 /****************************************************************************/
1247 /**
1248 *  @brief   Disables DDR SW phase alignment interrupt
1249 */
1250 /****************************************************************************/
1251 static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
1252 {
1253         REG_LOCAL_IRQ_SAVE;
1254         writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
1255                 &pChipcHw->Spare1);
1256         REG_LOCAL_IRQ_RESTORE;
1257 }
1258
1259 /****************************************************************************/
1260 /**
1261 *  @brief   Set VPM SW phase alignment interrupt mode
1262 *
1263 *  This function sets VPM phase alignment interrupt
1264 */
1265 /****************************************************************************/
1266 static inline void
1267 chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
1268 {
1269         REG_LOCAL_IRQ_SAVE;
1270         if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
1271                 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1272         } else {
1273                 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1274         }
1275         pChipcHw->VPMPhaseCtrl2 =
1276             (pChipcHw->
1277              VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
1278                                chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
1279         REG_LOCAL_IRQ_RESTORE;
1280 }
1281
1282 /****************************************************************************/
1283 /**
1284 *  @brief   Enable DDR phase alignment in software
1285 *
1286 */
1287 /****************************************************************************/
1288 static inline void chipcHw_ddrSwPhaseAlignEnable(void)
1289 {
1290         REG_LOCAL_IRQ_SAVE;
1291         pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1292         REG_LOCAL_IRQ_RESTORE;
1293 }
1294
1295 /****************************************************************************/
1296 /**
1297 *  @brief   Disable DDR phase alignment in software
1298 *
1299 */
1300 /****************************************************************************/
1301 static inline void chipcHw_ddrSwPhaseAlignDisable(void)
1302 {
1303         REG_LOCAL_IRQ_SAVE;
1304         pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1305         REG_LOCAL_IRQ_RESTORE;
1306 }
1307
1308 /****************************************************************************/
1309 /**
1310 *  @brief   Enable DDR phase alignment in hardware
1311 *
1312 */
1313 /****************************************************************************/
1314 static inline void chipcHw_ddrHwPhaseAlignEnable(void)
1315 {
1316         REG_LOCAL_IRQ_SAVE;
1317         pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1318         REG_LOCAL_IRQ_RESTORE;
1319 }
1320
1321 /****************************************************************************/
1322 /**
1323 *  @brief   Disable DDR phase alignment in hardware
1324 *
1325 */
1326 /****************************************************************************/
1327 static inline void chipcHw_ddrHwPhaseAlignDisable(void)
1328 {
1329         REG_LOCAL_IRQ_SAVE;
1330         pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1331         REG_LOCAL_IRQ_RESTORE;
1332 }
1333
1334 /****************************************************************************/
1335 /**
1336 *  @brief   Enable VPM phase alignment in software
1337 *
1338 */
1339 /****************************************************************************/
1340 static inline void chipcHw_vpmSwPhaseAlignEnable(void)
1341 {
1342         REG_LOCAL_IRQ_SAVE;
1343         writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
1344                         &pChipcHw->VPMPhaseCtrl1);
1345         REG_LOCAL_IRQ_RESTORE;
1346 }
1347
1348 /****************************************************************************/
1349 /**
1350 *  @brief   Disable VPM phase alignment in software
1351 *
1352 */
1353 /****************************************************************************/
1354 static inline void chipcHw_vpmSwPhaseAlignDisable(void)
1355 {
1356         REG_LOCAL_IRQ_SAVE;
1357         pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1358         REG_LOCAL_IRQ_RESTORE;
1359 }
1360
1361 /****************************************************************************/
1362 /**
1363 *  @brief   Enable VPM phase alignment in hardware
1364 *
1365 */
1366 /****************************************************************************/
1367 static inline void chipcHw_vpmHwPhaseAlignEnable(void)
1368 {
1369         REG_LOCAL_IRQ_SAVE;
1370         pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1371         REG_LOCAL_IRQ_RESTORE;
1372 }
1373
1374 /****************************************************************************/
1375 /**
1376 *  @brief   Disable VPM phase alignment in hardware
1377 *
1378 */
1379 /****************************************************************************/
1380 static inline void chipcHw_vpmHwPhaseAlignDisable(void)
1381 {
1382         REG_LOCAL_IRQ_SAVE;
1383         writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
1384                 &pChipcHw->VPMPhaseCtrl1);
1385         REG_LOCAL_IRQ_RESTORE;
1386 }
1387
1388 /****************************************************************************/
1389 /**
1390 *  @brief   Set DDR phase alignment margin in hardware
1391 *
1392 */
1393 /****************************************************************************/
1394 static inline void
1395 chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
1396 {
1397         uint32_t ge = 0;
1398         uint32_t le = 0;
1399
1400         switch (margin) {
1401         case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
1402                 ge = 0x0F;
1403                 le = 0x0F;
1404                 break;
1405         case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
1406                 ge = 0x03;
1407                 le = 0x3F;
1408                 break;
1409         case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
1410                 ge = 0x01;
1411                 le = 0x7F;
1412                 break;
1413         }
1414
1415         {
1416                 REG_LOCAL_IRQ_SAVE;
1417
1418                 pChipcHw->DDRPhaseCtrl1 &=
1419                     ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
1420                        chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1421                       || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
1422                           chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1423
1424                 pChipcHw->DDRPhaseCtrl1 |=
1425                     ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1426                      || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1427
1428                 REG_LOCAL_IRQ_RESTORE;
1429         }
1430 }
1431
1432 /****************************************************************************/
1433 /**
1434 *  @brief   Set VPM phase alignment margin in hardware
1435 *
1436 */
1437 /****************************************************************************/
1438 static inline void
1439 chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
1440 {
1441         uint32_t ge = 0;
1442         uint32_t le = 0;
1443
1444         switch (margin) {
1445         case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
1446                 ge = 0x0F;
1447                 le = 0x0F;
1448                 break;
1449         case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
1450                 ge = 0x03;
1451                 le = 0x3F;
1452                 break;
1453         case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
1454                 ge = 0x01;
1455                 le = 0x7F;
1456                 break;
1457         }
1458
1459         {
1460                 REG_LOCAL_IRQ_SAVE;
1461
1462                 pChipcHw->VPMPhaseCtrl1 &=
1463                     ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
1464                        chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1465                       || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
1466                           chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1467
1468                 pChipcHw->VPMPhaseCtrl1 |=
1469                     ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1470                      || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1471
1472                 REG_LOCAL_IRQ_RESTORE;
1473         }
1474 }
1475
1476 /****************************************************************************/
1477 /**
1478 *  @brief   Checks DDR phase aligned status done by HW
1479 *
1480 *  @return  1: When aligned
1481 *           0: When not aligned
1482 */
1483 /****************************************************************************/
1484 static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
1485 {
1486         return (readl(&pChipcHw->
1487                 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
1488 }
1489
1490 /****************************************************************************/
1491 /**
1492 *  @brief   Checks VPM phase aligned status done by HW
1493 *
1494 *  @return  1: When aligned
1495 *           0: When not aligned
1496 */
1497 /****************************************************************************/
1498 static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
1499 {
1500         return (readl(&pChipcHw->
1501                 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
1502 }
1503
1504 /****************************************************************************/
1505 /**
1506 *  @brief   Get DDR phase aligned status done by HW
1507 *
1508 */
1509 /****************************************************************************/
1510 static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
1511 {
1512         return (readl(&pChipcHw->
1513                 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
1514             chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
1515 }
1516
1517 /****************************************************************************/
1518 /**
1519 *  @brief   Get VPM phase aligned status done by HW
1520 *
1521 */
1522 /****************************************************************************/
1523 static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
1524 {
1525         return (readl(&pChipcHw->
1526                 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
1527             chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
1528 }
1529
1530 /****************************************************************************/
1531 /**
1532 *  @brief   Get DDR phase control value
1533 *
1534 */
1535 /****************************************************************************/
1536 static inline uint32_t chipcHw_getDdrPhaseControl(void)
1537 {
1538         return (readl(&pChipcHw->
1539                 PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
1540             chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
1541 }
1542
1543 /****************************************************************************/
1544 /**
1545 *  @brief   Get VPM phase control value
1546 *
1547 */
1548 /****************************************************************************/
1549 static inline uint32_t chipcHw_getVpmPhaseControl(void)
1550 {
1551         return (readl(&pChipcHw->
1552                 PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
1553             chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
1554 }
1555
1556 /****************************************************************************/
1557 /**
1558 *  @brief   DDR phase alignment timeout count
1559 *
1560 *  @note    If HW fails to perform the phase alignment, it will trigger
1561 *           a DDR phase alignment timeout interrupt.
1562 */
1563 /****************************************************************************/
1564 static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
1565 {
1566         REG_LOCAL_IRQ_SAVE;
1567         pChipcHw->DDRPhaseCtrl2 &=
1568             ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
1569               chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
1570         pChipcHw->DDRPhaseCtrl2 |=
1571             (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
1572             chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
1573         REG_LOCAL_IRQ_RESTORE;
1574 }
1575
1576 /****************************************************************************/
1577 /**
1578 *  @brief   VPM phase alignment timeout count
1579 *
1580 *  @note    If HW fails to perform the phase alignment, it will trigger
1581 *           a VPM phase alignment timeout interrupt.
1582 */
1583 /****************************************************************************/
1584 static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
1585 {
1586         REG_LOCAL_IRQ_SAVE;
1587         pChipcHw->VPMPhaseCtrl2 &=
1588             ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
1589               chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
1590         pChipcHw->VPMPhaseCtrl2 |=
1591             (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
1592             chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
1593         REG_LOCAL_IRQ_RESTORE;
1594 }
1595
1596 /****************************************************************************/
1597 /**
1598 *  @brief   Clear DDR phase alignment timeout interrupt
1599 *
1600 */
1601 /****************************************************************************/
1602 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
1603 {
1604         REG_LOCAL_IRQ_SAVE;
1605         /* Clear timeout interrupt service bit */
1606         pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
1607         pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
1608         REG_LOCAL_IRQ_RESTORE;
1609 }
1610
1611 /****************************************************************************/
1612 /**
1613 *  @brief   Clear VPM phase alignment timeout interrupt
1614 *
1615 */
1616 /****************************************************************************/
1617 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
1618 {
1619         REG_LOCAL_IRQ_SAVE;
1620         /* Clear timeout interrupt service bit */
1621         pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
1622         pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
1623         REG_LOCAL_IRQ_RESTORE;
1624 }
1625
1626 /****************************************************************************/
1627 /**
1628 *  @brief   DDR phase alignment timeout interrupt enable
1629 *
1630 */
1631 /****************************************************************************/
1632 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
1633 {
1634         REG_LOCAL_IRQ_SAVE;
1635         chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1636         /* Enable timeout interrupt */
1637         pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1638         REG_LOCAL_IRQ_RESTORE;
1639 }
1640
1641 /****************************************************************************/
1642 /**
1643 *  @brief   VPM phase alignment timeout interrupt enable
1644 *
1645 */
1646 /****************************************************************************/
1647 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
1648 {
1649         REG_LOCAL_IRQ_SAVE;
1650         chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1651         /* Enable timeout interrupt */
1652         pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1653         REG_LOCAL_IRQ_RESTORE;
1654 }
1655
1656 /****************************************************************************/
1657 /**
1658 *  @brief   DDR phase alignment timeout interrupt disable
1659 *
1660 */
1661 /****************************************************************************/
1662 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
1663 {
1664         REG_LOCAL_IRQ_SAVE;
1665         pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1666         REG_LOCAL_IRQ_RESTORE;
1667 }
1668
1669 /****************************************************************************/
1670 /**
1671 *  @brief   VPM phase alignment timeout interrupt disable
1672 *
1673 */
1674 /****************************************************************************/
1675 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
1676 {
1677         REG_LOCAL_IRQ_SAVE;
1678         pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1679         REG_LOCAL_IRQ_RESTORE;
1680 }
1681
1682 #endif /* CHIPC_INLINE_H */