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1 /*
2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3  *              http://www.samsung.com
4  *
5  * EXYNOS4 - Clock support
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/syscore_ops.h>
16
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
19 #include <plat/cpu.h>
20 #include <plat/pll.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
23 #include <plat/pm.h>
24
25 #include <mach/map.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
28
29 #include "common.h"
30 #include "clock-exynos4.h"
31
32 #ifdef CONFIG_PM_SLEEP
33 static struct sleep_save exynos4_clock_save[] = {
34         SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
35         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
36         SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
37         SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
38         SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
39         SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
40         SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
41         SAVE_ITEM(EXYNOS4_CLKSRC_TV),
42         SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
43         SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
44         SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
45         SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
46         SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
47         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
48         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
49         SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
50         SAVE_ITEM(EXYNOS4_CLKDIV_TV),
51         SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
52         SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
53         SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
54         SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
55         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
56         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
57         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
58         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
59         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
60         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
61         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
62         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
63         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
64         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
65         SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
66         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
67         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
68         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
69         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
70         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
71         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
72         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
73         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
74         SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
75         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
76         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
77         SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
78         SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
79         SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
80         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
81         SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
82         SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
83         SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
84         SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
85         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
86         SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
87         SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
88         SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
89         SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
90         SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
91         SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
92         SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
93         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
94         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
95 };
96 #endif
97
98 static struct clk exynos4_clk_sclk_hdmi27m = {
99         .name           = "sclk_hdmi27m",
100         .rate           = 27000000,
101 };
102
103 static struct clk exynos4_clk_sclk_hdmiphy = {
104         .name           = "sclk_hdmiphy",
105 };
106
107 static struct clk exynos4_clk_sclk_usbphy0 = {
108         .name           = "sclk_usbphy0",
109         .rate           = 27000000,
110 };
111
112 static struct clk exynos4_clk_sclk_usbphy1 = {
113         .name           = "sclk_usbphy1",
114 };
115
116 static struct clk dummy_apb_pclk = {
117         .name           = "apb_pclk",
118         .id             = -1,
119 };
120
121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122 {
123         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124 }
125
126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127 {
128         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129 }
130
131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132 {
133         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134 }
135
136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137 {
138         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139 }
140
141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142 {
143         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144 }
145
146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147 {
148         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149 }
150
151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152 {
153         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154 }
155
156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157 {
158         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159 }
160
161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162 {
163         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
164 }
165
166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167 {
168         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169 }
170
171 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172 {
173         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174 }
175
176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177 {
178         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
179 }
180
181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182 {
183         return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
184 }
185
186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187 {
188         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189 }
190
191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192 {
193         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194 }
195
196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197 {
198         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199 }
200
201 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
202 {
203         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
204 }
205
206 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
207 {
208         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
209 }
210
211 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
212 {
213         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
214 }
215
216 /* Core list of CMU_CPU side */
217
218 static struct clksrc_clk exynos4_clk_mout_apll = {
219         .clk    = {
220                 .name           = "mout_apll",
221         },
222         .sources = &clk_src_apll,
223         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
224 };
225
226 static struct clksrc_clk exynos4_clk_sclk_apll = {
227         .clk    = {
228                 .name           = "sclk_apll",
229                 .parent         = &exynos4_clk_mout_apll.clk,
230         },
231         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
232 };
233
234 static struct clksrc_clk exynos4_clk_mout_epll = {
235         .clk    = {
236                 .name           = "mout_epll",
237         },
238         .sources = &clk_src_epll,
239         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
240 };
241
242 struct clksrc_clk exynos4_clk_mout_mpll = {
243         .clk    = {
244                 .name           = "mout_mpll",
245         },
246         .sources = &clk_src_mpll,
247
248         /* reg_src will be added in each SoCs' clock */
249 };
250
251 static struct clk *exynos4_clkset_moutcore_list[] = {
252         [0] = &exynos4_clk_mout_apll.clk,
253         [1] = &exynos4_clk_mout_mpll.clk,
254 };
255
256 static struct clksrc_sources exynos4_clkset_moutcore = {
257         .sources        = exynos4_clkset_moutcore_list,
258         .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
259 };
260
261 static struct clksrc_clk exynos4_clk_moutcore = {
262         .clk    = {
263                 .name           = "moutcore",
264         },
265         .sources = &exynos4_clkset_moutcore,
266         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
267 };
268
269 static struct clksrc_clk exynos4_clk_coreclk = {
270         .clk    = {
271                 .name           = "core_clk",
272                 .parent         = &exynos4_clk_moutcore.clk,
273         },
274         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
275 };
276
277 static struct clksrc_clk exynos4_clk_armclk = {
278         .clk    = {
279                 .name           = "armclk",
280                 .parent         = &exynos4_clk_coreclk.clk,
281         },
282 };
283
284 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
285         .clk    = {
286                 .name           = "aclk_corem0",
287                 .parent         = &exynos4_clk_coreclk.clk,
288         },
289         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
290 };
291
292 static struct clksrc_clk exynos4_clk_aclk_cores = {
293         .clk    = {
294                 .name           = "aclk_cores",
295                 .parent         = &exynos4_clk_coreclk.clk,
296         },
297         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
298 };
299
300 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
301         .clk    = {
302                 .name           = "aclk_corem1",
303                 .parent         = &exynos4_clk_coreclk.clk,
304         },
305         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
306 };
307
308 static struct clksrc_clk exynos4_clk_periphclk = {
309         .clk    = {
310                 .name           = "periphclk",
311                 .parent         = &exynos4_clk_coreclk.clk,
312         },
313         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
314 };
315
316 /* Core list of CMU_CORE side */
317
318 static struct clk *exynos4_clkset_corebus_list[] = {
319         [0] = &exynos4_clk_mout_mpll.clk,
320         [1] = &exynos4_clk_sclk_apll.clk,
321 };
322
323 struct clksrc_sources exynos4_clkset_mout_corebus = {
324         .sources        = exynos4_clkset_corebus_list,
325         .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
326 };
327
328 static struct clksrc_clk exynos4_clk_mout_corebus = {
329         .clk    = {
330                 .name           = "mout_corebus",
331         },
332         .sources = &exynos4_clkset_mout_corebus,
333         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
334 };
335
336 static struct clksrc_clk exynos4_clk_sclk_dmc = {
337         .clk    = {
338                 .name           = "sclk_dmc",
339                 .parent         = &exynos4_clk_mout_corebus.clk,
340         },
341         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
342 };
343
344 static struct clksrc_clk exynos4_clk_aclk_cored = {
345         .clk    = {
346                 .name           = "aclk_cored",
347                 .parent         = &exynos4_clk_sclk_dmc.clk,
348         },
349         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
350 };
351
352 static struct clksrc_clk exynos4_clk_aclk_corep = {
353         .clk    = {
354                 .name           = "aclk_corep",
355                 .parent         = &exynos4_clk_aclk_cored.clk,
356         },
357         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
358 };
359
360 static struct clksrc_clk exynos4_clk_aclk_acp = {
361         .clk    = {
362                 .name           = "aclk_acp",
363                 .parent         = &exynos4_clk_mout_corebus.clk,
364         },
365         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
366 };
367
368 static struct clksrc_clk exynos4_clk_pclk_acp = {
369         .clk    = {
370                 .name           = "pclk_acp",
371                 .parent         = &exynos4_clk_aclk_acp.clk,
372         },
373         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
374 };
375
376 /* Core list of CMU_TOP side */
377
378 struct clk *exynos4_clkset_aclk_top_list[] = {
379         [0] = &exynos4_clk_mout_mpll.clk,
380         [1] = &exynos4_clk_sclk_apll.clk,
381 };
382
383 static struct clksrc_sources exynos4_clkset_aclk = {
384         .sources        = exynos4_clkset_aclk_top_list,
385         .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
386 };
387
388 static struct clksrc_clk exynos4_clk_aclk_200 = {
389         .clk    = {
390                 .name           = "aclk_200",
391         },
392         .sources = &exynos4_clkset_aclk,
393         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
394         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
395 };
396
397 static struct clksrc_clk exynos4_clk_aclk_100 = {
398         .clk    = {
399                 .name           = "aclk_100",
400         },
401         .sources = &exynos4_clkset_aclk,
402         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
403         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
404 };
405
406 static struct clksrc_clk exynos4_clk_aclk_160 = {
407         .clk    = {
408                 .name           = "aclk_160",
409         },
410         .sources = &exynos4_clkset_aclk,
411         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
412         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
413 };
414
415 struct clksrc_clk exynos4_clk_aclk_133 = {
416         .clk    = {
417                 .name           = "aclk_133",
418         },
419         .sources = &exynos4_clkset_aclk,
420         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
421         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
422 };
423
424 static struct clk *exynos4_clkset_vpllsrc_list[] = {
425         [0] = &clk_fin_vpll,
426         [1] = &exynos4_clk_sclk_hdmi27m,
427 };
428
429 static struct clksrc_sources exynos4_clkset_vpllsrc = {
430         .sources        = exynos4_clkset_vpllsrc_list,
431         .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
432 };
433
434 static struct clksrc_clk exynos4_clk_vpllsrc = {
435         .clk    = {
436                 .name           = "vpll_src",
437                 .enable         = exynos4_clksrc_mask_top_ctrl,
438                 .ctrlbit        = (1 << 0),
439         },
440         .sources = &exynos4_clkset_vpllsrc,
441         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
442 };
443
444 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
445         [0] = &exynos4_clk_vpllsrc.clk,
446         [1] = &clk_fout_vpll,
447 };
448
449 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
450         .sources        = exynos4_clkset_sclk_vpll_list,
451         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
452 };
453
454 static struct clksrc_clk exynos4_clk_sclk_vpll = {
455         .clk    = {
456                 .name           = "sclk_vpll",
457         },
458         .sources = &exynos4_clkset_sclk_vpll,
459         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
460 };
461
462 static struct clk exynos4_init_clocks_off[] = {
463         {
464                 .name           = "timers",
465                 .parent         = &exynos4_clk_aclk_100.clk,
466                 .enable         = exynos4_clk_ip_peril_ctrl,
467                 .ctrlbit        = (1<<24),
468         }, {
469                 .name           = "csis",
470                 .devname        = "s5p-mipi-csis.0",
471                 .enable         = exynos4_clk_ip_cam_ctrl,
472                 .ctrlbit        = (1 << 4),
473         }, {
474                 .name           = "csis",
475                 .devname        = "s5p-mipi-csis.1",
476                 .enable         = exynos4_clk_ip_cam_ctrl,
477                 .ctrlbit        = (1 << 5),
478         }, {
479                 .name           = "jpeg",
480                 .id             = 0,
481                 .enable         = exynos4_clk_ip_cam_ctrl,
482                 .ctrlbit        = (1 << 6),
483         }, {
484                 .name           = "fimc",
485                 .devname        = "exynos4-fimc.0",
486                 .enable         = exynos4_clk_ip_cam_ctrl,
487                 .ctrlbit        = (1 << 0),
488         }, {
489                 .name           = "fimc",
490                 .devname        = "exynos4-fimc.1",
491                 .enable         = exynos4_clk_ip_cam_ctrl,
492                 .ctrlbit        = (1 << 1),
493         }, {
494                 .name           = "fimc",
495                 .devname        = "exynos4-fimc.2",
496                 .enable         = exynos4_clk_ip_cam_ctrl,
497                 .ctrlbit        = (1 << 2),
498         }, {
499                 .name           = "fimc",
500                 .devname        = "exynos4-fimc.3",
501                 .enable         = exynos4_clk_ip_cam_ctrl,
502                 .ctrlbit        = (1 << 3),
503         }, {
504                 .name           = "hsmmc",
505                 .devname        = "exynos4-sdhci.0",
506                 .parent         = &exynos4_clk_aclk_133.clk,
507                 .enable         = exynos4_clk_ip_fsys_ctrl,
508                 .ctrlbit        = (1 << 5),
509         }, {
510                 .name           = "hsmmc",
511                 .devname        = "exynos4-sdhci.1",
512                 .parent         = &exynos4_clk_aclk_133.clk,
513                 .enable         = exynos4_clk_ip_fsys_ctrl,
514                 .ctrlbit        = (1 << 6),
515         }, {
516                 .name           = "hsmmc",
517                 .devname        = "exynos4-sdhci.2",
518                 .parent         = &exynos4_clk_aclk_133.clk,
519                 .enable         = exynos4_clk_ip_fsys_ctrl,
520                 .ctrlbit        = (1 << 7),
521         }, {
522                 .name           = "hsmmc",
523                 .devname        = "exynos4-sdhci.3",
524                 .parent         = &exynos4_clk_aclk_133.clk,
525                 .enable         = exynos4_clk_ip_fsys_ctrl,
526                 .ctrlbit        = (1 << 8),
527         }, {
528                 .name           = "dwmmc",
529                 .parent         = &exynos4_clk_aclk_133.clk,
530                 .enable         = exynos4_clk_ip_fsys_ctrl,
531                 .ctrlbit        = (1 << 9),
532         }, {
533                 .name           = "dac",
534                 .devname        = "s5p-sdo",
535                 .enable         = exynos4_clk_ip_tv_ctrl,
536                 .ctrlbit        = (1 << 2),
537         }, {
538                 .name           = "mixer",
539                 .devname        = "s5p-mixer",
540                 .enable         = exynos4_clk_ip_tv_ctrl,
541                 .ctrlbit        = (1 << 1),
542         }, {
543                 .name           = "vp",
544                 .devname        = "s5p-mixer",
545                 .enable         = exynos4_clk_ip_tv_ctrl,
546                 .ctrlbit        = (1 << 0),
547         }, {
548                 .name           = "hdmi",
549                 .devname        = "exynos4-hdmi",
550                 .enable         = exynos4_clk_ip_tv_ctrl,
551                 .ctrlbit        = (1 << 3),
552         }, {
553                 .name           = "hdmiphy",
554                 .devname        = "exynos4-hdmi",
555                 .enable         = exynos4_clk_hdmiphy_ctrl,
556                 .ctrlbit        = (1 << 0),
557         }, {
558                 .name           = "dacphy",
559                 .devname        = "s5p-sdo",
560                 .enable         = exynos4_clk_dac_ctrl,
561                 .ctrlbit        = (1 << 0),
562         }, {
563                 .name           = "adc",
564                 .enable         = exynos4_clk_ip_peril_ctrl,
565                 .ctrlbit        = (1 << 15),
566         }, {
567                 .name           = "keypad",
568                 .enable         = exynos4_clk_ip_perir_ctrl,
569                 .ctrlbit        = (1 << 16),
570         }, {
571                 .name           = "rtc",
572                 .enable         = exynos4_clk_ip_perir_ctrl,
573                 .ctrlbit        = (1 << 15),
574         }, {
575                 .name           = "watchdog",
576                 .parent         = &exynos4_clk_aclk_100.clk,
577                 .enable         = exynos4_clk_ip_perir_ctrl,
578                 .ctrlbit        = (1 << 14),
579         }, {
580                 .name           = "usbhost",
581                 .enable         = exynos4_clk_ip_fsys_ctrl ,
582                 .ctrlbit        = (1 << 12),
583         }, {
584                 .name           = "otg",
585                 .enable         = exynos4_clk_ip_fsys_ctrl,
586                 .ctrlbit        = (1 << 13),
587         }, {
588                 .name           = "spi",
589                 .devname        = "exynos4210-spi.0",
590                 .enable         = exynos4_clk_ip_peril_ctrl,
591                 .ctrlbit        = (1 << 16),
592         }, {
593                 .name           = "spi",
594                 .devname        = "exynos4210-spi.1",
595                 .enable         = exynos4_clk_ip_peril_ctrl,
596                 .ctrlbit        = (1 << 17),
597         }, {
598                 .name           = "spi",
599                 .devname        = "exynos4210-spi.2",
600                 .enable         = exynos4_clk_ip_peril_ctrl,
601                 .ctrlbit        = (1 << 18),
602         }, {
603                 .name           = "iis",
604                 .devname        = "samsung-i2s.1",
605                 .enable         = exynos4_clk_ip_peril_ctrl,
606                 .ctrlbit        = (1 << 20),
607         }, {
608                 .name           = "iis",
609                 .devname        = "samsung-i2s.2",
610                 .enable         = exynos4_clk_ip_peril_ctrl,
611                 .ctrlbit        = (1 << 21),
612         }, {
613                 .name           = "ac97",
614                 .devname        = "samsung-ac97",
615                 .enable         = exynos4_clk_ip_peril_ctrl,
616                 .ctrlbit        = (1 << 27),
617         }, {
618                 .name           = "mfc",
619                 .devname        = "s5p-mfc",
620                 .enable         = exynos4_clk_ip_mfc_ctrl,
621                 .ctrlbit        = (1 << 0),
622         }, {
623                 .name           = "i2c",
624                 .devname        = "s3c2440-i2c.0",
625                 .parent         = &exynos4_clk_aclk_100.clk,
626                 .enable         = exynos4_clk_ip_peril_ctrl,
627                 .ctrlbit        = (1 << 6),
628         }, {
629                 .name           = "i2c",
630                 .devname        = "s3c2440-i2c.1",
631                 .parent         = &exynos4_clk_aclk_100.clk,
632                 .enable         = exynos4_clk_ip_peril_ctrl,
633                 .ctrlbit        = (1 << 7),
634         }, {
635                 .name           = "i2c",
636                 .devname        = "s3c2440-i2c.2",
637                 .parent         = &exynos4_clk_aclk_100.clk,
638                 .enable         = exynos4_clk_ip_peril_ctrl,
639                 .ctrlbit        = (1 << 8),
640         }, {
641                 .name           = "i2c",
642                 .devname        = "s3c2440-i2c.3",
643                 .parent         = &exynos4_clk_aclk_100.clk,
644                 .enable         = exynos4_clk_ip_peril_ctrl,
645                 .ctrlbit        = (1 << 9),
646         }, {
647                 .name           = "i2c",
648                 .devname        = "s3c2440-i2c.4",
649                 .parent         = &exynos4_clk_aclk_100.clk,
650                 .enable         = exynos4_clk_ip_peril_ctrl,
651                 .ctrlbit        = (1 << 10),
652         }, {
653                 .name           = "i2c",
654                 .devname        = "s3c2440-i2c.5",
655                 .parent         = &exynos4_clk_aclk_100.clk,
656                 .enable         = exynos4_clk_ip_peril_ctrl,
657                 .ctrlbit        = (1 << 11),
658         }, {
659                 .name           = "i2c",
660                 .devname        = "s3c2440-i2c.6",
661                 .parent         = &exynos4_clk_aclk_100.clk,
662                 .enable         = exynos4_clk_ip_peril_ctrl,
663                 .ctrlbit        = (1 << 12),
664         }, {
665                 .name           = "i2c",
666                 .devname        = "s3c2440-i2c.7",
667                 .parent         = &exynos4_clk_aclk_100.clk,
668                 .enable         = exynos4_clk_ip_peril_ctrl,
669                 .ctrlbit        = (1 << 13),
670         }, {
671                 .name           = "i2c",
672                 .devname        = "s3c2440-hdmiphy-i2c",
673                 .parent         = &exynos4_clk_aclk_100.clk,
674                 .enable         = exynos4_clk_ip_peril_ctrl,
675                 .ctrlbit        = (1 << 14),
676         }, {
677                 .name           = SYSMMU_CLOCK_NAME,
678                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
679                 .enable         = exynos4_clk_ip_mfc_ctrl,
680                 .ctrlbit        = (1 << 1),
681         }, {
682                 .name           = SYSMMU_CLOCK_NAME,
683                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
684                 .enable         = exynos4_clk_ip_mfc_ctrl,
685                 .ctrlbit        = (1 << 2),
686         }, {
687                 .name           = SYSMMU_CLOCK_NAME,
688                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
689                 .enable         = exynos4_clk_ip_tv_ctrl,
690                 .ctrlbit        = (1 << 4),
691         }, {
692                 .name           = SYSMMU_CLOCK_NAME,
693                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
694                 .enable         = exynos4_clk_ip_cam_ctrl,
695                 .ctrlbit        = (1 << 11),
696         }, {
697                 .name           = SYSMMU_CLOCK_NAME,
698                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
699                 .enable         = exynos4_clk_ip_image_ctrl,
700                 .ctrlbit        = (1 << 4),
701         }, {
702                 .name           = SYSMMU_CLOCK_NAME,
703                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
704                 .enable         = exynos4_clk_ip_cam_ctrl,
705                 .ctrlbit        = (1 << 7),
706         }, {
707                 .name           = SYSMMU_CLOCK_NAME,
708                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
709                 .enable         = exynos4_clk_ip_cam_ctrl,
710                 .ctrlbit        = (1 << 8),
711         }, {
712                 .name           = SYSMMU_CLOCK_NAME,
713                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
714                 .enable         = exynos4_clk_ip_cam_ctrl,
715                 .ctrlbit        = (1 << 9),
716         }, {
717                 .name           = SYSMMU_CLOCK_NAME,
718                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
719                 .enable         = exynos4_clk_ip_cam_ctrl,
720                 .ctrlbit        = (1 << 10),
721         }, {
722                 .name           = SYSMMU_CLOCK_NAME,
723                 .devname        = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
724                 .enable         = exynos4_clk_ip_lcd0_ctrl,
725                 .ctrlbit        = (1 << 4),
726         }
727 };
728
729 static struct clk exynos4_init_clocks_on[] = {
730         {
731                 .name           = "uart",
732                 .devname        = "s5pv210-uart.0",
733                 .enable         = exynos4_clk_ip_peril_ctrl,
734                 .ctrlbit        = (1 << 0),
735         }, {
736                 .name           = "uart",
737                 .devname        = "s5pv210-uart.1",
738                 .enable         = exynos4_clk_ip_peril_ctrl,
739                 .ctrlbit        = (1 << 1),
740         }, {
741                 .name           = "uart",
742                 .devname        = "s5pv210-uart.2",
743                 .enable         = exynos4_clk_ip_peril_ctrl,
744                 .ctrlbit        = (1 << 2),
745         }, {
746                 .name           = "uart",
747                 .devname        = "s5pv210-uart.3",
748                 .enable         = exynos4_clk_ip_peril_ctrl,
749                 .ctrlbit        = (1 << 3),
750         }, {
751                 .name           = "uart",
752                 .devname        = "s5pv210-uart.4",
753                 .enable         = exynos4_clk_ip_peril_ctrl,
754                 .ctrlbit        = (1 << 4),
755         }, {
756                 .name           = "uart",
757                 .devname        = "s5pv210-uart.5",
758                 .enable         = exynos4_clk_ip_peril_ctrl,
759                 .ctrlbit        = (1 << 5),
760         }
761 };
762
763 static struct clk exynos4_clk_pdma0 = {
764         .name           = "dma",
765         .devname        = "dma-pl330.0",
766         .enable         = exynos4_clk_ip_fsys_ctrl,
767         .ctrlbit        = (1 << 0),
768 };
769
770 static struct clk exynos4_clk_pdma1 = {
771         .name           = "dma",
772         .devname        = "dma-pl330.1",
773         .enable         = exynos4_clk_ip_fsys_ctrl,
774         .ctrlbit        = (1 << 1),
775 };
776
777 static struct clk exynos4_clk_mdma1 = {
778         .name           = "dma",
779         .devname        = "dma-pl330.2",
780         .enable         = exynos4_clk_ip_image_ctrl,
781         .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
782 };
783
784 static struct clk exynos4_clk_fimd0 = {
785         .name           = "fimd",
786         .devname        = "exynos4-fb.0",
787         .enable         = exynos4_clk_ip_lcd0_ctrl,
788         .ctrlbit        = (1 << 0),
789 };
790
791 struct clk *exynos4_clkset_group_list[] = {
792         [0] = &clk_ext_xtal_mux,
793         [1] = &clk_xusbxti,
794         [2] = &exynos4_clk_sclk_hdmi27m,
795         [3] = &exynos4_clk_sclk_usbphy0,
796         [4] = &exynos4_clk_sclk_usbphy1,
797         [5] = &exynos4_clk_sclk_hdmiphy,
798         [6] = &exynos4_clk_mout_mpll.clk,
799         [7] = &exynos4_clk_mout_epll.clk,
800         [8] = &exynos4_clk_sclk_vpll.clk,
801 };
802
803 struct clksrc_sources exynos4_clkset_group = {
804         .sources        = exynos4_clkset_group_list,
805         .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
806 };
807
808 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
809         [0] = &exynos4_clk_mout_mpll.clk,
810         [1] = &exynos4_clk_sclk_apll.clk,
811 };
812
813 struct clksrc_sources exynos4_clkset_mout_g2d0 = {
814         .sources        = exynos4_clkset_mout_g2d0_list,
815         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
816 };
817
818 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
819         [0] = &exynos4_clk_mout_epll.clk,
820         [1] = &exynos4_clk_sclk_vpll.clk,
821 };
822
823 struct clksrc_sources exynos4_clkset_mout_g2d1 = {
824         .sources        = exynos4_clkset_mout_g2d1_list,
825         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
826 };
827
828 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
829         [0] = &exynos4_clk_mout_mpll.clk,
830         [1] = &exynos4_clk_sclk_apll.clk,
831 };
832
833 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
834         .sources        = exynos4_clkset_mout_mfc0_list,
835         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
836 };
837
838 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
839         .clk    = {
840                 .name           = "mout_mfc0",
841         },
842         .sources = &exynos4_clkset_mout_mfc0,
843         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
844 };
845
846 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
847         [0] = &exynos4_clk_mout_epll.clk,
848         [1] = &exynos4_clk_sclk_vpll.clk,
849 };
850
851 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
852         .sources        = exynos4_clkset_mout_mfc1_list,
853         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
854 };
855
856 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
857         .clk    = {
858                 .name           = "mout_mfc1",
859         },
860         .sources = &exynos4_clkset_mout_mfc1,
861         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
862 };
863
864 static struct clk *exynos4_clkset_mout_mfc_list[] = {
865         [0] = &exynos4_clk_mout_mfc0.clk,
866         [1] = &exynos4_clk_mout_mfc1.clk,
867 };
868
869 static struct clksrc_sources exynos4_clkset_mout_mfc = {
870         .sources        = exynos4_clkset_mout_mfc_list,
871         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
872 };
873
874 static struct clk *exynos4_clkset_sclk_dac_list[] = {
875         [0] = &exynos4_clk_sclk_vpll.clk,
876         [1] = &exynos4_clk_sclk_hdmiphy,
877 };
878
879 static struct clksrc_sources exynos4_clkset_sclk_dac = {
880         .sources        = exynos4_clkset_sclk_dac_list,
881         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
882 };
883
884 static struct clksrc_clk exynos4_clk_sclk_dac = {
885         .clk            = {
886                 .name           = "sclk_dac",
887                 .enable         = exynos4_clksrc_mask_tv_ctrl,
888                 .ctrlbit        = (1 << 8),
889         },
890         .sources = &exynos4_clkset_sclk_dac,
891         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
892 };
893
894 static struct clksrc_clk exynos4_clk_sclk_pixel = {
895         .clk            = {
896                 .name           = "sclk_pixel",
897                 .parent         = &exynos4_clk_sclk_vpll.clk,
898         },
899         .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
900 };
901
902 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
903         [0] = &exynos4_clk_sclk_pixel.clk,
904         [1] = &exynos4_clk_sclk_hdmiphy,
905 };
906
907 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
908         .sources        = exynos4_clkset_sclk_hdmi_list,
909         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
910 };
911
912 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
913         .clk            = {
914                 .name           = "sclk_hdmi",
915                 .enable         = exynos4_clksrc_mask_tv_ctrl,
916                 .ctrlbit        = (1 << 0),
917         },
918         .sources = &exynos4_clkset_sclk_hdmi,
919         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
920 };
921
922 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
923         [0] = &exynos4_clk_sclk_dac.clk,
924         [1] = &exynos4_clk_sclk_hdmi.clk,
925 };
926
927 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
928         .sources        = exynos4_clkset_sclk_mixer_list,
929         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
930 };
931
932 static struct clksrc_clk exynos4_clk_sclk_mixer = {
933         .clk    = {
934                 .name           = "sclk_mixer",
935                 .enable         = exynos4_clksrc_mask_tv_ctrl,
936                 .ctrlbit        = (1 << 4),
937         },
938         .sources = &exynos4_clkset_sclk_mixer,
939         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
940 };
941
942 static struct clksrc_clk *exynos4_sclk_tv[] = {
943         &exynos4_clk_sclk_dac,
944         &exynos4_clk_sclk_pixel,
945         &exynos4_clk_sclk_hdmi,
946         &exynos4_clk_sclk_mixer,
947 };
948
949 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
950         .clk    = {
951                 .name           = "dout_mmc0",
952         },
953         .sources = &exynos4_clkset_group,
954         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
955         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
956 };
957
958 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
959         .clk    = {
960                 .name           = "dout_mmc1",
961         },
962         .sources = &exynos4_clkset_group,
963         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
964         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
965 };
966
967 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
968         .clk    = {
969                 .name           = "dout_mmc2",
970         },
971         .sources = &exynos4_clkset_group,
972         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
973         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
974 };
975
976 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
977         .clk    = {
978                 .name           = "dout_mmc3",
979         },
980         .sources = &exynos4_clkset_group,
981         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
982         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
983 };
984
985 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
986         .clk            = {
987                 .name           = "dout_mmc4",
988         },
989         .sources = &exynos4_clkset_group,
990         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
991         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
992 };
993
994 static struct clksrc_clk exynos4_clksrcs[] = {
995         {
996                 .clk    = {
997                         .name           = "sclk_pwm",
998                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
999                         .ctrlbit        = (1 << 24),
1000                 },
1001                 .sources = &exynos4_clkset_group,
1002                 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1003                 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1004         }, {
1005                 .clk    = {
1006                         .name           = "sclk_csis",
1007                         .devname        = "s5p-mipi-csis.0",
1008                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1009                         .ctrlbit        = (1 << 24),
1010                 },
1011                 .sources = &exynos4_clkset_group,
1012                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1013                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1014         }, {
1015                 .clk    = {
1016                         .name           = "sclk_csis",
1017                         .devname        = "s5p-mipi-csis.1",
1018                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1019                         .ctrlbit        = (1 << 28),
1020                 },
1021                 .sources = &exynos4_clkset_group,
1022                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1023                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1024         }, {
1025                 .clk    = {
1026                         .name           = "sclk_cam0",
1027                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1028                         .ctrlbit        = (1 << 16),
1029                 },
1030                 .sources = &exynos4_clkset_group,
1031                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1032                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1033         }, {
1034                 .clk    = {
1035                         .name           = "sclk_cam1",
1036                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1037                         .ctrlbit        = (1 << 20),
1038                 },
1039                 .sources = &exynos4_clkset_group,
1040                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1041                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1042         }, {
1043                 .clk    = {
1044                         .name           = "sclk_fimc",
1045                         .devname        = "exynos4-fimc.0",
1046                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1047                         .ctrlbit        = (1 << 0),
1048                 },
1049                 .sources = &exynos4_clkset_group,
1050                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1051                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1052         }, {
1053                 .clk    = {
1054                         .name           = "sclk_fimc",
1055                         .devname        = "exynos4-fimc.1",
1056                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1057                         .ctrlbit        = (1 << 4),
1058                 },
1059                 .sources = &exynos4_clkset_group,
1060                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1061                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1062         }, {
1063                 .clk    = {
1064                         .name           = "sclk_fimc",
1065                         .devname        = "exynos4-fimc.2",
1066                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1067                         .ctrlbit        = (1 << 8),
1068                 },
1069                 .sources = &exynos4_clkset_group,
1070                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1071                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1072         }, {
1073                 .clk    = {
1074                         .name           = "sclk_fimc",
1075                         .devname        = "exynos4-fimc.3",
1076                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1077                         .ctrlbit        = (1 << 12),
1078                 },
1079                 .sources = &exynos4_clkset_group,
1080                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1081                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1082         }, {
1083                 .clk    = {
1084                         .name           = "sclk_fimd",
1085                         .devname        = "exynos4-fb.0",
1086                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1087                         .ctrlbit        = (1 << 0),
1088                 },
1089                 .sources = &exynos4_clkset_group,
1090                 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1091                 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1092         }, {
1093                 .clk    = {
1094                         .name           = "sclk_mfc",
1095                         .devname        = "s5p-mfc",
1096                 },
1097                 .sources = &exynos4_clkset_mout_mfc,
1098                 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1099                 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1100         }, {
1101                 .clk    = {
1102                         .name           = "sclk_dwmmc",
1103                         .parent         = &exynos4_clk_dout_mmc4.clk,
1104                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1105                         .ctrlbit        = (1 << 16),
1106                 },
1107                 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1108         }
1109 };
1110
1111 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1112         .clk    = {
1113                 .name           = "uclk1",
1114                 .devname        = "exynos4210-uart.0",
1115                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1116                 .ctrlbit        = (1 << 0),
1117         },
1118         .sources = &exynos4_clkset_group,
1119         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1120         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1121 };
1122
1123 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1124         .clk    = {
1125                 .name           = "uclk1",
1126                 .devname        = "exynos4210-uart.1",
1127                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1128                 .ctrlbit        = (1 << 4),
1129         },
1130         .sources = &exynos4_clkset_group,
1131         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1132         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1133 };
1134
1135 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1136         .clk    = {
1137                 .name           = "uclk1",
1138                 .devname        = "exynos4210-uart.2",
1139                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1140                 .ctrlbit        = (1 << 8),
1141         },
1142         .sources = &exynos4_clkset_group,
1143         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1144         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1145 };
1146
1147 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1148         .clk    = {
1149                 .name           = "uclk1",
1150                 .devname        = "exynos4210-uart.3",
1151                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1152                 .ctrlbit        = (1 << 12),
1153         },
1154         .sources = &exynos4_clkset_group,
1155         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1156         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1157 };
1158
1159 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1160         .clk    = {
1161                 .name           = "sclk_mmc",
1162                 .devname        = "exynos4-sdhci.0",
1163                 .parent         = &exynos4_clk_dout_mmc0.clk,
1164                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1165                 .ctrlbit        = (1 << 0),
1166         },
1167         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1168 };
1169
1170 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1171         .clk    = {
1172                 .name           = "sclk_mmc",
1173                 .devname        = "exynos4-sdhci.1",
1174                 .parent         = &exynos4_clk_dout_mmc1.clk,
1175                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1176                 .ctrlbit        = (1 << 4),
1177         },
1178         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1179 };
1180
1181 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1182         .clk    = {
1183                 .name           = "sclk_mmc",
1184                 .devname        = "exynos4-sdhci.2",
1185                 .parent         = &exynos4_clk_dout_mmc2.clk,
1186                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1187                 .ctrlbit        = (1 << 8),
1188         },
1189         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1190 };
1191
1192 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1193         .clk    = {
1194                 .name           = "sclk_mmc",
1195                 .devname        = "exynos4-sdhci.3",
1196                 .parent         = &exynos4_clk_dout_mmc3.clk,
1197                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1198                 .ctrlbit        = (1 << 12),
1199         },
1200         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1201 };
1202
1203 static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1204         .clk    = {
1205                 .name           = "mdout_spi",
1206                 .devname        = "exynos4210-spi.0",
1207         },
1208         .sources = &exynos4_clkset_group,
1209         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1210         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1211 };
1212
1213 static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1214         .clk    = {
1215                 .name           = "mdout_spi",
1216                 .devname        = "exynos4210-spi.1",
1217         },
1218         .sources = &exynos4_clkset_group,
1219         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1220         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1221 };
1222
1223 static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1224         .clk    = {
1225                 .name           = "mdout_spi",
1226                 .devname        = "exynos4210-spi.2",
1227         },
1228         .sources = &exynos4_clkset_group,
1229         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1230         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1231 };
1232
1233 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1234         .clk    = {
1235                 .name           = "sclk_spi",
1236                 .devname        = "exynos4210-spi.0",
1237                 .parent         = &exynos4_clk_mdout_spi0.clk,
1238                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1239                 .ctrlbit        = (1 << 16),
1240         },
1241         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1242 };
1243
1244 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1245         .clk    = {
1246                 .name           = "sclk_spi",
1247                 .devname        = "exynos4210-spi.1",
1248                 .parent         = &exynos4_clk_mdout_spi1.clk,
1249                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1250                 .ctrlbit        = (1 << 20),
1251         },
1252         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1253 };
1254
1255 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1256         .clk    = {
1257                 .name           = "sclk_spi",
1258                 .devname        = "exynos4210-spi.2",
1259                 .parent         = &exynos4_clk_mdout_spi2.clk,
1260                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1261                 .ctrlbit        = (1 << 24),
1262         },
1263         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1264 };
1265
1266 /* Clock initialization code */
1267 static struct clksrc_clk *exynos4_sysclks[] = {
1268         &exynos4_clk_mout_apll,
1269         &exynos4_clk_sclk_apll,
1270         &exynos4_clk_mout_epll,
1271         &exynos4_clk_mout_mpll,
1272         &exynos4_clk_moutcore,
1273         &exynos4_clk_coreclk,
1274         &exynos4_clk_armclk,
1275         &exynos4_clk_aclk_corem0,
1276         &exynos4_clk_aclk_cores,
1277         &exynos4_clk_aclk_corem1,
1278         &exynos4_clk_periphclk,
1279         &exynos4_clk_mout_corebus,
1280         &exynos4_clk_sclk_dmc,
1281         &exynos4_clk_aclk_cored,
1282         &exynos4_clk_aclk_corep,
1283         &exynos4_clk_aclk_acp,
1284         &exynos4_clk_pclk_acp,
1285         &exynos4_clk_vpllsrc,
1286         &exynos4_clk_sclk_vpll,
1287         &exynos4_clk_aclk_200,
1288         &exynos4_clk_aclk_100,
1289         &exynos4_clk_aclk_160,
1290         &exynos4_clk_aclk_133,
1291         &exynos4_clk_dout_mmc0,
1292         &exynos4_clk_dout_mmc1,
1293         &exynos4_clk_dout_mmc2,
1294         &exynos4_clk_dout_mmc3,
1295         &exynos4_clk_dout_mmc4,
1296         &exynos4_clk_mout_mfc0,
1297         &exynos4_clk_mout_mfc1,
1298 };
1299
1300 static struct clk *exynos4_clk_cdev[] = {
1301         &exynos4_clk_pdma0,
1302         &exynos4_clk_pdma1,
1303         &exynos4_clk_mdma1,
1304         &exynos4_clk_fimd0,
1305 };
1306
1307 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1308         &exynos4_clk_sclk_uart0,
1309         &exynos4_clk_sclk_uart1,
1310         &exynos4_clk_sclk_uart2,
1311         &exynos4_clk_sclk_uart3,
1312         &exynos4_clk_sclk_mmc0,
1313         &exynos4_clk_sclk_mmc1,
1314         &exynos4_clk_sclk_mmc2,
1315         &exynos4_clk_sclk_mmc3,
1316         &exynos4_clk_sclk_spi0,
1317         &exynos4_clk_sclk_spi1,
1318         &exynos4_clk_sclk_spi2,
1319         &exynos4_clk_mdout_spi0,
1320         &exynos4_clk_mdout_spi1,
1321         &exynos4_clk_mdout_spi2,
1322 };
1323
1324 static struct clk_lookup exynos4_clk_lookup[] = {
1325         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1326         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1327         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1328         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1329         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1330         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1331         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1332         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1333         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1334         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1335         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1336         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1337         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1338         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1339         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1340 };
1341
1342 static int xtal_rate;
1343
1344 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1345 {
1346         if (soc_is_exynos4210())
1347                 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1348                                         pll_4508);
1349         else if (soc_is_exynos4212() || soc_is_exynos4412())
1350                 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1351         else
1352                 return 0;
1353 }
1354
1355 static struct clk_ops exynos4_fout_apll_ops = {
1356         .get_rate = exynos4_fout_apll_get_rate,
1357 };
1358
1359 static u32 exynos4_vpll_div[][8] = {
1360         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1361         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1362 };
1363
1364 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1365 {
1366         return clk->rate;
1367 }
1368
1369 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1370 {
1371         unsigned int vpll_con0, vpll_con1 = 0;
1372         unsigned int i;
1373
1374         /* Return if nothing changed */
1375         if (clk->rate == rate)
1376                 return 0;
1377
1378         vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1379         vpll_con0 &= ~(0x1 << 27 |                                      \
1380                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1381                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1382                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1383
1384         vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1385         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1386                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1387                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1388
1389         for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1390                 if (exynos4_vpll_div[i][0] == rate) {
1391                         vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1392                         vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1393                         vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1394                         vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1395                         vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1396                         vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1397                         vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1398                         break;
1399                 }
1400         }
1401
1402         if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1403                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1404                                 __func__);
1405                 return -EINVAL;
1406         }
1407
1408         __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1409         __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1410
1411         /* Wait for VPLL lock */
1412         while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1413                 continue;
1414
1415         clk->rate = rate;
1416         return 0;
1417 }
1418
1419 static struct clk_ops exynos4_vpll_ops = {
1420         .get_rate = exynos4_vpll_get_rate,
1421         .set_rate = exynos4_vpll_set_rate,
1422 };
1423
1424 void __init_or_cpufreq exynos4_setup_clocks(void)
1425 {
1426         struct clk *xtal_clk;
1427         unsigned long apll = 0;
1428         unsigned long mpll = 0;
1429         unsigned long epll = 0;
1430         unsigned long vpll = 0;
1431         unsigned long vpllsrc;
1432         unsigned long xtal;
1433         unsigned long armclk;
1434         unsigned long sclk_dmc;
1435         unsigned long aclk_200;
1436         unsigned long aclk_100;
1437         unsigned long aclk_160;
1438         unsigned long aclk_133;
1439         unsigned int ptr;
1440
1441         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1442
1443         xtal_clk = clk_get(NULL, "xtal");
1444         BUG_ON(IS_ERR(xtal_clk));
1445
1446         xtal = clk_get_rate(xtal_clk);
1447
1448         xtal_rate = xtal;
1449
1450         clk_put(xtal_clk);
1451
1452         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1453
1454         if (soc_is_exynos4210()) {
1455                 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1456                                         pll_4508);
1457                 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1458                                         pll_4508);
1459                 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1460                                         __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1461
1462                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1463                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1464                                         __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1465         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1466                 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1467                 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1468                 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1469                                         __raw_readl(EXYNOS4_EPLL_CON1));
1470
1471                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1472                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1473                                         __raw_readl(EXYNOS4_VPLL_CON1));
1474         } else {
1475                 /* nothing */
1476         }
1477
1478         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1479         clk_fout_mpll.rate = mpll;
1480         clk_fout_epll.rate = epll;
1481         clk_fout_vpll.ops = &exynos4_vpll_ops;
1482         clk_fout_vpll.rate = vpll;
1483
1484         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1485                         apll, mpll, epll, vpll);
1486
1487         armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1488         sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1489
1490         aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1491         aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1492         aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1493         aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1494
1495         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1496                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1497                         armclk, sclk_dmc, aclk_200,
1498                         aclk_100, aclk_160, aclk_133);
1499
1500         clk_f.rate = armclk;
1501         clk_h.rate = sclk_dmc;
1502         clk_p.rate = aclk_100;
1503
1504         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1505                 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1506 }
1507
1508 static struct clk *exynos4_clks[] __initdata = {
1509         &exynos4_clk_sclk_hdmi27m,
1510         &exynos4_clk_sclk_hdmiphy,
1511         &exynos4_clk_sclk_usbphy0,
1512         &exynos4_clk_sclk_usbphy1,
1513 };
1514
1515 #ifdef CONFIG_PM_SLEEP
1516 static int exynos4_clock_suspend(void)
1517 {
1518         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1519         return 0;
1520 }
1521
1522 static void exynos4_clock_resume(void)
1523 {
1524         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1525 }
1526
1527 #else
1528 #define exynos4_clock_suspend NULL
1529 #define exynos4_clock_resume NULL
1530 #endif
1531
1532 static struct syscore_ops exynos4_clock_syscore_ops = {
1533         .suspend        = exynos4_clock_suspend,
1534         .resume         = exynos4_clock_resume,
1535 };
1536
1537 void __init exynos4_register_clocks(void)
1538 {
1539         int ptr;
1540
1541         s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1542
1543         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1544                 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1545
1546         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1547                 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1548
1549         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1550                 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1551
1552         s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1553         s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1554
1555         s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1556         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1557                 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1558
1559         s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1560         s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1561         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1562
1563         register_syscore_ops(&exynos4_clock_syscore_ops);
1564         s3c24xx_register_clock(&dummy_apb_pclk);
1565
1566         s3c_pwmclk_init();
1567 }