Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[~shefty/rdma-dev.git] / arch / arm / mach-exynos / clock-exynos5.c
1 /*
2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3  *              http://www.samsung.com
4  *
5  * Clock support for EXYNOS5 SoCs
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/syscore_ops.h>
16
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
19 #include <plat/cpu.h>
20 #include <plat/pll.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
23 #include <plat/pm.h>
24
25 #include <mach/map.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
28
29 #include "common.h"
30
31 #ifdef CONFIG_PM_SLEEP
32 static struct sleep_save exynos5_clock_save[] = {
33         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
34         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
35         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
36         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
37         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
38         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
39         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
40         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
41         SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
42         SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
43         SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
44         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
45         SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
46         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
47         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
48         SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
49         SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
50         SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
51         SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
52         SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
53         SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
54         SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
55         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
56         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
57         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
58         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
59         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
60         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
61         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
62         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
63         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
64         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
65         SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
66         SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
67         SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
68         SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
69         SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
70         SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
71         SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
72         SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
73         SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
74         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
75         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
76         SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
77         SAVE_ITEM(EXYNOS5_EPLL_CON0),
78         SAVE_ITEM(EXYNOS5_EPLL_CON1),
79         SAVE_ITEM(EXYNOS5_EPLL_CON2),
80         SAVE_ITEM(EXYNOS5_VPLL_CON0),
81         SAVE_ITEM(EXYNOS5_VPLL_CON1),
82         SAVE_ITEM(EXYNOS5_VPLL_CON2),
83         SAVE_ITEM(EXYNOS5_PWR_CTRL1),
84         SAVE_ITEM(EXYNOS5_PWR_CTRL2),
85 };
86 #endif
87
88 static struct clk exynos5_clk_sclk_dptxphy = {
89         .name           = "sclk_dptx",
90 };
91
92 static struct clk exynos5_clk_sclk_hdmi24m = {
93         .name           = "sclk_hdmi24m",
94         .rate           = 24000000,
95 };
96
97 static struct clk exynos5_clk_sclk_hdmi27m = {
98         .name           = "sclk_hdmi27m",
99         .rate           = 27000000,
100 };
101
102 static struct clk exynos5_clk_sclk_hdmiphy = {
103         .name           = "sclk_hdmiphy",
104 };
105
106 static struct clk exynos5_clk_sclk_usbphy = {
107         .name           = "sclk_usbphy",
108         .rate           = 48000000,
109 };
110
111 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
112 {
113         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
114 }
115
116 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
117 {
118         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
119 }
120
121 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
122 {
123         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
124 }
125
126 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
127 {
128         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
129 }
130
131 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
132 {
133         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
134 }
135
136 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
137 {
138         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
139 }
140
141 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
142 {
143         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
144 }
145
146 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
147 {
148         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
149 }
150
151 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
152 {
153         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
154 }
155
156 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
157 {
158         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
159 }
160
161 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
162 {
163         return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
164 }
165
166 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
167 {
168         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
169 }
170
171 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
172 {
173         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
174 }
175
176 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
177 {
178         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
179 }
180
181 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
182 {
183         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
184 }
185
186 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
187 {
188         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
189 }
190
191 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
192 {
193         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
194 }
195
196 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
197 {
198         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
199 }
200
201 static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202 {
203         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
204 }
205
206 /* Core list of CMU_CPU side */
207
208 static struct clksrc_clk exynos5_clk_mout_apll = {
209         .clk    = {
210                 .name           = "mout_apll",
211         },
212         .sources = &clk_src_apll,
213         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
214 };
215
216 static struct clksrc_clk exynos5_clk_sclk_apll = {
217         .clk    = {
218                 .name           = "sclk_apll",
219                 .parent         = &exynos5_clk_mout_apll.clk,
220         },
221         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
222 };
223
224 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
225         .clk    = {
226                 .name           = "mout_bpll_fout",
227         },
228         .sources = &clk_src_bpll_fout,
229         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
230 };
231
232 static struct clk *exynos5_clk_src_bpll_list[] = {
233         [0] = &clk_fin_bpll,
234         [1] = &exynos5_clk_mout_bpll_fout.clk,
235 };
236
237 static struct clksrc_sources exynos5_clk_src_bpll = {
238         .sources        = exynos5_clk_src_bpll_list,
239         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
240 };
241
242 static struct clksrc_clk exynos5_clk_mout_bpll = {
243         .clk    = {
244                 .name           = "mout_bpll",
245         },
246         .sources = &exynos5_clk_src_bpll,
247         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
248 };
249
250 static struct clk *exynos5_clk_src_bpll_user_list[] = {
251         [0] = &clk_fin_mpll,
252         [1] = &exynos5_clk_mout_bpll.clk,
253 };
254
255 static struct clksrc_sources exynos5_clk_src_bpll_user = {
256         .sources        = exynos5_clk_src_bpll_user_list,
257         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
258 };
259
260 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
261         .clk    = {
262                 .name           = "mout_bpll_user",
263         },
264         .sources = &exynos5_clk_src_bpll_user,
265         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
266 };
267
268 static struct clksrc_clk exynos5_clk_mout_cpll = {
269         .clk    = {
270                 .name           = "mout_cpll",
271         },
272         .sources = &clk_src_cpll,
273         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
274 };
275
276 static struct clksrc_clk exynos5_clk_mout_epll = {
277         .clk    = {
278                 .name           = "mout_epll",
279         },
280         .sources = &clk_src_epll,
281         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
282 };
283
284 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
285         .clk    = {
286                 .name           = "mout_mpll_fout",
287         },
288         .sources = &clk_src_mpll_fout,
289         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
290 };
291
292 static struct clk *exynos5_clk_src_mpll_list[] = {
293         [0] = &clk_fin_mpll,
294         [1] = &exynos5_clk_mout_mpll_fout.clk,
295 };
296
297 static struct clksrc_sources exynos5_clk_src_mpll = {
298         .sources        = exynos5_clk_src_mpll_list,
299         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
300 };
301
302 static struct clksrc_clk exynos5_clk_mout_mpll = {
303         .clk = {
304                 .name           = "mout_mpll",
305         },
306         .sources = &exynos5_clk_src_mpll,
307         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
308 };
309
310 static struct clk *exynos_clkset_vpllsrc_list[] = {
311         [0] = &clk_fin_vpll,
312         [1] = &exynos5_clk_sclk_hdmi27m,
313 };
314
315 static struct clksrc_sources exynos5_clkset_vpllsrc = {
316         .sources        = exynos_clkset_vpllsrc_list,
317         .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
318 };
319
320 static struct clksrc_clk exynos5_clk_vpllsrc = {
321         .clk    = {
322                 .name           = "vpll_src",
323                 .enable         = exynos5_clksrc_mask_top_ctrl,
324                 .ctrlbit        = (1 << 0),
325         },
326         .sources = &exynos5_clkset_vpllsrc,
327         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
328 };
329
330 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
331         [0] = &exynos5_clk_vpllsrc.clk,
332         [1] = &clk_fout_vpll,
333 };
334
335 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
336         .sources        = exynos5_clkset_sclk_vpll_list,
337         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
338 };
339
340 static struct clksrc_clk exynos5_clk_sclk_vpll = {
341         .clk    = {
342                 .name           = "sclk_vpll",
343         },
344         .sources = &exynos5_clkset_sclk_vpll,
345         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
346 };
347
348 static struct clksrc_clk exynos5_clk_sclk_pixel = {
349         .clk    = {
350                 .name           = "sclk_pixel",
351                 .parent         = &exynos5_clk_sclk_vpll.clk,
352         },
353         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
354 };
355
356 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
357         [0] = &exynos5_clk_sclk_pixel.clk,
358         [1] = &exynos5_clk_sclk_hdmiphy,
359 };
360
361 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
362         .sources        = exynos5_clkset_sclk_hdmi_list,
363         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
364 };
365
366 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
367         .clk    = {
368                 .name           = "sclk_hdmi",
369                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
370                 .ctrlbit        = (1 << 20),
371         },
372         .sources = &exynos5_clkset_sclk_hdmi,
373         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
374 };
375
376 static struct clksrc_clk *exynos5_sclk_tv[] = {
377         &exynos5_clk_sclk_pixel,
378         &exynos5_clk_sclk_hdmi,
379 };
380
381 static struct clk *exynos5_clk_src_mpll_user_list[] = {
382         [0] = &clk_fin_mpll,
383         [1] = &exynos5_clk_mout_mpll.clk,
384 };
385
386 static struct clksrc_sources exynos5_clk_src_mpll_user = {
387         .sources        = exynos5_clk_src_mpll_user_list,
388         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
389 };
390
391 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
392         .clk    = {
393                 .name           = "mout_mpll_user",
394         },
395         .sources = &exynos5_clk_src_mpll_user,
396         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
397 };
398
399 static struct clk *exynos5_clkset_mout_cpu_list[] = {
400         [0] = &exynos5_clk_mout_apll.clk,
401         [1] = &exynos5_clk_mout_mpll.clk,
402 };
403
404 static struct clksrc_sources exynos5_clkset_mout_cpu = {
405         .sources        = exynos5_clkset_mout_cpu_list,
406         .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
407 };
408
409 static struct clksrc_clk exynos5_clk_mout_cpu = {
410         .clk    = {
411                 .name           = "mout_cpu",
412         },
413         .sources = &exynos5_clkset_mout_cpu,
414         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
415 };
416
417 static struct clksrc_clk exynos5_clk_dout_armclk = {
418         .clk    = {
419                 .name           = "dout_armclk",
420                 .parent         = &exynos5_clk_mout_cpu.clk,
421         },
422         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
423 };
424
425 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
426         .clk    = {
427                 .name           = "dout_arm2clk",
428                 .parent         = &exynos5_clk_dout_armclk.clk,
429         },
430         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
431 };
432
433 static struct clk exynos5_clk_armclk = {
434         .name           = "armclk",
435         .parent         = &exynos5_clk_dout_arm2clk.clk,
436 };
437
438 /* Core list of CMU_CDREX side */
439
440 static struct clk *exynos5_clkset_cdrex_list[] = {
441         [0] = &exynos5_clk_mout_mpll.clk,
442         [1] = &exynos5_clk_mout_bpll.clk,
443 };
444
445 static struct clksrc_sources exynos5_clkset_cdrex = {
446         .sources        = exynos5_clkset_cdrex_list,
447         .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
448 };
449
450 static struct clksrc_clk exynos5_clk_cdrex = {
451         .clk    = {
452                 .name           = "clk_cdrex",
453         },
454         .sources = &exynos5_clkset_cdrex,
455         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
456         .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
457 };
458
459 static struct clksrc_clk exynos5_clk_aclk_acp = {
460         .clk    = {
461                 .name           = "aclk_acp",
462                 .parent         = &exynos5_clk_mout_mpll.clk,
463         },
464         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
465 };
466
467 static struct clksrc_clk exynos5_clk_pclk_acp = {
468         .clk    = {
469                 .name           = "pclk_acp",
470                 .parent         = &exynos5_clk_aclk_acp.clk,
471         },
472         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
473 };
474
475 /* Core list of CMU_TOP side */
476
477 static struct clk *exynos5_clkset_aclk_top_list[] = {
478         [0] = &exynos5_clk_mout_mpll_user.clk,
479         [1] = &exynos5_clk_mout_bpll_user.clk,
480 };
481
482 static struct clksrc_sources exynos5_clkset_aclk = {
483         .sources        = exynos5_clkset_aclk_top_list,
484         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
485 };
486
487 static struct clksrc_clk exynos5_clk_aclk_400 = {
488         .clk    = {
489                 .name           = "aclk_400",
490         },
491         .sources = &exynos5_clkset_aclk,
492         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
493         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
494 };
495
496 static struct clk *exynos5_clkset_aclk_333_166_list[] = {
497         [0] = &exynos5_clk_mout_cpll.clk,
498         [1] = &exynos5_clk_mout_mpll_user.clk,
499 };
500
501 static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
502         .sources        = exynos5_clkset_aclk_333_166_list,
503         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
504 };
505
506 static struct clksrc_clk exynos5_clk_aclk_333 = {
507         .clk    = {
508                 .name           = "aclk_333",
509         },
510         .sources = &exynos5_clkset_aclk_333_166,
511         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
512         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
513 };
514
515 static struct clksrc_clk exynos5_clk_aclk_166 = {
516         .clk    = {
517                 .name           = "aclk_166",
518         },
519         .sources = &exynos5_clkset_aclk_333_166,
520         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
521         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
522 };
523
524 static struct clksrc_clk exynos5_clk_aclk_266 = {
525         .clk    = {
526                 .name           = "aclk_266",
527                 .parent         = &exynos5_clk_mout_mpll_user.clk,
528         },
529         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
530 };
531
532 static struct clksrc_clk exynos5_clk_aclk_200 = {
533         .clk    = {
534                 .name           = "aclk_200",
535         },
536         .sources = &exynos5_clkset_aclk,
537         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
538         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
539 };
540
541 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
542         .clk    = {
543                 .name           = "aclk_66_pre",
544                 .parent         = &exynos5_clk_mout_mpll_user.clk,
545         },
546         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
547 };
548
549 static struct clksrc_clk exynos5_clk_aclk_66 = {
550         .clk    = {
551                 .name           = "aclk_66",
552                 .parent         = &exynos5_clk_aclk_66_pre.clk,
553         },
554         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
555 };
556
557 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
558         .clk    = {
559                 .name           = "mout_aclk_300_gscl_mid",
560         },
561         .sources = &exynos5_clkset_aclk,
562         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
563 };
564
565 static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
566         [0] = &exynos5_clk_sclk_vpll.clk,
567         [1] = &exynos5_clk_mout_cpll.clk,
568 };
569
570 static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
571         .sources        = exynos5_clkset_aclk_300_mid1_list,
572         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
573 };
574
575 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
576         .clk    = {
577                 .name           = "mout_aclk_300_gscl_mid1",
578         },
579         .sources = &exynos5_clkset_aclk_300_gscl_mid1,
580         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
581 };
582
583 static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
584         [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
585         [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
586 };
587
588 static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
589         .sources        = exynos5_clkset_aclk_300_gscl_list,
590         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
591 };
592
593 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
594         .clk    = {
595                 .name           = "mout_aclk_300_gscl",
596         },
597         .sources = &exynos5_clkset_aclk_300_gscl,
598         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
599 };
600
601 static struct clk *exynos5_clk_src_gscl_300_list[] = {
602         [0] = &clk_ext_xtal_mux,
603         [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
604 };
605
606 static struct clksrc_sources exynos5_clk_src_gscl_300 = {
607         .sources        = exynos5_clk_src_gscl_300_list,
608         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
609 };
610
611 static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
612         .clk    = {
613                 .name           = "aclk_300_gscl",
614         },
615         .sources = &exynos5_clk_src_gscl_300,
616         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
617 };
618
619 static struct clk exynos5_init_clocks_off[] = {
620         {
621                 .name           = "timers",
622                 .parent         = &exynos5_clk_aclk_66.clk,
623                 .enable         = exynos5_clk_ip_peric_ctrl,
624                 .ctrlbit        = (1 << 24),
625         }, {
626                 .name           = "tmu_apbif",
627                 .parent         = &exynos5_clk_aclk_66.clk,
628                 .enable         = exynos5_clk_ip_peris_ctrl,
629                 .ctrlbit        = (1 << 21),
630         }, {
631                 .name           = "rtc",
632                 .parent         = &exynos5_clk_aclk_66.clk,
633                 .enable         = exynos5_clk_ip_peris_ctrl,
634                 .ctrlbit        = (1 << 20),
635         }, {
636                 .name           = "watchdog",
637                 .parent         = &exynos5_clk_aclk_66.clk,
638                 .enable         = exynos5_clk_ip_peris_ctrl,
639                 .ctrlbit        = (1 << 19),
640         }, {
641                 .name           = "biu",        /* bus interface unit clock */
642                 .devname        = "dw_mmc.0",
643                 .parent         = &exynos5_clk_aclk_200.clk,
644                 .enable         = exynos5_clk_ip_fsys_ctrl,
645                 .ctrlbit        = (1 << 12),
646         }, {
647                 .name           = "biu",
648                 .devname        = "dw_mmc.1",
649                 .parent         = &exynos5_clk_aclk_200.clk,
650                 .enable         = exynos5_clk_ip_fsys_ctrl,
651                 .ctrlbit        = (1 << 13),
652         }, {
653                 .name           = "biu",
654                 .devname        = "dw_mmc.2",
655                 .parent         = &exynos5_clk_aclk_200.clk,
656                 .enable         = exynos5_clk_ip_fsys_ctrl,
657                 .ctrlbit        = (1 << 14),
658         }, {
659                 .name           = "biu",
660                 .devname        = "dw_mmc.3",
661                 .parent         = &exynos5_clk_aclk_200.clk,
662                 .enable         = exynos5_clk_ip_fsys_ctrl,
663                 .ctrlbit        = (1 << 15),
664         }, {
665                 .name           = "sata",
666                 .devname        = "exynos5-sata",
667                 .parent         = &exynos5_clk_aclk_200.clk,
668                 .enable         = exynos5_clk_ip_fsys_ctrl,
669                 .ctrlbit        = (1 << 6),
670         }, {
671                 .name           = "sata-phy",
672                 .devname        = "exynos5-sata-phy",
673                 .parent         = &exynos5_clk_aclk_200.clk,
674                 .enable         = exynos5_clk_ip_fsys_ctrl,
675                 .ctrlbit        = (1 << 24),
676         }, {
677                 .name           = "i2c",
678                 .devname        = "exynos5-sata-phy-i2c",
679                 .parent         = &exynos5_clk_aclk_200.clk,
680                 .enable         = exynos5_clk_ip_fsys_ctrl,
681                 .ctrlbit        = (1 << 25),
682         }, {
683                 .name           = "mfc",
684                 .devname        = "s5p-mfc-v6",
685                 .enable         = exynos5_clk_ip_mfc_ctrl,
686                 .ctrlbit        = (1 << 0),
687         }, {
688                 .name           = "hdmi",
689                 .devname        = "exynos5-hdmi",
690                 .enable         = exynos5_clk_ip_disp1_ctrl,
691                 .ctrlbit        = (1 << 6),
692         }, {
693                 .name           = "hdmiphy",
694                 .devname        = "exynos5-hdmi",
695                 .enable         = exynos5_clk_hdmiphy_ctrl,
696                 .ctrlbit        = (1 << 0),
697         }, {
698                 .name           = "mixer",
699                 .devname        = "exynos5-mixer",
700                 .enable         = exynos5_clk_ip_disp1_ctrl,
701                 .ctrlbit        = (1 << 5),
702         }, {
703                 .name           = "dp",
704                 .devname        = "exynos-dp",
705                 .enable         = exynos5_clk_ip_disp1_ctrl,
706                 .ctrlbit        = (1 << 4),
707         }, {
708                 .name           = "jpeg",
709                 .enable         = exynos5_clk_ip_gen_ctrl,
710                 .ctrlbit        = (1 << 2),
711         }, {
712                 .name           = "dsim0",
713                 .enable         = exynos5_clk_ip_disp1_ctrl,
714                 .ctrlbit        = (1 << 3),
715         }, {
716                 .name           = "iis",
717                 .devname        = "samsung-i2s.1",
718                 .enable         = exynos5_clk_ip_peric_ctrl,
719                 .ctrlbit        = (1 << 20),
720         }, {
721                 .name           = "iis",
722                 .devname        = "samsung-i2s.2",
723                 .enable         = exynos5_clk_ip_peric_ctrl,
724                 .ctrlbit        = (1 << 21),
725         }, {
726                 .name           = "pcm",
727                 .devname        = "samsung-pcm.1",
728                 .enable         = exynos5_clk_ip_peric_ctrl,
729                 .ctrlbit        = (1 << 22),
730         }, {
731                 .name           = "pcm",
732                 .devname        = "samsung-pcm.2",
733                 .enable         = exynos5_clk_ip_peric_ctrl,
734                 .ctrlbit        = (1 << 23),
735         }, {
736                 .name           = "spdif",
737                 .devname        = "samsung-spdif",
738                 .enable         = exynos5_clk_ip_peric_ctrl,
739                 .ctrlbit        = (1 << 26),
740         }, {
741                 .name           = "ac97",
742                 .devname        = "samsung-ac97",
743                 .enable         = exynos5_clk_ip_peric_ctrl,
744                 .ctrlbit        = (1 << 27),
745         }, {
746                 .name           = "usbhost",
747                 .enable         = exynos5_clk_ip_fsys_ctrl ,
748                 .ctrlbit        = (1 << 18),
749         }, {
750                 .name           = "usbotg",
751                 .enable         = exynos5_clk_ip_fsys_ctrl,
752                 .ctrlbit        = (1 << 7),
753         }, {
754                 .name           = "nfcon",
755                 .enable         = exynos5_clk_ip_fsys_ctrl,
756                 .ctrlbit        = (1 << 22),
757         }, {
758                 .name           = "iop",
759                 .enable         = exynos5_clk_ip_fsys_ctrl,
760                 .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
761         }, {
762                 .name           = "core_iop",
763                 .enable         = exynos5_clk_ip_core_ctrl,
764                 .ctrlbit        = ((1 << 21) | (1 << 3)),
765         }, {
766                 .name           = "mcu_iop",
767                 .enable         = exynos5_clk_ip_fsys_ctrl,
768                 .ctrlbit        = (1 << 0),
769         }, {
770                 .name           = "i2c",
771                 .devname        = "s3c2440-i2c.0",
772                 .parent         = &exynos5_clk_aclk_66.clk,
773                 .enable         = exynos5_clk_ip_peric_ctrl,
774                 .ctrlbit        = (1 << 6),
775         }, {
776                 .name           = "i2c",
777                 .devname        = "s3c2440-i2c.1",
778                 .parent         = &exynos5_clk_aclk_66.clk,
779                 .enable         = exynos5_clk_ip_peric_ctrl,
780                 .ctrlbit        = (1 << 7),
781         }, {
782                 .name           = "i2c",
783                 .devname        = "s3c2440-i2c.2",
784                 .parent         = &exynos5_clk_aclk_66.clk,
785                 .enable         = exynos5_clk_ip_peric_ctrl,
786                 .ctrlbit        = (1 << 8),
787         }, {
788                 .name           = "i2c",
789                 .devname        = "s3c2440-i2c.3",
790                 .parent         = &exynos5_clk_aclk_66.clk,
791                 .enable         = exynos5_clk_ip_peric_ctrl,
792                 .ctrlbit        = (1 << 9),
793         }, {
794                 .name           = "i2c",
795                 .devname        = "s3c2440-i2c.4",
796                 .parent         = &exynos5_clk_aclk_66.clk,
797                 .enable         = exynos5_clk_ip_peric_ctrl,
798                 .ctrlbit        = (1 << 10),
799         }, {
800                 .name           = "i2c",
801                 .devname        = "s3c2440-i2c.5",
802                 .parent         = &exynos5_clk_aclk_66.clk,
803                 .enable         = exynos5_clk_ip_peric_ctrl,
804                 .ctrlbit        = (1 << 11),
805         }, {
806                 .name           = "i2c",
807                 .devname        = "s3c2440-i2c.6",
808                 .parent         = &exynos5_clk_aclk_66.clk,
809                 .enable         = exynos5_clk_ip_peric_ctrl,
810                 .ctrlbit        = (1 << 12),
811         }, {
812                 .name           = "i2c",
813                 .devname        = "s3c2440-i2c.7",
814                 .parent         = &exynos5_clk_aclk_66.clk,
815                 .enable         = exynos5_clk_ip_peric_ctrl,
816                 .ctrlbit        = (1 << 13),
817         }, {
818                 .name           = "i2c",
819                 .devname        = "s3c2440-hdmiphy-i2c",
820                 .parent         = &exynos5_clk_aclk_66.clk,
821                 .enable         = exynos5_clk_ip_peric_ctrl,
822                 .ctrlbit        = (1 << 14),
823         }, {
824                 .name           = "spi",
825                 .devname        = "exynos4210-spi.0",
826                 .parent         = &exynos5_clk_aclk_66.clk,
827                 .enable         = exynos5_clk_ip_peric_ctrl,
828                 .ctrlbit        = (1 << 16),
829         }, {
830                 .name           = "spi",
831                 .devname        = "exynos4210-spi.1",
832                 .parent         = &exynos5_clk_aclk_66.clk,
833                 .enable         = exynos5_clk_ip_peric_ctrl,
834                 .ctrlbit        = (1 << 17),
835         }, {
836                 .name           = "spi",
837                 .devname        = "exynos4210-spi.2",
838                 .parent         = &exynos5_clk_aclk_66.clk,
839                 .enable         = exynos5_clk_ip_peric_ctrl,
840                 .ctrlbit        = (1 << 18),
841         }, {
842                 .name           = "gscl",
843                 .devname        = "exynos-gsc.0",
844                 .enable         = exynos5_clk_ip_gscl_ctrl,
845                 .ctrlbit        = (1 << 0),
846         }, {
847                 .name           = "gscl",
848                 .devname        = "exynos-gsc.1",
849                 .enable         = exynos5_clk_ip_gscl_ctrl,
850                 .ctrlbit        = (1 << 1),
851         }, {
852                 .name           = "gscl",
853                 .devname        = "exynos-gsc.2",
854                 .enable         = exynos5_clk_ip_gscl_ctrl,
855                 .ctrlbit        = (1 << 2),
856         }, {
857                 .name           = "gscl",
858                 .devname        = "exynos-gsc.3",
859                 .enable         = exynos5_clk_ip_gscl_ctrl,
860                 .ctrlbit        = (1 << 3),
861         }, {
862                 .name           = SYSMMU_CLOCK_NAME,
863                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
864                 .enable         = &exynos5_clk_ip_mfc_ctrl,
865                 .ctrlbit        = (1 << 1),
866         }, {
867                 .name           = SYSMMU_CLOCK_NAME,
868                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
869                 .enable         = &exynos5_clk_ip_mfc_ctrl,
870                 .ctrlbit        = (1 << 2),
871         }, {
872                 .name           = SYSMMU_CLOCK_NAME,
873                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
874                 .enable         = &exynos5_clk_ip_disp1_ctrl,
875                 .ctrlbit        = (1 << 9)
876         }, {
877                 .name           = SYSMMU_CLOCK_NAME,
878                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
879                 .enable         = &exynos5_clk_ip_gen_ctrl,
880                 .ctrlbit        = (1 << 7),
881         }, {
882                 .name           = SYSMMU_CLOCK_NAME,
883                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
884                 .enable         = &exynos5_clk_ip_gen_ctrl,
885                 .ctrlbit        = (1 << 6)
886         }, {
887                 .name           = SYSMMU_CLOCK_NAME,
888                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
889                 .enable         = &exynos5_clk_ip_gscl_ctrl,
890                 .ctrlbit        = (1 << 7),
891         }, {
892                 .name           = SYSMMU_CLOCK_NAME,
893                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
894                 .enable         = &exynos5_clk_ip_gscl_ctrl,
895                 .ctrlbit        = (1 << 8),
896         }, {
897                 .name           = SYSMMU_CLOCK_NAME,
898                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
899                 .enable         = &exynos5_clk_ip_gscl_ctrl,
900                 .ctrlbit        = (1 << 9),
901         }, {
902                 .name           = SYSMMU_CLOCK_NAME,
903                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
904                 .enable         = &exynos5_clk_ip_gscl_ctrl,
905                 .ctrlbit        = (1 << 10),
906         }, {
907                 .name           = SYSMMU_CLOCK_NAME,
908                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
909                 .enable         = &exynos5_clk_ip_isp0_ctrl,
910                 .ctrlbit        = (0x3F << 8),
911         }, {
912                 .name           = SYSMMU_CLOCK_NAME2,
913                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
914                 .enable         = &exynos5_clk_ip_isp1_ctrl,
915                 .ctrlbit        = (0xF << 4),
916         }, {
917                 .name           = SYSMMU_CLOCK_NAME,
918                 .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
919                 .enable         = &exynos5_clk_ip_gscl_ctrl,
920                 .ctrlbit        = (1 << 11),
921         }, {
922                 .name           = SYSMMU_CLOCK_NAME,
923                 .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
924                 .enable         = &exynos5_clk_ip_gscl_ctrl,
925                 .ctrlbit        = (1 << 12),
926         }, {
927                 .name           = SYSMMU_CLOCK_NAME,
928                 .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
929                 .enable         = &exynos5_clk_ip_acp_ctrl,
930                 .ctrlbit        = (1 << 7)
931         }
932 };
933
934 static struct clk exynos5_init_clocks_on[] = {
935         {
936                 .name           = "uart",
937                 .devname        = "s5pv210-uart.0",
938                 .enable         = exynos5_clk_ip_peric_ctrl,
939                 .ctrlbit        = (1 << 0),
940         }, {
941                 .name           = "uart",
942                 .devname        = "s5pv210-uart.1",
943                 .enable         = exynos5_clk_ip_peric_ctrl,
944                 .ctrlbit        = (1 << 1),
945         }, {
946                 .name           = "uart",
947                 .devname        = "s5pv210-uart.2",
948                 .enable         = exynos5_clk_ip_peric_ctrl,
949                 .ctrlbit        = (1 << 2),
950         }, {
951                 .name           = "uart",
952                 .devname        = "s5pv210-uart.3",
953                 .enable         = exynos5_clk_ip_peric_ctrl,
954                 .ctrlbit        = (1 << 3),
955         }, {
956                 .name           = "uart",
957                 .devname        = "s5pv210-uart.4",
958                 .enable         = exynos5_clk_ip_peric_ctrl,
959                 .ctrlbit        = (1 << 4),
960         }, {
961                 .name           = "uart",
962                 .devname        = "s5pv210-uart.5",
963                 .enable         = exynos5_clk_ip_peric_ctrl,
964                 .ctrlbit        = (1 << 5),
965         }
966 };
967
968 static struct clk exynos5_clk_pdma0 = {
969         .name           = "dma",
970         .devname        = "dma-pl330.0",
971         .enable         = exynos5_clk_ip_fsys_ctrl,
972         .ctrlbit        = (1 << 1),
973 };
974
975 static struct clk exynos5_clk_pdma1 = {
976         .name           = "dma",
977         .devname        = "dma-pl330.1",
978         .enable         = exynos5_clk_ip_fsys_ctrl,
979         .ctrlbit        = (1 << 2),
980 };
981
982 static struct clk exynos5_clk_mdma1 = {
983         .name           = "dma",
984         .devname        = "dma-pl330.2",
985         .enable         = exynos5_clk_ip_gen_ctrl,
986         .ctrlbit        = (1 << 4),
987 };
988
989 static struct clk exynos5_clk_fimd1 = {
990         .name           = "fimd",
991         .devname        = "exynos5-fb.1",
992         .enable         = exynos5_clk_ip_disp1_ctrl,
993         .ctrlbit        = (1 << 0),
994 };
995
996 static struct clk *exynos5_clkset_group_list[] = {
997         [0] = &clk_ext_xtal_mux,
998         [1] = NULL,
999         [2] = &exynos5_clk_sclk_hdmi24m,
1000         [3] = &exynos5_clk_sclk_dptxphy,
1001         [4] = &exynos5_clk_sclk_usbphy,
1002         [5] = &exynos5_clk_sclk_hdmiphy,
1003         [6] = &exynos5_clk_mout_mpll_user.clk,
1004         [7] = &exynos5_clk_mout_epll.clk,
1005         [8] = &exynos5_clk_sclk_vpll.clk,
1006         [9] = &exynos5_clk_mout_cpll.clk,
1007 };
1008
1009 static struct clksrc_sources exynos5_clkset_group = {
1010         .sources        = exynos5_clkset_group_list,
1011         .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
1012 };
1013
1014 /* Possible clock sources for aclk_266_gscl_sub Mux */
1015 static struct clk *clk_src_gscl_266_list[] = {
1016         [0] = &clk_ext_xtal_mux,
1017         [1] = &exynos5_clk_aclk_266.clk,
1018 };
1019
1020 static struct clksrc_sources clk_src_gscl_266 = {
1021         .sources        = clk_src_gscl_266_list,
1022         .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
1023 };
1024
1025 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
1026         .clk            = {
1027                 .name           = "dout_mmc0",
1028         },
1029         .sources = &exynos5_clkset_group,
1030         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1031         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1032 };
1033
1034 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1035         .clk            = {
1036                 .name           = "dout_mmc1",
1037         },
1038         .sources = &exynos5_clkset_group,
1039         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1040         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1041 };
1042
1043 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1044         .clk            = {
1045                 .name           = "dout_mmc2",
1046         },
1047         .sources = &exynos5_clkset_group,
1048         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1049         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1050 };
1051
1052 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1053         .clk            = {
1054                 .name           = "dout_mmc3",
1055         },
1056         .sources = &exynos5_clkset_group,
1057         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1058         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1059 };
1060
1061 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1062         .clk            = {
1063                 .name           = "dout_mmc4",
1064         },
1065         .sources = &exynos5_clkset_group,
1066         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1067         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1068 };
1069
1070 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1071         .clk    = {
1072                 .name           = "uclk1",
1073                 .devname        = "exynos4210-uart.0",
1074                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1075                 .ctrlbit        = (1 << 0),
1076         },
1077         .sources = &exynos5_clkset_group,
1078         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1079         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1080 };
1081
1082 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1083         .clk    = {
1084                 .name           = "uclk1",
1085                 .devname        = "exynos4210-uart.1",
1086                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1087                 .ctrlbit        = (1 << 4),
1088         },
1089         .sources = &exynos5_clkset_group,
1090         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1091         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1092 };
1093
1094 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1095         .clk    = {
1096                 .name           = "uclk1",
1097                 .devname        = "exynos4210-uart.2",
1098                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1099                 .ctrlbit        = (1 << 8),
1100         },
1101         .sources = &exynos5_clkset_group,
1102         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1103         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1104 };
1105
1106 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1107         .clk    = {
1108                 .name           = "uclk1",
1109                 .devname        = "exynos4210-uart.3",
1110                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1111                 .ctrlbit        = (1 << 12),
1112         },
1113         .sources = &exynos5_clkset_group,
1114         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1115         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1116 };
1117
1118 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1119         .clk    = {
1120                 .name           = "ciu",        /* card interface unit clock */
1121                 .devname        = "dw_mmc.0",
1122                 .parent         = &exynos5_clk_dout_mmc0.clk,
1123                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1124                 .ctrlbit        = (1 << 0),
1125         },
1126         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1127 };
1128
1129 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1130         .clk    = {
1131                 .name           = "ciu",
1132                 .devname        = "dw_mmc.1",
1133                 .parent         = &exynos5_clk_dout_mmc1.clk,
1134                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1135                 .ctrlbit        = (1 << 4),
1136         },
1137         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1138 };
1139
1140 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1141         .clk    = {
1142                 .name           = "ciu",
1143                 .devname        = "dw_mmc.2",
1144                 .parent         = &exynos5_clk_dout_mmc2.clk,
1145                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1146                 .ctrlbit        = (1 << 8),
1147         },
1148         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1149 };
1150
1151 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1152         .clk    = {
1153                 .name           = "ciu",
1154                 .devname        = "dw_mmc.3",
1155                 .parent         = &exynos5_clk_dout_mmc3.clk,
1156                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1157                 .ctrlbit        = (1 << 12),
1158         },
1159         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1160 };
1161
1162 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1163         .clk    = {
1164                 .name           = "mdout_spi",
1165                 .devname        = "exynos4210-spi.0",
1166         },
1167         .sources = &exynos5_clkset_group,
1168         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1169         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1170 };
1171
1172 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1173         .clk    = {
1174                 .name           = "mdout_spi",
1175                 .devname        = "exynos4210-spi.1",
1176         },
1177         .sources = &exynos5_clkset_group,
1178         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1179         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1180 };
1181
1182 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1183         .clk    = {
1184                 .name           = "mdout_spi",
1185                 .devname        = "exynos4210-spi.2",
1186         },
1187         .sources = &exynos5_clkset_group,
1188         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1189         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1190 };
1191
1192 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1193         .clk    = {
1194                 .name           = "sclk_spi",
1195                 .devname        = "exynos4210-spi.0",
1196                 .parent         = &exynos5_clk_mdout_spi0.clk,
1197                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1198                 .ctrlbit        = (1 << 16),
1199         },
1200         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1201 };
1202
1203 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1204         .clk    = {
1205                 .name           = "sclk_spi",
1206                 .devname        = "exynos4210-spi.1",
1207                 .parent         = &exynos5_clk_mdout_spi1.clk,
1208                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1209                 .ctrlbit        = (1 << 20),
1210         },
1211         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1212 };
1213
1214 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1215         .clk    = {
1216                 .name           = "sclk_spi",
1217                 .devname        = "exynos4210-spi.2",
1218                 .parent         = &exynos5_clk_mdout_spi2.clk,
1219                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1220                 .ctrlbit        = (1 << 24),
1221         },
1222         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1223 };
1224
1225 static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1226         .clk    = {
1227                 .name           = "sclk_fimd",
1228                 .devname        = "exynos5-fb.1",
1229                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
1230                 .ctrlbit        = (1 << 0),
1231         },
1232         .sources = &exynos5_clkset_group,
1233         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1234         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1235 };
1236
1237 static struct clksrc_clk exynos5_clksrcs[] = {
1238         {
1239                 .clk    = {
1240                         .name           = "aclk_266_gscl",
1241                 },
1242                 .sources = &clk_src_gscl_266,
1243                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1244         }, {
1245                 .clk    = {
1246                         .name           = "sclk_g3d",
1247                         .devname        = "mali-t604.0",
1248                         .enable         = exynos5_clk_block_ctrl,
1249                         .ctrlbit        = (1 << 1),
1250                 },
1251                 .sources = &exynos5_clkset_aclk,
1252                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1253                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1254         }, {
1255                 .clk    = {
1256                         .name           = "sclk_sata",
1257                         .devname        = "exynos5-sata",
1258                         .enable         = exynos5_clksrc_mask_fsys_ctrl,
1259                         .ctrlbit        = (1 << 24),
1260                 },
1261                 .sources = &exynos5_clkset_aclk,
1262                 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
1263                 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
1264         }, {
1265                 .clk    = {
1266                         .name           = "sclk_gscl_wrap",
1267                         .devname        = "s5p-mipi-csis.0",
1268                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1269                         .ctrlbit        = (1 << 24),
1270                 },
1271                 .sources = &exynos5_clkset_group,
1272                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1273                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1274         }, {
1275                 .clk    = {
1276                         .name           = "sclk_gscl_wrap",
1277                         .devname        = "s5p-mipi-csis.1",
1278                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1279                         .ctrlbit        = (1 << 28),
1280                 },
1281                 .sources = &exynos5_clkset_group,
1282                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1283                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1284         }, {
1285                 .clk    = {
1286                         .name           = "sclk_cam0",
1287                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1288                         .ctrlbit        = (1 << 16),
1289                 },
1290                 .sources = &exynos5_clkset_group,
1291                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1292                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1293         }, {
1294                 .clk    = {
1295                         .name           = "sclk_cam1",
1296                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1297                         .ctrlbit        = (1 << 20),
1298                 },
1299                 .sources = &exynos5_clkset_group,
1300                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1301                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1302         }, {
1303                 .clk    = {
1304                         .name           = "sclk_jpeg",
1305                         .parent         = &exynos5_clk_mout_cpll.clk,
1306                 },
1307                 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1308         },
1309 };
1310
1311 /* Clock initialization code */
1312 static struct clksrc_clk *exynos5_sysclks[] = {
1313         &exynos5_clk_mout_apll,
1314         &exynos5_clk_sclk_apll,
1315         &exynos5_clk_mout_bpll,
1316         &exynos5_clk_mout_bpll_fout,
1317         &exynos5_clk_mout_bpll_user,
1318         &exynos5_clk_mout_cpll,
1319         &exynos5_clk_mout_epll,
1320         &exynos5_clk_mout_mpll,
1321         &exynos5_clk_mout_mpll_fout,
1322         &exynos5_clk_mout_mpll_user,
1323         &exynos5_clk_vpllsrc,
1324         &exynos5_clk_sclk_vpll,
1325         &exynos5_clk_mout_cpu,
1326         &exynos5_clk_dout_armclk,
1327         &exynos5_clk_dout_arm2clk,
1328         &exynos5_clk_cdrex,
1329         &exynos5_clk_aclk_400,
1330         &exynos5_clk_aclk_333,
1331         &exynos5_clk_aclk_266,
1332         &exynos5_clk_aclk_200,
1333         &exynos5_clk_aclk_166,
1334         &exynos5_clk_aclk_300_gscl,
1335         &exynos5_clk_mout_aclk_300_gscl,
1336         &exynos5_clk_mout_aclk_300_gscl_mid,
1337         &exynos5_clk_mout_aclk_300_gscl_mid1,
1338         &exynos5_clk_aclk_66_pre,
1339         &exynos5_clk_aclk_66,
1340         &exynos5_clk_dout_mmc0,
1341         &exynos5_clk_dout_mmc1,
1342         &exynos5_clk_dout_mmc2,
1343         &exynos5_clk_dout_mmc3,
1344         &exynos5_clk_dout_mmc4,
1345         &exynos5_clk_aclk_acp,
1346         &exynos5_clk_pclk_acp,
1347         &exynos5_clk_sclk_spi0,
1348         &exynos5_clk_sclk_spi1,
1349         &exynos5_clk_sclk_spi2,
1350         &exynos5_clk_mdout_spi0,
1351         &exynos5_clk_mdout_spi1,
1352         &exynos5_clk_mdout_spi2,
1353         &exynos5_clk_sclk_fimd1,
1354 };
1355
1356 static struct clk *exynos5_clk_cdev[] = {
1357         &exynos5_clk_pdma0,
1358         &exynos5_clk_pdma1,
1359         &exynos5_clk_mdma1,
1360         &exynos5_clk_fimd1,
1361 };
1362
1363 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1364         &exynos5_clk_sclk_uart0,
1365         &exynos5_clk_sclk_uart1,
1366         &exynos5_clk_sclk_uart2,
1367         &exynos5_clk_sclk_uart3,
1368         &exynos5_clk_sclk_mmc0,
1369         &exynos5_clk_sclk_mmc1,
1370         &exynos5_clk_sclk_mmc2,
1371         &exynos5_clk_sclk_mmc3,
1372 };
1373
1374 static struct clk_lookup exynos5_clk_lookup[] = {
1375         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1376         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1377         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1378         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1379         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1380         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1381         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1382         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1383         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1384         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1385         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1386         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1387         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1388         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1389         CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1390 };
1391
1392 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1393 {
1394         return clk->rate;
1395 }
1396
1397 static struct clk *exynos5_clks[] __initdata = {
1398         &exynos5_clk_sclk_hdmi27m,
1399         &exynos5_clk_sclk_hdmiphy,
1400         &clk_fout_bpll,
1401         &clk_fout_bpll_div2,
1402         &clk_fout_cpll,
1403         &clk_fout_mpll_div2,
1404         &exynos5_clk_armclk,
1405 };
1406
1407 static u32 epll_div[][6] = {
1408         { 192000000, 0, 48, 3, 1, 0 },
1409         { 180000000, 0, 45, 3, 1, 0 },
1410         {  73728000, 1, 73, 3, 3, 47710 },
1411         {  67737600, 1, 90, 4, 3, 20762 },
1412         {  49152000, 0, 49, 3, 3, 9961 },
1413         {  45158400, 0, 45, 3, 3, 10381 },
1414         { 180633600, 0, 45, 3, 1, 10381 },
1415 };
1416
1417 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1418 {
1419         unsigned int epll_con, epll_con_k;
1420         unsigned int i;
1421         unsigned int tmp;
1422         unsigned int epll_rate;
1423         unsigned int locktime;
1424         unsigned int lockcnt;
1425
1426         /* Return if nothing changed */
1427         if (clk->rate == rate)
1428                 return 0;
1429
1430         if (clk->parent)
1431                 epll_rate = clk_get_rate(clk->parent);
1432         else
1433                 epll_rate = clk_ext_xtal_mux.rate;
1434
1435         if (epll_rate != 24000000) {
1436                 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1437                 return -EINVAL;
1438         }
1439
1440         epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1441         epll_con &= ~(0x1 << 27 | \
1442                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
1443                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1444                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1445
1446         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1447                 if (epll_div[i][0] == rate) {
1448                         epll_con_k = epll_div[i][5] << 0;
1449                         epll_con |= epll_div[i][1] << 27;
1450                         epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1451                         epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1452                         epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1453                         break;
1454                 }
1455         }
1456
1457         if (i == ARRAY_SIZE(epll_div)) {
1458                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1459                                 __func__);
1460                 return -EINVAL;
1461         }
1462
1463         epll_rate /= 1000000;
1464
1465         /* 3000 max_cycls : specification data */
1466         locktime = 3000 / epll_rate * epll_div[i][3];
1467         lockcnt = locktime * 10000 / (10000 / epll_rate);
1468
1469         __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1470
1471         __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1472         __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1473
1474         do {
1475                 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1476         } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1477
1478         clk->rate = rate;
1479
1480         return 0;
1481 }
1482
1483 static struct clk_ops exynos5_epll_ops = {
1484         .get_rate = exynos5_epll_get_rate,
1485         .set_rate = exynos5_epll_set_rate,
1486 };
1487
1488 static int xtal_rate;
1489
1490 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1491 {
1492         return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1493 }
1494
1495 static struct clk_ops exynos5_fout_apll_ops = {
1496         .get_rate = exynos5_fout_apll_get_rate,
1497 };
1498
1499 #ifdef CONFIG_PM
1500 static int exynos5_clock_suspend(void)
1501 {
1502         s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1503
1504         return 0;
1505 }
1506
1507 static void exynos5_clock_resume(void)
1508 {
1509         s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1510 }
1511 #else
1512 #define exynos5_clock_suspend NULL
1513 #define exynos5_clock_resume NULL
1514 #endif
1515
1516 static struct syscore_ops exynos5_clock_syscore_ops = {
1517         .suspend        = exynos5_clock_suspend,
1518         .resume         = exynos5_clock_resume,
1519 };
1520
1521 void __init_or_cpufreq exynos5_setup_clocks(void)
1522 {
1523         struct clk *xtal_clk;
1524         unsigned long apll;
1525         unsigned long bpll;
1526         unsigned long cpll;
1527         unsigned long mpll;
1528         unsigned long epll;
1529         unsigned long vpll;
1530         unsigned long vpllsrc;
1531         unsigned long xtal;
1532         unsigned long armclk;
1533         unsigned long mout_cdrex;
1534         unsigned long aclk_400;
1535         unsigned long aclk_333;
1536         unsigned long aclk_266;
1537         unsigned long aclk_200;
1538         unsigned long aclk_166;
1539         unsigned long aclk_66;
1540         unsigned int ptr;
1541
1542         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1543
1544         xtal_clk = clk_get(NULL, "xtal");
1545         BUG_ON(IS_ERR(xtal_clk));
1546
1547         xtal = clk_get_rate(xtal_clk);
1548
1549         xtal_rate = xtal;
1550
1551         clk_put(xtal_clk);
1552
1553         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1554
1555         apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1556         bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1557         cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1558         mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1559         epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1560                         __raw_readl(EXYNOS5_EPLL_CON1));
1561
1562         vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1563         vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1564                         __raw_readl(EXYNOS5_VPLL_CON1));
1565
1566         clk_fout_apll.ops = &exynos5_fout_apll_ops;
1567         clk_fout_bpll.rate = bpll;
1568         clk_fout_bpll_div2.rate = bpll >> 1;
1569         clk_fout_cpll.rate = cpll;
1570         clk_fout_mpll.rate = mpll;
1571         clk_fout_mpll_div2.rate = mpll >> 1;
1572         clk_fout_epll.rate = epll;
1573         clk_fout_vpll.rate = vpll;
1574
1575         printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1576                         "M=%ld, E=%ld V=%ld",
1577                         apll, bpll, cpll, mpll, epll, vpll);
1578
1579         armclk = clk_get_rate(&exynos5_clk_armclk);
1580         mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1581
1582         aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1583         aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1584         aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1585         aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1586         aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1587         aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1588
1589         printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1590                         "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1591                         "ACLK166=%ld, ACLK66=%ld\n",
1592                         armclk, mout_cdrex, aclk_400,
1593                         aclk_333, aclk_266, aclk_200,
1594                         aclk_166, aclk_66);
1595
1596
1597         clk_fout_epll.ops = &exynos5_epll_ops;
1598
1599         if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1600                 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1601                                 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1602
1603         clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1604         clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1605
1606         clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1607         clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1608
1609         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1610                 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1611 }
1612
1613 void __init exynos5_register_clocks(void)
1614 {
1615         int ptr;
1616
1617         s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1618
1619         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1620                 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1621
1622         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1623                 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1624
1625         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1626                 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1627
1628         s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1629         s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1630
1631         s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1632         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1633                 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1634
1635         s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1636         s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1637         clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1638
1639         register_syscore_ops(&exynos5_clock_syscore_ops);
1640         s3c_pwmclk_init();
1641 }