]> git.openfabrics.org - ~shefty/rdma-dev.git/blob - arch/arm/mach-exynos/common.c
647c8434610c724820f86b387d4b5afe8753d293
[~shefty/rdma-dev.git] / arch / arm / mach-exynos / common.c
1 /*
2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3  *              http://www.samsung.com
4  *
5  * Common Codes for EXYNOS
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/io.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/sched.h>
19 #include <linux/serial_core.h>
20
21 #include <asm/proc-fns.h>
22 #include <asm/exception.h>
23 #include <asm/hardware/cache-l2x0.h>
24 #include <asm/hardware/gic.h>
25 #include <asm/mach/map.h>
26 #include <asm/mach/irq.h>
27
28 #include <mach/regs-irq.h>
29 #include <mach/regs-pmu.h>
30 #include <mach/regs-gpio.h>
31
32 #include <plat/cpu.h>
33 #include <plat/clock.h>
34 #include <plat/devs.h>
35 #include <plat/pm.h>
36 #include <plat/sdhci.h>
37 #include <plat/gpio-cfg.h>
38 #include <plat/adc-core.h>
39 #include <plat/fb-core.h>
40 #include <plat/fimc-core.h>
41 #include <plat/iic-core.h>
42 #include <plat/tv-core.h>
43 #include <plat/regs-serial.h>
44
45 #include "common.h"
46
47 static const char name_exynos4210[] = "EXYNOS4210";
48 static const char name_exynos4212[] = "EXYNOS4212";
49 static const char name_exynos4412[] = "EXYNOS4412";
50
51 static struct cpu_table cpu_ids[] __initdata = {
52         {
53                 .idcode         = EXYNOS4210_CPU_ID,
54                 .idmask         = EXYNOS4_CPU_MASK,
55                 .map_io         = exynos4_map_io,
56                 .init_clocks    = exynos4_init_clocks,
57                 .init_uarts     = exynos4_init_uarts,
58                 .init           = exynos_init,
59                 .name           = name_exynos4210,
60         }, {
61                 .idcode         = EXYNOS4212_CPU_ID,
62                 .idmask         = EXYNOS4_CPU_MASK,
63                 .map_io         = exynos4_map_io,
64                 .init_clocks    = exynos4_init_clocks,
65                 .init_uarts     = exynos4_init_uarts,
66                 .init           = exynos_init,
67                 .name           = name_exynos4212,
68         }, {
69                 .idcode         = EXYNOS4412_CPU_ID,
70                 .idmask         = EXYNOS4_CPU_MASK,
71                 .map_io         = exynos4_map_io,
72                 .init_clocks    = exynos4_init_clocks,
73                 .init_uarts     = exynos4_init_uarts,
74                 .init           = exynos_init,
75                 .name           = name_exynos4412,
76         },
77 };
78
79 /* Initial IO mappings */
80
81 static struct map_desc exynos_iodesc[] __initdata = {
82         {
83                 .virtual        = (unsigned long)S5P_VA_CHIPID,
84                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
85                 .length         = SZ_4K,
86                 .type           = MT_DEVICE,
87         }, {
88                 .virtual        = (unsigned long)S3C_VA_SYS,
89                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
90                 .length         = SZ_64K,
91                 .type           = MT_DEVICE,
92         }, {
93                 .virtual        = (unsigned long)S3C_VA_TIMER,
94                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
95                 .length         = SZ_16K,
96                 .type           = MT_DEVICE,
97         }, {
98                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
99                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
100                 .length         = SZ_4K,
101                 .type           = MT_DEVICE,
102         }, {
103                 .virtual        = (unsigned long)S5P_VA_SROMC,
104                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
105                 .length         = SZ_4K,
106                 .type           = MT_DEVICE,
107         }, {
108                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
109                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
110                 .length         = SZ_4K,
111                 .type           = MT_DEVICE,
112         }, {
113                 .virtual        = (unsigned long)S5P_VA_PMU,
114                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
115                 .length         = SZ_64K,
116                 .type           = MT_DEVICE,
117         }, {
118                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
119                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
120                 .length         = SZ_4K,
121                 .type           = MT_DEVICE,
122         }, {
123                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
124                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
125                 .length         = SZ_64K,
126                 .type           = MT_DEVICE,
127         }, {
128                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
129                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
130                 .length         = SZ_64K,
131                 .type           = MT_DEVICE,
132         }, {
133                 .virtual        = (unsigned long)S3C_VA_UART,
134                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
135                 .length         = SZ_512K,
136                 .type           = MT_DEVICE,
137         },
138 };
139
140 static struct map_desc exynos4_iodesc[] __initdata = {
141         {
142                 .virtual        = (unsigned long)S5P_VA_CMU,
143                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
144                 .length         = SZ_128K,
145                 .type           = MT_DEVICE,
146         }, {
147                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
148                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
149                 .length         = SZ_8K,
150                 .type           = MT_DEVICE,
151         }, {
152                 .virtual        = (unsigned long)S5P_VA_L2CC,
153                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
154                 .length         = SZ_4K,
155                 .type           = MT_DEVICE,
156         }, {
157                 .virtual        = (unsigned long)S5P_VA_GPIO1,
158                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
159                 .length         = SZ_4K,
160                 .type           = MT_DEVICE,
161         }, {
162                 .virtual        = (unsigned long)S5P_VA_GPIO2,
163                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
164                 .length         = SZ_4K,
165                 .type           = MT_DEVICE,
166         }, {
167                 .virtual        = (unsigned long)S5P_VA_GPIO3,
168                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
169                 .length         = SZ_256,
170                 .type           = MT_DEVICE,
171         }, {
172                 .virtual        = (unsigned long)S5P_VA_DMC0,
173                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
174                 .length         = SZ_4K,
175                 .type           = MT_DEVICE,
176         }, {
177                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
178                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
179                 .length         = SZ_4K,
180                 .type           = MT_DEVICE,
181         },
182 };
183
184 static struct map_desc exynos4_iodesc0[] __initdata = {
185         {
186                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
187                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
188                 .length         = SZ_4K,
189                 .type           = MT_DEVICE,
190         },
191 };
192
193 static struct map_desc exynos4_iodesc1[] __initdata = {
194         {
195                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
196                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
197                 .length         = SZ_4K,
198                 .type           = MT_DEVICE,
199         },
200 };
201
202 static void exynos_idle(void)
203 {
204         if (!need_resched())
205                 cpu_do_idle();
206
207         local_irq_enable();
208 }
209
210 void exynos4_restart(char mode, const char *cmd)
211 {
212         __raw_writel(0x1, S5P_SWRESET);
213 }
214
215 /*
216  * exynos_map_io
217  *
218  * register the standard cpu IO areas
219  */
220
221 void __init exynos_init_io(struct map_desc *mach_desc, int size)
222 {
223         /* initialize the io descriptors we need for initialization */
224         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
225         if (mach_desc)
226                 iotable_init(mach_desc, size);
227
228         /* detect cpu id and rev. */
229         s5p_init_cpu(S5P_VA_CHIPID);
230
231         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
232 }
233
234 void __init exynos4_map_io(void)
235 {
236         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
237
238         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
239                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
240         else
241                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
242
243         /* initialize device information early */
244         exynos4_default_sdhci0();
245         exynos4_default_sdhci1();
246         exynos4_default_sdhci2();
247         exynos4_default_sdhci3();
248
249         s3c_adc_setname("samsung-adc-v3");
250
251         s3c_fimc_setname(0, "exynos4-fimc");
252         s3c_fimc_setname(1, "exynos4-fimc");
253         s3c_fimc_setname(2, "exynos4-fimc");
254         s3c_fimc_setname(3, "exynos4-fimc");
255
256         /* The I2C bus controllers are directly compatible with s3c2440 */
257         s3c_i2c0_setname("s3c2440-i2c");
258         s3c_i2c1_setname("s3c2440-i2c");
259         s3c_i2c2_setname("s3c2440-i2c");
260
261         s5p_fb_setname(0, "exynos4-fb");
262         s5p_hdmi_setname("exynos4-hdmi");
263 }
264
265 void __init exynos4_init_clocks(int xtal)
266 {
267         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
268
269         s3c24xx_register_baseclocks(xtal);
270         s5p_register_clocks(xtal);
271
272         if (soc_is_exynos4210())
273                 exynos4210_register_clocks();
274         else if (soc_is_exynos4212() || soc_is_exynos4412())
275                 exynos4212_register_clocks();
276
277         exynos4_register_clocks();
278         exynos4_setup_clocks();
279 }
280
281 #define COMBINER_ENABLE_SET     0x0
282 #define COMBINER_ENABLE_CLEAR   0x4
283 #define COMBINER_INT_STATUS     0xC
284
285 static DEFINE_SPINLOCK(irq_controller_lock);
286
287 struct combiner_chip_data {
288         unsigned int irq_offset;
289         unsigned int irq_mask;
290         void __iomem *base;
291 };
292
293 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
294
295 static inline void __iomem *combiner_base(struct irq_data *data)
296 {
297         struct combiner_chip_data *combiner_data =
298                 irq_data_get_irq_chip_data(data);
299
300         return combiner_data->base;
301 }
302
303 static void combiner_mask_irq(struct irq_data *data)
304 {
305         u32 mask = 1 << (data->irq % 32);
306
307         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
308 }
309
310 static void combiner_unmask_irq(struct irq_data *data)
311 {
312         u32 mask = 1 << (data->irq % 32);
313
314         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
315 }
316
317 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
318 {
319         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
320         struct irq_chip *chip = irq_get_chip(irq);
321         unsigned int cascade_irq, combiner_irq;
322         unsigned long status;
323
324         chained_irq_enter(chip, desc);
325
326         spin_lock(&irq_controller_lock);
327         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
328         spin_unlock(&irq_controller_lock);
329         status &= chip_data->irq_mask;
330
331         if (status == 0)
332                 goto out;
333
334         combiner_irq = __ffs(status);
335
336         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
337         if (unlikely(cascade_irq >= NR_IRQS))
338                 do_bad_IRQ(cascade_irq, desc);
339         else
340                 generic_handle_irq(cascade_irq);
341
342  out:
343         chained_irq_exit(chip, desc);
344 }
345
346 static struct irq_chip combiner_chip = {
347         .name           = "COMBINER",
348         .irq_mask       = combiner_mask_irq,
349         .irq_unmask     = combiner_unmask_irq,
350 };
351
352 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
353 {
354         if (combiner_nr >= MAX_COMBINER_NR)
355                 BUG();
356         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
357                 BUG();
358         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
359 }
360
361 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
362                           unsigned int irq_start)
363 {
364         unsigned int i;
365
366         if (combiner_nr >= MAX_COMBINER_NR)
367                 BUG();
368
369         combiner_data[combiner_nr].base = base;
370         combiner_data[combiner_nr].irq_offset = irq_start;
371         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
372
373         /* Disable all interrupts */
374
375         __raw_writel(combiner_data[combiner_nr].irq_mask,
376                      base + COMBINER_ENABLE_CLEAR);
377
378         /* Setup the Linux IRQ subsystem */
379
380         for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
381                                 + MAX_IRQ_IN_COMBINER; i++) {
382                 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
383                 irq_set_chip_data(i, &combiner_data[combiner_nr]);
384                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
385         }
386 }
387
388 void __init exynos4_init_irq(void)
389 {
390         int irq;
391         unsigned int gic_bank_offset;
392
393         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
394
395         gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
396
397         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
398
399                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
400                                 COMBINER_IRQ(irq, 0));
401                 combiner_cascade_irq(irq, IRQ_SPI(irq));
402         }
403
404         /*
405          * The parameters of s5p_init_irq() are for VIC init.
406          * Theses parameters should be NULL and 0 because EXYNOS4
407          * uses GIC instead of VIC.
408          */
409         s5p_init_irq(NULL, 0);
410 }
411
412 struct bus_type exynos4_subsys = {
413         .name           = "exynos4-core",
414         .dev_name       = "exynos4-core",
415 };
416
417 static struct device exynos4_dev = {
418         .bus    = &exynos4_subsys,
419 };
420
421 static int __init exynos4_core_init(void)
422 {
423         return subsys_system_register(&exynos4_subsys, NULL);
424 }
425 core_initcall(exynos4_core_init);
426
427 #ifdef CONFIG_CACHE_L2X0
428 static int __init exynos4_l2x0_cache_init(void)
429 {
430         /* TAG, Data Latency Control: 2cycle */
431         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
432
433         if (soc_is_exynos4210())
434                 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
435         else if (soc_is_exynos4212() || soc_is_exynos4412())
436                 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
437
438         /* L2X0 Prefetch Control */
439         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
440
441         /* L2X0 Power Control */
442         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
443                      S5P_VA_L2CC + L2X0_POWER_CTRL);
444
445         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
446
447         return 0;
448 }
449
450 early_initcall(exynos4_l2x0_cache_init);
451 #endif
452
453 int __init exynos_init(void)
454 {
455         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
456
457         /* set idle function */
458         pm_idle = exynos_idle;
459
460         return device_register(&exynos4_dev);
461 }
462
463 static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
464         [0] = {
465                 .name           = "uclk1",
466                 .divisor        = 1,
467                 .min_baud       = 0,
468                 .max_baud       = 0,
469         },
470 };
471
472 /* uart registration process */
473
474 void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
475 {
476         struct s3c2410_uartcfg *tcfg = cfg;
477         u32 ucnt;
478
479         for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
480                 if (!tcfg->clocks) {
481                         tcfg->has_fracval = 1;
482                         tcfg->clocks = exynos4_serial_clocks;
483                         tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
484                 }
485                 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
486         }
487
488         s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
489 }
490
491 static DEFINE_SPINLOCK(eint_lock);
492
493 static unsigned int eint0_15_data[16];
494
495 static unsigned int exynos4_get_irq_nr(unsigned int number)
496 {
497         u32 ret = 0;
498
499         switch (number) {
500         case 0 ... 3:
501                 ret = (number + IRQ_EINT0);
502                 break;
503         case 4 ... 7:
504                 ret = (number + (IRQ_EINT4 - 4));
505                 break;
506         case 8 ... 15:
507                 ret = (number + (IRQ_EINT8 - 8));
508                 break;
509         default:
510                 printk(KERN_ERR "number available : %d\n", number);
511         }
512
513         return ret;
514 }
515
516 static inline void exynos4_irq_eint_mask(struct irq_data *data)
517 {
518         u32 mask;
519
520         spin_lock(&eint_lock);
521         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
522         mask |= eint_irq_to_bit(data->irq);
523         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
524         spin_unlock(&eint_lock);
525 }
526
527 static void exynos4_irq_eint_unmask(struct irq_data *data)
528 {
529         u32 mask;
530
531         spin_lock(&eint_lock);
532         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
533         mask &= ~(eint_irq_to_bit(data->irq));
534         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
535         spin_unlock(&eint_lock);
536 }
537
538 static inline void exynos4_irq_eint_ack(struct irq_data *data)
539 {
540         __raw_writel(eint_irq_to_bit(data->irq),
541                      S5P_EINT_PEND(EINT_REG_NR(data->irq)));
542 }
543
544 static void exynos4_irq_eint_maskack(struct irq_data *data)
545 {
546         exynos4_irq_eint_mask(data);
547         exynos4_irq_eint_ack(data);
548 }
549
550 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
551 {
552         int offs = EINT_OFFSET(data->irq);
553         int shift;
554         u32 ctrl, mask;
555         u32 newvalue = 0;
556
557         switch (type) {
558         case IRQ_TYPE_EDGE_RISING:
559                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
560                 break;
561
562         case IRQ_TYPE_EDGE_FALLING:
563                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
564                 break;
565
566         case IRQ_TYPE_EDGE_BOTH:
567                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
568                 break;
569
570         case IRQ_TYPE_LEVEL_LOW:
571                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
572                 break;
573
574         case IRQ_TYPE_LEVEL_HIGH:
575                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
576                 break;
577
578         default:
579                 printk(KERN_ERR "No such irq type %d", type);
580                 return -EINVAL;
581         }
582
583         shift = (offs & 0x7) * 4;
584         mask = 0x7 << shift;
585
586         spin_lock(&eint_lock);
587         ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
588         ctrl &= ~mask;
589         ctrl |= newvalue << shift;
590         __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
591         spin_unlock(&eint_lock);
592
593         switch (offs) {
594         case 0 ... 7:
595                 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
596                 break;
597         case 8 ... 15:
598                 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
599                 break;
600         case 16 ... 23:
601                 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
602                 break;
603         case 24 ... 31:
604                 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
605                 break;
606         default:
607                 printk(KERN_ERR "No such irq number %d", offs);
608         }
609
610         return 0;
611 }
612
613 static struct irq_chip exynos4_irq_eint = {
614         .name           = "exynos4-eint",
615         .irq_mask       = exynos4_irq_eint_mask,
616         .irq_unmask     = exynos4_irq_eint_unmask,
617         .irq_mask_ack   = exynos4_irq_eint_maskack,
618         .irq_ack        = exynos4_irq_eint_ack,
619         .irq_set_type   = exynos4_irq_eint_set_type,
620 #ifdef CONFIG_PM
621         .irq_set_wake   = s3c_irqext_wake,
622 #endif
623 };
624
625 /*
626  * exynos4_irq_demux_eint
627  *
628  * This function demuxes the IRQ from from EINTs 16 to 31.
629  * It is designed to be inlined into the specific handler
630  * s5p_irq_demux_eintX_Y.
631  *
632  * Each EINT pend/mask registers handle eight of them.
633  */
634 static inline void exynos4_irq_demux_eint(unsigned int start)
635 {
636         unsigned int irq;
637
638         u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
639         u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
640
641         status &= ~mask;
642         status &= 0xff;
643
644         while (status) {
645                 irq = fls(status) - 1;
646                 generic_handle_irq(irq + start);
647                 status &= ~(1 << irq);
648         }
649 }
650
651 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
652 {
653         struct irq_chip *chip = irq_get_chip(irq);
654         chained_irq_enter(chip, desc);
655         exynos4_irq_demux_eint(IRQ_EINT(16));
656         exynos4_irq_demux_eint(IRQ_EINT(24));
657         chained_irq_exit(chip, desc);
658 }
659
660 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
661 {
662         u32 *irq_data = irq_get_handler_data(irq);
663         struct irq_chip *chip = irq_get_chip(irq);
664
665         chained_irq_enter(chip, desc);
666         chip->irq_mask(&desc->irq_data);
667
668         if (chip->irq_ack)
669                 chip->irq_ack(&desc->irq_data);
670
671         generic_handle_irq(*irq_data);
672
673         chip->irq_unmask(&desc->irq_data);
674         chained_irq_exit(chip, desc);
675 }
676
677 int __init exynos4_init_irq_eint(void)
678 {
679         int irq;
680
681         for (irq = 0 ; irq <= 31 ; irq++) {
682                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
683                                          handle_level_irq);
684                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
685         }
686
687         irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
688
689         for (irq = 0 ; irq <= 15 ; irq++) {
690                 eint0_15_data[irq] = IRQ_EINT(irq);
691
692                 irq_set_handler_data(exynos4_get_irq_nr(irq),
693                                      &eint0_15_data[irq]);
694                 irq_set_chained_handler(exynos4_get_irq_nr(irq),
695                                         exynos4_irq_eint0_15);
696         }
697
698         return 0;
699 }
700 arch_initcall(exynos4_init_irq_eint);