Merge tag 'writeback-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/wfg...
[~shefty/rdma-dev.git] / arch / arm / mach-exynos / common.c
1 /*
2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3  *              http://www.samsung.com
4  *
5  * Common Codes for EXYNOS
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/io.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/sched.h>
19 #include <linux/serial_core.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22
23 #include <asm/proc-fns.h>
24 #include <asm/exception.h>
25 #include <asm/hardware/cache-l2x0.h>
26 #include <asm/hardware/gic.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/irq.h>
29 #include <asm/cacheflush.h>
30
31 #include <mach/regs-irq.h>
32 #include <mach/regs-pmu.h>
33 #include <mach/regs-gpio.h>
34 #include <mach/pmu.h>
35
36 #include <plat/cpu.h>
37 #include <plat/clock.h>
38 #include <plat/devs.h>
39 #include <plat/pm.h>
40 #include <plat/sdhci.h>
41 #include <plat/gpio-cfg.h>
42 #include <plat/adc-core.h>
43 #include <plat/fb-core.h>
44 #include <plat/fimc-core.h>
45 #include <plat/iic-core.h>
46 #include <plat/tv-core.h>
47 #include <plat/regs-serial.h>
48
49 #include "common.h"
50 #define L2_AUX_VAL 0x7C470001
51 #define L2_AUX_MASK 0xC200ffff
52
53 static const char name_exynos4210[] = "EXYNOS4210";
54 static const char name_exynos4212[] = "EXYNOS4212";
55 static const char name_exynos4412[] = "EXYNOS4412";
56
57 static struct cpu_table cpu_ids[] __initdata = {
58         {
59                 .idcode         = EXYNOS4210_CPU_ID,
60                 .idmask         = EXYNOS4_CPU_MASK,
61                 .map_io         = exynos4_map_io,
62                 .init_clocks    = exynos4_init_clocks,
63                 .init_uarts     = exynos4_init_uarts,
64                 .init           = exynos_init,
65                 .name           = name_exynos4210,
66         }, {
67                 .idcode         = EXYNOS4212_CPU_ID,
68                 .idmask         = EXYNOS4_CPU_MASK,
69                 .map_io         = exynos4_map_io,
70                 .init_clocks    = exynos4_init_clocks,
71                 .init_uarts     = exynos4_init_uarts,
72                 .init           = exynos_init,
73                 .name           = name_exynos4212,
74         }, {
75                 .idcode         = EXYNOS4412_CPU_ID,
76                 .idmask         = EXYNOS4_CPU_MASK,
77                 .map_io         = exynos4_map_io,
78                 .init_clocks    = exynos4_init_clocks,
79                 .init_uarts     = exynos4_init_uarts,
80                 .init           = exynos_init,
81                 .name           = name_exynos4412,
82         },
83 };
84
85 /* Initial IO mappings */
86
87 static struct map_desc exynos_iodesc[] __initdata = {
88         {
89                 .virtual        = (unsigned long)S5P_VA_CHIPID,
90                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
91                 .length         = SZ_4K,
92                 .type           = MT_DEVICE,
93         }, {
94                 .virtual        = (unsigned long)S3C_VA_SYS,
95                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
96                 .length         = SZ_64K,
97                 .type           = MT_DEVICE,
98         }, {
99                 .virtual        = (unsigned long)S3C_VA_TIMER,
100                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
101                 .length         = SZ_16K,
102                 .type           = MT_DEVICE,
103         }, {
104                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
105                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
106                 .length         = SZ_4K,
107                 .type           = MT_DEVICE,
108         }, {
109                 .virtual        = (unsigned long)S5P_VA_SROMC,
110                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
111                 .length         = SZ_4K,
112                 .type           = MT_DEVICE,
113         }, {
114                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
115                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
116                 .length         = SZ_4K,
117                 .type           = MT_DEVICE,
118         }, {
119                 .virtual        = (unsigned long)S5P_VA_PMU,
120                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
121                 .length         = SZ_64K,
122                 .type           = MT_DEVICE,
123         }, {
124                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
125                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
126                 .length         = SZ_4K,
127                 .type           = MT_DEVICE,
128         }, {
129                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
130                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
131                 .length         = SZ_64K,
132                 .type           = MT_DEVICE,
133         }, {
134                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
135                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
136                 .length         = SZ_64K,
137                 .type           = MT_DEVICE,
138         }, {
139                 .virtual        = (unsigned long)S3C_VA_UART,
140                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
141                 .length         = SZ_512K,
142                 .type           = MT_DEVICE,
143         },
144 };
145
146 static struct map_desc exynos4_iodesc[] __initdata = {
147         {
148                 .virtual        = (unsigned long)S5P_VA_CMU,
149                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
150                 .length         = SZ_128K,
151                 .type           = MT_DEVICE,
152         }, {
153                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
154                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
155                 .length         = SZ_8K,
156                 .type           = MT_DEVICE,
157         }, {
158                 .virtual        = (unsigned long)S5P_VA_L2CC,
159                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
160                 .length         = SZ_4K,
161                 .type           = MT_DEVICE,
162         }, {
163                 .virtual        = (unsigned long)S5P_VA_GPIO1,
164                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
165                 .length         = SZ_4K,
166                 .type           = MT_DEVICE,
167         }, {
168                 .virtual        = (unsigned long)S5P_VA_GPIO2,
169                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
170                 .length         = SZ_4K,
171                 .type           = MT_DEVICE,
172         }, {
173                 .virtual        = (unsigned long)S5P_VA_GPIO3,
174                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
175                 .length         = SZ_256,
176                 .type           = MT_DEVICE,
177         }, {
178                 .virtual        = (unsigned long)S5P_VA_DMC0,
179                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
180                 .length         = SZ_64K,
181                 .type           = MT_DEVICE,
182         }, {
183                 .virtual        = (unsigned long)S5P_VA_DMC1,
184                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
185                 .length         = SZ_64K,
186                 .type           = MT_DEVICE,
187         }, {
188                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
189                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
190                 .length         = SZ_4K,
191                 .type           = MT_DEVICE,
192         },
193 };
194
195 static struct map_desc exynos4_iodesc0[] __initdata = {
196         {
197                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
198                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
199                 .length         = SZ_4K,
200                 .type           = MT_DEVICE,
201         },
202 };
203
204 static struct map_desc exynos4_iodesc1[] __initdata = {
205         {
206                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
207                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
208                 .length         = SZ_4K,
209                 .type           = MT_DEVICE,
210         },
211 };
212
213 void exynos4_restart(char mode, const char *cmd)
214 {
215         __raw_writel(0x1, S5P_SWRESET);
216 }
217
218 /*
219  * exynos_map_io
220  *
221  * register the standard cpu IO areas
222  */
223
224 void __init exynos_init_io(struct map_desc *mach_desc, int size)
225 {
226         /* initialize the io descriptors we need for initialization */
227         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
228         if (mach_desc)
229                 iotable_init(mach_desc, size);
230
231         /* detect cpu id and rev. */
232         s5p_init_cpu(S5P_VA_CHIPID);
233
234         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
235 }
236
237 void __init exynos4_map_io(void)
238 {
239         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
240
241         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
242                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
243         else
244                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
245
246         /* initialize device information early */
247         exynos4_default_sdhci0();
248         exynos4_default_sdhci1();
249         exynos4_default_sdhci2();
250         exynos4_default_sdhci3();
251
252         s3c_adc_setname("samsung-adc-v3");
253
254         s3c_fimc_setname(0, "exynos4-fimc");
255         s3c_fimc_setname(1, "exynos4-fimc");
256         s3c_fimc_setname(2, "exynos4-fimc");
257         s3c_fimc_setname(3, "exynos4-fimc");
258
259         /* The I2C bus controllers are directly compatible with s3c2440 */
260         s3c_i2c0_setname("s3c2440-i2c");
261         s3c_i2c1_setname("s3c2440-i2c");
262         s3c_i2c2_setname("s3c2440-i2c");
263
264         s5p_fb_setname(0, "exynos4-fb");
265         s5p_hdmi_setname("exynos4-hdmi");
266 }
267
268 void __init exynos4_init_clocks(int xtal)
269 {
270         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
271
272         s3c24xx_register_baseclocks(xtal);
273         s5p_register_clocks(xtal);
274
275         if (soc_is_exynos4210())
276                 exynos4210_register_clocks();
277         else if (soc_is_exynos4212() || soc_is_exynos4412())
278                 exynos4212_register_clocks();
279
280         exynos4_register_clocks();
281         exynos4_setup_clocks();
282 }
283
284 #define COMBINER_ENABLE_SET     0x0
285 #define COMBINER_ENABLE_CLEAR   0x4
286 #define COMBINER_INT_STATUS     0xC
287
288 static DEFINE_SPINLOCK(irq_controller_lock);
289
290 struct combiner_chip_data {
291         unsigned int irq_offset;
292         unsigned int irq_mask;
293         void __iomem *base;
294 };
295
296 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
297
298 static inline void __iomem *combiner_base(struct irq_data *data)
299 {
300         struct combiner_chip_data *combiner_data =
301                 irq_data_get_irq_chip_data(data);
302
303         return combiner_data->base;
304 }
305
306 static void combiner_mask_irq(struct irq_data *data)
307 {
308         u32 mask = 1 << (data->irq % 32);
309
310         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
311 }
312
313 static void combiner_unmask_irq(struct irq_data *data)
314 {
315         u32 mask = 1 << (data->irq % 32);
316
317         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
318 }
319
320 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
321 {
322         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
323         struct irq_chip *chip = irq_get_chip(irq);
324         unsigned int cascade_irq, combiner_irq;
325         unsigned long status;
326
327         chained_irq_enter(chip, desc);
328
329         spin_lock(&irq_controller_lock);
330         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
331         spin_unlock(&irq_controller_lock);
332         status &= chip_data->irq_mask;
333
334         if (status == 0)
335                 goto out;
336
337         combiner_irq = __ffs(status);
338
339         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
340         if (unlikely(cascade_irq >= NR_IRQS))
341                 do_bad_IRQ(cascade_irq, desc);
342         else
343                 generic_handle_irq(cascade_irq);
344
345  out:
346         chained_irq_exit(chip, desc);
347 }
348
349 static struct irq_chip combiner_chip = {
350         .name           = "COMBINER",
351         .irq_mask       = combiner_mask_irq,
352         .irq_unmask     = combiner_unmask_irq,
353 };
354
355 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
356 {
357         if (combiner_nr >= MAX_COMBINER_NR)
358                 BUG();
359         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
360                 BUG();
361         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
362 }
363
364 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
365                           unsigned int irq_start)
366 {
367         unsigned int i;
368
369         if (combiner_nr >= MAX_COMBINER_NR)
370                 BUG();
371
372         combiner_data[combiner_nr].base = base;
373         combiner_data[combiner_nr].irq_offset = irq_start;
374         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
375
376         /* Disable all interrupts */
377
378         __raw_writel(combiner_data[combiner_nr].irq_mask,
379                      base + COMBINER_ENABLE_CLEAR);
380
381         /* Setup the Linux IRQ subsystem */
382
383         for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
384                                 + MAX_IRQ_IN_COMBINER; i++) {
385                 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
386                 irq_set_chip_data(i, &combiner_data[combiner_nr]);
387                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
388         }
389 }
390
391 #ifdef CONFIG_OF
392 static const struct of_device_id exynos4_dt_irq_match[] = {
393         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
394         {},
395 };
396 #endif
397
398 void __init exynos4_init_irq(void)
399 {
400         int irq;
401         unsigned int gic_bank_offset;
402
403         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
404
405         if (!of_have_populated_dt())
406                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
407 #ifdef CONFIG_OF
408         else
409                 of_irq_init(exynos4_dt_irq_match);
410 #endif
411
412         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
413
414                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
415                                 COMBINER_IRQ(irq, 0));
416                 combiner_cascade_irq(irq, IRQ_SPI(irq));
417         }
418
419         /*
420          * The parameters of s5p_init_irq() are for VIC init.
421          * Theses parameters should be NULL and 0 because EXYNOS4
422          * uses GIC instead of VIC.
423          */
424         s5p_init_irq(NULL, 0);
425 }
426
427 struct bus_type exynos4_subsys = {
428         .name           = "exynos4-core",
429         .dev_name       = "exynos4-core",
430 };
431
432 static struct device exynos4_dev = {
433         .bus    = &exynos4_subsys,
434 };
435
436 static int __init exynos4_core_init(void)
437 {
438         return subsys_system_register(&exynos4_subsys, NULL);
439 }
440 core_initcall(exynos4_core_init);
441
442 #ifdef CONFIG_CACHE_L2X0
443 static int __init exynos4_l2x0_cache_init(void)
444 {
445         int ret;
446         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
447         if (!ret) {
448                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
449                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
450                 return 0;
451         }
452
453         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
454                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
455                 /* TAG, Data Latency Control: 2 cycles */
456                 l2x0_saved_regs.tag_latency = 0x110;
457
458                 if (soc_is_exynos4212() || soc_is_exynos4412())
459                         l2x0_saved_regs.data_latency = 0x120;
460                 else
461                         l2x0_saved_regs.data_latency = 0x110;
462
463                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
464                 l2x0_saved_regs.pwr_ctrl =
465                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
466
467                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
468
469                 __raw_writel(l2x0_saved_regs.tag_latency,
470                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
471                 __raw_writel(l2x0_saved_regs.data_latency,
472                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
473
474                 /* L2X0 Prefetch Control */
475                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
476                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
477
478                 /* L2X0 Power Control */
479                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
480                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
481
482                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
483                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
484         }
485
486         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
487         return 0;
488 }
489
490 early_initcall(exynos4_l2x0_cache_init);
491 #endif
492
493 int __init exynos_init(void)
494 {
495         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
496         return device_register(&exynos4_dev);
497 }
498
499 /* uart registration process */
500
501 void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
502 {
503         struct s3c2410_uartcfg *tcfg = cfg;
504         u32 ucnt;
505
506         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
507                 tcfg->has_fracval = 1;
508
509         s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
510 }
511
512 static DEFINE_SPINLOCK(eint_lock);
513
514 static unsigned int eint0_15_data[16];
515
516 static unsigned int exynos4_get_irq_nr(unsigned int number)
517 {
518         u32 ret = 0;
519
520         switch (number) {
521         case 0 ... 3:
522                 ret = (number + IRQ_EINT0);
523                 break;
524         case 4 ... 7:
525                 ret = (number + (IRQ_EINT4 - 4));
526                 break;
527         case 8 ... 15:
528                 ret = (number + (IRQ_EINT8 - 8));
529                 break;
530         default:
531                 printk(KERN_ERR "number available : %d\n", number);
532         }
533
534         return ret;
535 }
536
537 static inline void exynos4_irq_eint_mask(struct irq_data *data)
538 {
539         u32 mask;
540
541         spin_lock(&eint_lock);
542         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
543         mask |= eint_irq_to_bit(data->irq);
544         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
545         spin_unlock(&eint_lock);
546 }
547
548 static void exynos4_irq_eint_unmask(struct irq_data *data)
549 {
550         u32 mask;
551
552         spin_lock(&eint_lock);
553         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
554         mask &= ~(eint_irq_to_bit(data->irq));
555         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
556         spin_unlock(&eint_lock);
557 }
558
559 static inline void exynos4_irq_eint_ack(struct irq_data *data)
560 {
561         __raw_writel(eint_irq_to_bit(data->irq),
562                      S5P_EINT_PEND(EINT_REG_NR(data->irq)));
563 }
564
565 static void exynos4_irq_eint_maskack(struct irq_data *data)
566 {
567         exynos4_irq_eint_mask(data);
568         exynos4_irq_eint_ack(data);
569 }
570
571 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
572 {
573         int offs = EINT_OFFSET(data->irq);
574         int shift;
575         u32 ctrl, mask;
576         u32 newvalue = 0;
577
578         switch (type) {
579         case IRQ_TYPE_EDGE_RISING:
580                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
581                 break;
582
583         case IRQ_TYPE_EDGE_FALLING:
584                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
585                 break;
586
587         case IRQ_TYPE_EDGE_BOTH:
588                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
589                 break;
590
591         case IRQ_TYPE_LEVEL_LOW:
592                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
593                 break;
594
595         case IRQ_TYPE_LEVEL_HIGH:
596                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
597                 break;
598
599         default:
600                 printk(KERN_ERR "No such irq type %d", type);
601                 return -EINVAL;
602         }
603
604         shift = (offs & 0x7) * 4;
605         mask = 0x7 << shift;
606
607         spin_lock(&eint_lock);
608         ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
609         ctrl &= ~mask;
610         ctrl |= newvalue << shift;
611         __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
612         spin_unlock(&eint_lock);
613
614         switch (offs) {
615         case 0 ... 7:
616                 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
617                 break;
618         case 8 ... 15:
619                 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
620                 break;
621         case 16 ... 23:
622                 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
623                 break;
624         case 24 ... 31:
625                 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
626                 break;
627         default:
628                 printk(KERN_ERR "No such irq number %d", offs);
629         }
630
631         return 0;
632 }
633
634 static struct irq_chip exynos4_irq_eint = {
635         .name           = "exynos4-eint",
636         .irq_mask       = exynos4_irq_eint_mask,
637         .irq_unmask     = exynos4_irq_eint_unmask,
638         .irq_mask_ack   = exynos4_irq_eint_maskack,
639         .irq_ack        = exynos4_irq_eint_ack,
640         .irq_set_type   = exynos4_irq_eint_set_type,
641 #ifdef CONFIG_PM
642         .irq_set_wake   = s3c_irqext_wake,
643 #endif
644 };
645
646 /*
647  * exynos4_irq_demux_eint
648  *
649  * This function demuxes the IRQ from from EINTs 16 to 31.
650  * It is designed to be inlined into the specific handler
651  * s5p_irq_demux_eintX_Y.
652  *
653  * Each EINT pend/mask registers handle eight of them.
654  */
655 static inline void exynos4_irq_demux_eint(unsigned int start)
656 {
657         unsigned int irq;
658
659         u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
660         u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
661
662         status &= ~mask;
663         status &= 0xff;
664
665         while (status) {
666                 irq = fls(status) - 1;
667                 generic_handle_irq(irq + start);
668                 status &= ~(1 << irq);
669         }
670 }
671
672 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
673 {
674         struct irq_chip *chip = irq_get_chip(irq);
675         chained_irq_enter(chip, desc);
676         exynos4_irq_demux_eint(IRQ_EINT(16));
677         exynos4_irq_demux_eint(IRQ_EINT(24));
678         chained_irq_exit(chip, desc);
679 }
680
681 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
682 {
683         u32 *irq_data = irq_get_handler_data(irq);
684         struct irq_chip *chip = irq_get_chip(irq);
685
686         chained_irq_enter(chip, desc);
687         chip->irq_mask(&desc->irq_data);
688
689         if (chip->irq_ack)
690                 chip->irq_ack(&desc->irq_data);
691
692         generic_handle_irq(*irq_data);
693
694         chip->irq_unmask(&desc->irq_data);
695         chained_irq_exit(chip, desc);
696 }
697
698 static int __init exynos4_init_irq_eint(void)
699 {
700         int irq;
701
702         for (irq = 0 ; irq <= 31 ; irq++) {
703                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
704                                          handle_level_irq);
705                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
706         }
707
708         irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
709
710         for (irq = 0 ; irq <= 15 ; irq++) {
711                 eint0_15_data[irq] = IRQ_EINT(irq);
712
713                 irq_set_handler_data(exynos4_get_irq_nr(irq),
714                                      &eint0_15_data[irq]);
715                 irq_set_chained_handler(exynos4_get_irq_nr(irq),
716                                         exynos4_irq_eint0_15);
717         }
718
719         return 0;
720 }
721 arch_initcall(exynos4_init_irq_eint);