Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[~shefty/rdma-dev.git] / arch / arm / mach-exynos / mct.c
1 /* linux/arch/arm/mach-exynos4/mct.c
2  *
3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4  *              http://www.samsung.com
5  *
6  * EXYNOS4 MCT(Multi-Core Timer) support
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/percpu.h>
22
23 #include <asm/hardware/gic.h>
24 #include <asm/localtimer.h>
25
26 #include <plat/cpu.h>
27
28 #include <mach/map.h>
29 #include <mach/irqs.h>
30 #include <mach/regs-mct.h>
31 #include <asm/mach/time.h>
32
33 #define TICK_BASE_CNT   1
34
35 enum {
36         MCT_INT_SPI,
37         MCT_INT_PPI
38 };
39
40 static unsigned long clk_rate;
41 static unsigned int mct_int_type;
42
43 struct mct_clock_event_device {
44         struct clock_event_device *evt;
45         void __iomem *base;
46         char name[10];
47 };
48
49 static void exynos4_mct_write(unsigned int value, void *addr)
50 {
51         void __iomem *stat_addr;
52         u32 mask;
53         u32 i;
54
55         __raw_writel(value, addr);
56
57         if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
58                 u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
59                 switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
60                 case (u32) MCT_L_TCON_OFFSET:
61                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
62                         mask = 1 << 3;          /* L_TCON write status */
63                         break;
64                 case (u32) MCT_L_ICNTB_OFFSET:
65                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
66                         mask = 1 << 1;          /* L_ICNTB write status */
67                         break;
68                 case (u32) MCT_L_TCNTB_OFFSET:
69                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
70                         mask = 1 << 0;          /* L_TCNTB write status */
71                         break;
72                 default:
73                         return;
74                 }
75         } else {
76                 switch ((u32) addr) {
77                 case (u32) EXYNOS4_MCT_G_TCON:
78                         stat_addr = EXYNOS4_MCT_G_WSTAT;
79                         mask = 1 << 16;         /* G_TCON write status */
80                         break;
81                 case (u32) EXYNOS4_MCT_G_COMP0_L:
82                         stat_addr = EXYNOS4_MCT_G_WSTAT;
83                         mask = 1 << 0;          /* G_COMP0_L write status */
84                         break;
85                 case (u32) EXYNOS4_MCT_G_COMP0_U:
86                         stat_addr = EXYNOS4_MCT_G_WSTAT;
87                         mask = 1 << 1;          /* G_COMP0_U write status */
88                         break;
89                 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
90                         stat_addr = EXYNOS4_MCT_G_WSTAT;
91                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
92                         break;
93                 case (u32) EXYNOS4_MCT_G_CNT_L:
94                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
95                         mask = 1 << 0;          /* G_CNT_L write status */
96                         break;
97                 case (u32) EXYNOS4_MCT_G_CNT_U:
98                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
99                         mask = 1 << 1;          /* G_CNT_U write status */
100                         break;
101                 default:
102                         return;
103                 }
104         }
105
106         /* Wait maximum 1 ms until written values are applied */
107         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
108                 if (__raw_readl(stat_addr) & mask) {
109                         __raw_writel(mask, stat_addr);
110                         return;
111                 }
112
113         panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
114 }
115
116 /* Clocksource handling */
117 static void exynos4_mct_frc_start(u32 hi, u32 lo)
118 {
119         u32 reg;
120
121         exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
122         exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
123
124         reg = __raw_readl(EXYNOS4_MCT_G_TCON);
125         reg |= MCT_G_TCON_START;
126         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
127 }
128
129 static cycle_t exynos4_frc_read(struct clocksource *cs)
130 {
131         unsigned int lo, hi;
132         u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
133
134         do {
135                 hi = hi2;
136                 lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
137                 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
138         } while (hi != hi2);
139
140         return ((cycle_t)hi << 32) | lo;
141 }
142
143 static void exynos4_frc_resume(struct clocksource *cs)
144 {
145         exynos4_mct_frc_start(0, 0);
146 }
147
148 struct clocksource mct_frc = {
149         .name           = "mct-frc",
150         .rating         = 400,
151         .read           = exynos4_frc_read,
152         .mask           = CLOCKSOURCE_MASK(64),
153         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
154         .resume         = exynos4_frc_resume,
155 };
156
157 static void __init exynos4_clocksource_init(void)
158 {
159         exynos4_mct_frc_start(0, 0);
160
161         if (clocksource_register_hz(&mct_frc, clk_rate))
162                 panic("%s: can't register clocksource\n", mct_frc.name);
163 }
164
165 static void exynos4_mct_comp0_stop(void)
166 {
167         unsigned int tcon;
168
169         tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
170         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
171
172         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
173         exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
174 }
175
176 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
177                                     unsigned long cycles)
178 {
179         unsigned int tcon;
180         cycle_t comp_cycle;
181
182         tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
183
184         if (mode == CLOCK_EVT_MODE_PERIODIC) {
185                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
186                 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
187         }
188
189         comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
190         exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
191         exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
192
193         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
194
195         tcon |= MCT_G_TCON_COMP0_ENABLE;
196         exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
197 }
198
199 static int exynos4_comp_set_next_event(unsigned long cycles,
200                                        struct clock_event_device *evt)
201 {
202         exynos4_mct_comp0_start(evt->mode, cycles);
203
204         return 0;
205 }
206
207 static void exynos4_comp_set_mode(enum clock_event_mode mode,
208                                   struct clock_event_device *evt)
209 {
210         unsigned long cycles_per_jiffy;
211         exynos4_mct_comp0_stop();
212
213         switch (mode) {
214         case CLOCK_EVT_MODE_PERIODIC:
215                 cycles_per_jiffy =
216                         (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
217                 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
218                 break;
219
220         case CLOCK_EVT_MODE_ONESHOT:
221         case CLOCK_EVT_MODE_UNUSED:
222         case CLOCK_EVT_MODE_SHUTDOWN:
223         case CLOCK_EVT_MODE_RESUME:
224                 break;
225         }
226 }
227
228 static struct clock_event_device mct_comp_device = {
229         .name           = "mct-comp",
230         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
231         .rating         = 250,
232         .set_next_event = exynos4_comp_set_next_event,
233         .set_mode       = exynos4_comp_set_mode,
234 };
235
236 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
237 {
238         struct clock_event_device *evt = dev_id;
239
240         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
241
242         evt->event_handler(evt);
243
244         return IRQ_HANDLED;
245 }
246
247 static struct irqaction mct_comp_event_irq = {
248         .name           = "mct_comp_irq",
249         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
250         .handler        = exynos4_mct_comp_isr,
251         .dev_id         = &mct_comp_device,
252 };
253
254 static void exynos4_clockevent_init(void)
255 {
256         clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
257         mct_comp_device.max_delta_ns =
258                 clockevent_delta2ns(0xffffffff, &mct_comp_device);
259         mct_comp_device.min_delta_ns =
260                 clockevent_delta2ns(0xf, &mct_comp_device);
261         mct_comp_device.cpumask = cpumask_of(0);
262         clockevents_register_device(&mct_comp_device);
263
264         setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
265 }
266
267 #ifdef CONFIG_LOCAL_TIMERS
268
269 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
270
271 /* Clock event handling */
272 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
273 {
274         unsigned long tmp;
275         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
276         void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
277
278         tmp = __raw_readl(addr);
279         if (tmp & mask) {
280                 tmp &= ~mask;
281                 exynos4_mct_write(tmp, addr);
282         }
283 }
284
285 static void exynos4_mct_tick_start(unsigned long cycles,
286                                    struct mct_clock_event_device *mevt)
287 {
288         unsigned long tmp;
289
290         exynos4_mct_tick_stop(mevt);
291
292         tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
293
294         /* update interrupt count buffer */
295         exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
296
297         /* enable MCT tick interrupt */
298         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
299
300         tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
301         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
302                MCT_L_TCON_INTERVAL_MODE;
303         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
304 }
305
306 static int exynos4_tick_set_next_event(unsigned long cycles,
307                                        struct clock_event_device *evt)
308 {
309         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
310
311         exynos4_mct_tick_start(cycles, mevt);
312
313         return 0;
314 }
315
316 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
317                                          struct clock_event_device *evt)
318 {
319         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
320         unsigned long cycles_per_jiffy;
321
322         exynos4_mct_tick_stop(mevt);
323
324         switch (mode) {
325         case CLOCK_EVT_MODE_PERIODIC:
326                 cycles_per_jiffy =
327                         (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
328                 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
329                 break;
330
331         case CLOCK_EVT_MODE_ONESHOT:
332         case CLOCK_EVT_MODE_UNUSED:
333         case CLOCK_EVT_MODE_SHUTDOWN:
334         case CLOCK_EVT_MODE_RESUME:
335                 break;
336         }
337 }
338
339 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
340 {
341         struct clock_event_device *evt = mevt->evt;
342
343         /*
344          * This is for supporting oneshot mode.
345          * Mct would generate interrupt periodically
346          * without explicit stopping.
347          */
348         if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
349                 exynos4_mct_tick_stop(mevt);
350
351         /* Clear the MCT tick interrupt */
352         if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
353                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
354                 return 1;
355         } else {
356                 return 0;
357         }
358 }
359
360 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
361 {
362         struct mct_clock_event_device *mevt = dev_id;
363         struct clock_event_device *evt = mevt->evt;
364
365         exynos4_mct_tick_clear(mevt);
366
367         evt->event_handler(evt);
368
369         return IRQ_HANDLED;
370 }
371
372 static struct irqaction mct_tick0_event_irq = {
373         .name           = "mct_tick0_irq",
374         .flags          = IRQF_TIMER | IRQF_NOBALANCING,
375         .handler        = exynos4_mct_tick_isr,
376 };
377
378 static struct irqaction mct_tick1_event_irq = {
379         .name           = "mct_tick1_irq",
380         .flags          = IRQF_TIMER | IRQF_NOBALANCING,
381         .handler        = exynos4_mct_tick_isr,
382 };
383
384 static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
385 {
386         struct mct_clock_event_device *mevt;
387         unsigned int cpu = smp_processor_id();
388
389         mevt = this_cpu_ptr(&percpu_mct_tick);
390         mevt->evt = evt;
391
392         mevt->base = EXYNOS4_MCT_L_BASE(cpu);
393         sprintf(mevt->name, "mct_tick%d", cpu);
394
395         evt->name = mevt->name;
396         evt->cpumask = cpumask_of(cpu);
397         evt->set_next_event = exynos4_tick_set_next_event;
398         evt->set_mode = exynos4_tick_set_mode;
399         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
400         evt->rating = 450;
401
402         clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
403         evt->max_delta_ns =
404                 clockevent_delta2ns(0x7fffffff, evt);
405         evt->min_delta_ns =
406                 clockevent_delta2ns(0xf, evt);
407
408         clockevents_register_device(evt);
409
410         exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
411
412         if (mct_int_type == MCT_INT_SPI) {
413                 if (cpu == 0) {
414                         mct_tick0_event_irq.dev_id = mevt;
415                         evt->irq = IRQ_MCT_L0;
416                         setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
417                 } else {
418                         mct_tick1_event_irq.dev_id = mevt;
419                         evt->irq = IRQ_MCT_L1;
420                         setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
421                         irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
422                 }
423         } else {
424                 enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
425         }
426
427         return 0;
428 }
429
430 static void exynos4_local_timer_stop(struct clock_event_device *evt)
431 {
432         unsigned int cpu = smp_processor_id();
433         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
434         if (mct_int_type == MCT_INT_SPI)
435                 if (cpu == 0)
436                         remove_irq(evt->irq, &mct_tick0_event_irq);
437                 else
438                         remove_irq(evt->irq, &mct_tick1_event_irq);
439         else
440                 disable_percpu_irq(IRQ_MCT_LOCALTIMER);
441 }
442
443 static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
444         .setup  = exynos4_local_timer_setup,
445         .stop   = exynos4_local_timer_stop,
446 };
447 #endif /* CONFIG_LOCAL_TIMERS */
448
449 static void __init exynos4_timer_resources(void)
450 {
451         struct clk *mct_clk;
452         mct_clk = clk_get(NULL, "xtal");
453
454         clk_rate = clk_get_rate(mct_clk);
455
456 #ifdef CONFIG_LOCAL_TIMERS
457         if (mct_int_type == MCT_INT_PPI) {
458                 int err;
459
460                 err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
461                                          exynos4_mct_tick_isr, "MCT",
462                                          &percpu_mct_tick);
463                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
464                      IRQ_MCT_LOCALTIMER, err);
465         }
466
467         local_timer_register(&exynos4_mct_tick_ops);
468 #endif /* CONFIG_LOCAL_TIMERS */
469 }
470
471 static void __init exynos4_timer_init(void)
472 {
473         if (soc_is_exynos4210())
474                 mct_int_type = MCT_INT_SPI;
475         else
476                 mct_int_type = MCT_INT_PPI;
477
478         exynos4_timer_resources();
479         exynos4_clocksource_init();
480         exynos4_clockevent_init();
481 }
482
483 struct sys_timer exynos4_timer = {
484         .init           = exynos4_timer_init,
485 };