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1 /*
2  * OMAP4 Clock data
3  *
4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley (paul@pwsan.com)
8  * Rajendra Nayak (rnayak@ti.com)
9  * Benoit Cousson (b-cousson@ti.com)
10  *
11  * This file is automatically generated from the OMAP hardware databases.
12  * We respectfully ask that any modifications to this file be coordinated
13  * with the public linux-omap@vger.kernel.org mailing list and the
14  * authors above to ensure that the autogeneration scripts are kept
15  * up-to-date with the file contents.
16  *
17  * This program is free software; you can redistribute it and/or modify
18  * it under the terms of the GNU General Public License version 2 as
19  * published by the Free Software Foundation.
20  *
21  * XXX Some of the ES1 clocks have been removed/changed; once support
22  * is added for discriminating clocks by ES level, these should be added back
23  * in.
24  */
25
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/clk.h>
29 #include <plat/clkdev_omap.h>
30
31 #include "clock.h"
32 #include "clock44xx.h"
33 #include "cm1_44xx.h"
34 #include "cm2_44xx.h"
35 #include "cm-regbits-44xx.h"
36 #include "prm44xx.h"
37 #include "prm-regbits-44xx.h"
38 #include "control.h"
39 #include "scrm44xx.h"
40
41 /* OMAP4 modulemode control */
42 #define OMAP4430_MODULEMODE_HWCTRL                      0
43 #define OMAP4430_MODULEMODE_SWCTRL                      1
44
45 /* Root clocks */
46
47 static struct clk extalt_clkin_ck = {
48         .name           = "extalt_clkin_ck",
49         .rate           = 59000000,
50         .ops            = &clkops_null,
51 };
52
53 static struct clk pad_clks_ck = {
54         .name           = "pad_clks_ck",
55         .rate           = 12000000,
56         .ops            = &clkops_omap2_dflt,
57         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
58         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
59 };
60
61 static struct clk pad_slimbus_core_clks_ck = {
62         .name           = "pad_slimbus_core_clks_ck",
63         .rate           = 12000000,
64         .ops            = &clkops_null,
65 };
66
67 static struct clk secure_32k_clk_src_ck = {
68         .name           = "secure_32k_clk_src_ck",
69         .rate           = 32768,
70         .ops            = &clkops_null,
71 };
72
73 static struct clk slimbus_clk = {
74         .name           = "slimbus_clk",
75         .rate           = 12000000,
76         .ops            = &clkops_omap2_dflt,
77         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
78         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
79 };
80
81 static struct clk sys_32k_ck = {
82         .name           = "sys_32k_ck",
83         .rate           = 32768,
84         .ops            = &clkops_null,
85 };
86
87 static struct clk virt_12000000_ck = {
88         .name           = "virt_12000000_ck",
89         .ops            = &clkops_null,
90         .rate           = 12000000,
91 };
92
93 static struct clk virt_13000000_ck = {
94         .name           = "virt_13000000_ck",
95         .ops            = &clkops_null,
96         .rate           = 13000000,
97 };
98
99 static struct clk virt_16800000_ck = {
100         .name           = "virt_16800000_ck",
101         .ops            = &clkops_null,
102         .rate           = 16800000,
103 };
104
105 static struct clk virt_19200000_ck = {
106         .name           = "virt_19200000_ck",
107         .ops            = &clkops_null,
108         .rate           = 19200000,
109 };
110
111 static struct clk virt_26000000_ck = {
112         .name           = "virt_26000000_ck",
113         .ops            = &clkops_null,
114         .rate           = 26000000,
115 };
116
117 static struct clk virt_27000000_ck = {
118         .name           = "virt_27000000_ck",
119         .ops            = &clkops_null,
120         .rate           = 27000000,
121 };
122
123 static struct clk virt_38400000_ck = {
124         .name           = "virt_38400000_ck",
125         .ops            = &clkops_null,
126         .rate           = 38400000,
127 };
128
129 static const struct clksel_rate div_1_0_rates[] = {
130         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
131         { .div = 0 },
132 };
133
134 static const struct clksel_rate div_1_1_rates[] = {
135         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
136         { .div = 0 },
137 };
138
139 static const struct clksel_rate div_1_2_rates[] = {
140         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
141         { .div = 0 },
142 };
143
144 static const struct clksel_rate div_1_3_rates[] = {
145         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
146         { .div = 0 },
147 };
148
149 static const struct clksel_rate div_1_4_rates[] = {
150         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
151         { .div = 0 },
152 };
153
154 static const struct clksel_rate div_1_5_rates[] = {
155         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
156         { .div = 0 },
157 };
158
159 static const struct clksel_rate div_1_6_rates[] = {
160         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
161         { .div = 0 },
162 };
163
164 static const struct clksel_rate div_1_7_rates[] = {
165         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
166         { .div = 0 },
167 };
168
169 static const struct clksel sys_clkin_sel[] = {
170         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
171         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
172         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
173         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
174         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
175         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
176         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
177         { .parent = NULL },
178 };
179
180 static struct clk sys_clkin_ck = {
181         .name           = "sys_clkin_ck",
182         .rate           = 38400000,
183         .clksel         = sys_clkin_sel,
184         .init           = &omap2_init_clksel_parent,
185         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
186         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
187         .ops            = &clkops_null,
188         .recalc         = &omap2_clksel_recalc,
189 };
190
191 static struct clk tie_low_clock_ck = {
192         .name           = "tie_low_clock_ck",
193         .rate           = 0,
194         .ops            = &clkops_null,
195 };
196
197 static struct clk utmi_phy_clkout_ck = {
198         .name           = "utmi_phy_clkout_ck",
199         .rate           = 60000000,
200         .ops            = &clkops_null,
201 };
202
203 static struct clk xclk60mhsp1_ck = {
204         .name           = "xclk60mhsp1_ck",
205         .rate           = 60000000,
206         .ops            = &clkops_null,
207 };
208
209 static struct clk xclk60mhsp2_ck = {
210         .name           = "xclk60mhsp2_ck",
211         .rate           = 60000000,
212         .ops            = &clkops_null,
213 };
214
215 static struct clk xclk60motg_ck = {
216         .name           = "xclk60motg_ck",
217         .rate           = 60000000,
218         .ops            = &clkops_null,
219 };
220
221 /* Module clocks and DPLL outputs */
222
223 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
224         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
225         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
226         { .parent = NULL },
227 };
228
229 static struct clk abe_dpll_bypass_clk_mux_ck = {
230         .name           = "abe_dpll_bypass_clk_mux_ck",
231         .parent         = &sys_clkin_ck,
232         .ops            = &clkops_null,
233         .recalc         = &followparent_recalc,
234 };
235
236 static struct clk abe_dpll_refclk_mux_ck = {
237         .name           = "abe_dpll_refclk_mux_ck",
238         .parent         = &sys_clkin_ck,
239         .clksel         = abe_dpll_bypass_clk_mux_sel,
240         .init           = &omap2_init_clksel_parent,
241         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
242         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
243         .ops            = &clkops_null,
244         .recalc         = &omap2_clksel_recalc,
245 };
246
247 /* DPLL_ABE */
248 static struct dpll_data dpll_abe_dd = {
249         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
250         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
251         .clk_ref        = &abe_dpll_refclk_mux_ck,
252         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
253         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
254         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
255         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
256         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
257         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
258         .enable_mask    = OMAP4430_DPLL_EN_MASK,
259         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
260         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
261         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
262         .max_divider    = OMAP4430_MAX_DPLL_DIV,
263         .min_divider    = 1,
264 };
265
266
267 static struct clk dpll_abe_ck = {
268         .name           = "dpll_abe_ck",
269         .parent         = &abe_dpll_refclk_mux_ck,
270         .dpll_data      = &dpll_abe_dd,
271         .init           = &omap2_init_dpll_parent,
272         .ops            = &clkops_omap3_noncore_dpll_ops,
273         .recalc         = &omap3_dpll_recalc,
274         .round_rate     = &omap2_dpll_round_rate,
275         .set_rate       = &omap3_noncore_dpll_set_rate,
276 };
277
278 static struct clk dpll_abe_x2_ck = {
279         .name           = "dpll_abe_x2_ck",
280         .parent         = &dpll_abe_ck,
281         .flags          = CLOCK_CLKOUTX2,
282         .ops            = &clkops_omap4_dpllmx_ops,
283         .recalc         = &omap3_clkoutx2_recalc,
284         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
285 };
286
287 static const struct clksel_rate div31_1to31_rates[] = {
288         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
289         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
290         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
291         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
292         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
293         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
294         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
295         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
296         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
297         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
298         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
299         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
300         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
301         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
302         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
303         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
304         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
305         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
306         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
307         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
308         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
309         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
310         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
311         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
312         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
313         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
314         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
315         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
316         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
317         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
318         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
319         { .div = 0 },
320 };
321
322 static const struct clksel dpll_abe_m2x2_div[] = {
323         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
324         { .parent = NULL },
325 };
326
327 static struct clk dpll_abe_m2x2_ck = {
328         .name           = "dpll_abe_m2x2_ck",
329         .parent         = &dpll_abe_x2_ck,
330         .clksel         = dpll_abe_m2x2_div,
331         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
332         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
333         .ops            = &clkops_omap4_dpllmx_ops,
334         .recalc         = &omap2_clksel_recalc,
335         .round_rate     = &omap2_clksel_round_rate,
336         .set_rate       = &omap2_clksel_set_rate,
337 };
338
339 static struct clk abe_24m_fclk = {
340         .name           = "abe_24m_fclk",
341         .parent         = &dpll_abe_m2x2_ck,
342         .ops            = &clkops_null,
343         .fixed_div      = 8,
344         .recalc         = &omap_fixed_divisor_recalc,
345 };
346
347 static const struct clksel_rate div3_1to4_rates[] = {
348         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
349         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
350         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
351         { .div = 0 },
352 };
353
354 static const struct clksel abe_clk_div[] = {
355         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
356         { .parent = NULL },
357 };
358
359 static struct clk abe_clk = {
360         .name           = "abe_clk",
361         .parent         = &dpll_abe_m2x2_ck,
362         .clksel         = abe_clk_div,
363         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
364         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
365         .ops            = &clkops_null,
366         .recalc         = &omap2_clksel_recalc,
367         .round_rate     = &omap2_clksel_round_rate,
368         .set_rate       = &omap2_clksel_set_rate,
369 };
370
371 static const struct clksel_rate div2_1to2_rates[] = {
372         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
373         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
374         { .div = 0 },
375 };
376
377 static const struct clksel aess_fclk_div[] = {
378         { .parent = &abe_clk, .rates = div2_1to2_rates },
379         { .parent = NULL },
380 };
381
382 static struct clk aess_fclk = {
383         .name           = "aess_fclk",
384         .parent         = &abe_clk,
385         .clksel         = aess_fclk_div,
386         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
387         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
388         .ops            = &clkops_null,
389         .recalc         = &omap2_clksel_recalc,
390         .round_rate     = &omap2_clksel_round_rate,
391         .set_rate       = &omap2_clksel_set_rate,
392 };
393
394 static struct clk dpll_abe_m3x2_ck = {
395         .name           = "dpll_abe_m3x2_ck",
396         .parent         = &dpll_abe_x2_ck,
397         .clksel         = dpll_abe_m2x2_div,
398         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
399         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
400         .ops            = &clkops_omap4_dpllmx_ops,
401         .recalc         = &omap2_clksel_recalc,
402         .round_rate     = &omap2_clksel_round_rate,
403         .set_rate       = &omap2_clksel_set_rate,
404 };
405
406 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
407         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
408         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
409         { .parent = NULL },
410 };
411
412 static struct clk core_hsd_byp_clk_mux_ck = {
413         .name           = "core_hsd_byp_clk_mux_ck",
414         .parent         = &sys_clkin_ck,
415         .clksel         = core_hsd_byp_clk_mux_sel,
416         .init           = &omap2_init_clksel_parent,
417         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
418         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
419         .ops            = &clkops_null,
420         .recalc         = &omap2_clksel_recalc,
421 };
422
423 /* DPLL_CORE */
424 static struct dpll_data dpll_core_dd = {
425         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
426         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
427         .clk_ref        = &sys_clkin_ck,
428         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
429         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
430         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
431         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
432         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
433         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
434         .enable_mask    = OMAP4430_DPLL_EN_MASK,
435         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
436         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
437         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
438         .max_divider    = OMAP4430_MAX_DPLL_DIV,
439         .min_divider    = 1,
440 };
441
442
443 static struct clk dpll_core_ck = {
444         .name           = "dpll_core_ck",
445         .parent         = &sys_clkin_ck,
446         .dpll_data      = &dpll_core_dd,
447         .init           = &omap2_init_dpll_parent,
448         .ops            = &clkops_omap3_core_dpll_ops,
449         .recalc         = &omap3_dpll_recalc,
450 };
451
452 static struct clk dpll_core_x2_ck = {
453         .name           = "dpll_core_x2_ck",
454         .parent         = &dpll_core_ck,
455         .flags          = CLOCK_CLKOUTX2,
456         .ops            = &clkops_null,
457         .recalc         = &omap3_clkoutx2_recalc,
458 };
459
460 static const struct clksel dpll_core_m6x2_div[] = {
461         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
462         { .parent = NULL },
463 };
464
465 static struct clk dpll_core_m6x2_ck = {
466         .name           = "dpll_core_m6x2_ck",
467         .parent         = &dpll_core_x2_ck,
468         .clksel         = dpll_core_m6x2_div,
469         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
470         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
471         .ops            = &clkops_omap4_dpllmx_ops,
472         .recalc         = &omap2_clksel_recalc,
473         .round_rate     = &omap2_clksel_round_rate,
474         .set_rate       = &omap2_clksel_set_rate,
475 };
476
477 static const struct clksel dbgclk_mux_sel[] = {
478         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
479         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
480         { .parent = NULL },
481 };
482
483 static struct clk dbgclk_mux_ck = {
484         .name           = "dbgclk_mux_ck",
485         .parent         = &sys_clkin_ck,
486         .ops            = &clkops_null,
487         .recalc         = &followparent_recalc,
488 };
489
490 static const struct clksel dpll_core_m2_div[] = {
491         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
492         { .parent = NULL },
493 };
494
495 static struct clk dpll_core_m2_ck = {
496         .name           = "dpll_core_m2_ck",
497         .parent         = &dpll_core_ck,
498         .clksel         = dpll_core_m2_div,
499         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
500         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
501         .ops            = &clkops_omap4_dpllmx_ops,
502         .recalc         = &omap2_clksel_recalc,
503         .round_rate     = &omap2_clksel_round_rate,
504         .set_rate       = &omap2_clksel_set_rate,
505 };
506
507 static struct clk ddrphy_ck = {
508         .name           = "ddrphy_ck",
509         .parent         = &dpll_core_m2_ck,
510         .ops            = &clkops_null,
511         .fixed_div      = 2,
512         .recalc         = &omap_fixed_divisor_recalc,
513 };
514
515 static struct clk dpll_core_m5x2_ck = {
516         .name           = "dpll_core_m5x2_ck",
517         .parent         = &dpll_core_x2_ck,
518         .clksel         = dpll_core_m6x2_div,
519         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
520         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
521         .ops            = &clkops_omap4_dpllmx_ops,
522         .recalc         = &omap2_clksel_recalc,
523         .round_rate     = &omap2_clksel_round_rate,
524         .set_rate       = &omap2_clksel_set_rate,
525 };
526
527 static const struct clksel div_core_div[] = {
528         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
529         { .parent = NULL },
530 };
531
532 static struct clk div_core_ck = {
533         .name           = "div_core_ck",
534         .parent         = &dpll_core_m5x2_ck,
535         .clksel         = div_core_div,
536         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
537         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
538         .ops            = &clkops_null,
539         .recalc         = &omap2_clksel_recalc,
540         .round_rate     = &omap2_clksel_round_rate,
541         .set_rate       = &omap2_clksel_set_rate,
542 };
543
544 static const struct clksel_rate div4_1to8_rates[] = {
545         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
546         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
547         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
548         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
549         { .div = 0 },
550 };
551
552 static const struct clksel div_iva_hs_clk_div[] = {
553         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
554         { .parent = NULL },
555 };
556
557 static struct clk div_iva_hs_clk = {
558         .name           = "div_iva_hs_clk",
559         .parent         = &dpll_core_m5x2_ck,
560         .clksel         = div_iva_hs_clk_div,
561         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
562         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
563         .ops            = &clkops_null,
564         .recalc         = &omap2_clksel_recalc,
565         .round_rate     = &omap2_clksel_round_rate,
566         .set_rate       = &omap2_clksel_set_rate,
567 };
568
569 static struct clk div_mpu_hs_clk = {
570         .name           = "div_mpu_hs_clk",
571         .parent         = &dpll_core_m5x2_ck,
572         .clksel         = div_iva_hs_clk_div,
573         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
574         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
575         .ops            = &clkops_null,
576         .recalc         = &omap2_clksel_recalc,
577         .round_rate     = &omap2_clksel_round_rate,
578         .set_rate       = &omap2_clksel_set_rate,
579 };
580
581 static struct clk dpll_core_m4x2_ck = {
582         .name           = "dpll_core_m4x2_ck",
583         .parent         = &dpll_core_x2_ck,
584         .clksel         = dpll_core_m6x2_div,
585         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
586         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
587         .ops            = &clkops_omap4_dpllmx_ops,
588         .recalc         = &omap2_clksel_recalc,
589         .round_rate     = &omap2_clksel_round_rate,
590         .set_rate       = &omap2_clksel_set_rate,
591 };
592
593 static struct clk dll_clk_div_ck = {
594         .name           = "dll_clk_div_ck",
595         .parent         = &dpll_core_m4x2_ck,
596         .ops            = &clkops_null,
597         .fixed_div      = 2,
598         .recalc         = &omap_fixed_divisor_recalc,
599 };
600
601 static const struct clksel dpll_abe_m2_div[] = {
602         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
603         { .parent = NULL },
604 };
605
606 static struct clk dpll_abe_m2_ck = {
607         .name           = "dpll_abe_m2_ck",
608         .parent         = &dpll_abe_ck,
609         .clksel         = dpll_abe_m2_div,
610         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
611         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
612         .ops            = &clkops_omap4_dpllmx_ops,
613         .recalc         = &omap2_clksel_recalc,
614         .round_rate     = &omap2_clksel_round_rate,
615         .set_rate       = &omap2_clksel_set_rate,
616 };
617
618 static struct clk dpll_core_m3x2_ck = {
619         .name           = "dpll_core_m3x2_ck",
620         .parent         = &dpll_core_x2_ck,
621         .clksel         = dpll_core_m6x2_div,
622         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
623         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
624         .ops            = &clkops_omap2_dflt,
625         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
626         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
627         .recalc         = &omap2_clksel_recalc,
628         .round_rate     = &omap2_clksel_round_rate,
629         .set_rate       = &omap2_clksel_set_rate,
630 };
631
632 static struct clk dpll_core_m7x2_ck = {
633         .name           = "dpll_core_m7x2_ck",
634         .parent         = &dpll_core_x2_ck,
635         .clksel         = dpll_core_m6x2_div,
636         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
637         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
638         .ops            = &clkops_omap4_dpllmx_ops,
639         .recalc         = &omap2_clksel_recalc,
640         .round_rate     = &omap2_clksel_round_rate,
641         .set_rate       = &omap2_clksel_set_rate,
642 };
643
644 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
645         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
646         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
647         { .parent = NULL },
648 };
649
650 static struct clk iva_hsd_byp_clk_mux_ck = {
651         .name           = "iva_hsd_byp_clk_mux_ck",
652         .parent         = &sys_clkin_ck,
653         .clksel         = iva_hsd_byp_clk_mux_sel,
654         .init           = &omap2_init_clksel_parent,
655         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
656         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
657         .ops            = &clkops_null,
658         .recalc         = &omap2_clksel_recalc,
659 };
660
661 /* DPLL_IVA */
662 static struct dpll_data dpll_iva_dd = {
663         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
664         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
665         .clk_ref        = &sys_clkin_ck,
666         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
667         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
668         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
669         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
670         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
671         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
672         .enable_mask    = OMAP4430_DPLL_EN_MASK,
673         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
674         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
675         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
676         .max_divider    = OMAP4430_MAX_DPLL_DIV,
677         .min_divider    = 1,
678 };
679
680
681 static struct clk dpll_iva_ck = {
682         .name           = "dpll_iva_ck",
683         .parent         = &sys_clkin_ck,
684         .dpll_data      = &dpll_iva_dd,
685         .init           = &omap2_init_dpll_parent,
686         .ops            = &clkops_omap3_noncore_dpll_ops,
687         .recalc         = &omap3_dpll_recalc,
688         .round_rate     = &omap2_dpll_round_rate,
689         .set_rate       = &omap3_noncore_dpll_set_rate,
690 };
691
692 static struct clk dpll_iva_x2_ck = {
693         .name           = "dpll_iva_x2_ck",
694         .parent         = &dpll_iva_ck,
695         .flags          = CLOCK_CLKOUTX2,
696         .ops            = &clkops_null,
697         .recalc         = &omap3_clkoutx2_recalc,
698 };
699
700 static const struct clksel dpll_iva_m4x2_div[] = {
701         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
702         { .parent = NULL },
703 };
704
705 static struct clk dpll_iva_m4x2_ck = {
706         .name           = "dpll_iva_m4x2_ck",
707         .parent         = &dpll_iva_x2_ck,
708         .clksel         = dpll_iva_m4x2_div,
709         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
710         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
711         .ops            = &clkops_omap4_dpllmx_ops,
712         .recalc         = &omap2_clksel_recalc,
713         .round_rate     = &omap2_clksel_round_rate,
714         .set_rate       = &omap2_clksel_set_rate,
715 };
716
717 static struct clk dpll_iva_m5x2_ck = {
718         .name           = "dpll_iva_m5x2_ck",
719         .parent         = &dpll_iva_x2_ck,
720         .clksel         = dpll_iva_m4x2_div,
721         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
722         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
723         .ops            = &clkops_omap4_dpllmx_ops,
724         .recalc         = &omap2_clksel_recalc,
725         .round_rate     = &omap2_clksel_round_rate,
726         .set_rate       = &omap2_clksel_set_rate,
727 };
728
729 /* DPLL_MPU */
730 static struct dpll_data dpll_mpu_dd = {
731         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
732         .clk_bypass     = &div_mpu_hs_clk,
733         .clk_ref        = &sys_clkin_ck,
734         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
735         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
736         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
737         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
738         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
739         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
740         .enable_mask    = OMAP4430_DPLL_EN_MASK,
741         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
742         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
743         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
744         .max_divider    = OMAP4430_MAX_DPLL_DIV,
745         .min_divider    = 1,
746 };
747
748
749 static struct clk dpll_mpu_ck = {
750         .name           = "dpll_mpu_ck",
751         .parent         = &sys_clkin_ck,
752         .dpll_data      = &dpll_mpu_dd,
753         .init           = &omap2_init_dpll_parent,
754         .ops            = &clkops_omap3_noncore_dpll_ops,
755         .recalc         = &omap3_dpll_recalc,
756         .round_rate     = &omap2_dpll_round_rate,
757         .set_rate       = &omap3_noncore_dpll_set_rate,
758 };
759
760 static const struct clksel dpll_mpu_m2_div[] = {
761         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
762         { .parent = NULL },
763 };
764
765 static struct clk dpll_mpu_m2_ck = {
766         .name           = "dpll_mpu_m2_ck",
767         .parent         = &dpll_mpu_ck,
768         .clksel         = dpll_mpu_m2_div,
769         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
770         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
771         .ops            = &clkops_omap4_dpllmx_ops,
772         .recalc         = &omap2_clksel_recalc,
773         .round_rate     = &omap2_clksel_round_rate,
774         .set_rate       = &omap2_clksel_set_rate,
775 };
776
777 static struct clk per_hs_clk_div_ck = {
778         .name           = "per_hs_clk_div_ck",
779         .parent         = &dpll_abe_m3x2_ck,
780         .ops            = &clkops_null,
781         .fixed_div      = 2,
782         .recalc         = &omap_fixed_divisor_recalc,
783 };
784
785 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
786         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
787         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
788         { .parent = NULL },
789 };
790
791 static struct clk per_hsd_byp_clk_mux_ck = {
792         .name           = "per_hsd_byp_clk_mux_ck",
793         .parent         = &sys_clkin_ck,
794         .clksel         = per_hsd_byp_clk_mux_sel,
795         .init           = &omap2_init_clksel_parent,
796         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
797         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
798         .ops            = &clkops_null,
799         .recalc         = &omap2_clksel_recalc,
800 };
801
802 /* DPLL_PER */
803 static struct dpll_data dpll_per_dd = {
804         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
805         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
806         .clk_ref        = &sys_clkin_ck,
807         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
808         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
809         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
810         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
811         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
812         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
813         .enable_mask    = OMAP4430_DPLL_EN_MASK,
814         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
815         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
816         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
817         .max_divider    = OMAP4430_MAX_DPLL_DIV,
818         .min_divider    = 1,
819 };
820
821
822 static struct clk dpll_per_ck = {
823         .name           = "dpll_per_ck",
824         .parent         = &sys_clkin_ck,
825         .dpll_data      = &dpll_per_dd,
826         .init           = &omap2_init_dpll_parent,
827         .ops            = &clkops_omap3_noncore_dpll_ops,
828         .recalc         = &omap3_dpll_recalc,
829         .round_rate     = &omap2_dpll_round_rate,
830         .set_rate       = &omap3_noncore_dpll_set_rate,
831 };
832
833 static const struct clksel dpll_per_m2_div[] = {
834         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
835         { .parent = NULL },
836 };
837
838 static struct clk dpll_per_m2_ck = {
839         .name           = "dpll_per_m2_ck",
840         .parent         = &dpll_per_ck,
841         .clksel         = dpll_per_m2_div,
842         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
843         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
844         .ops            = &clkops_omap4_dpllmx_ops,
845         .recalc         = &omap2_clksel_recalc,
846         .round_rate     = &omap2_clksel_round_rate,
847         .set_rate       = &omap2_clksel_set_rate,
848 };
849
850 static struct clk dpll_per_x2_ck = {
851         .name           = "dpll_per_x2_ck",
852         .parent         = &dpll_per_ck,
853         .flags          = CLOCK_CLKOUTX2,
854         .ops            = &clkops_omap4_dpllmx_ops,
855         .recalc         = &omap3_clkoutx2_recalc,
856         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
857 };
858
859 static const struct clksel dpll_per_m2x2_div[] = {
860         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
861         { .parent = NULL },
862 };
863
864 static struct clk dpll_per_m2x2_ck = {
865         .name           = "dpll_per_m2x2_ck",
866         .parent         = &dpll_per_x2_ck,
867         .clksel         = dpll_per_m2x2_div,
868         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
869         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
870         .ops            = &clkops_omap4_dpllmx_ops,
871         .recalc         = &omap2_clksel_recalc,
872         .round_rate     = &omap2_clksel_round_rate,
873         .set_rate       = &omap2_clksel_set_rate,
874 };
875
876 static struct clk dpll_per_m3x2_ck = {
877         .name           = "dpll_per_m3x2_ck",
878         .parent         = &dpll_per_x2_ck,
879         .clksel         = dpll_per_m2x2_div,
880         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
881         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
882         .ops            = &clkops_omap2_dflt,
883         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
884         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
885         .recalc         = &omap2_clksel_recalc,
886         .round_rate     = &omap2_clksel_round_rate,
887         .set_rate       = &omap2_clksel_set_rate,
888 };
889
890 static struct clk dpll_per_m4x2_ck = {
891         .name           = "dpll_per_m4x2_ck",
892         .parent         = &dpll_per_x2_ck,
893         .clksel         = dpll_per_m2x2_div,
894         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
895         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
896         .ops            = &clkops_omap4_dpllmx_ops,
897         .recalc         = &omap2_clksel_recalc,
898         .round_rate     = &omap2_clksel_round_rate,
899         .set_rate       = &omap2_clksel_set_rate,
900 };
901
902 static struct clk dpll_per_m5x2_ck = {
903         .name           = "dpll_per_m5x2_ck",
904         .parent         = &dpll_per_x2_ck,
905         .clksel         = dpll_per_m2x2_div,
906         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
907         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
908         .ops            = &clkops_omap4_dpllmx_ops,
909         .recalc         = &omap2_clksel_recalc,
910         .round_rate     = &omap2_clksel_round_rate,
911         .set_rate       = &omap2_clksel_set_rate,
912 };
913
914 static struct clk dpll_per_m6x2_ck = {
915         .name           = "dpll_per_m6x2_ck",
916         .parent         = &dpll_per_x2_ck,
917         .clksel         = dpll_per_m2x2_div,
918         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
919         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
920         .ops            = &clkops_omap4_dpllmx_ops,
921         .recalc         = &omap2_clksel_recalc,
922         .round_rate     = &omap2_clksel_round_rate,
923         .set_rate       = &omap2_clksel_set_rate,
924 };
925
926 static struct clk dpll_per_m7x2_ck = {
927         .name           = "dpll_per_m7x2_ck",
928         .parent         = &dpll_per_x2_ck,
929         .clksel         = dpll_per_m2x2_div,
930         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
931         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
932         .ops            = &clkops_omap4_dpllmx_ops,
933         .recalc         = &omap2_clksel_recalc,
934         .round_rate     = &omap2_clksel_round_rate,
935         .set_rate       = &omap2_clksel_set_rate,
936 };
937
938 /* DPLL_UNIPRO */
939 static struct dpll_data dpll_unipro_dd = {
940         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
941         .clk_bypass     = &sys_clkin_ck,
942         .clk_ref        = &sys_clkin_ck,
943         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
944         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
945         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
946         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
947         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
948         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
949         .enable_mask    = OMAP4430_DPLL_EN_MASK,
950         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
951         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
952         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
953         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
954         .max_divider    = OMAP4430_MAX_DPLL_DIV,
955         .min_divider    = 1,
956 };
957
958
959 static struct clk dpll_unipro_ck = {
960         .name           = "dpll_unipro_ck",
961         .parent         = &sys_clkin_ck,
962         .dpll_data      = &dpll_unipro_dd,
963         .init           = &omap2_init_dpll_parent,
964         .ops            = &clkops_omap3_noncore_dpll_ops,
965         .recalc         = &omap3_dpll_recalc,
966         .round_rate     = &omap2_dpll_round_rate,
967         .set_rate       = &omap3_noncore_dpll_set_rate,
968 };
969
970 static struct clk dpll_unipro_x2_ck = {
971         .name           = "dpll_unipro_x2_ck",
972         .parent         = &dpll_unipro_ck,
973         .flags          = CLOCK_CLKOUTX2,
974         .ops            = &clkops_null,
975         .recalc         = &omap3_clkoutx2_recalc,
976 };
977
978 static const struct clksel dpll_unipro_m2x2_div[] = {
979         { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
980         { .parent = NULL },
981 };
982
983 static struct clk dpll_unipro_m2x2_ck = {
984         .name           = "dpll_unipro_m2x2_ck",
985         .parent         = &dpll_unipro_x2_ck,
986         .clksel         = dpll_unipro_m2x2_div,
987         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
988         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
989         .ops            = &clkops_omap4_dpllmx_ops,
990         .recalc         = &omap2_clksel_recalc,
991         .round_rate     = &omap2_clksel_round_rate,
992         .set_rate       = &omap2_clksel_set_rate,
993 };
994
995 static struct clk usb_hs_clk_div_ck = {
996         .name           = "usb_hs_clk_div_ck",
997         .parent         = &dpll_abe_m3x2_ck,
998         .ops            = &clkops_null,
999         .fixed_div      = 3,
1000         .recalc         = &omap_fixed_divisor_recalc,
1001 };
1002
1003 /* DPLL_USB */
1004 static struct dpll_data dpll_usb_dd = {
1005         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
1006         .clk_bypass     = &usb_hs_clk_div_ck,
1007         .flags          = DPLL_J_TYPE,
1008         .clk_ref        = &sys_clkin_ck,
1009         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
1010         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1011         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
1012         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
1013         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
1014         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
1015         .enable_mask    = OMAP4430_DPLL_EN_MASK,
1016         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
1017         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
1018         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
1019         .max_divider    = OMAP4430_MAX_DPLL_DIV,
1020         .min_divider    = 1,
1021 };
1022
1023
1024 static struct clk dpll_usb_ck = {
1025         .name           = "dpll_usb_ck",
1026         .parent         = &sys_clkin_ck,
1027         .dpll_data      = &dpll_usb_dd,
1028         .init           = &omap2_init_dpll_parent,
1029         .ops            = &clkops_omap3_noncore_dpll_ops,
1030         .recalc         = &omap3_dpll_recalc,
1031         .round_rate     = &omap2_dpll_round_rate,
1032         .set_rate       = &omap3_noncore_dpll_set_rate,
1033 };
1034
1035 static struct clk dpll_usb_clkdcoldo_ck = {
1036         .name           = "dpll_usb_clkdcoldo_ck",
1037         .parent         = &dpll_usb_ck,
1038         .ops            = &clkops_omap4_dpllmx_ops,
1039         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
1040         .recalc         = &followparent_recalc,
1041 };
1042
1043 static const struct clksel dpll_usb_m2_div[] = {
1044         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
1045         { .parent = NULL },
1046 };
1047
1048 static struct clk dpll_usb_m2_ck = {
1049         .name           = "dpll_usb_m2_ck",
1050         .parent         = &dpll_usb_ck,
1051         .clksel         = dpll_usb_m2_div,
1052         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
1053         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1054         .ops            = &clkops_omap4_dpllmx_ops,
1055         .recalc         = &omap2_clksel_recalc,
1056         .round_rate     = &omap2_clksel_round_rate,
1057         .set_rate       = &omap2_clksel_set_rate,
1058 };
1059
1060 static const struct clksel ducati_clk_mux_sel[] = {
1061         { .parent = &div_core_ck, .rates = div_1_0_rates },
1062         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1063         { .parent = NULL },
1064 };
1065
1066 static struct clk ducati_clk_mux_ck = {
1067         .name           = "ducati_clk_mux_ck",
1068         .parent         = &div_core_ck,
1069         .clksel         = ducati_clk_mux_sel,
1070         .init           = &omap2_init_clksel_parent,
1071         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1072         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1073         .ops            = &clkops_null,
1074         .recalc         = &omap2_clksel_recalc,
1075 };
1076
1077 static struct clk func_12m_fclk = {
1078         .name           = "func_12m_fclk",
1079         .parent         = &dpll_per_m2x2_ck,
1080         .ops            = &clkops_null,
1081         .fixed_div      = 16,
1082         .recalc         = &omap_fixed_divisor_recalc,
1083 };
1084
1085 static struct clk func_24m_clk = {
1086         .name           = "func_24m_clk",
1087         .parent         = &dpll_per_m2_ck,
1088         .ops            = &clkops_null,
1089         .fixed_div      = 4,
1090         .recalc         = &omap_fixed_divisor_recalc,
1091 };
1092
1093 static struct clk func_24mc_fclk = {
1094         .name           = "func_24mc_fclk",
1095         .parent         = &dpll_per_m2x2_ck,
1096         .ops            = &clkops_null,
1097         .fixed_div      = 8,
1098         .recalc         = &omap_fixed_divisor_recalc,
1099 };
1100
1101 static const struct clksel_rate div2_4to8_rates[] = {
1102         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1103         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1104         { .div = 0 },
1105 };
1106
1107 static const struct clksel func_48m_fclk_div[] = {
1108         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1109         { .parent = NULL },
1110 };
1111
1112 static struct clk func_48m_fclk = {
1113         .name           = "func_48m_fclk",
1114         .parent         = &dpll_per_m2x2_ck,
1115         .clksel         = func_48m_fclk_div,
1116         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1117         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1118         .ops            = &clkops_null,
1119         .recalc         = &omap2_clksel_recalc,
1120         .round_rate     = &omap2_clksel_round_rate,
1121         .set_rate       = &omap2_clksel_set_rate,
1122 };
1123
1124 static struct clk func_48mc_fclk = {
1125         .name           = "func_48mc_fclk",
1126         .parent         = &dpll_per_m2x2_ck,
1127         .ops            = &clkops_null,
1128         .fixed_div      = 4,
1129         .recalc         = &omap_fixed_divisor_recalc,
1130 };
1131
1132 static const struct clksel_rate div2_2to4_rates[] = {
1133         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1134         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1135         { .div = 0 },
1136 };
1137
1138 static const struct clksel func_64m_fclk_div[] = {
1139         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1140         { .parent = NULL },
1141 };
1142
1143 static struct clk func_64m_fclk = {
1144         .name           = "func_64m_fclk",
1145         .parent         = &dpll_per_m4x2_ck,
1146         .clksel         = func_64m_fclk_div,
1147         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1148         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1149         .ops            = &clkops_null,
1150         .recalc         = &omap2_clksel_recalc,
1151         .round_rate     = &omap2_clksel_round_rate,
1152         .set_rate       = &omap2_clksel_set_rate,
1153 };
1154
1155 static const struct clksel func_96m_fclk_div[] = {
1156         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1157         { .parent = NULL },
1158 };
1159
1160 static struct clk func_96m_fclk = {
1161         .name           = "func_96m_fclk",
1162         .parent         = &dpll_per_m2x2_ck,
1163         .clksel         = func_96m_fclk_div,
1164         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1165         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1166         .ops            = &clkops_null,
1167         .recalc         = &omap2_clksel_recalc,
1168         .round_rate     = &omap2_clksel_round_rate,
1169         .set_rate       = &omap2_clksel_set_rate,
1170 };
1171
1172 static const struct clksel hsmmc6_fclk_sel[] = {
1173         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1174         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1175         { .parent = NULL },
1176 };
1177
1178 static struct clk hsmmc6_fclk = {
1179         .name           = "hsmmc6_fclk",
1180         .parent         = &func_64m_fclk,
1181         .ops            = &clkops_null,
1182         .recalc         = &followparent_recalc,
1183 };
1184
1185 static const struct clksel_rate div2_1to8_rates[] = {
1186         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1187         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1188         { .div = 0 },
1189 };
1190
1191 static const struct clksel init_60m_fclk_div[] = {
1192         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1193         { .parent = NULL },
1194 };
1195
1196 static struct clk init_60m_fclk = {
1197         .name           = "init_60m_fclk",
1198         .parent         = &dpll_usb_m2_ck,
1199         .clksel         = init_60m_fclk_div,
1200         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1201         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1202         .ops            = &clkops_null,
1203         .recalc         = &omap2_clksel_recalc,
1204         .round_rate     = &omap2_clksel_round_rate,
1205         .set_rate       = &omap2_clksel_set_rate,
1206 };
1207
1208 static const struct clksel l3_div_div[] = {
1209         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1210         { .parent = NULL },
1211 };
1212
1213 static struct clk l3_div_ck = {
1214         .name           = "l3_div_ck",
1215         .parent         = &div_core_ck,
1216         .clksel         = l3_div_div,
1217         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1218         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1219         .ops            = &clkops_null,
1220         .recalc         = &omap2_clksel_recalc,
1221         .round_rate     = &omap2_clksel_round_rate,
1222         .set_rate       = &omap2_clksel_set_rate,
1223 };
1224
1225 static const struct clksel l4_div_div[] = {
1226         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1227         { .parent = NULL },
1228 };
1229
1230 static struct clk l4_div_ck = {
1231         .name           = "l4_div_ck",
1232         .parent         = &l3_div_ck,
1233         .clksel         = l4_div_div,
1234         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1235         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1236         .ops            = &clkops_null,
1237         .recalc         = &omap2_clksel_recalc,
1238         .round_rate     = &omap2_clksel_round_rate,
1239         .set_rate       = &omap2_clksel_set_rate,
1240 };
1241
1242 static struct clk lp_clk_div_ck = {
1243         .name           = "lp_clk_div_ck",
1244         .parent         = &dpll_abe_m2x2_ck,
1245         .ops            = &clkops_null,
1246         .fixed_div      = 16,
1247         .recalc         = &omap_fixed_divisor_recalc,
1248 };
1249
1250 static const struct clksel l4_wkup_clk_mux_sel[] = {
1251         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1252         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1253         { .parent = NULL },
1254 };
1255
1256 static struct clk l4_wkup_clk_mux_ck = {
1257         .name           = "l4_wkup_clk_mux_ck",
1258         .parent         = &sys_clkin_ck,
1259         .clksel         = l4_wkup_clk_mux_sel,
1260         .init           = &omap2_init_clksel_parent,
1261         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1262         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1263         .ops            = &clkops_null,
1264         .recalc         = &omap2_clksel_recalc,
1265 };
1266
1267 static const struct clksel per_abe_nc_fclk_div[] = {
1268         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1269         { .parent = NULL },
1270 };
1271
1272 static struct clk per_abe_nc_fclk = {
1273         .name           = "per_abe_nc_fclk",
1274         .parent         = &dpll_abe_m2_ck,
1275         .clksel         = per_abe_nc_fclk_div,
1276         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1277         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1278         .ops            = &clkops_null,
1279         .recalc         = &omap2_clksel_recalc,
1280         .round_rate     = &omap2_clksel_round_rate,
1281         .set_rate       = &omap2_clksel_set_rate,
1282 };
1283
1284 static const struct clksel mcasp2_fclk_sel[] = {
1285         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1286         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1287         { .parent = NULL },
1288 };
1289
1290 static struct clk mcasp2_fclk = {
1291         .name           = "mcasp2_fclk",
1292         .parent         = &func_96m_fclk,
1293         .ops            = &clkops_null,
1294         .recalc         = &followparent_recalc,
1295 };
1296
1297 static struct clk mcasp3_fclk = {
1298         .name           = "mcasp3_fclk",
1299         .parent         = &func_96m_fclk,
1300         .ops            = &clkops_null,
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 static struct clk ocp_abe_iclk = {
1305         .name           = "ocp_abe_iclk",
1306         .parent         = &aess_fclk,
1307         .ops            = &clkops_null,
1308         .recalc         = &followparent_recalc,
1309 };
1310
1311 static struct clk per_abe_24m_fclk = {
1312         .name           = "per_abe_24m_fclk",
1313         .parent         = &dpll_abe_m2_ck,
1314         .ops            = &clkops_null,
1315         .fixed_div      = 4,
1316         .recalc         = &omap_fixed_divisor_recalc,
1317 };
1318
1319 static const struct clksel pmd_stm_clock_mux_sel[] = {
1320         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1321         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1322         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1323         { .parent = NULL },
1324 };
1325
1326 static struct clk pmd_stm_clock_mux_ck = {
1327         .name           = "pmd_stm_clock_mux_ck",
1328         .parent         = &sys_clkin_ck,
1329         .ops            = &clkops_null,
1330         .recalc         = &followparent_recalc,
1331 };
1332
1333 static struct clk pmd_trace_clk_mux_ck = {
1334         .name           = "pmd_trace_clk_mux_ck",
1335         .parent         = &sys_clkin_ck,
1336         .ops            = &clkops_null,
1337         .recalc         = &followparent_recalc,
1338 };
1339
1340 static const struct clksel syc_clk_div_div[] = {
1341         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1342         { .parent = NULL },
1343 };
1344
1345 static struct clk syc_clk_div_ck = {
1346         .name           = "syc_clk_div_ck",
1347         .parent         = &sys_clkin_ck,
1348         .clksel         = syc_clk_div_div,
1349         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1350         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1351         .ops            = &clkops_null,
1352         .recalc         = &omap2_clksel_recalc,
1353         .round_rate     = &omap2_clksel_round_rate,
1354         .set_rate       = &omap2_clksel_set_rate,
1355 };
1356
1357 /* Leaf clocks controlled by modules */
1358
1359 static struct clk aes1_fck = {
1360         .name           = "aes1_fck",
1361         .ops            = &clkops_omap2_dflt,
1362         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1363         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1364         .clkdm_name     = "l4_secure_clkdm",
1365         .parent         = &l3_div_ck,
1366         .recalc         = &followparent_recalc,
1367 };
1368
1369 static struct clk aes2_fck = {
1370         .name           = "aes2_fck",
1371         .ops            = &clkops_omap2_dflt,
1372         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1373         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1374         .clkdm_name     = "l4_secure_clkdm",
1375         .parent         = &l3_div_ck,
1376         .recalc         = &followparent_recalc,
1377 };
1378
1379 static struct clk aess_fck = {
1380         .name           = "aess_fck",
1381         .ops            = &clkops_omap2_dflt,
1382         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1383         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1384         .clkdm_name     = "abe_clkdm",
1385         .parent         = &aess_fclk,
1386         .recalc         = &followparent_recalc,
1387 };
1388
1389 static struct clk bandgap_fclk = {
1390         .name           = "bandgap_fclk",
1391         .ops            = &clkops_omap2_dflt,
1392         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1393         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1394         .clkdm_name     = "l4_wkup_clkdm",
1395         .parent         = &sys_32k_ck,
1396         .recalc         = &followparent_recalc,
1397 };
1398
1399 static struct clk des3des_fck = {
1400         .name           = "des3des_fck",
1401         .ops            = &clkops_omap2_dflt,
1402         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1403         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1404         .clkdm_name     = "l4_secure_clkdm",
1405         .parent         = &l4_div_ck,
1406         .recalc         = &followparent_recalc,
1407 };
1408
1409 static const struct clksel dmic_sync_mux_sel[] = {
1410         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1411         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1412         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1413         { .parent = NULL },
1414 };
1415
1416 static struct clk dmic_sync_mux_ck = {
1417         .name           = "dmic_sync_mux_ck",
1418         .parent         = &abe_24m_fclk,
1419         .clksel         = dmic_sync_mux_sel,
1420         .init           = &omap2_init_clksel_parent,
1421         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1422         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1423         .ops            = &clkops_null,
1424         .recalc         = &omap2_clksel_recalc,
1425 };
1426
1427 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1428         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1429         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1430         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1431         { .parent = NULL },
1432 };
1433
1434 /* Merged func_dmic_abe_gfclk into dmic */
1435 static struct clk dmic_fck = {
1436         .name           = "dmic_fck",
1437         .parent         = &dmic_sync_mux_ck,
1438         .clksel         = func_dmic_abe_gfclk_sel,
1439         .init           = &omap2_init_clksel_parent,
1440         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1441         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1442         .ops            = &clkops_omap2_dflt,
1443         .recalc         = &omap2_clksel_recalc,
1444         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1445         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1446         .clkdm_name     = "abe_clkdm",
1447 };
1448
1449 static struct clk dsp_fck = {
1450         .name           = "dsp_fck",
1451         .ops            = &clkops_omap2_dflt,
1452         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1453         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1454         .clkdm_name     = "tesla_clkdm",
1455         .parent         = &dpll_iva_m4x2_ck,
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 static struct clk dss_sys_clk = {
1460         .name           = "dss_sys_clk",
1461         .ops            = &clkops_omap2_dflt,
1462         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1463         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1464         .clkdm_name     = "l3_dss_clkdm",
1465         .parent         = &syc_clk_div_ck,
1466         .recalc         = &followparent_recalc,
1467 };
1468
1469 static struct clk dss_tv_clk = {
1470         .name           = "dss_tv_clk",
1471         .ops            = &clkops_omap2_dflt,
1472         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1473         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1474         .clkdm_name     = "l3_dss_clkdm",
1475         .parent         = &extalt_clkin_ck,
1476         .recalc         = &followparent_recalc,
1477 };
1478
1479 static struct clk dss_dss_clk = {
1480         .name           = "dss_dss_clk",
1481         .ops            = &clkops_omap2_dflt,
1482         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1483         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1484         .clkdm_name     = "l3_dss_clkdm",
1485         .parent         = &dpll_per_m5x2_ck,
1486         .recalc         = &followparent_recalc,
1487 };
1488
1489 static const struct clksel_rate div3_8to32_rates[] = {
1490         { .div = 8, .val = 0, .flags = RATE_IN_44XX },
1491         { .div = 16, .val = 1, .flags = RATE_IN_44XX },
1492         { .div = 32, .val = 2, .flags = RATE_IN_44XX },
1493         { .div = 0 },
1494 };
1495
1496 static const struct clksel div_ts_div[] = {
1497         { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1498         { .parent = NULL },
1499 };
1500
1501 static struct clk div_ts_ck = {
1502         .name           = "div_ts_ck",
1503         .parent         = &l4_wkup_clk_mux_ck,
1504         .clksel         = div_ts_div,
1505         .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1506         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1507         .ops            = &clkops_null,
1508         .recalc         = &omap2_clksel_recalc,
1509         .round_rate     = &omap2_clksel_round_rate,
1510         .set_rate       = &omap2_clksel_set_rate,
1511 };
1512
1513 static struct clk bandgap_ts_fclk = {
1514         .name           = "bandgap_ts_fclk",
1515         .ops            = &clkops_omap2_dflt,
1516         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1517         .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1518         .clkdm_name     = "l4_wkup_clkdm",
1519         .parent         = &div_ts_ck,
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 static struct clk dss_48mhz_clk = {
1524         .name           = "dss_48mhz_clk",
1525         .ops            = &clkops_omap2_dflt,
1526         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1527         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1528         .clkdm_name     = "l3_dss_clkdm",
1529         .parent         = &func_48mc_fclk,
1530         .recalc         = &followparent_recalc,
1531 };
1532
1533 static struct clk dss_fck = {
1534         .name           = "dss_fck",
1535         .ops            = &clkops_omap2_dflt,
1536         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1537         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1538         .clkdm_name     = "l3_dss_clkdm",
1539         .parent         = &l3_div_ck,
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk efuse_ctrl_cust_fck = {
1544         .name           = "efuse_ctrl_cust_fck",
1545         .ops            = &clkops_omap2_dflt,
1546         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1547         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1548         .clkdm_name     = "l4_cefuse_clkdm",
1549         .parent         = &sys_clkin_ck,
1550         .recalc         = &followparent_recalc,
1551 };
1552
1553 static struct clk emif1_fck = {
1554         .name           = "emif1_fck",
1555         .ops            = &clkops_omap2_dflt,
1556         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1557         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1558         .flags          = ENABLE_ON_INIT,
1559         .clkdm_name     = "l3_emif_clkdm",
1560         .parent         = &ddrphy_ck,
1561         .recalc         = &followparent_recalc,
1562 };
1563
1564 static struct clk emif2_fck = {
1565         .name           = "emif2_fck",
1566         .ops            = &clkops_omap2_dflt,
1567         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1568         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1569         .flags          = ENABLE_ON_INIT,
1570         .clkdm_name     = "l3_emif_clkdm",
1571         .parent         = &ddrphy_ck,
1572         .recalc         = &followparent_recalc,
1573 };
1574
1575 static const struct clksel fdif_fclk_div[] = {
1576         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1577         { .parent = NULL },
1578 };
1579
1580 /* Merged fdif_fclk into fdif */
1581 static struct clk fdif_fck = {
1582         .name           = "fdif_fck",
1583         .parent         = &dpll_per_m4x2_ck,
1584         .clksel         = fdif_fclk_div,
1585         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1586         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1587         .ops            = &clkops_omap2_dflt,
1588         .recalc         = &omap2_clksel_recalc,
1589         .round_rate     = &omap2_clksel_round_rate,
1590         .set_rate       = &omap2_clksel_set_rate,
1591         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1592         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1593         .clkdm_name     = "iss_clkdm",
1594 };
1595
1596 static struct clk fpka_fck = {
1597         .name           = "fpka_fck",
1598         .ops            = &clkops_omap2_dflt,
1599         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1600         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1601         .clkdm_name     = "l4_secure_clkdm",
1602         .parent         = &l4_div_ck,
1603         .recalc         = &followparent_recalc,
1604 };
1605
1606 static struct clk gpio1_dbclk = {
1607         .name           = "gpio1_dbclk",
1608         .ops            = &clkops_omap2_dflt,
1609         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1610         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1611         .clkdm_name     = "l4_wkup_clkdm",
1612         .parent         = &sys_32k_ck,
1613         .recalc         = &followparent_recalc,
1614 };
1615
1616 static struct clk gpio1_ick = {
1617         .name           = "gpio1_ick",
1618         .ops            = &clkops_omap2_dflt,
1619         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1620         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1621         .clkdm_name     = "l4_wkup_clkdm",
1622         .parent         = &l4_wkup_clk_mux_ck,
1623         .recalc         = &followparent_recalc,
1624 };
1625
1626 static struct clk gpio2_dbclk = {
1627         .name           = "gpio2_dbclk",
1628         .ops            = &clkops_omap2_dflt,
1629         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1630         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1631         .clkdm_name     = "l4_per_clkdm",
1632         .parent         = &sys_32k_ck,
1633         .recalc         = &followparent_recalc,
1634 };
1635
1636 static struct clk gpio2_ick = {
1637         .name           = "gpio2_ick",
1638         .ops            = &clkops_omap2_dflt,
1639         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1640         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1641         .clkdm_name     = "l4_per_clkdm",
1642         .parent         = &l4_div_ck,
1643         .recalc         = &followparent_recalc,
1644 };
1645
1646 static struct clk gpio3_dbclk = {
1647         .name           = "gpio3_dbclk",
1648         .ops            = &clkops_omap2_dflt,
1649         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1650         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1651         .clkdm_name     = "l4_per_clkdm",
1652         .parent         = &sys_32k_ck,
1653         .recalc         = &followparent_recalc,
1654 };
1655
1656 static struct clk gpio3_ick = {
1657         .name           = "gpio3_ick",
1658         .ops            = &clkops_omap2_dflt,
1659         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1660         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1661         .clkdm_name     = "l4_per_clkdm",
1662         .parent         = &l4_div_ck,
1663         .recalc         = &followparent_recalc,
1664 };
1665
1666 static struct clk gpio4_dbclk = {
1667         .name           = "gpio4_dbclk",
1668         .ops            = &clkops_omap2_dflt,
1669         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1670         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1671         .clkdm_name     = "l4_per_clkdm",
1672         .parent         = &sys_32k_ck,
1673         .recalc         = &followparent_recalc,
1674 };
1675
1676 static struct clk gpio4_ick = {
1677         .name           = "gpio4_ick",
1678         .ops            = &clkops_omap2_dflt,
1679         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1680         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1681         .clkdm_name     = "l4_per_clkdm",
1682         .parent         = &l4_div_ck,
1683         .recalc         = &followparent_recalc,
1684 };
1685
1686 static struct clk gpio5_dbclk = {
1687         .name           = "gpio5_dbclk",
1688         .ops            = &clkops_omap2_dflt,
1689         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1690         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1691         .clkdm_name     = "l4_per_clkdm",
1692         .parent         = &sys_32k_ck,
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 static struct clk gpio5_ick = {
1697         .name           = "gpio5_ick",
1698         .ops            = &clkops_omap2_dflt,
1699         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1700         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1701         .clkdm_name     = "l4_per_clkdm",
1702         .parent         = &l4_div_ck,
1703         .recalc         = &followparent_recalc,
1704 };
1705
1706 static struct clk gpio6_dbclk = {
1707         .name           = "gpio6_dbclk",
1708         .ops            = &clkops_omap2_dflt,
1709         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1710         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1711         .clkdm_name     = "l4_per_clkdm",
1712         .parent         = &sys_32k_ck,
1713         .recalc         = &followparent_recalc,
1714 };
1715
1716 static struct clk gpio6_ick = {
1717         .name           = "gpio6_ick",
1718         .ops            = &clkops_omap2_dflt,
1719         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1720         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1721         .clkdm_name     = "l4_per_clkdm",
1722         .parent         = &l4_div_ck,
1723         .recalc         = &followparent_recalc,
1724 };
1725
1726 static struct clk gpmc_ick = {
1727         .name           = "gpmc_ick",
1728         .ops            = &clkops_omap2_dflt,
1729         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1730         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1731         .clkdm_name     = "l3_2_clkdm",
1732         .parent         = &l3_div_ck,
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static const struct clksel sgx_clk_mux_sel[] = {
1737         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1738         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1739         { .parent = NULL },
1740 };
1741
1742 /* Merged sgx_clk_mux into gpu */
1743 static struct clk gpu_fck = {
1744         .name           = "gpu_fck",
1745         .parent         = &dpll_core_m7x2_ck,
1746         .clksel         = sgx_clk_mux_sel,
1747         .init           = &omap2_init_clksel_parent,
1748         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1749         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1750         .ops            = &clkops_omap2_dflt,
1751         .recalc         = &omap2_clksel_recalc,
1752         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1753         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1754         .clkdm_name     = "l3_gfx_clkdm",
1755 };
1756
1757 static struct clk hdq1w_fck = {
1758         .name           = "hdq1w_fck",
1759         .ops            = &clkops_omap2_dflt,
1760         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1761         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1762         .clkdm_name     = "l4_per_clkdm",
1763         .parent         = &func_12m_fclk,
1764         .recalc         = &followparent_recalc,
1765 };
1766
1767 static const struct clksel hsi_fclk_div[] = {
1768         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1769         { .parent = NULL },
1770 };
1771
1772 /* Merged hsi_fclk into hsi */
1773 static struct clk hsi_fck = {
1774         .name           = "hsi_fck",
1775         .parent         = &dpll_per_m2x2_ck,
1776         .clksel         = hsi_fclk_div,
1777         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1778         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1779         .ops            = &clkops_omap2_dflt,
1780         .recalc         = &omap2_clksel_recalc,
1781         .round_rate     = &omap2_clksel_round_rate,
1782         .set_rate       = &omap2_clksel_set_rate,
1783         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1784         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1785         .clkdm_name     = "l3_init_clkdm",
1786 };
1787
1788 static struct clk i2c1_fck = {
1789         .name           = "i2c1_fck",
1790         .ops            = &clkops_omap2_dflt,
1791         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1792         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1793         .clkdm_name     = "l4_per_clkdm",
1794         .parent         = &func_96m_fclk,
1795         .recalc         = &followparent_recalc,
1796 };
1797
1798 static struct clk i2c2_fck = {
1799         .name           = "i2c2_fck",
1800         .ops            = &clkops_omap2_dflt,
1801         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1802         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1803         .clkdm_name     = "l4_per_clkdm",
1804         .parent         = &func_96m_fclk,
1805         .recalc         = &followparent_recalc,
1806 };
1807
1808 static struct clk i2c3_fck = {
1809         .name           = "i2c3_fck",
1810         .ops            = &clkops_omap2_dflt,
1811         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1812         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1813         .clkdm_name     = "l4_per_clkdm",
1814         .parent         = &func_96m_fclk,
1815         .recalc         = &followparent_recalc,
1816 };
1817
1818 static struct clk i2c4_fck = {
1819         .name           = "i2c4_fck",
1820         .ops            = &clkops_omap2_dflt,
1821         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1822         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1823         .clkdm_name     = "l4_per_clkdm",
1824         .parent         = &func_96m_fclk,
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk ipu_fck = {
1829         .name           = "ipu_fck",
1830         .ops            = &clkops_omap2_dflt,
1831         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1832         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1833         .clkdm_name     = "ducati_clkdm",
1834         .parent         = &ducati_clk_mux_ck,
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk iss_ctrlclk = {
1839         .name           = "iss_ctrlclk",
1840         .ops            = &clkops_omap2_dflt,
1841         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1842         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1843         .clkdm_name     = "iss_clkdm",
1844         .parent         = &func_96m_fclk,
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk iss_fck = {
1849         .name           = "iss_fck",
1850         .ops            = &clkops_omap2_dflt,
1851         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1852         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1853         .clkdm_name     = "iss_clkdm",
1854         .parent         = &ducati_clk_mux_ck,
1855         .recalc         = &followparent_recalc,
1856 };
1857
1858 static struct clk iva_fck = {
1859         .name           = "iva_fck",
1860         .ops            = &clkops_omap2_dflt,
1861         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1862         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1863         .clkdm_name     = "ivahd_clkdm",
1864         .parent         = &dpll_iva_m5x2_ck,
1865         .recalc         = &followparent_recalc,
1866 };
1867
1868 static struct clk kbd_fck = {
1869         .name           = "kbd_fck",
1870         .ops            = &clkops_omap2_dflt,
1871         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1872         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1873         .clkdm_name     = "l4_wkup_clkdm",
1874         .parent         = &sys_32k_ck,
1875         .recalc         = &followparent_recalc,
1876 };
1877
1878 static struct clk l3_instr_ick = {
1879         .name           = "l3_instr_ick",
1880         .ops            = &clkops_omap2_dflt,
1881         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1882         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1883         .clkdm_name     = "l3_instr_clkdm",
1884         .flags          = ENABLE_ON_INIT,
1885         .parent         = &l3_div_ck,
1886         .recalc         = &followparent_recalc,
1887 };
1888
1889 static struct clk l3_main_3_ick = {
1890         .name           = "l3_main_3_ick",
1891         .ops            = &clkops_omap2_dflt,
1892         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1893         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1894         .clkdm_name     = "l3_instr_clkdm",
1895         .flags          = ENABLE_ON_INIT,
1896         .parent         = &l3_div_ck,
1897         .recalc         = &followparent_recalc,
1898 };
1899
1900 static struct clk mcasp_sync_mux_ck = {
1901         .name           = "mcasp_sync_mux_ck",
1902         .parent         = &abe_24m_fclk,
1903         .clksel         = dmic_sync_mux_sel,
1904         .init           = &omap2_init_clksel_parent,
1905         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1906         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1907         .ops            = &clkops_null,
1908         .recalc         = &omap2_clksel_recalc,
1909 };
1910
1911 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1912         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1913         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1914         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1915         { .parent = NULL },
1916 };
1917
1918 /* Merged func_mcasp_abe_gfclk into mcasp */
1919 static struct clk mcasp_fck = {
1920         .name           = "mcasp_fck",
1921         .parent         = &mcasp_sync_mux_ck,
1922         .clksel         = func_mcasp_abe_gfclk_sel,
1923         .init           = &omap2_init_clksel_parent,
1924         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1925         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1926         .ops            = &clkops_omap2_dflt,
1927         .recalc         = &omap2_clksel_recalc,
1928         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1929         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1930         .clkdm_name     = "abe_clkdm",
1931 };
1932
1933 static struct clk mcbsp1_sync_mux_ck = {
1934         .name           = "mcbsp1_sync_mux_ck",
1935         .parent         = &abe_24m_fclk,
1936         .clksel         = dmic_sync_mux_sel,
1937         .init           = &omap2_init_clksel_parent,
1938         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1939         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1940         .ops            = &clkops_null,
1941         .recalc         = &omap2_clksel_recalc,
1942 };
1943
1944 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1945         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1946         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1947         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1948         { .parent = NULL },
1949 };
1950
1951 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1952 static struct clk mcbsp1_fck = {
1953         .name           = "mcbsp1_fck",
1954         .parent         = &mcbsp1_sync_mux_ck,
1955         .clksel         = func_mcbsp1_gfclk_sel,
1956         .init           = &omap2_init_clksel_parent,
1957         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1958         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1959         .ops            = &clkops_omap2_dflt,
1960         .recalc         = &omap2_clksel_recalc,
1961         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1962         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1963         .clkdm_name     = "abe_clkdm",
1964 };
1965
1966 static struct clk mcbsp2_sync_mux_ck = {
1967         .name           = "mcbsp2_sync_mux_ck",
1968         .parent         = &abe_24m_fclk,
1969         .clksel         = dmic_sync_mux_sel,
1970         .init           = &omap2_init_clksel_parent,
1971         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1972         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1973         .ops            = &clkops_null,
1974         .recalc         = &omap2_clksel_recalc,
1975 };
1976
1977 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1978         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1979         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1980         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1981         { .parent = NULL },
1982 };
1983
1984 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1985 static struct clk mcbsp2_fck = {
1986         .name           = "mcbsp2_fck",
1987         .parent         = &mcbsp2_sync_mux_ck,
1988         .clksel         = func_mcbsp2_gfclk_sel,
1989         .init           = &omap2_init_clksel_parent,
1990         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1991         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1992         .ops            = &clkops_omap2_dflt,
1993         .recalc         = &omap2_clksel_recalc,
1994         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1995         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1996         .clkdm_name     = "abe_clkdm",
1997 };
1998
1999 static struct clk mcbsp3_sync_mux_ck = {
2000         .name           = "mcbsp3_sync_mux_ck",
2001         .parent         = &abe_24m_fclk,
2002         .clksel         = dmic_sync_mux_sel,
2003         .init           = &omap2_init_clksel_parent,
2004         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2005         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2006         .ops            = &clkops_null,
2007         .recalc         = &omap2_clksel_recalc,
2008 };
2009
2010 static const struct clksel func_mcbsp3_gfclk_sel[] = {
2011         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
2012         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2013         { .parent = &slimbus_clk, .rates = div_1_2_rates },
2014         { .parent = NULL },
2015 };
2016
2017 /* Merged func_mcbsp3_gfclk into mcbsp3 */
2018 static struct clk mcbsp3_fck = {
2019         .name           = "mcbsp3_fck",
2020         .parent         = &mcbsp3_sync_mux_ck,
2021         .clksel         = func_mcbsp3_gfclk_sel,
2022         .init           = &omap2_init_clksel_parent,
2023         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2024         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
2025         .ops            = &clkops_omap2_dflt,
2026         .recalc         = &omap2_clksel_recalc,
2027         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2028         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2029         .clkdm_name     = "abe_clkdm",
2030 };
2031
2032 static struct clk mcbsp4_sync_mux_ck = {
2033         .name           = "mcbsp4_sync_mux_ck",
2034         .parent         = &func_96m_fclk,
2035         .clksel         = mcasp2_fclk_sel,
2036         .init           = &omap2_init_clksel_parent,
2037         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2038         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2039         .ops            = &clkops_null,
2040         .recalc         = &omap2_clksel_recalc,
2041 };
2042
2043 static const struct clksel per_mcbsp4_gfclk_sel[] = {
2044         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
2045         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2046         { .parent = NULL },
2047 };
2048
2049 /* Merged per_mcbsp4_gfclk into mcbsp4 */
2050 static struct clk mcbsp4_fck = {
2051         .name           = "mcbsp4_fck",
2052         .parent         = &mcbsp4_sync_mux_ck,
2053         .clksel         = per_mcbsp4_gfclk_sel,
2054         .init           = &omap2_init_clksel_parent,
2055         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2056         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2057         .ops            = &clkops_omap2_dflt,
2058         .recalc         = &omap2_clksel_recalc,
2059         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2060         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2061         .clkdm_name     = "l4_per_clkdm",
2062 };
2063
2064 static struct clk mcpdm_fck = {
2065         .name           = "mcpdm_fck",
2066         .ops            = &clkops_omap2_dflt,
2067         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2068         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2069         .clkdm_name     = "abe_clkdm",
2070         .parent         = &pad_clks_ck,
2071         .recalc         = &followparent_recalc,
2072 };
2073
2074 static struct clk mcspi1_fck = {
2075         .name           = "mcspi1_fck",
2076         .ops            = &clkops_omap2_dflt,
2077         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2078         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2079         .clkdm_name     = "l4_per_clkdm",
2080         .parent         = &func_48m_fclk,
2081         .recalc         = &followparent_recalc,
2082 };
2083
2084 static struct clk mcspi2_fck = {
2085         .name           = "mcspi2_fck",
2086         .ops            = &clkops_omap2_dflt,
2087         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2088         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2089         .clkdm_name     = "l4_per_clkdm",
2090         .parent         = &func_48m_fclk,
2091         .recalc         = &followparent_recalc,
2092 };
2093
2094 static struct clk mcspi3_fck = {
2095         .name           = "mcspi3_fck",
2096         .ops            = &clkops_omap2_dflt,
2097         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2098         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2099         .clkdm_name     = "l4_per_clkdm",
2100         .parent         = &func_48m_fclk,
2101         .recalc         = &followparent_recalc,
2102 };
2103
2104 static struct clk mcspi4_fck = {
2105         .name           = "mcspi4_fck",
2106         .ops            = &clkops_omap2_dflt,
2107         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2108         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2109         .clkdm_name     = "l4_per_clkdm",
2110         .parent         = &func_48m_fclk,
2111         .recalc         = &followparent_recalc,
2112 };
2113
2114 /* Merged hsmmc1_fclk into mmc1 */
2115 static struct clk mmc1_fck = {
2116         .name           = "mmc1_fck",
2117         .parent         = &func_64m_fclk,
2118         .clksel         = hsmmc6_fclk_sel,
2119         .init           = &omap2_init_clksel_parent,
2120         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2121         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2122         .ops            = &clkops_omap2_dflt,
2123         .recalc         = &omap2_clksel_recalc,
2124         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2125         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2126         .clkdm_name     = "l3_init_clkdm",
2127 };
2128
2129 /* Merged hsmmc2_fclk into mmc2 */
2130 static struct clk mmc2_fck = {
2131         .name           = "mmc2_fck",
2132         .parent         = &func_64m_fclk,
2133         .clksel         = hsmmc6_fclk_sel,
2134         .init           = &omap2_init_clksel_parent,
2135         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2136         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2137         .ops            = &clkops_omap2_dflt,
2138         .recalc         = &omap2_clksel_recalc,
2139         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2140         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2141         .clkdm_name     = "l3_init_clkdm",
2142 };
2143
2144 static struct clk mmc3_fck = {
2145         .name           = "mmc3_fck",
2146         .ops            = &clkops_omap2_dflt,
2147         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2148         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2149         .clkdm_name     = "l4_per_clkdm",
2150         .parent         = &func_48m_fclk,
2151         .recalc         = &followparent_recalc,
2152 };
2153
2154 static struct clk mmc4_fck = {
2155         .name           = "mmc4_fck",
2156         .ops            = &clkops_omap2_dflt,
2157         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2158         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2159         .clkdm_name     = "l4_per_clkdm",
2160         .parent         = &func_48m_fclk,
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 static struct clk mmc5_fck = {
2165         .name           = "mmc5_fck",
2166         .ops            = &clkops_omap2_dflt,
2167         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2168         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2169         .clkdm_name     = "l4_per_clkdm",
2170         .parent         = &func_48m_fclk,
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk ocp2scp_usb_phy_phy_48m = {
2175         .name           = "ocp2scp_usb_phy_phy_48m",
2176         .ops            = &clkops_omap2_dflt,
2177         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2178         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2179         .clkdm_name     = "l3_init_clkdm",
2180         .parent         = &func_48m_fclk,
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 static struct clk ocp2scp_usb_phy_ick = {
2185         .name           = "ocp2scp_usb_phy_ick",
2186         .ops            = &clkops_omap2_dflt,
2187         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2188         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2189         .clkdm_name     = "l3_init_clkdm",
2190         .parent         = &l4_div_ck,
2191         .recalc         = &followparent_recalc,
2192 };
2193
2194 static struct clk ocp_wp_noc_ick = {
2195         .name           = "ocp_wp_noc_ick",
2196         .ops            = &clkops_omap2_dflt,
2197         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2198         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2199         .clkdm_name     = "l3_instr_clkdm",
2200         .flags          = ENABLE_ON_INIT,
2201         .parent         = &l3_div_ck,
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk rng_ick = {
2206         .name           = "rng_ick",
2207         .ops            = &clkops_omap2_dflt,
2208         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2209         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2210         .clkdm_name     = "l4_secure_clkdm",
2211         .parent         = &l4_div_ck,
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 static struct clk sha2md5_fck = {
2216         .name           = "sha2md5_fck",
2217         .ops            = &clkops_omap2_dflt,
2218         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2219         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2220         .clkdm_name     = "l4_secure_clkdm",
2221         .parent         = &l3_div_ck,
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk sl2if_ick = {
2226         .name           = "sl2if_ick",
2227         .ops            = &clkops_omap2_dflt,
2228         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2229         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2230         .clkdm_name     = "ivahd_clkdm",
2231         .parent         = &dpll_iva_m5x2_ck,
2232         .recalc         = &followparent_recalc,
2233 };
2234
2235 static struct clk slimbus1_fclk_1 = {
2236         .name           = "slimbus1_fclk_1",
2237         .ops            = &clkops_omap2_dflt,
2238         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2239         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2240         .clkdm_name     = "abe_clkdm",
2241         .parent         = &func_24m_clk,
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk slimbus1_fclk_0 = {
2246         .name           = "slimbus1_fclk_0",
2247         .ops            = &clkops_omap2_dflt,
2248         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2249         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2250         .clkdm_name     = "abe_clkdm",
2251         .parent         = &abe_24m_fclk,
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 static struct clk slimbus1_fclk_2 = {
2256         .name           = "slimbus1_fclk_2",
2257         .ops            = &clkops_omap2_dflt,
2258         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2259         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2260         .clkdm_name     = "abe_clkdm",
2261         .parent         = &pad_clks_ck,
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 static struct clk slimbus1_slimbus_clk = {
2266         .name           = "slimbus1_slimbus_clk",
2267         .ops            = &clkops_omap2_dflt,
2268         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2269         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2270         .clkdm_name     = "abe_clkdm",
2271         .parent         = &slimbus_clk,
2272         .recalc         = &followparent_recalc,
2273 };
2274
2275 static struct clk slimbus1_fck = {
2276         .name           = "slimbus1_fck",
2277         .ops            = &clkops_omap2_dflt,
2278         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2279         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2280         .clkdm_name     = "abe_clkdm",
2281         .parent         = &ocp_abe_iclk,
2282         .recalc         = &followparent_recalc,
2283 };
2284
2285 static struct clk slimbus2_fclk_1 = {
2286         .name           = "slimbus2_fclk_1",
2287         .ops            = &clkops_omap2_dflt,
2288         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2289         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2290         .clkdm_name     = "l4_per_clkdm",
2291         .parent         = &per_abe_24m_fclk,
2292         .recalc         = &followparent_recalc,
2293 };
2294
2295 static struct clk slimbus2_fclk_0 = {
2296         .name           = "slimbus2_fclk_0",
2297         .ops            = &clkops_omap2_dflt,
2298         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2299         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2300         .clkdm_name     = "l4_per_clkdm",
2301         .parent         = &func_24mc_fclk,
2302         .recalc         = &followparent_recalc,
2303 };
2304
2305 static struct clk slimbus2_slimbus_clk = {
2306         .name           = "slimbus2_slimbus_clk",
2307         .ops            = &clkops_omap2_dflt,
2308         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2309         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2310         .clkdm_name     = "l4_per_clkdm",
2311         .parent         = &pad_slimbus_core_clks_ck,
2312         .recalc         = &followparent_recalc,
2313 };
2314
2315 static struct clk slimbus2_fck = {
2316         .name           = "slimbus2_fck",
2317         .ops            = &clkops_omap2_dflt,
2318         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2319         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2320         .clkdm_name     = "l4_per_clkdm",
2321         .parent         = &l4_div_ck,
2322         .recalc         = &followparent_recalc,
2323 };
2324
2325 static struct clk smartreflex_core_fck = {
2326         .name           = "smartreflex_core_fck",
2327         .ops            = &clkops_omap2_dflt,
2328         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2329         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2330         .clkdm_name     = "l4_ao_clkdm",
2331         .parent         = &l4_wkup_clk_mux_ck,
2332         .recalc         = &followparent_recalc,
2333 };
2334
2335 static struct clk smartreflex_iva_fck = {
2336         .name           = "smartreflex_iva_fck",
2337         .ops            = &clkops_omap2_dflt,
2338         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2339         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2340         .clkdm_name     = "l4_ao_clkdm",
2341         .parent         = &l4_wkup_clk_mux_ck,
2342         .recalc         = &followparent_recalc,
2343 };
2344
2345 static struct clk smartreflex_mpu_fck = {
2346         .name           = "smartreflex_mpu_fck",
2347         .ops            = &clkops_omap2_dflt,
2348         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2349         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2350         .clkdm_name     = "l4_ao_clkdm",
2351         .parent         = &l4_wkup_clk_mux_ck,
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 /* Merged dmt1_clk_mux into timer1 */
2356 static struct clk timer1_fck = {
2357         .name           = "timer1_fck",
2358         .parent         = &sys_clkin_ck,
2359         .clksel         = abe_dpll_bypass_clk_mux_sel,
2360         .init           = &omap2_init_clksel_parent,
2361         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2362         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2363         .ops            = &clkops_omap2_dflt,
2364         .recalc         = &omap2_clksel_recalc,
2365         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2366         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2367         .clkdm_name     = "l4_wkup_clkdm",
2368 };
2369
2370 /* Merged cm2_dm10_mux into timer10 */
2371 static struct clk timer10_fck = {
2372         .name           = "timer10_fck",
2373         .parent         = &sys_clkin_ck,
2374         .clksel         = abe_dpll_bypass_clk_mux_sel,
2375         .init           = &omap2_init_clksel_parent,
2376         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2377         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2378         .ops            = &clkops_omap2_dflt,
2379         .recalc         = &omap2_clksel_recalc,
2380         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2381         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2382         .clkdm_name     = "l4_per_clkdm",
2383 };
2384
2385 /* Merged cm2_dm11_mux into timer11 */
2386 static struct clk timer11_fck = {
2387         .name           = "timer11_fck",
2388         .parent         = &sys_clkin_ck,
2389         .clksel         = abe_dpll_bypass_clk_mux_sel,
2390         .init           = &omap2_init_clksel_parent,
2391         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2392         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2393         .ops            = &clkops_omap2_dflt,
2394         .recalc         = &omap2_clksel_recalc,
2395         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2396         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2397         .clkdm_name     = "l4_per_clkdm",
2398 };
2399
2400 /* Merged cm2_dm2_mux into timer2 */
2401 static struct clk timer2_fck = {
2402         .name           = "timer2_fck",
2403         .parent         = &sys_clkin_ck,
2404         .clksel         = abe_dpll_bypass_clk_mux_sel,
2405         .init           = &omap2_init_clksel_parent,
2406         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2407         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2408         .ops            = &clkops_omap2_dflt,
2409         .recalc         = &omap2_clksel_recalc,
2410         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2411         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2412         .clkdm_name     = "l4_per_clkdm",
2413 };
2414
2415 /* Merged cm2_dm3_mux into timer3 */
2416 static struct clk timer3_fck = {
2417         .name           = "timer3_fck",
2418         .parent         = &sys_clkin_ck,
2419         .clksel         = abe_dpll_bypass_clk_mux_sel,
2420         .init           = &omap2_init_clksel_parent,
2421         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2422         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2423         .ops            = &clkops_omap2_dflt,
2424         .recalc         = &omap2_clksel_recalc,
2425         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2426         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2427         .clkdm_name     = "l4_per_clkdm",
2428 };
2429
2430 /* Merged cm2_dm4_mux into timer4 */
2431 static struct clk timer4_fck = {
2432         .name           = "timer4_fck",
2433         .parent         = &sys_clkin_ck,
2434         .clksel         = abe_dpll_bypass_clk_mux_sel,
2435         .init           = &omap2_init_clksel_parent,
2436         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2437         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2438         .ops            = &clkops_omap2_dflt,
2439         .recalc         = &omap2_clksel_recalc,
2440         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2441         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2442         .clkdm_name     = "l4_per_clkdm",
2443 };
2444
2445 static const struct clksel timer5_sync_mux_sel[] = {
2446         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2447         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2448         { .parent = NULL },
2449 };
2450
2451 /* Merged timer5_sync_mux into timer5 */
2452 static struct clk timer5_fck = {
2453         .name           = "timer5_fck",
2454         .parent         = &syc_clk_div_ck,
2455         .clksel         = timer5_sync_mux_sel,
2456         .init           = &omap2_init_clksel_parent,
2457         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2458         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2459         .ops            = &clkops_omap2_dflt,
2460         .recalc         = &omap2_clksel_recalc,
2461         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2462         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2463         .clkdm_name     = "abe_clkdm",
2464 };
2465
2466 /* Merged timer6_sync_mux into timer6 */
2467 static struct clk timer6_fck = {
2468         .name           = "timer6_fck",
2469         .parent         = &syc_clk_div_ck,
2470         .clksel         = timer5_sync_mux_sel,
2471         .init           = &omap2_init_clksel_parent,
2472         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2473         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2474         .ops            = &clkops_omap2_dflt,
2475         .recalc         = &omap2_clksel_recalc,
2476         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2477         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2478         .clkdm_name     = "abe_clkdm",
2479 };
2480
2481 /* Merged timer7_sync_mux into timer7 */
2482 static struct clk timer7_fck = {
2483         .name           = "timer7_fck",
2484         .parent         = &syc_clk_div_ck,
2485         .clksel         = timer5_sync_mux_sel,
2486         .init           = &omap2_init_clksel_parent,
2487         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2488         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2489         .ops            = &clkops_omap2_dflt,
2490         .recalc         = &omap2_clksel_recalc,
2491         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2492         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2493         .clkdm_name     = "abe_clkdm",
2494 };
2495
2496 /* Merged timer8_sync_mux into timer8 */
2497 static struct clk timer8_fck = {
2498         .name           = "timer8_fck",
2499         .parent         = &syc_clk_div_ck,
2500         .clksel         = timer5_sync_mux_sel,
2501         .init           = &omap2_init_clksel_parent,
2502         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2503         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2504         .ops            = &clkops_omap2_dflt,
2505         .recalc         = &omap2_clksel_recalc,
2506         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2507         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2508         .clkdm_name     = "abe_clkdm",
2509 };
2510
2511 /* Merged cm2_dm9_mux into timer9 */
2512 static struct clk timer9_fck = {
2513         .name           = "timer9_fck",
2514         .parent         = &sys_clkin_ck,
2515         .clksel         = abe_dpll_bypass_clk_mux_sel,
2516         .init           = &omap2_init_clksel_parent,
2517         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2518         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2519         .ops            = &clkops_omap2_dflt,
2520         .recalc         = &omap2_clksel_recalc,
2521         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2522         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2523         .clkdm_name     = "l4_per_clkdm",
2524 };
2525
2526 static struct clk uart1_fck = {
2527         .name           = "uart1_fck",
2528         .ops            = &clkops_omap2_dflt,
2529         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2530         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2531         .clkdm_name     = "l4_per_clkdm",
2532         .parent         = &func_48m_fclk,
2533         .recalc         = &followparent_recalc,
2534 };
2535
2536 static struct clk uart2_fck = {
2537         .name           = "uart2_fck",
2538         .ops            = &clkops_omap2_dflt,
2539         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2540         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2541         .clkdm_name     = "l4_per_clkdm",
2542         .parent         = &func_48m_fclk,
2543         .recalc         = &followparent_recalc,
2544 };
2545
2546 static struct clk uart3_fck = {
2547         .name           = "uart3_fck",
2548         .ops            = &clkops_omap2_dflt,
2549         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2550         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2551         .clkdm_name     = "l4_per_clkdm",
2552         .parent         = &func_48m_fclk,
2553         .recalc         = &followparent_recalc,
2554 };
2555
2556 static struct clk uart4_fck = {
2557         .name           = "uart4_fck",
2558         .ops            = &clkops_omap2_dflt,
2559         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2560         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2561         .clkdm_name     = "l4_per_clkdm",
2562         .parent         = &func_48m_fclk,
2563         .recalc         = &followparent_recalc,
2564 };
2565
2566 static struct clk usb_host_fs_fck = {
2567         .name           = "usb_host_fs_fck",
2568         .ops            = &clkops_omap2_dflt,
2569         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2570         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2571         .clkdm_name     = "l3_init_clkdm",
2572         .parent         = &func_48mc_fclk,
2573         .recalc         = &followparent_recalc,
2574 };
2575
2576 static const struct clksel utmi_p1_gfclk_sel[] = {
2577         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2578         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2579         { .parent = NULL },
2580 };
2581
2582 static struct clk utmi_p1_gfclk = {
2583         .name           = "utmi_p1_gfclk",
2584         .parent         = &init_60m_fclk,
2585         .clksel         = utmi_p1_gfclk_sel,
2586         .init           = &omap2_init_clksel_parent,
2587         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2588         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2589         .ops            = &clkops_null,
2590         .recalc         = &omap2_clksel_recalc,
2591 };
2592
2593 static struct clk usb_host_hs_utmi_p1_clk = {
2594         .name           = "usb_host_hs_utmi_p1_clk",
2595         .ops            = &clkops_omap2_dflt,
2596         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2597         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2598         .clkdm_name     = "l3_init_clkdm",
2599         .parent         = &utmi_p1_gfclk,
2600         .recalc         = &followparent_recalc,
2601 };
2602
2603 static const struct clksel utmi_p2_gfclk_sel[] = {
2604         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2605         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2606         { .parent = NULL },
2607 };
2608
2609 static struct clk utmi_p2_gfclk = {
2610         .name           = "utmi_p2_gfclk",
2611         .parent         = &init_60m_fclk,
2612         .clksel         = utmi_p2_gfclk_sel,
2613         .init           = &omap2_init_clksel_parent,
2614         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2615         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2616         .ops            = &clkops_null,
2617         .recalc         = &omap2_clksel_recalc,
2618 };
2619
2620 static struct clk usb_host_hs_utmi_p2_clk = {
2621         .name           = "usb_host_hs_utmi_p2_clk",
2622         .ops            = &clkops_omap2_dflt,
2623         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2624         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2625         .clkdm_name     = "l3_init_clkdm",
2626         .parent         = &utmi_p2_gfclk,
2627         .recalc         = &followparent_recalc,
2628 };
2629
2630 static struct clk usb_host_hs_utmi_p3_clk = {
2631         .name           = "usb_host_hs_utmi_p3_clk",
2632         .ops            = &clkops_omap2_dflt,
2633         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2634         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2635         .clkdm_name     = "l3_init_clkdm",
2636         .parent         = &init_60m_fclk,
2637         .recalc         = &followparent_recalc,
2638 };
2639
2640 static struct clk usb_host_hs_hsic480m_p1_clk = {
2641         .name           = "usb_host_hs_hsic480m_p1_clk",
2642         .ops            = &clkops_omap2_dflt,
2643         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2644         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2645         .clkdm_name     = "l3_init_clkdm",
2646         .parent         = &dpll_usb_m2_ck,
2647         .recalc         = &followparent_recalc,
2648 };
2649
2650 static struct clk usb_host_hs_hsic60m_p1_clk = {
2651         .name           = "usb_host_hs_hsic60m_p1_clk",
2652         .ops            = &clkops_omap2_dflt,
2653         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2654         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2655         .clkdm_name     = "l3_init_clkdm",
2656         .parent         = &init_60m_fclk,
2657         .recalc         = &followparent_recalc,
2658 };
2659
2660 static struct clk usb_host_hs_hsic60m_p2_clk = {
2661         .name           = "usb_host_hs_hsic60m_p2_clk",
2662         .ops            = &clkops_omap2_dflt,
2663         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2664         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2665         .clkdm_name     = "l3_init_clkdm",
2666         .parent         = &init_60m_fclk,
2667         .recalc         = &followparent_recalc,
2668 };
2669
2670 static struct clk usb_host_hs_hsic480m_p2_clk = {
2671         .name           = "usb_host_hs_hsic480m_p2_clk",
2672         .ops            = &clkops_omap2_dflt,
2673         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2674         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2675         .clkdm_name     = "l3_init_clkdm",
2676         .parent         = &dpll_usb_m2_ck,
2677         .recalc         = &followparent_recalc,
2678 };
2679
2680 static struct clk usb_host_hs_func48mclk = {
2681         .name           = "usb_host_hs_func48mclk",
2682         .ops            = &clkops_omap2_dflt,
2683         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2684         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2685         .clkdm_name     = "l3_init_clkdm",
2686         .parent         = &func_48mc_fclk,
2687         .recalc         = &followparent_recalc,
2688 };
2689
2690 static struct clk usb_host_hs_fck = {
2691         .name           = "usb_host_hs_fck",
2692         .ops            = &clkops_omap2_dflt,
2693         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2694         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2695         .clkdm_name     = "l3_init_clkdm",
2696         .parent         = &init_60m_fclk,
2697         .recalc         = &followparent_recalc,
2698 };
2699
2700 static const struct clksel otg_60m_gfclk_sel[] = {
2701         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2702         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2703         { .parent = NULL },
2704 };
2705
2706 static struct clk otg_60m_gfclk = {
2707         .name           = "otg_60m_gfclk",
2708         .parent         = &utmi_phy_clkout_ck,
2709         .clksel         = otg_60m_gfclk_sel,
2710         .init           = &omap2_init_clksel_parent,
2711         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2712         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2713         .ops            = &clkops_null,
2714         .recalc         = &omap2_clksel_recalc,
2715 };
2716
2717 static struct clk usb_otg_hs_xclk = {
2718         .name           = "usb_otg_hs_xclk",
2719         .ops            = &clkops_omap2_dflt,
2720         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2721         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2722         .clkdm_name     = "l3_init_clkdm",
2723         .parent         = &otg_60m_gfclk,
2724         .recalc         = &followparent_recalc,
2725 };
2726
2727 static struct clk usb_otg_hs_ick = {
2728         .name           = "usb_otg_hs_ick",
2729         .ops            = &clkops_omap2_dflt,
2730         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2731         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2732         .clkdm_name     = "l3_init_clkdm",
2733         .parent         = &l3_div_ck,
2734         .recalc         = &followparent_recalc,
2735 };
2736
2737 static struct clk usb_phy_cm_clk32k = {
2738         .name           = "usb_phy_cm_clk32k",
2739         .ops            = &clkops_omap2_dflt,
2740         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2741         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2742         .clkdm_name     = "l4_ao_clkdm",
2743         .parent         = &sys_32k_ck,
2744         .recalc         = &followparent_recalc,
2745 };
2746
2747 static struct clk usb_tll_hs_usb_ch2_clk = {
2748         .name           = "usb_tll_hs_usb_ch2_clk",
2749         .ops            = &clkops_omap2_dflt,
2750         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2751         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2752         .clkdm_name     = "l3_init_clkdm",
2753         .parent         = &init_60m_fclk,
2754         .recalc         = &followparent_recalc,
2755 };
2756
2757 static struct clk usb_tll_hs_usb_ch0_clk = {
2758         .name           = "usb_tll_hs_usb_ch0_clk",
2759         .ops            = &clkops_omap2_dflt,
2760         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2761         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2762         .clkdm_name     = "l3_init_clkdm",
2763         .parent         = &init_60m_fclk,
2764         .recalc         = &followparent_recalc,
2765 };
2766
2767 static struct clk usb_tll_hs_usb_ch1_clk = {
2768         .name           = "usb_tll_hs_usb_ch1_clk",
2769         .ops            = &clkops_omap2_dflt,
2770         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2771         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2772         .clkdm_name     = "l3_init_clkdm",
2773         .parent         = &init_60m_fclk,
2774         .recalc         = &followparent_recalc,
2775 };
2776
2777 static struct clk usb_tll_hs_ick = {
2778         .name           = "usb_tll_hs_ick",
2779         .ops            = &clkops_omap2_dflt,
2780         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2781         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2782         .clkdm_name     = "l3_init_clkdm",
2783         .parent         = &l4_div_ck,
2784         .recalc         = &followparent_recalc,
2785 };
2786
2787 static const struct clksel_rate div2_14to18_rates[] = {
2788         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2789         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2790         { .div = 0 },
2791 };
2792
2793 static const struct clksel usim_fclk_div[] = {
2794         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2795         { .parent = NULL },
2796 };
2797
2798 static struct clk usim_ck = {
2799         .name           = "usim_ck",
2800         .parent         = &dpll_per_m4x2_ck,
2801         .clksel         = usim_fclk_div,
2802         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2803         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2804         .ops            = &clkops_null,
2805         .recalc         = &omap2_clksel_recalc,
2806         .round_rate     = &omap2_clksel_round_rate,
2807         .set_rate       = &omap2_clksel_set_rate,
2808 };
2809
2810 static struct clk usim_fclk = {
2811         .name           = "usim_fclk",
2812         .ops            = &clkops_omap2_dflt,
2813         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2814         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2815         .clkdm_name     = "l4_wkup_clkdm",
2816         .parent         = &usim_ck,
2817         .recalc         = &followparent_recalc,
2818 };
2819
2820 static struct clk usim_fck = {
2821         .name           = "usim_fck",
2822         .ops            = &clkops_omap2_dflt,
2823         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2824         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2825         .clkdm_name     = "l4_wkup_clkdm",
2826         .parent         = &sys_32k_ck,
2827         .recalc         = &followparent_recalc,
2828 };
2829
2830 static struct clk wd_timer2_fck = {
2831         .name           = "wd_timer2_fck",
2832         .ops            = &clkops_omap2_dflt,
2833         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2834         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2835         .clkdm_name     = "l4_wkup_clkdm",
2836         .parent         = &sys_32k_ck,
2837         .recalc         = &followparent_recalc,
2838 };
2839
2840 static struct clk wd_timer3_fck = {
2841         .name           = "wd_timer3_fck",
2842         .ops            = &clkops_omap2_dflt,
2843         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2844         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2845         .clkdm_name     = "abe_clkdm",
2846         .parent         = &sys_32k_ck,
2847         .recalc         = &followparent_recalc,
2848 };
2849
2850 /* Remaining optional clocks */
2851 static const struct clksel stm_clk_div_div[] = {
2852         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2853         { .parent = NULL },
2854 };
2855
2856 static struct clk stm_clk_div_ck = {
2857         .name           = "stm_clk_div_ck",
2858         .parent         = &pmd_stm_clock_mux_ck,
2859         .clksel         = stm_clk_div_div,
2860         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2861         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2862         .ops            = &clkops_null,
2863         .recalc         = &omap2_clksel_recalc,
2864         .round_rate     = &omap2_clksel_round_rate,
2865         .set_rate       = &omap2_clksel_set_rate,
2866 };
2867
2868 static const struct clksel trace_clk_div_div[] = {
2869         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2870         { .parent = NULL },
2871 };
2872
2873 static struct clk trace_clk_div_ck = {
2874         .name           = "trace_clk_div_ck",
2875         .parent         = &pmd_trace_clk_mux_ck,
2876         .clksel         = trace_clk_div_div,
2877         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2878         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2879         .ops            = &clkops_null,
2880         .recalc         = &omap2_clksel_recalc,
2881         .round_rate     = &omap2_clksel_round_rate,
2882         .set_rate       = &omap2_clksel_set_rate,
2883 };
2884
2885 /* SCRM aux clk nodes */
2886
2887 static const struct clksel auxclk_sel[] = {
2888         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2889         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2890         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2891         { .parent = NULL },
2892 };
2893
2894 static struct clk auxclk0_ck = {
2895         .name           = "auxclk0_ck",
2896         .parent         = &sys_clkin_ck,
2897         .init           = &omap2_init_clksel_parent,
2898         .ops            = &clkops_omap2_dflt,
2899         .clksel         = auxclk_sel,
2900         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2901         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2902         .recalc         = &omap2_clksel_recalc,
2903         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2904         .enable_bit     = OMAP4_ENABLE_SHIFT,
2905 };
2906
2907 static struct clk auxclk1_ck = {
2908         .name           = "auxclk1_ck",
2909         .parent         = &sys_clkin_ck,
2910         .init           = &omap2_init_clksel_parent,
2911         .ops            = &clkops_omap2_dflt,
2912         .clksel         = auxclk_sel,
2913         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2914         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2915         .recalc         = &omap2_clksel_recalc,
2916         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2917         .enable_bit     = OMAP4_ENABLE_SHIFT,
2918 };
2919
2920 static struct clk auxclk2_ck = {
2921         .name           = "auxclk2_ck",
2922         .parent         = &sys_clkin_ck,
2923         .init           = &omap2_init_clksel_parent,
2924         .ops            = &clkops_omap2_dflt,
2925         .clksel         = auxclk_sel,
2926         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2927         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2928         .recalc         = &omap2_clksel_recalc,
2929         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2930         .enable_bit     = OMAP4_ENABLE_SHIFT,
2931 };
2932 static struct clk auxclk3_ck = {
2933         .name           = "auxclk3_ck",
2934         .parent         = &sys_clkin_ck,
2935         .init           = &omap2_init_clksel_parent,
2936         .ops            = &clkops_omap2_dflt,
2937         .clksel         = auxclk_sel,
2938         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2939         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2940         .recalc         = &omap2_clksel_recalc,
2941         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2942         .enable_bit     = OMAP4_ENABLE_SHIFT,
2943 };
2944
2945 static struct clk auxclk4_ck = {
2946         .name           = "auxclk4_ck",
2947         .parent         = &sys_clkin_ck,
2948         .init           = &omap2_init_clksel_parent,
2949         .ops            = &clkops_omap2_dflt,
2950         .clksel         = auxclk_sel,
2951         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2952         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2953         .recalc         = &omap2_clksel_recalc,
2954         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2955         .enable_bit     = OMAP4_ENABLE_SHIFT,
2956 };
2957
2958 static struct clk auxclk5_ck = {
2959         .name           = "auxclk5_ck",
2960         .parent         = &sys_clkin_ck,
2961         .init           = &omap2_init_clksel_parent,
2962         .ops            = &clkops_omap2_dflt,
2963         .clksel         = auxclk_sel,
2964         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
2965         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2966         .recalc         = &omap2_clksel_recalc,
2967         .enable_reg     = OMAP4_SCRM_AUXCLK5,
2968         .enable_bit     = OMAP4_ENABLE_SHIFT,
2969 };
2970
2971 static const struct clksel auxclkreq_sel[] = {
2972         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2973         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2974         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2975         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2976         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2977         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2978         { .parent = NULL },
2979 };
2980
2981 static struct clk auxclkreq0_ck = {
2982         .name           = "auxclkreq0_ck",
2983         .parent         = &auxclk0_ck,
2984         .init           = &omap2_init_clksel_parent,
2985         .ops            = &clkops_null,
2986         .clksel         = auxclkreq_sel,
2987         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
2988         .clksel_mask    = OMAP4_MAPPING_MASK,
2989         .recalc         = &omap2_clksel_recalc,
2990 };
2991
2992 static struct clk auxclkreq1_ck = {
2993         .name           = "auxclkreq1_ck",
2994         .parent         = &auxclk1_ck,
2995         .init           = &omap2_init_clksel_parent,
2996         .ops            = &clkops_null,
2997         .clksel         = auxclkreq_sel,
2998         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
2999         .clksel_mask    = OMAP4_MAPPING_MASK,
3000         .recalc         = &omap2_clksel_recalc,
3001 };
3002
3003 static struct clk auxclkreq2_ck = {
3004         .name           = "auxclkreq2_ck",
3005         .parent         = &auxclk2_ck,
3006         .init           = &omap2_init_clksel_parent,
3007         .ops            = &clkops_null,
3008         .clksel         = auxclkreq_sel,
3009         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
3010         .clksel_mask    = OMAP4_MAPPING_MASK,
3011         .recalc         = &omap2_clksel_recalc,
3012 };
3013
3014 static struct clk auxclkreq3_ck = {
3015         .name           = "auxclkreq3_ck",
3016         .parent         = &auxclk3_ck,
3017         .init           = &omap2_init_clksel_parent,
3018         .ops            = &clkops_null,
3019         .clksel         = auxclkreq_sel,
3020         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
3021         .clksel_mask    = OMAP4_MAPPING_MASK,
3022         .recalc         = &omap2_clksel_recalc,
3023 };
3024
3025 static struct clk auxclkreq4_ck = {
3026         .name           = "auxclkreq4_ck",
3027         .parent         = &auxclk4_ck,
3028         .init           = &omap2_init_clksel_parent,
3029         .ops            = &clkops_null,
3030         .clksel         = auxclkreq_sel,
3031         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
3032         .clksel_mask    = OMAP4_MAPPING_MASK,
3033         .recalc         = &omap2_clksel_recalc,
3034 };
3035
3036 static struct clk auxclkreq5_ck = {
3037         .name           = "auxclkreq5_ck",
3038         .parent         = &auxclk5_ck,
3039         .init           = &omap2_init_clksel_parent,
3040         .ops            = &clkops_null,
3041         .clksel         = auxclkreq_sel,
3042         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
3043         .clksel_mask    = OMAP4_MAPPING_MASK,
3044         .recalc         = &omap2_clksel_recalc,
3045 };
3046
3047 /*
3048  * clkdev
3049  */
3050
3051 static struct omap_clk omap44xx_clks[] = {
3052         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
3053         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
3054         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
3055         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
3056         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
3057         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
3058         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
3059         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
3060         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
3061         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
3062         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
3063         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
3064         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
3065         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
3066         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
3067         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
3068         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
3069         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
3070         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
3071         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
3072         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
3073         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
3074         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
3075         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3076         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3077         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3078         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3079         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3080         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3081         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3082         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3083         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3084         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3085         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3086         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3087         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3088         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3089         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3090         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3091         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3092         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3093         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3094         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3095         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3096         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3097         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3098         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3099         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3100         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3101         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3102         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3103         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3104         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3105         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3106         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3107         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3108         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3109         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3110         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3111         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3112         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3113         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3114         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
3115         CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
3116         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
3117         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3118         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3119         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3120         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3121         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3122         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3123         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),