Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[~shefty/rdma-dev.git] / arch / arm / mach-omap2 / irq.c
1 /*
2  * linux/arch/arm/mach-omap2/irq.c
3  *
4  * Interrupt handler for OMAP2 boards.
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  * Author: Paul Mundt <paul.mundt@nokia.com>
8  *
9  * This file is subject to the terms and conditions of the GNU General Public
10  * License. See the file "COPYING" in the main directory of this archive
11  * for more details.
12  */
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17
18 #include <asm/exception.h>
19 #include <asm/mach/irq.h>
20
21 #include <mach/hardware.h>
22
23 #include "iomap.h"
24
25 /* selected INTC register offsets */
26
27 #define INTC_REVISION           0x0000
28 #define INTC_SYSCONFIG          0x0010
29 #define INTC_SYSSTATUS          0x0014
30 #define INTC_SIR                0x0040
31 #define INTC_CONTROL            0x0048
32 #define INTC_PROTECTION         0x004C
33 #define INTC_IDLE               0x0050
34 #define INTC_THRESHOLD          0x0068
35 #define INTC_MIR0               0x0084
36 #define INTC_MIR_CLEAR0         0x0088
37 #define INTC_MIR_SET0           0x008c
38 #define INTC_PENDING_IRQ0       0x0098
39 /* Number of IRQ state bits in each MIR register */
40 #define IRQ_BITS_PER_REG        32
41
42 #define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
43 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
44 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
45 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
46
47 /*
48  * OMAP2 has a number of different interrupt controllers, each interrupt
49  * controller is identified as its own "bank". Register definitions are
50  * fairly consistent for each bank, but not all registers are implemented
51  * for each bank.. when in doubt, consult the TRM.
52  */
53 static struct omap_irq_bank {
54         void __iomem *base_reg;
55         unsigned int nr_irqs;
56 } __attribute__ ((aligned(4))) irq_banks[] = {
57         {
58                 /* MPU INTC */
59                 .nr_irqs        = 96,
60         },
61 };
62
63 /* Structure to save interrupt controller context */
64 struct omap3_intc_regs {
65         u32 sysconfig;
66         u32 protection;
67         u32 idle;
68         u32 threshold;
69         u32 ilr[INTCPS_NR_IRQS];
70         u32 mir[INTCPS_NR_MIR_REGS];
71 };
72
73 /* INTC bank register get/set */
74
75 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
76 {
77         __raw_writel(val, bank->base_reg + reg);
78 }
79
80 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
81 {
82         return __raw_readl(bank->base_reg + reg);
83 }
84
85 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
86 static void omap_ack_irq(struct irq_data *d)
87 {
88         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
89 }
90
91 static void omap_mask_ack_irq(struct irq_data *d)
92 {
93         irq_gc_mask_disable_reg(d);
94         omap_ack_irq(d);
95 }
96
97 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
98 {
99         unsigned long tmp;
100
101         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
102         printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
103                          "(revision %ld.%ld) with %d interrupts\n",
104                          bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
105
106         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
107         tmp |= 1 << 1;  /* soft reset */
108         intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
109
110         while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
111                 /* Wait for reset to complete */;
112
113         /* Enable autoidle */
114         intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
115 }
116
117 int omap_irq_pending(void)
118 {
119         int i;
120
121         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
122                 struct omap_irq_bank *bank = irq_banks + i;
123                 int irq;
124
125                 for (irq = 0; irq < bank->nr_irqs; irq += 32)
126                         if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
127                                                ((irq >> 5) << 5)))
128                                 return 1;
129         }
130         return 0;
131 }
132
133 static __init void
134 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
135 {
136         struct irq_chip_generic *gc;
137         struct irq_chip_type *ct;
138
139         gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
140                                         handle_level_irq);
141         ct = gc->chip_types;
142         ct->chip.irq_ack = omap_mask_ack_irq;
143         ct->chip.irq_mask = irq_gc_mask_disable_reg;
144         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
145
146         ct->regs.ack = INTC_CONTROL;
147         ct->regs.enable = INTC_MIR_CLEAR0;
148         ct->regs.disable = INTC_MIR_SET0;
149         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
150                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
151 }
152
153 static void __init omap_init_irq(u32 base, int nr_irqs)
154 {
155         void __iomem *omap_irq_base;
156         unsigned long nr_of_irqs = 0;
157         unsigned int nr_banks = 0;
158         int i, j;
159
160         omap_irq_base = ioremap(base, SZ_4K);
161         if (WARN_ON(!omap_irq_base))
162                 return;
163
164         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
165                 struct omap_irq_bank *bank = irq_banks + i;
166
167                 bank->nr_irqs = nr_irqs;
168
169                 /* Static mapping, never released */
170                 bank->base_reg = ioremap(base, SZ_4K);
171                 if (!bank->base_reg) {
172                         printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
173                         continue;
174                 }
175
176                 omap_irq_bank_init_one(bank);
177
178                 for (j = 0; j < bank->nr_irqs; j += 32)
179                         omap_alloc_gc(bank->base_reg + j, j, 32);
180
181                 nr_of_irqs += bank->nr_irqs;
182                 nr_banks++;
183         }
184
185         printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
186                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
187 }
188
189 void __init omap2_init_irq(void)
190 {
191         omap_init_irq(OMAP24XX_IC_BASE, 96);
192 }
193
194 void __init omap3_init_irq(void)
195 {
196         omap_init_irq(OMAP34XX_IC_BASE, 96);
197 }
198
199 void __init ti81xx_init_irq(void)
200 {
201         omap_init_irq(OMAP34XX_IC_BASE, 128);
202 }
203
204 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
205 {
206         u32 irqnr;
207
208         do {
209                 irqnr = readl_relaxed(base_addr + 0x98);
210                 if (irqnr)
211                         goto out;
212
213                 irqnr = readl_relaxed(base_addr + 0xb8);
214                 if (irqnr)
215                         goto out;
216
217                 irqnr = readl_relaxed(base_addr + 0xd8);
218 #ifdef CONFIG_SOC_OMAPTI816X
219                 if (irqnr)
220                         goto out;
221                 irqnr = readl_relaxed(base_addr + 0xf8);
222 #endif
223
224 out:
225                 if (!irqnr)
226                         break;
227
228                 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
229                 irqnr &= ACTIVEIRQ_MASK;
230
231                 if (irqnr)
232                         handle_IRQ(irqnr, regs);
233         } while (irqnr);
234 }
235
236 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
237 {
238         void __iomem *base_addr = OMAP2_IRQ_BASE;
239         omap_intc_handle_irq(base_addr, regs);
240 }
241
242 #ifdef CONFIG_ARCH_OMAP3
243 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
244
245 void omap_intc_save_context(void)
246 {
247         int ind = 0, i = 0;
248         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
249                 struct omap_irq_bank *bank = irq_banks + ind;
250                 intc_context[ind].sysconfig =
251                         intc_bank_read_reg(bank, INTC_SYSCONFIG);
252                 intc_context[ind].protection =
253                         intc_bank_read_reg(bank, INTC_PROTECTION);
254                 intc_context[ind].idle =
255                         intc_bank_read_reg(bank, INTC_IDLE);
256                 intc_context[ind].threshold =
257                         intc_bank_read_reg(bank, INTC_THRESHOLD);
258                 for (i = 0; i < INTCPS_NR_IRQS; i++)
259                         intc_context[ind].ilr[i] =
260                                 intc_bank_read_reg(bank, (0x100 + 0x4*i));
261                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
262                         intc_context[ind].mir[i] =
263                                 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
264                                 (0x20 * i));
265         }
266 }
267
268 void omap_intc_restore_context(void)
269 {
270         int ind = 0, i = 0;
271
272         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
273                 struct omap_irq_bank *bank = irq_banks + ind;
274                 intc_bank_write_reg(intc_context[ind].sysconfig,
275                                         bank, INTC_SYSCONFIG);
276                 intc_bank_write_reg(intc_context[ind].sysconfig,
277                                         bank, INTC_SYSCONFIG);
278                 intc_bank_write_reg(intc_context[ind].protection,
279                                         bank, INTC_PROTECTION);
280                 intc_bank_write_reg(intc_context[ind].idle,
281                                         bank, INTC_IDLE);
282                 intc_bank_write_reg(intc_context[ind].threshold,
283                                         bank, INTC_THRESHOLD);
284                 for (i = 0; i < INTCPS_NR_IRQS; i++)
285                         intc_bank_write_reg(intc_context[ind].ilr[i],
286                                 bank, (0x100 + 0x4*i));
287                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
288                         intc_bank_write_reg(intc_context[ind].mir[i],
289                                  &irq_banks[0], INTC_MIR0 + (0x20 * i));
290         }
291         /* MIRs are saved and restore with other PRCM registers */
292 }
293
294 void omap3_intc_suspend(void)
295 {
296         /* A pending interrupt would prevent OMAP from entering suspend */
297         omap_ack_irq(0);
298 }
299
300 void omap3_intc_prepare_idle(void)
301 {
302         /*
303          * Disable autoidle as it can stall interrupt controller,
304          * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
305          */
306         intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
307 }
308
309 void omap3_intc_resume_idle(void)
310 {
311         /* Re-enable autoidle */
312         intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
313 }
314
315 asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
316 {
317         void __iomem *base_addr = OMAP3_IRQ_BASE;
318         omap_intc_handle_irq(base_addr, regs);
319 }
320 #endif /* CONFIG_ARCH_OMAP3 */