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1 /*
2  * Hardware modules present on the OMAP44xx chips
3  *
4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Benoit Cousson
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/io.h>
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/platform_data/omap_ocp2scp.h>
25 #include <linux/i2c-omap.h>
26
27 #include <plat-omap/dma-omap.h>
28
29 #include <linux/platform_data/spi-omap2-mcspi.h>
30 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <plat/dmtimer.h>
32 #include <plat/iommu.h>
33
34 #include "../plat-omap/common.h"
35
36 #include "omap_hwmod.h"
37 #include "omap_hwmod_common_data.h"
38 #include "cm1_44xx.h"
39 #include "cm2_44xx.h"
40 #include "prm44xx.h"
41 #include "prm-regbits-44xx.h"
42 #include "i2c.h"
43 #include "mmc.h"
44 #include "wd_timer.h"
45
46 /* Base offset for all OMAP4 interrupts external to MPUSS */
47 #define OMAP44XX_IRQ_GIC_START  32
48
49 /* Base offset for all OMAP4 dma requests */
50 #define OMAP44XX_DMA_REQ_START  1
51
52 /*
53  * IP blocks
54  */
55
56 /*
57  * 'c2c_target_fw' class
58  * instance(s): c2c_target_fw
59  */
60 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
61         .name   = "c2c_target_fw",
62 };
63
64 /* c2c_target_fw */
65 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
66         .name           = "c2c_target_fw",
67         .class          = &omap44xx_c2c_target_fw_hwmod_class,
68         .clkdm_name     = "d2d_clkdm",
69         .prcm = {
70                 .omap4 = {
71                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
72                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
73                 },
74         },
75 };
76
77 /*
78  * 'dmm' class
79  * instance(s): dmm
80  */
81 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
82         .name   = "dmm",
83 };
84
85 /* dmm */
86 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
87         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
88         { .irq = -1 }
89 };
90
91 static struct omap_hwmod omap44xx_dmm_hwmod = {
92         .name           = "dmm",
93         .class          = &omap44xx_dmm_hwmod_class,
94         .clkdm_name     = "l3_emif_clkdm",
95         .mpu_irqs       = omap44xx_dmm_irqs,
96         .prcm = {
97                 .omap4 = {
98                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
99                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
100                 },
101         },
102 };
103
104 /*
105  * 'emif_fw' class
106  * instance(s): emif_fw
107  */
108 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
109         .name   = "emif_fw",
110 };
111
112 /* emif_fw */
113 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
114         .name           = "emif_fw",
115         .class          = &omap44xx_emif_fw_hwmod_class,
116         .clkdm_name     = "l3_emif_clkdm",
117         .prcm = {
118                 .omap4 = {
119                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
120                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
121                 },
122         },
123 };
124
125 /*
126  * 'l3' class
127  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
128  */
129 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
130         .name   = "l3",
131 };
132
133 /* l3_instr */
134 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
135         .name           = "l3_instr",
136         .class          = &omap44xx_l3_hwmod_class,
137         .clkdm_name     = "l3_instr_clkdm",
138         .prcm = {
139                 .omap4 = {
140                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
141                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
142                         .modulemode   = MODULEMODE_HWCTRL,
143                 },
144         },
145 };
146
147 /* l3_main_1 */
148 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
149         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
150         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
151         { .irq = -1 }
152 };
153
154 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
155         .name           = "l3_main_1",
156         .class          = &omap44xx_l3_hwmod_class,
157         .clkdm_name     = "l3_1_clkdm",
158         .mpu_irqs       = omap44xx_l3_main_1_irqs,
159         .prcm = {
160                 .omap4 = {
161                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
162                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
163                 },
164         },
165 };
166
167 /* l3_main_2 */
168 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
169         .name           = "l3_main_2",
170         .class          = &omap44xx_l3_hwmod_class,
171         .clkdm_name     = "l3_2_clkdm",
172         .prcm = {
173                 .omap4 = {
174                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
175                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
176                 },
177         },
178 };
179
180 /* l3_main_3 */
181 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
182         .name           = "l3_main_3",
183         .class          = &omap44xx_l3_hwmod_class,
184         .clkdm_name     = "l3_instr_clkdm",
185         .prcm = {
186                 .omap4 = {
187                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
188                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
189                         .modulemode   = MODULEMODE_HWCTRL,
190                 },
191         },
192 };
193
194 /*
195  * 'l4' class
196  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
197  */
198 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
199         .name   = "l4",
200 };
201
202 /* l4_abe */
203 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
204         .name           = "l4_abe",
205         .class          = &omap44xx_l4_hwmod_class,
206         .clkdm_name     = "abe_clkdm",
207         .prcm = {
208                 .omap4 = {
209                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
210                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
211                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
212                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
213                 },
214         },
215 };
216
217 /* l4_cfg */
218 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
219         .name           = "l4_cfg",
220         .class          = &omap44xx_l4_hwmod_class,
221         .clkdm_name     = "l4_cfg_clkdm",
222         .prcm = {
223                 .omap4 = {
224                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
225                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
226                 },
227         },
228 };
229
230 /* l4_per */
231 static struct omap_hwmod omap44xx_l4_per_hwmod = {
232         .name           = "l4_per",
233         .class          = &omap44xx_l4_hwmod_class,
234         .clkdm_name     = "l4_per_clkdm",
235         .prcm = {
236                 .omap4 = {
237                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
238                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
239                 },
240         },
241 };
242
243 /* l4_wkup */
244 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
245         .name           = "l4_wkup",
246         .class          = &omap44xx_l4_hwmod_class,
247         .clkdm_name     = "l4_wkup_clkdm",
248         .prcm = {
249                 .omap4 = {
250                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
251                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
252                 },
253         },
254 };
255
256 /*
257  * 'mpu_bus' class
258  * instance(s): mpu_private
259  */
260 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
261         .name   = "mpu_bus",
262 };
263
264 /* mpu_private */
265 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
266         .name           = "mpu_private",
267         .class          = &omap44xx_mpu_bus_hwmod_class,
268         .clkdm_name     = "mpuss_clkdm",
269         .prcm = {
270                 .omap4 = {
271                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
272                 },
273         },
274 };
275
276 /*
277  * 'ocp_wp_noc' class
278  * instance(s): ocp_wp_noc
279  */
280 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
281         .name   = "ocp_wp_noc",
282 };
283
284 /* ocp_wp_noc */
285 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
286         .name           = "ocp_wp_noc",
287         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
288         .clkdm_name     = "l3_instr_clkdm",
289         .prcm = {
290                 .omap4 = {
291                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
292                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
293                         .modulemode   = MODULEMODE_HWCTRL,
294                 },
295         },
296 };
297
298 /*
299  * Modules omap_hwmod structures
300  *
301  * The following IPs are excluded for the moment because:
302  * - They do not need an explicit SW control using omap_hwmod API.
303  * - They still need to be validated with the driver
304  *   properly adapted to omap_hwmod / omap_device
305  *
306  * usim
307  */
308
309 /*
310  * 'aess' class
311  * audio engine sub system
312  */
313
314 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
315         .rev_offs       = 0x0000,
316         .sysc_offs      = 0x0010,
317         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
318         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
319                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
320                            MSTANDBY_SMART_WKUP),
321         .sysc_fields    = &omap_hwmod_sysc_type2,
322 };
323
324 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
325         .name   = "aess",
326         .sysc   = &omap44xx_aess_sysc,
327 };
328
329 /* aess */
330 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
331         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
332         { .irq = -1 }
333 };
334
335 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
336         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
337         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
338         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
339         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
340         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
341         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
342         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
343         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
344         { .dma_req = -1 }
345 };
346
347 static struct omap_hwmod omap44xx_aess_hwmod = {
348         .name           = "aess",
349         .class          = &omap44xx_aess_hwmod_class,
350         .clkdm_name     = "abe_clkdm",
351         .mpu_irqs       = omap44xx_aess_irqs,
352         .sdma_reqs      = omap44xx_aess_sdma_reqs,
353         .main_clk       = "aess_fck",
354         .prcm = {
355                 .omap4 = {
356                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
357                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
358                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
359                         .modulemode   = MODULEMODE_SWCTRL,
360                 },
361         },
362 };
363
364 /*
365  * 'c2c' class
366  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
367  * soc
368  */
369
370 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
371         .name   = "c2c",
372 };
373
374 /* c2c */
375 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
376         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
377         { .irq = -1 }
378 };
379
380 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
381         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
382         { .dma_req = -1 }
383 };
384
385 static struct omap_hwmod omap44xx_c2c_hwmod = {
386         .name           = "c2c",
387         .class          = &omap44xx_c2c_hwmod_class,
388         .clkdm_name     = "d2d_clkdm",
389         .mpu_irqs       = omap44xx_c2c_irqs,
390         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
391         .prcm = {
392                 .omap4 = {
393                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
394                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
395                 },
396         },
397 };
398
399 /*
400  * 'counter' class
401  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
402  */
403
404 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
405         .rev_offs       = 0x0000,
406         .sysc_offs      = 0x0004,
407         .sysc_flags     = SYSC_HAS_SIDLEMODE,
408         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
409         .sysc_fields    = &omap_hwmod_sysc_type1,
410 };
411
412 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
413         .name   = "counter",
414         .sysc   = &omap44xx_counter_sysc,
415 };
416
417 /* counter_32k */
418 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
419         .name           = "counter_32k",
420         .class          = &omap44xx_counter_hwmod_class,
421         .clkdm_name     = "l4_wkup_clkdm",
422         .flags          = HWMOD_SWSUP_SIDLE,
423         .main_clk       = "sys_32k_ck",
424         .prcm = {
425                 .omap4 = {
426                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
427                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
428                 },
429         },
430 };
431
432 /*
433  * 'ctrl_module' class
434  * attila core control module + core pad control module + wkup pad control
435  * module + attila wkup control module
436  */
437
438 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
439         .rev_offs       = 0x0000,
440         .sysc_offs      = 0x0010,
441         .sysc_flags     = SYSC_HAS_SIDLEMODE,
442         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
443                            SIDLE_SMART_WKUP),
444         .sysc_fields    = &omap_hwmod_sysc_type2,
445 };
446
447 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
448         .name   = "ctrl_module",
449         .sysc   = &omap44xx_ctrl_module_sysc,
450 };
451
452 /* ctrl_module_core */
453 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
454         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
455         { .irq = -1 }
456 };
457
458 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
459         .name           = "ctrl_module_core",
460         .class          = &omap44xx_ctrl_module_hwmod_class,
461         .clkdm_name     = "l4_cfg_clkdm",
462         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
463         .prcm = {
464                 .omap4 = {
465                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
466                 },
467         },
468 };
469
470 /* ctrl_module_pad_core */
471 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
472         .name           = "ctrl_module_pad_core",
473         .class          = &omap44xx_ctrl_module_hwmod_class,
474         .clkdm_name     = "l4_cfg_clkdm",
475         .prcm = {
476                 .omap4 = {
477                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
478                 },
479         },
480 };
481
482 /* ctrl_module_wkup */
483 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
484         .name           = "ctrl_module_wkup",
485         .class          = &omap44xx_ctrl_module_hwmod_class,
486         .clkdm_name     = "l4_wkup_clkdm",
487         .prcm = {
488                 .omap4 = {
489                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
490                 },
491         },
492 };
493
494 /* ctrl_module_pad_wkup */
495 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
496         .name           = "ctrl_module_pad_wkup",
497         .class          = &omap44xx_ctrl_module_hwmod_class,
498         .clkdm_name     = "l4_wkup_clkdm",
499         .prcm = {
500                 .omap4 = {
501                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
502                 },
503         },
504 };
505
506 /*
507  * 'debugss' class
508  * debug and emulation sub system
509  */
510
511 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
512         .name   = "debugss",
513 };
514
515 /* debugss */
516 static struct omap_hwmod omap44xx_debugss_hwmod = {
517         .name           = "debugss",
518         .class          = &omap44xx_debugss_hwmod_class,
519         .clkdm_name     = "emu_sys_clkdm",
520         .main_clk       = "trace_clk_div_ck",
521         .prcm = {
522                 .omap4 = {
523                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
524                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
525                 },
526         },
527 };
528
529 /*
530  * 'dma' class
531  * dma controller for data exchange between memory to memory (i.e. internal or
532  * external memory) and gp peripherals to memory or memory to gp peripherals
533  */
534
535 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
536         .rev_offs       = 0x0000,
537         .sysc_offs      = 0x002c,
538         .syss_offs      = 0x0028,
539         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
540                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
541                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
542                            SYSS_HAS_RESET_STATUS),
543         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
544                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
545         .sysc_fields    = &omap_hwmod_sysc_type1,
546 };
547
548 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
549         .name   = "dma",
550         .sysc   = &omap44xx_dma_sysc,
551 };
552
553 /* dma dev_attr */
554 static struct omap_dma_dev_attr dma_dev_attr = {
555         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
556                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
557         .lch_count      = 32,
558 };
559
560 /* dma_system */
561 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
562         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
563         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
564         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
565         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
566         { .irq = -1 }
567 };
568
569 static struct omap_hwmod omap44xx_dma_system_hwmod = {
570         .name           = "dma_system",
571         .class          = &omap44xx_dma_hwmod_class,
572         .clkdm_name     = "l3_dma_clkdm",
573         .mpu_irqs       = omap44xx_dma_system_irqs,
574         .main_clk       = "l3_div_ck",
575         .prcm = {
576                 .omap4 = {
577                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
578                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
579                 },
580         },
581         .dev_attr       = &dma_dev_attr,
582 };
583
584 /*
585  * 'dmic' class
586  * digital microphone controller
587  */
588
589 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
590         .rev_offs       = 0x0000,
591         .sysc_offs      = 0x0010,
592         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
593                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
594         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
595                            SIDLE_SMART_WKUP),
596         .sysc_fields    = &omap_hwmod_sysc_type2,
597 };
598
599 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
600         .name   = "dmic",
601         .sysc   = &omap44xx_dmic_sysc,
602 };
603
604 /* dmic */
605 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
606         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
607         { .irq = -1 }
608 };
609
610 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
611         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
612         { .dma_req = -1 }
613 };
614
615 static struct omap_hwmod omap44xx_dmic_hwmod = {
616         .name           = "dmic",
617         .class          = &omap44xx_dmic_hwmod_class,
618         .clkdm_name     = "abe_clkdm",
619         .mpu_irqs       = omap44xx_dmic_irqs,
620         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
621         .main_clk       = "dmic_fck",
622         .prcm = {
623                 .omap4 = {
624                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
625                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
626                         .modulemode   = MODULEMODE_SWCTRL,
627                 },
628         },
629 };
630
631 /*
632  * 'dsp' class
633  * dsp sub-system
634  */
635
636 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
637         .name   = "dsp",
638 };
639
640 /* dsp */
641 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
642         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
643         { .irq = -1 }
644 };
645
646 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
647         { .name = "dsp", .rst_shift = 0 },
648 };
649
650 static struct omap_hwmod omap44xx_dsp_hwmod = {
651         .name           = "dsp",
652         .class          = &omap44xx_dsp_hwmod_class,
653         .clkdm_name     = "tesla_clkdm",
654         .mpu_irqs       = omap44xx_dsp_irqs,
655         .rst_lines      = omap44xx_dsp_resets,
656         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
657         .main_clk       = "dsp_fck",
658         .prcm = {
659                 .omap4 = {
660                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
661                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
662                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
663                         .modulemode   = MODULEMODE_HWCTRL,
664                 },
665         },
666 };
667
668 /*
669  * 'dss' class
670  * display sub-system
671  */
672
673 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
674         .rev_offs       = 0x0000,
675         .syss_offs      = 0x0014,
676         .sysc_flags     = SYSS_HAS_RESET_STATUS,
677 };
678
679 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
680         .name   = "dss",
681         .sysc   = &omap44xx_dss_sysc,
682         .reset  = omap_dss_reset,
683 };
684
685 /* dss */
686 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
687         { .role = "sys_clk", .clk = "dss_sys_clk" },
688         { .role = "tv_clk", .clk = "dss_tv_clk" },
689         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
690 };
691
692 static struct omap_hwmod omap44xx_dss_hwmod = {
693         .name           = "dss_core",
694         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
695         .class          = &omap44xx_dss_hwmod_class,
696         .clkdm_name     = "l3_dss_clkdm",
697         .main_clk       = "dss_dss_clk",
698         .prcm = {
699                 .omap4 = {
700                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
701                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
702                 },
703         },
704         .opt_clks       = dss_opt_clks,
705         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
706 };
707
708 /*
709  * 'dispc' class
710  * display controller
711  */
712
713 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
714         .rev_offs       = 0x0000,
715         .sysc_offs      = 0x0010,
716         .syss_offs      = 0x0014,
717         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
718                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
719                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
720                            SYSS_HAS_RESET_STATUS),
721         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
722                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
723         .sysc_fields    = &omap_hwmod_sysc_type1,
724 };
725
726 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
727         .name   = "dispc",
728         .sysc   = &omap44xx_dispc_sysc,
729 };
730
731 /* dss_dispc */
732 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
733         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
734         { .irq = -1 }
735 };
736
737 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
738         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
739         { .dma_req = -1 }
740 };
741
742 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
743         .manager_count          = 3,
744         .has_framedonetv_irq    = 1
745 };
746
747 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
748         .name           = "dss_dispc",
749         .class          = &omap44xx_dispc_hwmod_class,
750         .clkdm_name     = "l3_dss_clkdm",
751         .mpu_irqs       = omap44xx_dss_dispc_irqs,
752         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
753         .main_clk       = "dss_dss_clk",
754         .prcm = {
755                 .omap4 = {
756                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
757                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
758                 },
759         },
760         .dev_attr       = &omap44xx_dss_dispc_dev_attr
761 };
762
763 /*
764  * 'dsi' class
765  * display serial interface controller
766  */
767
768 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
769         .rev_offs       = 0x0000,
770         .sysc_offs      = 0x0010,
771         .syss_offs      = 0x0014,
772         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
773                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
774                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
775         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
776         .sysc_fields    = &omap_hwmod_sysc_type1,
777 };
778
779 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
780         .name   = "dsi",
781         .sysc   = &omap44xx_dsi_sysc,
782 };
783
784 /* dss_dsi1 */
785 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
786         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
787         { .irq = -1 }
788 };
789
790 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
791         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
792         { .dma_req = -1 }
793 };
794
795 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
796         { .role = "sys_clk", .clk = "dss_sys_clk" },
797 };
798
799 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
800         .name           = "dss_dsi1",
801         .class          = &omap44xx_dsi_hwmod_class,
802         .clkdm_name     = "l3_dss_clkdm",
803         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
804         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
805         .main_clk       = "dss_dss_clk",
806         .prcm = {
807                 .omap4 = {
808                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
809                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
810                 },
811         },
812         .opt_clks       = dss_dsi1_opt_clks,
813         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
814 };
815
816 /* dss_dsi2 */
817 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
818         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
819         { .irq = -1 }
820 };
821
822 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
823         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
824         { .dma_req = -1 }
825 };
826
827 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
828         { .role = "sys_clk", .clk = "dss_sys_clk" },
829 };
830
831 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
832         .name           = "dss_dsi2",
833         .class          = &omap44xx_dsi_hwmod_class,
834         .clkdm_name     = "l3_dss_clkdm",
835         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
836         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
837         .main_clk       = "dss_dss_clk",
838         .prcm = {
839                 .omap4 = {
840                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
841                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
842                 },
843         },
844         .opt_clks       = dss_dsi2_opt_clks,
845         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
846 };
847
848 /*
849  * 'hdmi' class
850  * hdmi controller
851  */
852
853 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
854         .rev_offs       = 0x0000,
855         .sysc_offs      = 0x0010,
856         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
857                            SYSC_HAS_SOFTRESET),
858         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
859                            SIDLE_SMART_WKUP),
860         .sysc_fields    = &omap_hwmod_sysc_type2,
861 };
862
863 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
864         .name   = "hdmi",
865         .sysc   = &omap44xx_hdmi_sysc,
866 };
867
868 /* dss_hdmi */
869 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
870         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
871         { .irq = -1 }
872 };
873
874 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
875         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
876         { .dma_req = -1 }
877 };
878
879 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
880         { .role = "sys_clk", .clk = "dss_sys_clk" },
881 };
882
883 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
884         .name           = "dss_hdmi",
885         .class          = &omap44xx_hdmi_hwmod_class,
886         .clkdm_name     = "l3_dss_clkdm",
887         /*
888          * HDMI audio requires to use no-idle mode. Hence,
889          * set idle mode by software.
890          */
891         .flags          = HWMOD_SWSUP_SIDLE,
892         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
893         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
894         .main_clk       = "dss_48mhz_clk",
895         .prcm = {
896                 .omap4 = {
897                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
898                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
899                 },
900         },
901         .opt_clks       = dss_hdmi_opt_clks,
902         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
903 };
904
905 /*
906  * 'rfbi' class
907  * remote frame buffer interface
908  */
909
910 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
911         .rev_offs       = 0x0000,
912         .sysc_offs      = 0x0010,
913         .syss_offs      = 0x0014,
914         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
915                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
916         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
917         .sysc_fields    = &omap_hwmod_sysc_type1,
918 };
919
920 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
921         .name   = "rfbi",
922         .sysc   = &omap44xx_rfbi_sysc,
923 };
924
925 /* dss_rfbi */
926 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
927         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
928         { .dma_req = -1 }
929 };
930
931 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
932         { .role = "ick", .clk = "dss_fck" },
933 };
934
935 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
936         .name           = "dss_rfbi",
937         .class          = &omap44xx_rfbi_hwmod_class,
938         .clkdm_name     = "l3_dss_clkdm",
939         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
940         .main_clk       = "dss_dss_clk",
941         .prcm = {
942                 .omap4 = {
943                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
944                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
945                 },
946         },
947         .opt_clks       = dss_rfbi_opt_clks,
948         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
949 };
950
951 /*
952  * 'venc' class
953  * video encoder
954  */
955
956 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
957         .name   = "venc",
958 };
959
960 /* dss_venc */
961 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
962         .name           = "dss_venc",
963         .class          = &omap44xx_venc_hwmod_class,
964         .clkdm_name     = "l3_dss_clkdm",
965         .main_clk       = "dss_tv_clk",
966         .prcm = {
967                 .omap4 = {
968                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
969                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
970                 },
971         },
972 };
973
974 /*
975  * 'elm' class
976  * bch error location module
977  */
978
979 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
980         .rev_offs       = 0x0000,
981         .sysc_offs      = 0x0010,
982         .syss_offs      = 0x0014,
983         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
984                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
985                            SYSS_HAS_RESET_STATUS),
986         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
987         .sysc_fields    = &omap_hwmod_sysc_type1,
988 };
989
990 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
991         .name   = "elm",
992         .sysc   = &omap44xx_elm_sysc,
993 };
994
995 /* elm */
996 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
997         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
998         { .irq = -1 }
999 };
1000
1001 static struct omap_hwmod omap44xx_elm_hwmod = {
1002         .name           = "elm",
1003         .class          = &omap44xx_elm_hwmod_class,
1004         .clkdm_name     = "l4_per_clkdm",
1005         .mpu_irqs       = omap44xx_elm_irqs,
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1009                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1010                 },
1011         },
1012 };
1013
1014 /*
1015  * 'emif' class
1016  * external memory interface no1
1017  */
1018
1019 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1020         .rev_offs       = 0x0000,
1021 };
1022
1023 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1024         .name   = "emif",
1025         .sysc   = &omap44xx_emif_sysc,
1026 };
1027
1028 /* emif1 */
1029 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1030         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1031         { .irq = -1 }
1032 };
1033
1034 static struct omap_hwmod omap44xx_emif1_hwmod = {
1035         .name           = "emif1",
1036         .class          = &omap44xx_emif_hwmod_class,
1037         .clkdm_name     = "l3_emif_clkdm",
1038         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1039         .mpu_irqs       = omap44xx_emif1_irqs,
1040         .main_clk       = "ddrphy_ck",
1041         .prcm = {
1042                 .omap4 = {
1043                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1044                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1045                         .modulemode   = MODULEMODE_HWCTRL,
1046                 },
1047         },
1048 };
1049
1050 /* emif2 */
1051 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1052         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1053         { .irq = -1 }
1054 };
1055
1056 static struct omap_hwmod omap44xx_emif2_hwmod = {
1057         .name           = "emif2",
1058         .class          = &omap44xx_emif_hwmod_class,
1059         .clkdm_name     = "l3_emif_clkdm",
1060         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1061         .mpu_irqs       = omap44xx_emif2_irqs,
1062         .main_clk       = "ddrphy_ck",
1063         .prcm = {
1064                 .omap4 = {
1065                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1066                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1067                         .modulemode   = MODULEMODE_HWCTRL,
1068                 },
1069         },
1070 };
1071
1072 /*
1073  * 'fdif' class
1074  * face detection hw accelerator module
1075  */
1076
1077 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1078         .rev_offs       = 0x0000,
1079         .sysc_offs      = 0x0010,
1080         /*
1081          * FDIF needs 100 OCP clk cycles delay after a softreset before
1082          * accessing sysconfig again.
1083          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1084          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1085          *
1086          * TODO: Indicate errata when available.
1087          */
1088         .srst_udelay    = 2,
1089         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1090                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1091         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1092                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1093         .sysc_fields    = &omap_hwmod_sysc_type2,
1094 };
1095
1096 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1097         .name   = "fdif",
1098         .sysc   = &omap44xx_fdif_sysc,
1099 };
1100
1101 /* fdif */
1102 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1103         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1104         { .irq = -1 }
1105 };
1106
1107 static struct omap_hwmod omap44xx_fdif_hwmod = {
1108         .name           = "fdif",
1109         .class          = &omap44xx_fdif_hwmod_class,
1110         .clkdm_name     = "iss_clkdm",
1111         .mpu_irqs       = omap44xx_fdif_irqs,
1112         .main_clk       = "fdif_fck",
1113         .prcm = {
1114                 .omap4 = {
1115                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1116                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1117                         .modulemode   = MODULEMODE_SWCTRL,
1118                 },
1119         },
1120 };
1121
1122 /*
1123  * 'gpio' class
1124  * general purpose io module
1125  */
1126
1127 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1128         .rev_offs       = 0x0000,
1129         .sysc_offs      = 0x0010,
1130         .syss_offs      = 0x0114,
1131         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1132                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1133                            SYSS_HAS_RESET_STATUS),
1134         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1135                            SIDLE_SMART_WKUP),
1136         .sysc_fields    = &omap_hwmod_sysc_type1,
1137 };
1138
1139 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1140         .name   = "gpio",
1141         .sysc   = &omap44xx_gpio_sysc,
1142         .rev    = 2,
1143 };
1144
1145 /* gpio dev_attr */
1146 static struct omap_gpio_dev_attr gpio_dev_attr = {
1147         .bank_width     = 32,
1148         .dbck_flag      = true,
1149 };
1150
1151 /* gpio1 */
1152 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1153         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1154         { .irq = -1 }
1155 };
1156
1157 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1158         { .role = "dbclk", .clk = "gpio1_dbclk" },
1159 };
1160
1161 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1162         .name           = "gpio1",
1163         .class          = &omap44xx_gpio_hwmod_class,
1164         .clkdm_name     = "l4_wkup_clkdm",
1165         .mpu_irqs       = omap44xx_gpio1_irqs,
1166         .main_clk       = "gpio1_ick",
1167         .prcm = {
1168                 .omap4 = {
1169                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1170                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1171                         .modulemode   = MODULEMODE_HWCTRL,
1172                 },
1173         },
1174         .opt_clks       = gpio1_opt_clks,
1175         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1176         .dev_attr       = &gpio_dev_attr,
1177 };
1178
1179 /* gpio2 */
1180 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1181         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1182         { .irq = -1 }
1183 };
1184
1185 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1186         { .role = "dbclk", .clk = "gpio2_dbclk" },
1187 };
1188
1189 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1190         .name           = "gpio2",
1191         .class          = &omap44xx_gpio_hwmod_class,
1192         .clkdm_name     = "l4_per_clkdm",
1193         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1194         .mpu_irqs       = omap44xx_gpio2_irqs,
1195         .main_clk       = "gpio2_ick",
1196         .prcm = {
1197                 .omap4 = {
1198                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1199                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1200                         .modulemode   = MODULEMODE_HWCTRL,
1201                 },
1202         },
1203         .opt_clks       = gpio2_opt_clks,
1204         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1205         .dev_attr       = &gpio_dev_attr,
1206 };
1207
1208 /* gpio3 */
1209 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1210         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1211         { .irq = -1 }
1212 };
1213
1214 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1215         { .role = "dbclk", .clk = "gpio3_dbclk" },
1216 };
1217
1218 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1219         .name           = "gpio3",
1220         .class          = &omap44xx_gpio_hwmod_class,
1221         .clkdm_name     = "l4_per_clkdm",
1222         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1223         .mpu_irqs       = omap44xx_gpio3_irqs,
1224         .main_clk       = "gpio3_ick",
1225         .prcm = {
1226                 .omap4 = {
1227                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1228                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1229                         .modulemode   = MODULEMODE_HWCTRL,
1230                 },
1231         },
1232         .opt_clks       = gpio3_opt_clks,
1233         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1234         .dev_attr       = &gpio_dev_attr,
1235 };
1236
1237 /* gpio4 */
1238 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1239         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1240         { .irq = -1 }
1241 };
1242
1243 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1244         { .role = "dbclk", .clk = "gpio4_dbclk" },
1245 };
1246
1247 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1248         .name           = "gpio4",
1249         .class          = &omap44xx_gpio_hwmod_class,
1250         .clkdm_name     = "l4_per_clkdm",
1251         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1252         .mpu_irqs       = omap44xx_gpio4_irqs,
1253         .main_clk       = "gpio4_ick",
1254         .prcm = {
1255                 .omap4 = {
1256                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1257                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1258                         .modulemode   = MODULEMODE_HWCTRL,
1259                 },
1260         },
1261         .opt_clks       = gpio4_opt_clks,
1262         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1263         .dev_attr       = &gpio_dev_attr,
1264 };
1265
1266 /* gpio5 */
1267 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1268         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1269         { .irq = -1 }
1270 };
1271
1272 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1273         { .role = "dbclk", .clk = "gpio5_dbclk" },
1274 };
1275
1276 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1277         .name           = "gpio5",
1278         .class          = &omap44xx_gpio_hwmod_class,
1279         .clkdm_name     = "l4_per_clkdm",
1280         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1281         .mpu_irqs       = omap44xx_gpio5_irqs,
1282         .main_clk       = "gpio5_ick",
1283         .prcm = {
1284                 .omap4 = {
1285                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1286                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1287                         .modulemode   = MODULEMODE_HWCTRL,
1288                 },
1289         },
1290         .opt_clks       = gpio5_opt_clks,
1291         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1292         .dev_attr       = &gpio_dev_attr,
1293 };
1294
1295 /* gpio6 */
1296 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1297         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1298         { .irq = -1 }
1299 };
1300
1301 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1302         { .role = "dbclk", .clk = "gpio6_dbclk" },
1303 };
1304
1305 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1306         .name           = "gpio6",
1307         .class          = &omap44xx_gpio_hwmod_class,
1308         .clkdm_name     = "l4_per_clkdm",
1309         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1310         .mpu_irqs       = omap44xx_gpio6_irqs,
1311         .main_clk       = "gpio6_ick",
1312         .prcm = {
1313                 .omap4 = {
1314                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1315                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1316                         .modulemode   = MODULEMODE_HWCTRL,
1317                 },
1318         },
1319         .opt_clks       = gpio6_opt_clks,
1320         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1321         .dev_attr       = &gpio_dev_attr,
1322 };
1323
1324 /*
1325  * 'gpmc' class
1326  * general purpose memory controller
1327  */
1328
1329 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1330         .rev_offs       = 0x0000,
1331         .sysc_offs      = 0x0010,
1332         .syss_offs      = 0x0014,
1333         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1334                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1335         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1336         .sysc_fields    = &omap_hwmod_sysc_type1,
1337 };
1338
1339 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1340         .name   = "gpmc",
1341         .sysc   = &omap44xx_gpmc_sysc,
1342 };
1343
1344 /* gpmc */
1345 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1346         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1347         { .irq = -1 }
1348 };
1349
1350 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1351         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1352         { .dma_req = -1 }
1353 };
1354
1355 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1356         .name           = "gpmc",
1357         .class          = &omap44xx_gpmc_hwmod_class,
1358         .clkdm_name     = "l3_2_clkdm",
1359         /*
1360          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1361          * block.  It is not being added due to any known bugs with
1362          * resetting the GPMC IP block, but rather because any timings
1363          * set by the bootloader are not being correctly programmed by
1364          * the kernel from the board file or DT data.
1365          * HWMOD_INIT_NO_RESET should be removed ASAP.
1366          */
1367         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1368         .mpu_irqs       = omap44xx_gpmc_irqs,
1369         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1370         .prcm = {
1371                 .omap4 = {
1372                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1373                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1374                         .modulemode   = MODULEMODE_HWCTRL,
1375                 },
1376         },
1377 };
1378
1379 /*
1380  * 'gpu' class
1381  * 2d/3d graphics accelerator
1382  */
1383
1384 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1385         .rev_offs       = 0x1fc00,
1386         .sysc_offs      = 0x1fc10,
1387         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1388         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1389                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1390                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1391         .sysc_fields    = &omap_hwmod_sysc_type2,
1392 };
1393
1394 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1395         .name   = "gpu",
1396         .sysc   = &omap44xx_gpu_sysc,
1397 };
1398
1399 /* gpu */
1400 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1401         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1402         { .irq = -1 }
1403 };
1404
1405 static struct omap_hwmod omap44xx_gpu_hwmod = {
1406         .name           = "gpu",
1407         .class          = &omap44xx_gpu_hwmod_class,
1408         .clkdm_name     = "l3_gfx_clkdm",
1409         .mpu_irqs       = omap44xx_gpu_irqs,
1410         .main_clk       = "gpu_fck",
1411         .prcm = {
1412                 .omap4 = {
1413                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1414                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1415                         .modulemode   = MODULEMODE_SWCTRL,
1416                 },
1417         },
1418 };
1419
1420 /*
1421  * 'hdq1w' class
1422  * hdq / 1-wire serial interface controller
1423  */
1424
1425 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1426         .rev_offs       = 0x0000,
1427         .sysc_offs      = 0x0014,
1428         .syss_offs      = 0x0018,
1429         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1430                            SYSS_HAS_RESET_STATUS),
1431         .sysc_fields    = &omap_hwmod_sysc_type1,
1432 };
1433
1434 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1435         .name   = "hdq1w",
1436         .sysc   = &omap44xx_hdq1w_sysc,
1437 };
1438
1439 /* hdq1w */
1440 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1441         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1442         { .irq = -1 }
1443 };
1444
1445 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1446         .name           = "hdq1w",
1447         .class          = &omap44xx_hdq1w_hwmod_class,
1448         .clkdm_name     = "l4_per_clkdm",
1449         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1450         .mpu_irqs       = omap44xx_hdq1w_irqs,
1451         .main_clk       = "hdq1w_fck",
1452         .prcm = {
1453                 .omap4 = {
1454                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1455                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1456                         .modulemode   = MODULEMODE_SWCTRL,
1457                 },
1458         },
1459 };
1460
1461 /*
1462  * 'hsi' class
1463  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1464  * serial if)
1465  */
1466
1467 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1468         .rev_offs       = 0x0000,
1469         .sysc_offs      = 0x0010,
1470         .syss_offs      = 0x0014,
1471         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1472                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1473                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1474         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1475                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1476                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1477         .sysc_fields    = &omap_hwmod_sysc_type1,
1478 };
1479
1480 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1481         .name   = "hsi",
1482         .sysc   = &omap44xx_hsi_sysc,
1483 };
1484
1485 /* hsi */
1486 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1487         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1488         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1489         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1490         { .irq = -1 }
1491 };
1492
1493 static struct omap_hwmod omap44xx_hsi_hwmod = {
1494         .name           = "hsi",
1495         .class          = &omap44xx_hsi_hwmod_class,
1496         .clkdm_name     = "l3_init_clkdm",
1497         .mpu_irqs       = omap44xx_hsi_irqs,
1498         .main_clk       = "hsi_fck",
1499         .prcm = {
1500                 .omap4 = {
1501                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1502                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1503                         .modulemode   = MODULEMODE_HWCTRL,
1504                 },
1505         },
1506 };
1507
1508 /*
1509  * 'i2c' class
1510  * multimaster high-speed i2c controller
1511  */
1512
1513 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1514         .sysc_offs      = 0x0010,
1515         .syss_offs      = 0x0090,
1516         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1517                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1518                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1519         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1520                            SIDLE_SMART_WKUP),
1521         .clockact       = CLOCKACT_TEST_ICLK,
1522         .sysc_fields    = &omap_hwmod_sysc_type1,
1523 };
1524
1525 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1526         .name   = "i2c",
1527         .sysc   = &omap44xx_i2c_sysc,
1528         .rev    = OMAP_I2C_IP_VERSION_2,
1529         .reset  = &omap_i2c_reset,
1530 };
1531
1532 static struct omap_i2c_dev_attr i2c_dev_attr = {
1533         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1534                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1535 };
1536
1537 /* i2c1 */
1538 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1539         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1540         { .irq = -1 }
1541 };
1542
1543 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1544         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1545         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1546         { .dma_req = -1 }
1547 };
1548
1549 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1550         .name           = "i2c1",
1551         .class          = &omap44xx_i2c_hwmod_class,
1552         .clkdm_name     = "l4_per_clkdm",
1553         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1554         .mpu_irqs       = omap44xx_i2c1_irqs,
1555         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1556         .main_clk       = "i2c1_fck",
1557         .prcm = {
1558                 .omap4 = {
1559                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1560                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1561                         .modulemode   = MODULEMODE_SWCTRL,
1562                 },
1563         },
1564         .dev_attr       = &i2c_dev_attr,
1565 };
1566
1567 /* i2c2 */
1568 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1569         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1570         { .irq = -1 }
1571 };
1572
1573 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1574         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1575         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1576         { .dma_req = -1 }
1577 };
1578
1579 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1580         .name           = "i2c2",
1581         .class          = &omap44xx_i2c_hwmod_class,
1582         .clkdm_name     = "l4_per_clkdm",
1583         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1584         .mpu_irqs       = omap44xx_i2c2_irqs,
1585         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1586         .main_clk       = "i2c2_fck",
1587         .prcm = {
1588                 .omap4 = {
1589                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1590                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1591                         .modulemode   = MODULEMODE_SWCTRL,
1592                 },
1593         },
1594         .dev_attr       = &i2c_dev_attr,
1595 };
1596
1597 /* i2c3 */
1598 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1599         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1600         { .irq = -1 }
1601 };
1602
1603 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1604         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1605         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1606         { .dma_req = -1 }
1607 };
1608
1609 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1610         .name           = "i2c3",
1611         .class          = &omap44xx_i2c_hwmod_class,
1612         .clkdm_name     = "l4_per_clkdm",
1613         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1614         .mpu_irqs       = omap44xx_i2c3_irqs,
1615         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1616         .main_clk       = "i2c3_fck",
1617         .prcm = {
1618                 .omap4 = {
1619                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1620                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1621                         .modulemode   = MODULEMODE_SWCTRL,
1622                 },
1623         },
1624         .dev_attr       = &i2c_dev_attr,
1625 };
1626
1627 /* i2c4 */
1628 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1629         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1630         { .irq = -1 }
1631 };
1632
1633 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1634         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1635         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1636         { .dma_req = -1 }
1637 };
1638
1639 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1640         .name           = "i2c4",
1641         .class          = &omap44xx_i2c_hwmod_class,
1642         .clkdm_name     = "l4_per_clkdm",
1643         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1644         .mpu_irqs       = omap44xx_i2c4_irqs,
1645         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1646         .main_clk       = "i2c4_fck",
1647         .prcm = {
1648                 .omap4 = {
1649                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1650                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1651                         .modulemode   = MODULEMODE_SWCTRL,
1652                 },
1653         },
1654         .dev_attr       = &i2c_dev_attr,
1655 };
1656
1657 /*
1658  * 'ipu' class
1659  * imaging processor unit
1660  */
1661
1662 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1663         .name   = "ipu",
1664 };
1665
1666 /* ipu */
1667 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1668         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1669         { .irq = -1 }
1670 };
1671
1672 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1673         { .name = "cpu0", .rst_shift = 0 },
1674         { .name = "cpu1", .rst_shift = 1 },
1675 };
1676
1677 static struct omap_hwmod omap44xx_ipu_hwmod = {
1678         .name           = "ipu",
1679         .class          = &omap44xx_ipu_hwmod_class,
1680         .clkdm_name     = "ducati_clkdm",
1681         .mpu_irqs       = omap44xx_ipu_irqs,
1682         .rst_lines      = omap44xx_ipu_resets,
1683         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1684         .main_clk       = "ipu_fck",
1685         .prcm = {
1686                 .omap4 = {
1687                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1688                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1689                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1690                         .modulemode   = MODULEMODE_HWCTRL,
1691                 },
1692         },
1693 };
1694
1695 /*
1696  * 'iss' class
1697  * external images sensor pixel data processor
1698  */
1699
1700 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1701         .rev_offs       = 0x0000,
1702         .sysc_offs      = 0x0010,
1703         /*
1704          * ISS needs 100 OCP clk cycles delay after a softreset before
1705          * accessing sysconfig again.
1706          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1707          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1708          *
1709          * TODO: Indicate errata when available.
1710          */
1711         .srst_udelay    = 2,
1712         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1713                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1714         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1715                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1716                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1717         .sysc_fields    = &omap_hwmod_sysc_type2,
1718 };
1719
1720 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1721         .name   = "iss",
1722         .sysc   = &omap44xx_iss_sysc,
1723 };
1724
1725 /* iss */
1726 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1727         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1728         { .irq = -1 }
1729 };
1730
1731 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1732         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1733         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1734         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1735         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1736         { .dma_req = -1 }
1737 };
1738
1739 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1740         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1741 };
1742
1743 static struct omap_hwmod omap44xx_iss_hwmod = {
1744         .name           = "iss",
1745         .class          = &omap44xx_iss_hwmod_class,
1746         .clkdm_name     = "iss_clkdm",
1747         .mpu_irqs       = omap44xx_iss_irqs,
1748         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1749         .main_clk       = "iss_fck",
1750         .prcm = {
1751                 .omap4 = {
1752                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1753                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1754                         .modulemode   = MODULEMODE_SWCTRL,
1755                 },
1756         },
1757         .opt_clks       = iss_opt_clks,
1758         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1759 };
1760
1761 /*
1762  * 'iva' class
1763  * multi-standard video encoder/decoder hardware accelerator
1764  */
1765
1766 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1767         .name   = "iva",
1768 };
1769
1770 /* iva */
1771 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1772         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1773         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1774         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1775         { .irq = -1 }
1776 };
1777
1778 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1779         { .name = "seq0", .rst_shift = 0 },
1780         { .name = "seq1", .rst_shift = 1 },
1781         { .name = "logic", .rst_shift = 2 },
1782 };
1783
1784 static struct omap_hwmod omap44xx_iva_hwmod = {
1785         .name           = "iva",
1786         .class          = &omap44xx_iva_hwmod_class,
1787         .clkdm_name     = "ivahd_clkdm",
1788         .mpu_irqs       = omap44xx_iva_irqs,
1789         .rst_lines      = omap44xx_iva_resets,
1790         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1791         .main_clk       = "iva_fck",
1792         .prcm = {
1793                 .omap4 = {
1794                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1795                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1796                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1797                         .modulemode   = MODULEMODE_HWCTRL,
1798                 },
1799         },
1800 };
1801
1802 /*
1803  * 'kbd' class
1804  * keyboard controller
1805  */
1806
1807 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1808         .rev_offs       = 0x0000,
1809         .sysc_offs      = 0x0010,
1810         .syss_offs      = 0x0014,
1811         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1812                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1813                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1814                            SYSS_HAS_RESET_STATUS),
1815         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1816         .sysc_fields    = &omap_hwmod_sysc_type1,
1817 };
1818
1819 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1820         .name   = "kbd",
1821         .sysc   = &omap44xx_kbd_sysc,
1822 };
1823
1824 /* kbd */
1825 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1826         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1827         { .irq = -1 }
1828 };
1829
1830 static struct omap_hwmod omap44xx_kbd_hwmod = {
1831         .name           = "kbd",
1832         .class          = &omap44xx_kbd_hwmod_class,
1833         .clkdm_name     = "l4_wkup_clkdm",
1834         .mpu_irqs       = omap44xx_kbd_irqs,
1835         .main_clk       = "kbd_fck",
1836         .prcm = {
1837                 .omap4 = {
1838                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1839                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1840                         .modulemode   = MODULEMODE_SWCTRL,
1841                 },
1842         },
1843 };
1844
1845 /*
1846  * 'mailbox' class
1847  * mailbox module allowing communication between the on-chip processors using a
1848  * queued mailbox-interrupt mechanism.
1849  */
1850
1851 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1852         .rev_offs       = 0x0000,
1853         .sysc_offs      = 0x0010,
1854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1855                            SYSC_HAS_SOFTRESET),
1856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1857         .sysc_fields    = &omap_hwmod_sysc_type2,
1858 };
1859
1860 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1861         .name   = "mailbox",
1862         .sysc   = &omap44xx_mailbox_sysc,
1863 };
1864
1865 /* mailbox */
1866 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1867         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1868         { .irq = -1 }
1869 };
1870
1871 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1872         .name           = "mailbox",
1873         .class          = &omap44xx_mailbox_hwmod_class,
1874         .clkdm_name     = "l4_cfg_clkdm",
1875         .mpu_irqs       = omap44xx_mailbox_irqs,
1876         .prcm = {
1877                 .omap4 = {
1878                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1879                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1880                 },
1881         },
1882 };
1883
1884 /*
1885  * 'mcasp' class
1886  * multi-channel audio serial port controller
1887  */
1888
1889 /* The IP is not compliant to type1 / type2 scheme */
1890 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1891         .sidle_shift    = 0,
1892 };
1893
1894 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1895         .sysc_offs      = 0x0004,
1896         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1897         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1898                            SIDLE_SMART_WKUP),
1899         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1900 };
1901
1902 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1903         .name   = "mcasp",
1904         .sysc   = &omap44xx_mcasp_sysc,
1905 };
1906
1907 /* mcasp */
1908 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1909         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1910         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1911         { .irq = -1 }
1912 };
1913
1914 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1915         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1916         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1917         { .dma_req = -1 }
1918 };
1919
1920 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1921         .name           = "mcasp",
1922         .class          = &omap44xx_mcasp_hwmod_class,
1923         .clkdm_name     = "abe_clkdm",
1924         .mpu_irqs       = omap44xx_mcasp_irqs,
1925         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1926         .main_clk       = "mcasp_fck",
1927         .prcm = {
1928                 .omap4 = {
1929                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1930                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1931                         .modulemode   = MODULEMODE_SWCTRL,
1932                 },
1933         },
1934 };
1935
1936 /*
1937  * 'mcbsp' class
1938  * multi channel buffered serial port controller
1939  */
1940
1941 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1942         .sysc_offs      = 0x008c,
1943         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1944                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1945         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1946         .sysc_fields    = &omap_hwmod_sysc_type1,
1947 };
1948
1949 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1950         .name   = "mcbsp",
1951         .sysc   = &omap44xx_mcbsp_sysc,
1952         .rev    = MCBSP_CONFIG_TYPE4,
1953 };
1954
1955 /* mcbsp1 */
1956 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1957         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1958         { .irq = -1 }
1959 };
1960
1961 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1962         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1963         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1964         { .dma_req = -1 }
1965 };
1966
1967 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1968         { .role = "pad_fck", .clk = "pad_clks_ck" },
1969         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1970 };
1971
1972 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1973         .name           = "mcbsp1",
1974         .class          = &omap44xx_mcbsp_hwmod_class,
1975         .clkdm_name     = "abe_clkdm",
1976         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1977         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1978         .main_clk       = "mcbsp1_fck",
1979         .prcm = {
1980                 .omap4 = {
1981                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1982                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1983                         .modulemode   = MODULEMODE_SWCTRL,
1984                 },
1985         },
1986         .opt_clks       = mcbsp1_opt_clks,
1987         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1988 };
1989
1990 /* mcbsp2 */
1991 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1992         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1993         { .irq = -1 }
1994 };
1995
1996 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1997         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1998         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1999         { .dma_req = -1 }
2000 };
2001
2002 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2003         { .role = "pad_fck", .clk = "pad_clks_ck" },
2004         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2005 };
2006
2007 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2008         .name           = "mcbsp2",
2009         .class          = &omap44xx_mcbsp_hwmod_class,
2010         .clkdm_name     = "abe_clkdm",
2011         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2012         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2013         .main_clk       = "mcbsp2_fck",
2014         .prcm = {
2015                 .omap4 = {
2016                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2017                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2018                         .modulemode   = MODULEMODE_SWCTRL,
2019                 },
2020         },
2021         .opt_clks       = mcbsp2_opt_clks,
2022         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2023 };
2024
2025 /* mcbsp3 */
2026 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2027         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2028         { .irq = -1 }
2029 };
2030
2031 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2032         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2033         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2034         { .dma_req = -1 }
2035 };
2036
2037 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2038         { .role = "pad_fck", .clk = "pad_clks_ck" },
2039         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2040 };
2041
2042 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2043         .name           = "mcbsp3",
2044         .class          = &omap44xx_mcbsp_hwmod_class,
2045         .clkdm_name     = "abe_clkdm",
2046         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2047         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2048         .main_clk       = "mcbsp3_fck",
2049         .prcm = {
2050                 .omap4 = {
2051                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2052                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2053                         .modulemode   = MODULEMODE_SWCTRL,
2054                 },
2055         },
2056         .opt_clks       = mcbsp3_opt_clks,
2057         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2058 };
2059
2060 /* mcbsp4 */
2061 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2062         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2063         { .irq = -1 }
2064 };
2065
2066 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2067         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2068         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2069         { .dma_req = -1 }
2070 };
2071
2072 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2073         { .role = "pad_fck", .clk = "pad_clks_ck" },
2074         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2075 };
2076
2077 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2078         .name           = "mcbsp4",
2079         .class          = &omap44xx_mcbsp_hwmod_class,
2080         .clkdm_name     = "l4_per_clkdm",
2081         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2082         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2083         .main_clk       = "mcbsp4_fck",
2084         .prcm = {
2085                 .omap4 = {
2086                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2087                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2088                         .modulemode   = MODULEMODE_SWCTRL,
2089                 },
2090         },
2091         .opt_clks       = mcbsp4_opt_clks,
2092         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2093 };
2094
2095 /*
2096  * 'mcpdm' class
2097  * multi channel pdm controller (proprietary interface with phoenix power
2098  * ic)
2099  */
2100
2101 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2102         .rev_offs       = 0x0000,
2103         .sysc_offs      = 0x0010,
2104         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2105                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2106         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2107                            SIDLE_SMART_WKUP),
2108         .sysc_fields    = &omap_hwmod_sysc_type2,
2109 };
2110
2111 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2112         .name   = "mcpdm",
2113         .sysc   = &omap44xx_mcpdm_sysc,
2114 };
2115
2116 /* mcpdm */
2117 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2118         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2119         { .irq = -1 }
2120 };
2121
2122 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2123         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2124         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2125         { .dma_req = -1 }
2126 };
2127
2128 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2129         .name           = "mcpdm",
2130         .class          = &omap44xx_mcpdm_hwmod_class,
2131         .clkdm_name     = "abe_clkdm",
2132         /*
2133          * It's suspected that the McPDM requires an off-chip main
2134          * functional clock, controlled via I2C.  This IP block is
2135          * currently reset very early during boot, before I2C is
2136          * available, so it doesn't seem that we have any choice in
2137          * the kernel other than to avoid resetting it.
2138          */
2139         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2140         .mpu_irqs       = omap44xx_mcpdm_irqs,
2141         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2142         .main_clk       = "mcpdm_fck",
2143         .prcm = {
2144                 .omap4 = {
2145                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2146                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2147                         .modulemode   = MODULEMODE_SWCTRL,
2148                 },
2149         },
2150 };
2151
2152 /*
2153  * 'mcspi' class
2154  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2155  * bus
2156  */
2157
2158 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2159         .rev_offs       = 0x0000,
2160         .sysc_offs      = 0x0010,
2161         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2162                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2164                            SIDLE_SMART_WKUP),
2165         .sysc_fields    = &omap_hwmod_sysc_type2,
2166 };
2167
2168 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2169         .name   = "mcspi",
2170         .sysc   = &omap44xx_mcspi_sysc,
2171         .rev    = OMAP4_MCSPI_REV,
2172 };
2173
2174 /* mcspi1 */
2175 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2176         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2177         { .irq = -1 }
2178 };
2179
2180 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2181         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2182         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2183         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2184         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2185         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2186         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2187         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2188         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2189         { .dma_req = -1 }
2190 };
2191
2192 /* mcspi1 dev_attr */
2193 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2194         .num_chipselect = 4,
2195 };
2196
2197 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2198         .name           = "mcspi1",
2199         .class          = &omap44xx_mcspi_hwmod_class,
2200         .clkdm_name     = "l4_per_clkdm",
2201         .mpu_irqs       = omap44xx_mcspi1_irqs,
2202         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2203         .main_clk       = "mcspi1_fck",
2204         .prcm = {
2205                 .omap4 = {
2206                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2207                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2208                         .modulemode   = MODULEMODE_SWCTRL,
2209                 },
2210         },
2211         .dev_attr       = &mcspi1_dev_attr,
2212 };
2213
2214 /* mcspi2 */
2215 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2216         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2217         { .irq = -1 }
2218 };
2219
2220 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2221         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2222         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2223         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2224         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2225         { .dma_req = -1 }
2226 };
2227
2228 /* mcspi2 dev_attr */
2229 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2230         .num_chipselect = 2,
2231 };
2232
2233 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2234         .name           = "mcspi2",
2235         .class          = &omap44xx_mcspi_hwmod_class,
2236         .clkdm_name     = "l4_per_clkdm",
2237         .mpu_irqs       = omap44xx_mcspi2_irqs,
2238         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2239         .main_clk       = "mcspi2_fck",
2240         .prcm = {
2241                 .omap4 = {
2242                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2243                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2244                         .modulemode   = MODULEMODE_SWCTRL,
2245                 },
2246         },
2247         .dev_attr       = &mcspi2_dev_attr,
2248 };
2249
2250 /* mcspi3 */
2251 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2252         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2253         { .irq = -1 }
2254 };
2255
2256 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2257         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2258         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2259         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2260         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2261         { .dma_req = -1 }
2262 };
2263
2264 /* mcspi3 dev_attr */
2265 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2266         .num_chipselect = 2,
2267 };
2268
2269 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2270         .name           = "mcspi3",
2271         .class          = &omap44xx_mcspi_hwmod_class,
2272         .clkdm_name     = "l4_per_clkdm",
2273         .mpu_irqs       = omap44xx_mcspi3_irqs,
2274         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2275         .main_clk       = "mcspi3_fck",
2276         .prcm = {
2277                 .omap4 = {
2278                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2279                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2280                         .modulemode   = MODULEMODE_SWCTRL,
2281                 },
2282         },
2283         .dev_attr       = &mcspi3_dev_attr,
2284 };
2285
2286 /* mcspi4 */
2287 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2288         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2289         { .irq = -1 }
2290 };
2291
2292 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2293         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2294         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2295         { .dma_req = -1 }
2296 };
2297
2298 /* mcspi4 dev_attr */
2299 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2300         .num_chipselect = 1,
2301 };
2302
2303 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2304         .name           = "mcspi4",
2305         .class          = &omap44xx_mcspi_hwmod_class,
2306         .clkdm_name     = "l4_per_clkdm",
2307         .mpu_irqs       = omap44xx_mcspi4_irqs,
2308         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2309         .main_clk       = "mcspi4_fck",
2310         .prcm = {
2311                 .omap4 = {
2312                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2313                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2314                         .modulemode   = MODULEMODE_SWCTRL,
2315                 },
2316         },
2317         .dev_attr       = &mcspi4_dev_attr,
2318 };
2319
2320 /*
2321  * 'mmc' class
2322  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2323  */
2324
2325 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2326         .rev_offs       = 0x0000,
2327         .sysc_offs      = 0x0010,
2328         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2329                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2330                            SYSC_HAS_SOFTRESET),
2331         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2332                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2333                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2334         .sysc_fields    = &omap_hwmod_sysc_type2,
2335 };
2336
2337 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2338         .name   = "mmc",
2339         .sysc   = &omap44xx_mmc_sysc,
2340 };
2341
2342 /* mmc1 */
2343 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2344         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2345         { .irq = -1 }
2346 };
2347
2348 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2349         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2350         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2351         { .dma_req = -1 }
2352 };
2353
2354 /* mmc1 dev_attr */
2355 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2356         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2357 };
2358
2359 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2360         .name           = "mmc1",
2361         .class          = &omap44xx_mmc_hwmod_class,
2362         .clkdm_name     = "l3_init_clkdm",
2363         .mpu_irqs       = omap44xx_mmc1_irqs,
2364         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2365         .main_clk       = "mmc1_fck",
2366         .prcm = {
2367                 .omap4 = {
2368                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2369                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2370                         .modulemode   = MODULEMODE_SWCTRL,
2371                 },
2372         },
2373         .dev_attr       = &mmc1_dev_attr,
2374 };
2375
2376 /* mmc2 */
2377 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2378         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2379         { .irq = -1 }
2380 };
2381
2382 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2383         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2384         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2385         { .dma_req = -1 }
2386 };
2387
2388 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2389         .name           = "mmc2",
2390         .class          = &omap44xx_mmc_hwmod_class,
2391         .clkdm_name     = "l3_init_clkdm",
2392         .mpu_irqs       = omap44xx_mmc2_irqs,
2393         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2394         .main_clk       = "mmc2_fck",
2395         .prcm = {
2396                 .omap4 = {
2397                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2398                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2399                         .modulemode   = MODULEMODE_SWCTRL,
2400                 },
2401         },
2402 };
2403
2404 /* mmc3 */
2405 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2406         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2407         { .irq = -1 }
2408 };
2409
2410 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2411         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2412         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2413         { .dma_req = -1 }
2414 };
2415
2416 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2417         .name           = "mmc3",
2418         .class          = &omap44xx_mmc_hwmod_class,
2419         .clkdm_name     = "l4_per_clkdm",
2420         .mpu_irqs       = omap44xx_mmc3_irqs,
2421         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2422         .main_clk       = "mmc3_fck",
2423         .prcm = {
2424                 .omap4 = {
2425                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2426                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2427                         .modulemode   = MODULEMODE_SWCTRL,
2428                 },
2429         },
2430 };
2431
2432 /* mmc4 */
2433 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2434         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2435         { .irq = -1 }
2436 };
2437
2438 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2439         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2440         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2441         { .dma_req = -1 }
2442 };
2443
2444 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2445         .name           = "mmc4",
2446         .class          = &omap44xx_mmc_hwmod_class,
2447         .clkdm_name     = "l4_per_clkdm",
2448         .mpu_irqs       = omap44xx_mmc4_irqs,
2449         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2450         .main_clk       = "mmc4_fck",
2451         .prcm = {
2452                 .omap4 = {
2453                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2454                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2455                         .modulemode   = MODULEMODE_SWCTRL,
2456                 },
2457         },
2458 };
2459
2460 /* mmc5 */
2461 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2462         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2463         { .irq = -1 }
2464 };
2465
2466 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2467         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2468         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2469         { .dma_req = -1 }
2470 };
2471
2472 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2473         .name           = "mmc5",
2474         .class          = &omap44xx_mmc_hwmod_class,
2475         .clkdm_name     = "l4_per_clkdm",
2476         .mpu_irqs       = omap44xx_mmc5_irqs,
2477         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2478         .main_clk       = "mmc5_fck",
2479         .prcm = {
2480                 .omap4 = {
2481                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2482                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2483                         .modulemode   = MODULEMODE_SWCTRL,
2484                 },
2485         },
2486 };
2487
2488 /*
2489  * 'mmu' class
2490  * The memory management unit performs virtual to physical address translation
2491  * for its requestors.
2492  */
2493
2494 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2495         .rev_offs       = 0x000,
2496         .sysc_offs      = 0x010,
2497         .syss_offs      = 0x014,
2498         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2499                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2500         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2501         .sysc_fields    = &omap_hwmod_sysc_type1,
2502 };
2503
2504 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2505         .name = "mmu",
2506         .sysc = &mmu_sysc,
2507 };
2508
2509 /* mmu ipu */
2510
2511 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2512         .da_start       = 0x0,
2513         .da_end         = 0xfffff000,
2514         .nr_tlb_entries = 32,
2515 };
2516
2517 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2518 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2519         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2520         { .irq = -1 }
2521 };
2522
2523 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2524         { .name = "mmu_cache", .rst_shift = 2 },
2525 };
2526
2527 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2528         {
2529                 .pa_start       = 0x55082000,
2530                 .pa_end         = 0x550820ff,
2531                 .flags          = ADDR_TYPE_RT,
2532         },
2533         { }
2534 };
2535
2536 /* l3_main_2 -> mmu_ipu */
2537 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2538         .master         = &omap44xx_l3_main_2_hwmod,
2539         .slave          = &omap44xx_mmu_ipu_hwmod,
2540         .clk            = "l3_div_ck",
2541         .addr           = omap44xx_mmu_ipu_addrs,
2542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2543 };
2544
2545 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2546         .name           = "mmu_ipu",
2547         .class          = &omap44xx_mmu_hwmod_class,
2548         .clkdm_name     = "ducati_clkdm",
2549         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2550         .rst_lines      = omap44xx_mmu_ipu_resets,
2551         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2552         .main_clk       = "ducati_clk_mux_ck",
2553         .prcm = {
2554                 .omap4 = {
2555                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2556                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2557                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2558                         .modulemode   = MODULEMODE_HWCTRL,
2559                 },
2560         },
2561         .dev_attr       = &mmu_ipu_dev_attr,
2562 };
2563
2564 /* mmu dsp */
2565
2566 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2567         .da_start       = 0x0,
2568         .da_end         = 0xfffff000,
2569         .nr_tlb_entries = 32,
2570 };
2571
2572 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2573 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2574         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2575         { .irq = -1 }
2576 };
2577
2578 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2579         { .name = "mmu_cache", .rst_shift = 1 },
2580 };
2581
2582 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2583         {
2584                 .pa_start       = 0x4a066000,
2585                 .pa_end         = 0x4a0660ff,
2586                 .flags          = ADDR_TYPE_RT,
2587         },
2588         { }
2589 };
2590
2591 /* l4_cfg -> dsp */
2592 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2593         .master         = &omap44xx_l4_cfg_hwmod,
2594         .slave          = &omap44xx_mmu_dsp_hwmod,
2595         .clk            = "l4_div_ck",
2596         .addr           = omap44xx_mmu_dsp_addrs,
2597         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2598 };
2599
2600 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2601         .name           = "mmu_dsp",
2602         .class          = &omap44xx_mmu_hwmod_class,
2603         .clkdm_name     = "tesla_clkdm",
2604         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2605         .rst_lines      = omap44xx_mmu_dsp_resets,
2606         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2607         .main_clk       = "dpll_iva_m4x2_ck",
2608         .prcm = {
2609                 .omap4 = {
2610                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2611                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2612                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2613                         .modulemode   = MODULEMODE_HWCTRL,
2614                 },
2615         },
2616         .dev_attr       = &mmu_dsp_dev_attr,
2617 };
2618
2619 /*
2620  * 'mpu' class
2621  * mpu sub-system
2622  */
2623
2624 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2625         .name   = "mpu",
2626 };
2627
2628 /* mpu */
2629 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2630         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2631         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2632         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2633         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2634         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2635         { .irq = -1 }
2636 };
2637
2638 static struct omap_hwmod omap44xx_mpu_hwmod = {
2639         .name           = "mpu",
2640         .class          = &omap44xx_mpu_hwmod_class,
2641         .clkdm_name     = "mpuss_clkdm",
2642         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2643         .mpu_irqs       = omap44xx_mpu_irqs,
2644         .main_clk       = "dpll_mpu_m2_ck",
2645         .prcm = {
2646                 .omap4 = {
2647                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2648                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2649                 },
2650         },
2651 };
2652
2653 /*
2654  * 'ocmc_ram' class
2655  * top-level core on-chip ram
2656  */
2657
2658 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2659         .name   = "ocmc_ram",
2660 };
2661
2662 /* ocmc_ram */
2663 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2664         .name           = "ocmc_ram",
2665         .class          = &omap44xx_ocmc_ram_hwmod_class,
2666         .clkdm_name     = "l3_2_clkdm",
2667         .prcm = {
2668                 .omap4 = {
2669                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2670                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2671                 },
2672         },
2673 };
2674
2675 /*
2676  * 'ocp2scp' class
2677  * bridge to transform ocp interface protocol to scp (serial control port)
2678  * protocol
2679  */
2680
2681 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2682         .rev_offs       = 0x0000,
2683         .sysc_offs      = 0x0010,
2684         .syss_offs      = 0x0014,
2685         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2686                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2687         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2688         .sysc_fields    = &omap_hwmod_sysc_type1,
2689 };
2690
2691 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2692         .name   = "ocp2scp",
2693         .sysc   = &omap44xx_ocp2scp_sysc,
2694 };
2695
2696 /* ocp2scp dev_attr */
2697 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2698         {
2699                 .name           = "usb_phy",
2700                 .start          = 0x4a0ad080,
2701                 .end            = 0x4a0ae000,
2702                 .flags          = IORESOURCE_MEM,
2703         },
2704         {
2705                 /* XXX: Remove this once control module driver is in place */
2706                 .name           = "ctrl_dev",
2707                 .start          = 0x4a002300,
2708                 .end            = 0x4a002303,
2709                 .flags          = IORESOURCE_MEM,
2710         },
2711         { }
2712 };
2713
2714 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2715         {
2716                 .drv_name       = "omap-usb2",
2717                 .res            = omap44xx_usb_phy_and_pll_addrs,
2718         },
2719         { }
2720 };
2721
2722 /* ocp2scp_usb_phy */
2723 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2724         .name           = "ocp2scp_usb_phy",
2725         .class          = &omap44xx_ocp2scp_hwmod_class,
2726         .clkdm_name     = "l3_init_clkdm",
2727         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2728         .prcm = {
2729                 .omap4 = {
2730                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2731                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2732                         .modulemode   = MODULEMODE_HWCTRL,
2733                 },
2734         },
2735         .dev_attr       = ocp2scp_dev_attr,
2736 };
2737
2738 /*
2739  * 'prcm' class
2740  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2741  * + clock manager 1 (in always on power domain) + local prm in mpu
2742  */
2743
2744 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2745         .name   = "prcm",
2746 };
2747
2748 /* prcm_mpu */
2749 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2750         .name           = "prcm_mpu",
2751         .class          = &omap44xx_prcm_hwmod_class,
2752         .clkdm_name     = "l4_wkup_clkdm",
2753         .flags          = HWMOD_NO_IDLEST,
2754         .prcm = {
2755                 .omap4 = {
2756                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2757                 },
2758         },
2759 };
2760
2761 /* cm_core_aon */
2762 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2763         .name           = "cm_core_aon",
2764         .class          = &omap44xx_prcm_hwmod_class,
2765         .flags          = HWMOD_NO_IDLEST,
2766         .prcm = {
2767                 .omap4 = {
2768                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2769                 },
2770         },
2771 };
2772
2773 /* cm_core */
2774 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2775         .name           = "cm_core",
2776         .class          = &omap44xx_prcm_hwmod_class,
2777         .flags          = HWMOD_NO_IDLEST,
2778         .prcm = {
2779                 .omap4 = {
2780                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2781                 },
2782         },
2783 };
2784
2785 /* prm */
2786 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2787         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2788         { .irq = -1 }
2789 };
2790
2791 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2792         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2793         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2794 };
2795
2796 static struct omap_hwmod omap44xx_prm_hwmod = {
2797         .name           = "prm",
2798         .class          = &omap44xx_prcm_hwmod_class,
2799         .mpu_irqs       = omap44xx_prm_irqs,
2800         .rst_lines      = omap44xx_prm_resets,
2801         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2802 };
2803
2804 /*
2805  * 'scrm' class
2806  * system clock and reset manager
2807  */
2808
2809 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2810         .name   = "scrm",
2811 };
2812
2813 /* scrm */
2814 static struct omap_hwmod omap44xx_scrm_hwmod = {
2815         .name           = "scrm",
2816         .class          = &omap44xx_scrm_hwmod_class,
2817         .clkdm_name     = "l4_wkup_clkdm",
2818         .prcm = {
2819                 .omap4 = {
2820                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2821                 },
2822         },
2823 };
2824
2825 /*
2826  * 'sl2if' class
2827  * shared level 2 memory interface
2828  */
2829
2830 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2831         .name   = "sl2if",
2832 };
2833
2834 /* sl2if */
2835 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2836         .name           = "sl2if",
2837         .class          = &omap44xx_sl2if_hwmod_class,
2838         .clkdm_name     = "ivahd_clkdm",
2839         .prcm = {
2840                 .omap4 = {
2841                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2842                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2843                         .modulemode   = MODULEMODE_HWCTRL,
2844                 },
2845         },
2846 };
2847
2848 /*
2849  * 'slimbus' class
2850  * bidirectional, multi-drop, multi-channel two-line serial interface between
2851  * the device and external components
2852  */
2853
2854 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2855         .rev_offs       = 0x0000,
2856         .sysc_offs      = 0x0010,
2857         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2858                            SYSC_HAS_SOFTRESET),
2859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2860                            SIDLE_SMART_WKUP),
2861         .sysc_fields    = &omap_hwmod_sysc_type2,
2862 };
2863
2864 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2865         .name   = "slimbus",
2866         .sysc   = &omap44xx_slimbus_sysc,
2867 };
2868
2869 /* slimbus1 */
2870 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2871         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2872         { .irq = -1 }
2873 };
2874
2875 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2876         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2877         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2878         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2879         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2880         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2881         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2882         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2883         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2884         { .dma_req = -1 }
2885 };
2886
2887 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2888         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2889         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2890         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2891         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2892 };
2893
2894 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2895         .name           = "slimbus1",
2896         .class          = &omap44xx_slimbus_hwmod_class,
2897         .clkdm_name     = "abe_clkdm",
2898         .mpu_irqs       = omap44xx_slimbus1_irqs,
2899         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2900         .prcm = {
2901                 .omap4 = {
2902                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2903                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2904                         .modulemode   = MODULEMODE_SWCTRL,
2905                 },
2906         },
2907         .opt_clks       = slimbus1_opt_clks,
2908         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2909 };
2910
2911 /* slimbus2 */
2912 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2913         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2914         { .irq = -1 }
2915 };
2916
2917 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2918         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2919         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2920         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2921         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2922         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2923         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2924         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2925         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2926         { .dma_req = -1 }
2927 };
2928
2929 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2930         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2931         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2932         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2933 };
2934
2935 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2936         .name           = "slimbus2",
2937         .class          = &omap44xx_slimbus_hwmod_class,
2938         .clkdm_name     = "l4_per_clkdm",
2939         .mpu_irqs       = omap44xx_slimbus2_irqs,
2940         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2941         .prcm = {
2942                 .omap4 = {
2943                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2944                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2945                         .modulemode   = MODULEMODE_SWCTRL,
2946                 },
2947         },
2948         .opt_clks       = slimbus2_opt_clks,
2949         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2950 };
2951
2952 /*
2953  * 'smartreflex' class
2954  * smartreflex module (monitor silicon performance and outputs a measure of
2955  * performance error)
2956  */
2957
2958 /* The IP is not compliant to type1 / type2 scheme */
2959 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2960         .sidle_shift    = 24,
2961         .enwkup_shift   = 26,
2962 };
2963
2964 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2965         .sysc_offs      = 0x0038,
2966         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2967         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2968                            SIDLE_SMART_WKUP),
2969         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2970 };
2971
2972 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2973         .name   = "smartreflex",
2974         .sysc   = &omap44xx_smartreflex_sysc,
2975         .rev    = 2,
2976 };
2977
2978 /* smartreflex_core */
2979 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2980         .sensor_voltdm_name   = "core",
2981 };
2982
2983 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2984         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2985         { .irq = -1 }
2986 };
2987
2988 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2989         .name           = "smartreflex_core",
2990         .class          = &omap44xx_smartreflex_hwmod_class,
2991         .clkdm_name     = "l4_ao_clkdm",
2992         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2993
2994         .main_clk       = "smartreflex_core_fck",
2995         .prcm = {
2996                 .omap4 = {
2997                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2998                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2999                         .modulemode   = MODULEMODE_SWCTRL,
3000                 },
3001         },
3002         .dev_attr       = &smartreflex_core_dev_attr,
3003 };
3004
3005 /* smartreflex_iva */
3006 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3007         .sensor_voltdm_name     = "iva",
3008 };
3009
3010 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3011         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3012         { .irq = -1 }
3013 };
3014
3015 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3016         .name           = "smartreflex_iva",
3017         .class          = &omap44xx_smartreflex_hwmod_class,
3018         .clkdm_name     = "l4_ao_clkdm",
3019         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3020         .main_clk       = "smartreflex_iva_fck",
3021         .prcm = {
3022                 .omap4 = {
3023                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3024                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3025                         .modulemode   = MODULEMODE_SWCTRL,
3026                 },
3027         },
3028         .dev_attr       = &smartreflex_iva_dev_attr,
3029 };
3030
3031 /* smartreflex_mpu */
3032 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3033         .sensor_voltdm_name     = "mpu",
3034 };
3035
3036 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3037         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3038         { .irq = -1 }
3039 };
3040
3041 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3042         .name           = "smartreflex_mpu",
3043         .class          = &omap44xx_smartreflex_hwmod_class,
3044         .clkdm_name     = "l4_ao_clkdm",
3045         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3046         .main_clk       = "smartreflex_mpu_fck",
3047         .prcm = {
3048                 .omap4 = {
3049                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3050                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3051                         .modulemode   = MODULEMODE_SWCTRL,
3052                 },
3053         },
3054         .dev_attr       = &smartreflex_mpu_dev_attr,
3055 };
3056
3057 /*
3058  * 'spinlock' class
3059  * spinlock provides hardware assistance for synchronizing the processes
3060  * running on multiple processors
3061  */
3062
3063 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3064         .rev_offs       = 0x0000,
3065         .sysc_offs      = 0x0010,
3066         .syss_offs      = 0x0014,
3067         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3068                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3069                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3070         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3071                            SIDLE_SMART_WKUP),
3072         .sysc_fields    = &omap_hwmod_sysc_type1,
3073 };
3074
3075 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3076         .name   = "spinlock",
3077         .sysc   = &omap44xx_spinlock_sysc,
3078 };
3079
3080 /* spinlock */
3081 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3082         .name           = "spinlock",
3083         .class          = &omap44xx_spinlock_hwmod_class,
3084         .clkdm_name     = "l4_cfg_clkdm",
3085         .prcm = {
3086                 .omap4 = {
3087                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3088                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3089                 },
3090         },
3091 };
3092
3093 /*
3094  * 'timer' class
3095  * general purpose timer module with accurate 1ms tick
3096  * This class contains several variants: ['timer_1ms', 'timer']
3097  */
3098
3099 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3100         .rev_offs       = 0x0000,
3101         .sysc_offs      = 0x0010,
3102         .syss_offs      = 0x0014,
3103         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3104                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3105                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3106                            SYSS_HAS_RESET_STATUS),
3107         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3108         .sysc_fields    = &omap_hwmod_sysc_type1,
3109 };
3110
3111 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3112         .name   = "timer",
3113         .sysc   = &omap44xx_timer_1ms_sysc,
3114 };
3115
3116 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3117         .rev_offs       = 0x0000,
3118         .sysc_offs      = 0x0010,
3119         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3120                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3121         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3122                            SIDLE_SMART_WKUP),
3123         .sysc_fields    = &omap_hwmod_sysc_type2,
3124 };
3125
3126 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3127         .name   = "timer",
3128         .sysc   = &omap44xx_timer_sysc,
3129 };
3130
3131 /* always-on timers dev attribute */
3132 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3133         .timer_capability       = OMAP_TIMER_ALWON,
3134 };
3135
3136 /* pwm timers dev attribute */
3137 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3138         .timer_capability       = OMAP_TIMER_HAS_PWM,
3139 };
3140
3141 /* timers with DSP interrupt dev attribute */
3142 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3143         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3144 };
3145
3146 /* pwm timers with DSP interrupt dev attribute */
3147 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3148         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3149 };
3150
3151 /* timer1 */
3152 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3153         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3154         { .irq = -1 }
3155 };
3156
3157 static struct omap_hwmod omap44xx_timer1_hwmod = {
3158         .name           = "timer1",
3159         .class          = &omap44xx_timer_1ms_hwmod_class,
3160         .clkdm_name     = "l4_wkup_clkdm",
3161         .mpu_irqs       = omap44xx_timer1_irqs,
3162         .main_clk       = "timer1_fck",
3163         .prcm = {
3164                 .omap4 = {
3165                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3166                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3167                         .modulemode   = MODULEMODE_SWCTRL,
3168                 },
3169         },
3170         .dev_attr       = &capability_alwon_dev_attr,
3171 };
3172
3173 /* timer2 */
3174 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3175         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3176         { .irq = -1 }
3177 };
3178
3179 static struct omap_hwmod omap44xx_timer2_hwmod = {
3180         .name           = "timer2",
3181         .class          = &omap44xx_timer_1ms_hwmod_class,
3182         .clkdm_name     = "l4_per_clkdm",
3183         .mpu_irqs       = omap44xx_timer2_irqs,
3184         .main_clk       = "timer2_fck",
3185         .prcm = {
3186                 .omap4 = {
3187                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3188                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3189                         .modulemode   = MODULEMODE_SWCTRL,
3190                 },
3191         },
3192 };
3193
3194 /* timer3 */
3195 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3196         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3197         { .irq = -1 }
3198 };
3199
3200 static struct omap_hwmod omap44xx_timer3_hwmod = {
3201         .name           = "timer3",
3202         .class          = &omap44xx_timer_hwmod_class,
3203         .clkdm_name     = "l4_per_clkdm",
3204         .mpu_irqs       = omap44xx_timer3_irqs,
3205         .main_clk       = "timer3_fck",
3206         .prcm = {
3207                 .omap4 = {
3208                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3209                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3210                         .modulemode   = MODULEMODE_SWCTRL,</