Merge tag 'iommu-updates-v3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/joro...
[~shefty/rdma-dev.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2  * Hardware modules present on the OMAP44xx chips
3  *
4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Benoit Cousson
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/io.h>
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/platform_data/omap_ocp2scp.h>
25 #include <linux/i2c-omap.h>
26
27 #include <linux/omap-dma.h>
28
29 #include <linux/platform_data/omap_ocp2scp.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
31 #include <linux/platform_data/asoc-ti-mcbsp.h>
32 #include <linux/platform_data/iommu-omap.h>
33 #include <plat/dmtimer.h>
34
35 #include "omap_hwmod.h"
36 #include "omap_hwmod_common_data.h"
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "prm44xx.h"
40 #include "prm-regbits-44xx.h"
41 #include "i2c.h"
42 #include "mmc.h"
43 #include "wd_timer.h"
44
45 /* Base offset for all OMAP4 interrupts external to MPUSS */
46 #define OMAP44XX_IRQ_GIC_START  32
47
48 /* Base offset for all OMAP4 dma requests */
49 #define OMAP44XX_DMA_REQ_START  1
50
51 /*
52  * IP blocks
53  */
54
55 /*
56  * 'c2c_target_fw' class
57  * instance(s): c2c_target_fw
58  */
59 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
60         .name   = "c2c_target_fw",
61 };
62
63 /* c2c_target_fw */
64 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
65         .name           = "c2c_target_fw",
66         .class          = &omap44xx_c2c_target_fw_hwmod_class,
67         .clkdm_name     = "d2d_clkdm",
68         .prcm = {
69                 .omap4 = {
70                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
71                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
72                 },
73         },
74 };
75
76 /*
77  * 'dmm' class
78  * instance(s): dmm
79  */
80 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
81         .name   = "dmm",
82 };
83
84 /* dmm */
85 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
86         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
87         { .irq = -1 }
88 };
89
90 static struct omap_hwmod omap44xx_dmm_hwmod = {
91         .name           = "dmm",
92         .class          = &omap44xx_dmm_hwmod_class,
93         .clkdm_name     = "l3_emif_clkdm",
94         .mpu_irqs       = omap44xx_dmm_irqs,
95         .prcm = {
96                 .omap4 = {
97                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
98                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
99                 },
100         },
101 };
102
103 /*
104  * 'emif_fw' class
105  * instance(s): emif_fw
106  */
107 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
108         .name   = "emif_fw",
109 };
110
111 /* emif_fw */
112 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
113         .name           = "emif_fw",
114         .class          = &omap44xx_emif_fw_hwmod_class,
115         .clkdm_name     = "l3_emif_clkdm",
116         .prcm = {
117                 .omap4 = {
118                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
119                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
120                 },
121         },
122 };
123
124 /*
125  * 'l3' class
126  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
127  */
128 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
129         .name   = "l3",
130 };
131
132 /* l3_instr */
133 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
134         .name           = "l3_instr",
135         .class          = &omap44xx_l3_hwmod_class,
136         .clkdm_name     = "l3_instr_clkdm",
137         .prcm = {
138                 .omap4 = {
139                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
140                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
141                         .modulemode   = MODULEMODE_HWCTRL,
142                 },
143         },
144 };
145
146 /* l3_main_1 */
147 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
148         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
149         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
150         { .irq = -1 }
151 };
152
153 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
154         .name           = "l3_main_1",
155         .class          = &omap44xx_l3_hwmod_class,
156         .clkdm_name     = "l3_1_clkdm",
157         .mpu_irqs       = omap44xx_l3_main_1_irqs,
158         .prcm = {
159                 .omap4 = {
160                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
161                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
162                 },
163         },
164 };
165
166 /* l3_main_2 */
167 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
168         .name           = "l3_main_2",
169         .class          = &omap44xx_l3_hwmod_class,
170         .clkdm_name     = "l3_2_clkdm",
171         .prcm = {
172                 .omap4 = {
173                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
174                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
175                 },
176         },
177 };
178
179 /* l3_main_3 */
180 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
181         .name           = "l3_main_3",
182         .class          = &omap44xx_l3_hwmod_class,
183         .clkdm_name     = "l3_instr_clkdm",
184         .prcm = {
185                 .omap4 = {
186                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
187                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
188                         .modulemode   = MODULEMODE_HWCTRL,
189                 },
190         },
191 };
192
193 /*
194  * 'l4' class
195  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
196  */
197 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
198         .name   = "l4",
199 };
200
201 /* l4_abe */
202 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
203         .name           = "l4_abe",
204         .class          = &omap44xx_l4_hwmod_class,
205         .clkdm_name     = "abe_clkdm",
206         .prcm = {
207                 .omap4 = {
208                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
209                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
210                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
211                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
212                 },
213         },
214 };
215
216 /* l4_cfg */
217 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
218         .name           = "l4_cfg",
219         .class          = &omap44xx_l4_hwmod_class,
220         .clkdm_name     = "l4_cfg_clkdm",
221         .prcm = {
222                 .omap4 = {
223                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
224                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
225                 },
226         },
227 };
228
229 /* l4_per */
230 static struct omap_hwmod omap44xx_l4_per_hwmod = {
231         .name           = "l4_per",
232         .class          = &omap44xx_l4_hwmod_class,
233         .clkdm_name     = "l4_per_clkdm",
234         .prcm = {
235                 .omap4 = {
236                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
237                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
238                 },
239         },
240 };
241
242 /* l4_wkup */
243 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
244         .name           = "l4_wkup",
245         .class          = &omap44xx_l4_hwmod_class,
246         .clkdm_name     = "l4_wkup_clkdm",
247         .prcm = {
248                 .omap4 = {
249                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
250                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
251                 },
252         },
253 };
254
255 /*
256  * 'mpu_bus' class
257  * instance(s): mpu_private
258  */
259 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
260         .name   = "mpu_bus",
261 };
262
263 /* mpu_private */
264 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
265         .name           = "mpu_private",
266         .class          = &omap44xx_mpu_bus_hwmod_class,
267         .clkdm_name     = "mpuss_clkdm",
268         .prcm = {
269                 .omap4 = {
270                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
271                 },
272         },
273 };
274
275 /*
276  * 'ocp_wp_noc' class
277  * instance(s): ocp_wp_noc
278  */
279 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
280         .name   = "ocp_wp_noc",
281 };
282
283 /* ocp_wp_noc */
284 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
285         .name           = "ocp_wp_noc",
286         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
287         .clkdm_name     = "l3_instr_clkdm",
288         .prcm = {
289                 .omap4 = {
290                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
291                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
292                         .modulemode   = MODULEMODE_HWCTRL,
293                 },
294         },
295 };
296
297 /*
298  * Modules omap_hwmod structures
299  *
300  * The following IPs are excluded for the moment because:
301  * - They do not need an explicit SW control using omap_hwmod API.
302  * - They still need to be validated with the driver
303  *   properly adapted to omap_hwmod / omap_device
304  *
305  * usim
306  */
307
308 /*
309  * 'aess' class
310  * audio engine sub system
311  */
312
313 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
314         .rev_offs       = 0x0000,
315         .sysc_offs      = 0x0010,
316         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
317         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
318                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
319                            MSTANDBY_SMART_WKUP),
320         .sysc_fields    = &omap_hwmod_sysc_type2,
321 };
322
323 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
324         .name   = "aess",
325         .sysc   = &omap44xx_aess_sysc,
326 };
327
328 /* aess */
329 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
330         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
331         { .irq = -1 }
332 };
333
334 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
335         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
336         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
337         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
338         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
339         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
340         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
341         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
342         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
343         { .dma_req = -1 }
344 };
345
346 static struct omap_hwmod omap44xx_aess_hwmod = {
347         .name           = "aess",
348         .class          = &omap44xx_aess_hwmod_class,
349         .clkdm_name     = "abe_clkdm",
350         .mpu_irqs       = omap44xx_aess_irqs,
351         .sdma_reqs      = omap44xx_aess_sdma_reqs,
352         .main_clk       = "aess_fck",
353         .prcm = {
354                 .omap4 = {
355                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
356                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
357                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
358                         .modulemode   = MODULEMODE_SWCTRL,
359                 },
360         },
361 };
362
363 /*
364  * 'c2c' class
365  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
366  * soc
367  */
368
369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
370         .name   = "c2c",
371 };
372
373 /* c2c */
374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
375         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
376         { .irq = -1 }
377 };
378
379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
380         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
381         { .dma_req = -1 }
382 };
383
384 static struct omap_hwmod omap44xx_c2c_hwmod = {
385         .name           = "c2c",
386         .class          = &omap44xx_c2c_hwmod_class,
387         .clkdm_name     = "d2d_clkdm",
388         .mpu_irqs       = omap44xx_c2c_irqs,
389         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
390         .prcm = {
391                 .omap4 = {
392                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
393                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
394                 },
395         },
396 };
397
398 /*
399  * 'counter' class
400  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
401  */
402
403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
404         .rev_offs       = 0x0000,
405         .sysc_offs      = 0x0004,
406         .sysc_flags     = SYSC_HAS_SIDLEMODE,
407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
408         .sysc_fields    = &omap_hwmod_sysc_type1,
409 };
410
411 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
412         .name   = "counter",
413         .sysc   = &omap44xx_counter_sysc,
414 };
415
416 /* counter_32k */
417 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
418         .name           = "counter_32k",
419         .class          = &omap44xx_counter_hwmod_class,
420         .clkdm_name     = "l4_wkup_clkdm",
421         .flags          = HWMOD_SWSUP_SIDLE,
422         .main_clk       = "sys_32k_ck",
423         .prcm = {
424                 .omap4 = {
425                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
426                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
427                 },
428         },
429 };
430
431 /*
432  * 'ctrl_module' class
433  * attila core control module + core pad control module + wkup pad control
434  * module + attila wkup control module
435  */
436
437 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
438         .rev_offs       = 0x0000,
439         .sysc_offs      = 0x0010,
440         .sysc_flags     = SYSC_HAS_SIDLEMODE,
441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
442                            SIDLE_SMART_WKUP),
443         .sysc_fields    = &omap_hwmod_sysc_type2,
444 };
445
446 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
447         .name   = "ctrl_module",
448         .sysc   = &omap44xx_ctrl_module_sysc,
449 };
450
451 /* ctrl_module_core */
452 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
453         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
454         { .irq = -1 }
455 };
456
457 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
458         .name           = "ctrl_module_core",
459         .class          = &omap44xx_ctrl_module_hwmod_class,
460         .clkdm_name     = "l4_cfg_clkdm",
461         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
462         .prcm = {
463                 .omap4 = {
464                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
465                 },
466         },
467 };
468
469 /* ctrl_module_pad_core */
470 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
471         .name           = "ctrl_module_pad_core",
472         .class          = &omap44xx_ctrl_module_hwmod_class,
473         .clkdm_name     = "l4_cfg_clkdm",
474         .prcm = {
475                 .omap4 = {
476                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
477                 },
478         },
479 };
480
481 /* ctrl_module_wkup */
482 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
483         .name           = "ctrl_module_wkup",
484         .class          = &omap44xx_ctrl_module_hwmod_class,
485         .clkdm_name     = "l4_wkup_clkdm",
486         .prcm = {
487                 .omap4 = {
488                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
489                 },
490         },
491 };
492
493 /* ctrl_module_pad_wkup */
494 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
495         .name           = "ctrl_module_pad_wkup",
496         .class          = &omap44xx_ctrl_module_hwmod_class,
497         .clkdm_name     = "l4_wkup_clkdm",
498         .prcm = {
499                 .omap4 = {
500                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
501                 },
502         },
503 };
504
505 /*
506  * 'debugss' class
507  * debug and emulation sub system
508  */
509
510 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
511         .name   = "debugss",
512 };
513
514 /* debugss */
515 static struct omap_hwmod omap44xx_debugss_hwmod = {
516         .name           = "debugss",
517         .class          = &omap44xx_debugss_hwmod_class,
518         .clkdm_name     = "emu_sys_clkdm",
519         .main_clk       = "trace_clk_div_ck",
520         .prcm = {
521                 .omap4 = {
522                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
523                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
524                 },
525         },
526 };
527
528 /*
529  * 'dma' class
530  * dma controller for data exchange between memory to memory (i.e. internal or
531  * external memory) and gp peripherals to memory or memory to gp peripherals
532  */
533
534 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
535         .rev_offs       = 0x0000,
536         .sysc_offs      = 0x002c,
537         .syss_offs      = 0x0028,
538         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
539                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
540                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
541                            SYSS_HAS_RESET_STATUS),
542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
543                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
544         .sysc_fields    = &omap_hwmod_sysc_type1,
545 };
546
547 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
548         .name   = "dma",
549         .sysc   = &omap44xx_dma_sysc,
550 };
551
552 /* dma dev_attr */
553 static struct omap_dma_dev_attr dma_dev_attr = {
554         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
555                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
556         .lch_count      = 32,
557 };
558
559 /* dma_system */
560 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
561         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
562         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
563         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
564         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
565         { .irq = -1 }
566 };
567
568 static struct omap_hwmod omap44xx_dma_system_hwmod = {
569         .name           = "dma_system",
570         .class          = &omap44xx_dma_hwmod_class,
571         .clkdm_name     = "l3_dma_clkdm",
572         .mpu_irqs       = omap44xx_dma_system_irqs,
573         .main_clk       = "l3_div_ck",
574         .prcm = {
575                 .omap4 = {
576                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
577                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
578                 },
579         },
580         .dev_attr       = &dma_dev_attr,
581 };
582
583 /*
584  * 'dmic' class
585  * digital microphone controller
586  */
587
588 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
589         .rev_offs       = 0x0000,
590         .sysc_offs      = 0x0010,
591         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
592                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
593         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
594                            SIDLE_SMART_WKUP),
595         .sysc_fields    = &omap_hwmod_sysc_type2,
596 };
597
598 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
599         .name   = "dmic",
600         .sysc   = &omap44xx_dmic_sysc,
601 };
602
603 /* dmic */
604 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
605         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
606         { .irq = -1 }
607 };
608
609 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
610         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
611         { .dma_req = -1 }
612 };
613
614 static struct omap_hwmod omap44xx_dmic_hwmod = {
615         .name           = "dmic",
616         .class          = &omap44xx_dmic_hwmod_class,
617         .clkdm_name     = "abe_clkdm",
618         .mpu_irqs       = omap44xx_dmic_irqs,
619         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
620         .main_clk       = "dmic_fck",
621         .prcm = {
622                 .omap4 = {
623                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
624                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
625                         .modulemode   = MODULEMODE_SWCTRL,
626                 },
627         },
628 };
629
630 /*
631  * 'dsp' class
632  * dsp sub-system
633  */
634
635 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
636         .name   = "dsp",
637 };
638
639 /* dsp */
640 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
641         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
642         { .irq = -1 }
643 };
644
645 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
646         { .name = "dsp", .rst_shift = 0 },
647 };
648
649 static struct omap_hwmod omap44xx_dsp_hwmod = {
650         .name           = "dsp",
651         .class          = &omap44xx_dsp_hwmod_class,
652         .clkdm_name     = "tesla_clkdm",
653         .mpu_irqs       = omap44xx_dsp_irqs,
654         .rst_lines      = omap44xx_dsp_resets,
655         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
656         .main_clk       = "dpll_iva_m4x2_ck",
657         .prcm = {
658                 .omap4 = {
659                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
660                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
661                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
662                         .modulemode   = MODULEMODE_HWCTRL,
663                 },
664         },
665 };
666
667 /*
668  * 'dss' class
669  * display sub-system
670  */
671
672 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
673         .rev_offs       = 0x0000,
674         .syss_offs      = 0x0014,
675         .sysc_flags     = SYSS_HAS_RESET_STATUS,
676 };
677
678 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
679         .name   = "dss",
680         .sysc   = &omap44xx_dss_sysc,
681         .reset  = omap_dss_reset,
682 };
683
684 /* dss */
685 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
686         { .role = "sys_clk", .clk = "dss_sys_clk" },
687         { .role = "tv_clk", .clk = "dss_tv_clk" },
688         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
689 };
690
691 static struct omap_hwmod omap44xx_dss_hwmod = {
692         .name           = "dss_core",
693         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694         .class          = &omap44xx_dss_hwmod_class,
695         .clkdm_name     = "l3_dss_clkdm",
696         .main_clk       = "dss_dss_clk",
697         .prcm = {
698                 .omap4 = {
699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
701                 },
702         },
703         .opt_clks       = dss_opt_clks,
704         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
705 };
706
707 /*
708  * 'dispc' class
709  * display controller
710  */
711
712 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
713         .rev_offs       = 0x0000,
714         .sysc_offs      = 0x0010,
715         .syss_offs      = 0x0014,
716         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
717                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
719                            SYSS_HAS_RESET_STATUS),
720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
721                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
722         .sysc_fields    = &omap_hwmod_sysc_type1,
723 };
724
725 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
726         .name   = "dispc",
727         .sysc   = &omap44xx_dispc_sysc,
728 };
729
730 /* dss_dispc */
731 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
732         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
733         { .irq = -1 }
734 };
735
736 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
737         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
738         { .dma_req = -1 }
739 };
740
741 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
742         .manager_count          = 3,
743         .has_framedonetv_irq    = 1
744 };
745
746 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
747         .name           = "dss_dispc",
748         .class          = &omap44xx_dispc_hwmod_class,
749         .clkdm_name     = "l3_dss_clkdm",
750         .mpu_irqs       = omap44xx_dss_dispc_irqs,
751         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
752         .main_clk       = "dss_dss_clk",
753         .prcm = {
754                 .omap4 = {
755                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
756                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
757                 },
758         },
759         .dev_attr       = &omap44xx_dss_dispc_dev_attr
760 };
761
762 /*
763  * 'dsi' class
764  * display serial interface controller
765  */
766
767 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
768         .rev_offs       = 0x0000,
769         .sysc_offs      = 0x0010,
770         .syss_offs      = 0x0014,
771         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
772                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
773                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
775         .sysc_fields    = &omap_hwmod_sysc_type1,
776 };
777
778 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
779         .name   = "dsi",
780         .sysc   = &omap44xx_dsi_sysc,
781 };
782
783 /* dss_dsi1 */
784 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
785         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
786         { .irq = -1 }
787 };
788
789 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
790         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
791         { .dma_req = -1 }
792 };
793
794 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
795         { .role = "sys_clk", .clk = "dss_sys_clk" },
796 };
797
798 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
799         .name           = "dss_dsi1",
800         .class          = &omap44xx_dsi_hwmod_class,
801         .clkdm_name     = "l3_dss_clkdm",
802         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
803         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
804         .main_clk       = "dss_dss_clk",
805         .prcm = {
806                 .omap4 = {
807                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
808                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
809                 },
810         },
811         .opt_clks       = dss_dsi1_opt_clks,
812         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
813 };
814
815 /* dss_dsi2 */
816 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
817         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
818         { .irq = -1 }
819 };
820
821 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
822         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
823         { .dma_req = -1 }
824 };
825
826 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
827         { .role = "sys_clk", .clk = "dss_sys_clk" },
828 };
829
830 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
831         .name           = "dss_dsi2",
832         .class          = &omap44xx_dsi_hwmod_class,
833         .clkdm_name     = "l3_dss_clkdm",
834         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
835         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
836         .main_clk       = "dss_dss_clk",
837         .prcm = {
838                 .omap4 = {
839                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
840                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
841                 },
842         },
843         .opt_clks       = dss_dsi2_opt_clks,
844         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
845 };
846
847 /*
848  * 'hdmi' class
849  * hdmi controller
850  */
851
852 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
853         .rev_offs       = 0x0000,
854         .sysc_offs      = 0x0010,
855         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
856                            SYSC_HAS_SOFTRESET),
857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
858                            SIDLE_SMART_WKUP),
859         .sysc_fields    = &omap_hwmod_sysc_type2,
860 };
861
862 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
863         .name   = "hdmi",
864         .sysc   = &omap44xx_hdmi_sysc,
865 };
866
867 /* dss_hdmi */
868 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
869         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
870         { .irq = -1 }
871 };
872
873 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
874         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
875         { .dma_req = -1 }
876 };
877
878 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
879         { .role = "sys_clk", .clk = "dss_sys_clk" },
880 };
881
882 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
883         .name           = "dss_hdmi",
884         .class          = &omap44xx_hdmi_hwmod_class,
885         .clkdm_name     = "l3_dss_clkdm",
886         /*
887          * HDMI audio requires to use no-idle mode. Hence,
888          * set idle mode by software.
889          */
890         .flags          = HWMOD_SWSUP_SIDLE,
891         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
892         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
893         .main_clk       = "dss_48mhz_clk",
894         .prcm = {
895                 .omap4 = {
896                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
897                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
898                 },
899         },
900         .opt_clks       = dss_hdmi_opt_clks,
901         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
902 };
903
904 /*
905  * 'rfbi' class
906  * remote frame buffer interface
907  */
908
909 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
910         .rev_offs       = 0x0000,
911         .sysc_offs      = 0x0010,
912         .syss_offs      = 0x0014,
913         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
914                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
916         .sysc_fields    = &omap_hwmod_sysc_type1,
917 };
918
919 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
920         .name   = "rfbi",
921         .sysc   = &omap44xx_rfbi_sysc,
922 };
923
924 /* dss_rfbi */
925 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
926         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
927         { .dma_req = -1 }
928 };
929
930 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
931         { .role = "ick", .clk = "dss_fck" },
932 };
933
934 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
935         .name           = "dss_rfbi",
936         .class          = &omap44xx_rfbi_hwmod_class,
937         .clkdm_name     = "l3_dss_clkdm",
938         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
939         .main_clk       = "dss_dss_clk",
940         .prcm = {
941                 .omap4 = {
942                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
943                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
944                 },
945         },
946         .opt_clks       = dss_rfbi_opt_clks,
947         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
948 };
949
950 /*
951  * 'venc' class
952  * video encoder
953  */
954
955 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
956         .name   = "venc",
957 };
958
959 /* dss_venc */
960 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
961         .name           = "dss_venc",
962         .class          = &omap44xx_venc_hwmod_class,
963         .clkdm_name     = "l3_dss_clkdm",
964         .main_clk       = "dss_tv_clk",
965         .prcm = {
966                 .omap4 = {
967                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
968                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
969                 },
970         },
971 };
972
973 /*
974  * 'elm' class
975  * bch error location module
976  */
977
978 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
979         .rev_offs       = 0x0000,
980         .sysc_offs      = 0x0010,
981         .syss_offs      = 0x0014,
982         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
983                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
984                            SYSS_HAS_RESET_STATUS),
985         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
986         .sysc_fields    = &omap_hwmod_sysc_type1,
987 };
988
989 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
990         .name   = "elm",
991         .sysc   = &omap44xx_elm_sysc,
992 };
993
994 /* elm */
995 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
996         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
997         { .irq = -1 }
998 };
999
1000 static struct omap_hwmod omap44xx_elm_hwmod = {
1001         .name           = "elm",
1002         .class          = &omap44xx_elm_hwmod_class,
1003         .clkdm_name     = "l4_per_clkdm",
1004         .mpu_irqs       = omap44xx_elm_irqs,
1005         .prcm = {
1006                 .omap4 = {
1007                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1008                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1009                 },
1010         },
1011 };
1012
1013 /*
1014  * 'emif' class
1015  * external memory interface no1
1016  */
1017
1018 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1019         .rev_offs       = 0x0000,
1020 };
1021
1022 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1023         .name   = "emif",
1024         .sysc   = &omap44xx_emif_sysc,
1025 };
1026
1027 /* emif1 */
1028 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1029         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1030         { .irq = -1 }
1031 };
1032
1033 static struct omap_hwmod omap44xx_emif1_hwmod = {
1034         .name           = "emif1",
1035         .class          = &omap44xx_emif_hwmod_class,
1036         .clkdm_name     = "l3_emif_clkdm",
1037         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1038         .mpu_irqs       = omap44xx_emif1_irqs,
1039         .main_clk       = "ddrphy_ck",
1040         .prcm = {
1041                 .omap4 = {
1042                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1043                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1044                         .modulemode   = MODULEMODE_HWCTRL,
1045                 },
1046         },
1047 };
1048
1049 /* emif2 */
1050 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1051         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1052         { .irq = -1 }
1053 };
1054
1055 static struct omap_hwmod omap44xx_emif2_hwmod = {
1056         .name           = "emif2",
1057         .class          = &omap44xx_emif_hwmod_class,
1058         .clkdm_name     = "l3_emif_clkdm",
1059         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1060         .mpu_irqs       = omap44xx_emif2_irqs,
1061         .main_clk       = "ddrphy_ck",
1062         .prcm = {
1063                 .omap4 = {
1064                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1065                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1066                         .modulemode   = MODULEMODE_HWCTRL,
1067                 },
1068         },
1069 };
1070
1071 /*
1072  * 'fdif' class
1073  * face detection hw accelerator module
1074  */
1075
1076 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1077         .rev_offs       = 0x0000,
1078         .sysc_offs      = 0x0010,
1079         /*
1080          * FDIF needs 100 OCP clk cycles delay after a softreset before
1081          * accessing sysconfig again.
1082          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1083          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1084          *
1085          * TODO: Indicate errata when available.
1086          */
1087         .srst_udelay    = 2,
1088         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1089                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1091                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1092         .sysc_fields    = &omap_hwmod_sysc_type2,
1093 };
1094
1095 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1096         .name   = "fdif",
1097         .sysc   = &omap44xx_fdif_sysc,
1098 };
1099
1100 /* fdif */
1101 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1102         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod omap44xx_fdif_hwmod = {
1107         .name           = "fdif",
1108         .class          = &omap44xx_fdif_hwmod_class,
1109         .clkdm_name     = "iss_clkdm",
1110         .mpu_irqs       = omap44xx_fdif_irqs,
1111         .main_clk       = "fdif_fck",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1115                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1116                         .modulemode   = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119 };
1120
1121 /*
1122  * 'gpio' class
1123  * general purpose io module
1124  */
1125
1126 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1127         .rev_offs       = 0x0000,
1128         .sysc_offs      = 0x0010,
1129         .syss_offs      = 0x0114,
1130         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1131                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1132                            SYSS_HAS_RESET_STATUS),
1133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1134                            SIDLE_SMART_WKUP),
1135         .sysc_fields    = &omap_hwmod_sysc_type1,
1136 };
1137
1138 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1139         .name   = "gpio",
1140         .sysc   = &omap44xx_gpio_sysc,
1141         .rev    = 2,
1142 };
1143
1144 /* gpio dev_attr */
1145 static struct omap_gpio_dev_attr gpio_dev_attr = {
1146         .bank_width     = 32,
1147         .dbck_flag      = true,
1148 };
1149
1150 /* gpio1 */
1151 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1152         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1153         { .irq = -1 }
1154 };
1155
1156 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1157         { .role = "dbclk", .clk = "gpio1_dbclk" },
1158 };
1159
1160 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161         .name           = "gpio1",
1162         .class          = &omap44xx_gpio_hwmod_class,
1163         .clkdm_name     = "l4_wkup_clkdm",
1164         .mpu_irqs       = omap44xx_gpio1_irqs,
1165         .main_clk       = "gpio1_ick",
1166         .prcm = {
1167                 .omap4 = {
1168                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1169                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1170                         .modulemode   = MODULEMODE_HWCTRL,
1171                 },
1172         },
1173         .opt_clks       = gpio1_opt_clks,
1174         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1175         .dev_attr       = &gpio_dev_attr,
1176 };
1177
1178 /* gpio2 */
1179 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1180         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1181         { .irq = -1 }
1182 };
1183
1184 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1185         { .role = "dbclk", .clk = "gpio2_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1189         .name           = "gpio2",
1190         .class          = &omap44xx_gpio_hwmod_class,
1191         .clkdm_name     = "l4_per_clkdm",
1192         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193         .mpu_irqs       = omap44xx_gpio2_irqs,
1194         .main_clk       = "gpio2_ick",
1195         .prcm = {
1196                 .omap4 = {
1197                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1198                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1199                         .modulemode   = MODULEMODE_HWCTRL,
1200                 },
1201         },
1202         .opt_clks       = gpio2_opt_clks,
1203         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1204         .dev_attr       = &gpio_dev_attr,
1205 };
1206
1207 /* gpio3 */
1208 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1209         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1210         { .irq = -1 }
1211 };
1212
1213 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1214         { .role = "dbclk", .clk = "gpio3_dbclk" },
1215 };
1216
1217 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1218         .name           = "gpio3",
1219         .class          = &omap44xx_gpio_hwmod_class,
1220         .clkdm_name     = "l4_per_clkdm",
1221         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222         .mpu_irqs       = omap44xx_gpio3_irqs,
1223         .main_clk       = "gpio3_ick",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_HWCTRL,
1229                 },
1230         },
1231         .opt_clks       = gpio3_opt_clks,
1232         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1233         .dev_attr       = &gpio_dev_attr,
1234 };
1235
1236 /* gpio4 */
1237 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1238         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1239         { .irq = -1 }
1240 };
1241
1242 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1243         { .role = "dbclk", .clk = "gpio4_dbclk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1247         .name           = "gpio4",
1248         .class          = &omap44xx_gpio_hwmod_class,
1249         .clkdm_name     = "l4_per_clkdm",
1250         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1251         .mpu_irqs       = omap44xx_gpio4_irqs,
1252         .main_clk       = "gpio4_ick",
1253         .prcm = {
1254                 .omap4 = {
1255                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1256                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1257                         .modulemode   = MODULEMODE_HWCTRL,
1258                 },
1259         },
1260         .opt_clks       = gpio4_opt_clks,
1261         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1262         .dev_attr       = &gpio_dev_attr,
1263 };
1264
1265 /* gpio5 */
1266 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1267         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1268         { .irq = -1 }
1269 };
1270
1271 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1272         { .role = "dbclk", .clk = "gpio5_dbclk" },
1273 };
1274
1275 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1276         .name           = "gpio5",
1277         .class          = &omap44xx_gpio_hwmod_class,
1278         .clkdm_name     = "l4_per_clkdm",
1279         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1280         .mpu_irqs       = omap44xx_gpio5_irqs,
1281         .main_clk       = "gpio5_ick",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_HWCTRL,
1287                 },
1288         },
1289         .opt_clks       = gpio5_opt_clks,
1290         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1291         .dev_attr       = &gpio_dev_attr,
1292 };
1293
1294 /* gpio6 */
1295 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1296         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1297         { .irq = -1 }
1298 };
1299
1300 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1301         { .role = "dbclk", .clk = "gpio6_dbclk" },
1302 };
1303
1304 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1305         .name           = "gpio6",
1306         .class          = &omap44xx_gpio_hwmod_class,
1307         .clkdm_name     = "l4_per_clkdm",
1308         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1309         .mpu_irqs       = omap44xx_gpio6_irqs,
1310         .main_clk       = "gpio6_ick",
1311         .prcm = {
1312                 .omap4 = {
1313                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1314                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1315                         .modulemode   = MODULEMODE_HWCTRL,
1316                 },
1317         },
1318         .opt_clks       = gpio6_opt_clks,
1319         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1320         .dev_attr       = &gpio_dev_attr,
1321 };
1322
1323 /*
1324  * 'gpmc' class
1325  * general purpose memory controller
1326  */
1327
1328 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1329         .rev_offs       = 0x0000,
1330         .sysc_offs      = 0x0010,
1331         .syss_offs      = 0x0014,
1332         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1333                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1334         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1335         .sysc_fields    = &omap_hwmod_sysc_type1,
1336 };
1337
1338 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1339         .name   = "gpmc",
1340         .sysc   = &omap44xx_gpmc_sysc,
1341 };
1342
1343 /* gpmc */
1344 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1345         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1346         { .irq = -1 }
1347 };
1348
1349 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1350         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1351         { .dma_req = -1 }
1352 };
1353
1354 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1355         .name           = "gpmc",
1356         .class          = &omap44xx_gpmc_hwmod_class,
1357         .clkdm_name     = "l3_2_clkdm",
1358         /*
1359          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1360          * block.  It is not being added due to any known bugs with
1361          * resetting the GPMC IP block, but rather because any timings
1362          * set by the bootloader are not being correctly programmed by
1363          * the kernel from the board file or DT data.
1364          * HWMOD_INIT_NO_RESET should be removed ASAP.
1365          */
1366         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1367         .mpu_irqs       = omap44xx_gpmc_irqs,
1368         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1369         .prcm = {
1370                 .omap4 = {
1371                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1372                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1373                         .modulemode   = MODULEMODE_HWCTRL,
1374                 },
1375         },
1376 };
1377
1378 /*
1379  * 'gpu' class
1380  * 2d/3d graphics accelerator
1381  */
1382
1383 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1384         .rev_offs       = 0x1fc00,
1385         .sysc_offs      = 0x1fc10,
1386         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1388                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1389                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1390         .sysc_fields    = &omap_hwmod_sysc_type2,
1391 };
1392
1393 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1394         .name   = "gpu",
1395         .sysc   = &omap44xx_gpu_sysc,
1396 };
1397
1398 /* gpu */
1399 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1400         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1401         { .irq = -1 }
1402 };
1403
1404 static struct omap_hwmod omap44xx_gpu_hwmod = {
1405         .name           = "gpu",
1406         .class          = &omap44xx_gpu_hwmod_class,
1407         .clkdm_name     = "l3_gfx_clkdm",
1408         .mpu_irqs       = omap44xx_gpu_irqs,
1409         .main_clk       = "gpu_fck",
1410         .prcm = {
1411                 .omap4 = {
1412                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1413                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1414                         .modulemode   = MODULEMODE_SWCTRL,
1415                 },
1416         },
1417 };
1418
1419 /*
1420  * 'hdq1w' class
1421  * hdq / 1-wire serial interface controller
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0014,
1427         .syss_offs      = 0x0018,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1429                            SYSS_HAS_RESET_STATUS),
1430         .sysc_fields    = &omap_hwmod_sysc_type1,
1431 };
1432
1433 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1434         .name   = "hdq1w",
1435         .sysc   = &omap44xx_hdq1w_sysc,
1436 };
1437
1438 /* hdq1w */
1439 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1440         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1441         { .irq = -1 }
1442 };
1443
1444 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1445         .name           = "hdq1w",
1446         .class          = &omap44xx_hdq1w_hwmod_class,
1447         .clkdm_name     = "l4_per_clkdm",
1448         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1449         .mpu_irqs       = omap44xx_hdq1w_irqs,
1450         .main_clk       = "hdq1w_fck",
1451         .prcm = {
1452                 .omap4 = {
1453                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1454                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1455                         .modulemode   = MODULEMODE_SWCTRL,
1456                 },
1457         },
1458 };
1459
1460 /*
1461  * 'hsi' class
1462  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1463  * serial if)
1464  */
1465
1466 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1467         .rev_offs       = 0x0000,
1468         .sysc_offs      = 0x0010,
1469         .syss_offs      = 0x0014,
1470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1471                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1472                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1473         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1474                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1475                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1476         .sysc_fields    = &omap_hwmod_sysc_type1,
1477 };
1478
1479 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1480         .name   = "hsi",
1481         .sysc   = &omap44xx_hsi_sysc,
1482 };
1483
1484 /* hsi */
1485 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1486         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1488         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1489         { .irq = -1 }
1490 };
1491
1492 static struct omap_hwmod omap44xx_hsi_hwmod = {
1493         .name           = "hsi",
1494         .class          = &omap44xx_hsi_hwmod_class,
1495         .clkdm_name     = "l3_init_clkdm",
1496         .mpu_irqs       = omap44xx_hsi_irqs,
1497         .main_clk       = "hsi_fck",
1498         .prcm = {
1499                 .omap4 = {
1500                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1501                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1502                         .modulemode   = MODULEMODE_HWCTRL,
1503                 },
1504         },
1505 };
1506
1507 /*
1508  * 'i2c' class
1509  * multimaster high-speed i2c controller
1510  */
1511
1512 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1513         .sysc_offs      = 0x0010,
1514         .syss_offs      = 0x0090,
1515         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1516                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1517                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1518         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1519                            SIDLE_SMART_WKUP),
1520         .clockact       = CLOCKACT_TEST_ICLK,
1521         .sysc_fields    = &omap_hwmod_sysc_type1,
1522 };
1523
1524 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1525         .name   = "i2c",
1526         .sysc   = &omap44xx_i2c_sysc,
1527         .rev    = OMAP_I2C_IP_VERSION_2,
1528         .reset  = &omap_i2c_reset,
1529 };
1530
1531 static struct omap_i2c_dev_attr i2c_dev_attr = {
1532         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1533 };
1534
1535 /* i2c1 */
1536 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1537         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1538         { .irq = -1 }
1539 };
1540
1541 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1542         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1543         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1544         { .dma_req = -1 }
1545 };
1546
1547 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548         .name           = "i2c1",
1549         .class          = &omap44xx_i2c_hwmod_class,
1550         .clkdm_name     = "l4_per_clkdm",
1551         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1552         .mpu_irqs       = omap44xx_i2c1_irqs,
1553         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1554         .main_clk       = "i2c1_fck",
1555         .prcm = {
1556                 .omap4 = {
1557                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1558                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1559                         .modulemode   = MODULEMODE_SWCTRL,
1560                 },
1561         },
1562         .dev_attr       = &i2c_dev_attr,
1563 };
1564
1565 /* i2c2 */
1566 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1567         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1568         { .irq = -1 }
1569 };
1570
1571 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1572         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1573         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1574         { .dma_req = -1 }
1575 };
1576
1577 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578         .name           = "i2c2",
1579         .class          = &omap44xx_i2c_hwmod_class,
1580         .clkdm_name     = "l4_per_clkdm",
1581         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1582         .mpu_irqs       = omap44xx_i2c2_irqs,
1583         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1584         .main_clk       = "i2c2_fck",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1588                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1589                         .modulemode   = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592         .dev_attr       = &i2c_dev_attr,
1593 };
1594
1595 /* i2c3 */
1596 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1597         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1598         { .irq = -1 }
1599 };
1600
1601 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1602         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1603         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1604         { .dma_req = -1 }
1605 };
1606
1607 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608         .name           = "i2c3",
1609         .class          = &omap44xx_i2c_hwmod_class,
1610         .clkdm_name     = "l4_per_clkdm",
1611         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1612         .mpu_irqs       = omap44xx_i2c3_irqs,
1613         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1614         .main_clk       = "i2c3_fck",
1615         .prcm = {
1616                 .omap4 = {
1617                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1618                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1619                         .modulemode   = MODULEMODE_SWCTRL,
1620                 },
1621         },
1622         .dev_attr       = &i2c_dev_attr,
1623 };
1624
1625 /* i2c4 */
1626 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1627         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1628         { .irq = -1 }
1629 };
1630
1631 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1632         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1633         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1634         { .dma_req = -1 }
1635 };
1636
1637 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638         .name           = "i2c4",
1639         .class          = &omap44xx_i2c_hwmod_class,
1640         .clkdm_name     = "l4_per_clkdm",
1641         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1642         .mpu_irqs       = omap44xx_i2c4_irqs,
1643         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1644         .main_clk       = "i2c4_fck",
1645         .prcm = {
1646                 .omap4 = {
1647                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1648                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1649                         .modulemode   = MODULEMODE_SWCTRL,
1650                 },
1651         },
1652         .dev_attr       = &i2c_dev_attr,
1653 };
1654
1655 /*
1656  * 'ipu' class
1657  * imaging processor unit
1658  */
1659
1660 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1661         .name   = "ipu",
1662 };
1663
1664 /* ipu */
1665 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1666         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1667         { .irq = -1 }
1668 };
1669
1670 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1671         { .name = "cpu0", .rst_shift = 0 },
1672         { .name = "cpu1", .rst_shift = 1 },
1673 };
1674
1675 static struct omap_hwmod omap44xx_ipu_hwmod = {
1676         .name           = "ipu",
1677         .class          = &omap44xx_ipu_hwmod_class,
1678         .clkdm_name     = "ducati_clkdm",
1679         .mpu_irqs       = omap44xx_ipu_irqs,
1680         .rst_lines      = omap44xx_ipu_resets,
1681         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1682         .main_clk       = "ducati_clk_mux_ck",
1683         .prcm = {
1684                 .omap4 = {
1685                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1686                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1687                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_HWCTRL,
1689                 },
1690         },
1691 };
1692
1693 /*
1694  * 'iss' class
1695  * external images sensor pixel data processor
1696  */
1697
1698 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1699         .rev_offs       = 0x0000,
1700         .sysc_offs      = 0x0010,
1701         /*
1702          * ISS needs 100 OCP clk cycles delay after a softreset before
1703          * accessing sysconfig again.
1704          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1705          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706          *
1707          * TODO: Indicate errata when available.
1708          */
1709         .srst_udelay    = 2,
1710         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1711                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1713                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1714                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1715         .sysc_fields    = &omap_hwmod_sysc_type2,
1716 };
1717
1718 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1719         .name   = "iss",
1720         .sysc   = &omap44xx_iss_sysc,
1721 };
1722
1723 /* iss */
1724 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1725         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1726         { .irq = -1 }
1727 };
1728
1729 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1730         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1731         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1732         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1733         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1734         { .dma_req = -1 }
1735 };
1736
1737 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1738         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1739 };
1740
1741 static struct omap_hwmod omap44xx_iss_hwmod = {
1742         .name           = "iss",
1743         .class          = &omap44xx_iss_hwmod_class,
1744         .clkdm_name     = "iss_clkdm",
1745         .mpu_irqs       = omap44xx_iss_irqs,
1746         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1747         .main_clk       = "iss_fck",
1748         .prcm = {
1749                 .omap4 = {
1750                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1751                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1752                         .modulemode   = MODULEMODE_SWCTRL,
1753                 },
1754         },
1755         .opt_clks       = iss_opt_clks,
1756         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1757 };
1758
1759 /*
1760  * 'iva' class
1761  * multi-standard video encoder/decoder hardware accelerator
1762  */
1763
1764 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1765         .name   = "iva",
1766 };
1767
1768 /* iva */
1769 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1770         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1772         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1773         { .irq = -1 }
1774 };
1775
1776 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1777         { .name = "seq0", .rst_shift = 0 },
1778         { .name = "seq1", .rst_shift = 1 },
1779         { .name = "logic", .rst_shift = 2 },
1780 };
1781
1782 static struct omap_hwmod omap44xx_iva_hwmod = {
1783         .name           = "iva",
1784         .class          = &omap44xx_iva_hwmod_class,
1785         .clkdm_name     = "ivahd_clkdm",
1786         .mpu_irqs       = omap44xx_iva_irqs,
1787         .rst_lines      = omap44xx_iva_resets,
1788         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1789         .main_clk       = "iva_fck",
1790         .prcm = {
1791                 .omap4 = {
1792                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1793                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1794                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1795                         .modulemode   = MODULEMODE_HWCTRL,
1796                 },
1797         },
1798 };
1799
1800 /*
1801  * 'kbd' class
1802  * keyboard controller
1803  */
1804
1805 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1806         .rev_offs       = 0x0000,
1807         .sysc_offs      = 0x0010,
1808         .syss_offs      = 0x0014,
1809         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1810                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1811                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1812                            SYSS_HAS_RESET_STATUS),
1813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1814         .sysc_fields    = &omap_hwmod_sysc_type1,
1815 };
1816
1817 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1818         .name   = "kbd",
1819         .sysc   = &omap44xx_kbd_sysc,
1820 };
1821
1822 /* kbd */
1823 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1824         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod omap44xx_kbd_hwmod = {
1829         .name           = "kbd",
1830         .class          = &omap44xx_kbd_hwmod_class,
1831         .clkdm_name     = "l4_wkup_clkdm",
1832         .mpu_irqs       = omap44xx_kbd_irqs,
1833         .main_clk       = "kbd_fck",
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1837                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1838                         .modulemode   = MODULEMODE_SWCTRL,
1839                 },
1840         },
1841 };
1842
1843 /*
1844  * 'mailbox' class
1845  * mailbox module allowing communication between the on-chip processors using a
1846  * queued mailbox-interrupt mechanism.
1847  */
1848
1849 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1850         .rev_offs       = 0x0000,
1851         .sysc_offs      = 0x0010,
1852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1853                            SYSC_HAS_SOFTRESET),
1854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1855         .sysc_fields    = &omap_hwmod_sysc_type2,
1856 };
1857
1858 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1859         .name   = "mailbox",
1860         .sysc   = &omap44xx_mailbox_sysc,
1861 };
1862
1863 /* mailbox */
1864 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1865         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1866         { .irq = -1 }
1867 };
1868
1869 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870         .name           = "mailbox",
1871         .class          = &omap44xx_mailbox_hwmod_class,
1872         .clkdm_name     = "l4_cfg_clkdm",
1873         .mpu_irqs       = omap44xx_mailbox_irqs,
1874         .prcm = {
1875                 .omap4 = {
1876                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1877                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1878                 },
1879         },
1880 };
1881
1882 /*
1883  * 'mcasp' class
1884  * multi-channel audio serial port controller
1885  */
1886
1887 /* The IP is not compliant to type1 / type2 scheme */
1888 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1889         .sidle_shift    = 0,
1890 };
1891
1892 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1893         .sysc_offs      = 0x0004,
1894         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896                            SIDLE_SMART_WKUP),
1897         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1898 };
1899
1900 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1901         .name   = "mcasp",
1902         .sysc   = &omap44xx_mcasp_sysc,
1903 };
1904
1905 /* mcasp */
1906 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1907         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1908         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1909         { .irq = -1 }
1910 };
1911
1912 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1913         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1914         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1915         { .dma_req = -1 }
1916 };
1917
1918 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919         .name           = "mcasp",
1920         .class          = &omap44xx_mcasp_hwmod_class,
1921         .clkdm_name     = "abe_clkdm",
1922         .mpu_irqs       = omap44xx_mcasp_irqs,
1923         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1924         .main_clk       = "mcasp_fck",
1925         .prcm = {
1926                 .omap4 = {
1927                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1928                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1929                         .modulemode   = MODULEMODE_SWCTRL,
1930                 },
1931         },
1932 };
1933
1934 /*
1935  * 'mcbsp' class
1936  * multi channel buffered serial port controller
1937  */
1938
1939 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1940         .sysc_offs      = 0x008c,
1941         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1942                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1943         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1944         .sysc_fields    = &omap_hwmod_sysc_type1,
1945 };
1946
1947 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1948         .name   = "mcbsp",
1949         .sysc   = &omap44xx_mcbsp_sysc,
1950         .rev    = MCBSP_CONFIG_TYPE4,
1951 };
1952
1953 /* mcbsp1 */
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1955         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1956         { .irq = -1 }
1957 };
1958
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1960         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1961         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1962         { .dma_req = -1 }
1963 };
1964
1965 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1966         { .role = "pad_fck", .clk = "pad_clks_ck" },
1967         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1968 };
1969
1970 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971         .name           = "mcbsp1",
1972         .class          = &omap44xx_mcbsp_hwmod_class,
1973         .clkdm_name     = "abe_clkdm",
1974         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1975         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1976         .main_clk       = "mcbsp1_fck",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1980                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1981                         .modulemode   = MODULEMODE_SWCTRL,
1982                 },
1983         },
1984         .opt_clks       = mcbsp1_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1986 };
1987
1988 /* mcbsp2 */
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1990         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1991         { .irq = -1 }
1992 };
1993
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1995         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1996         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1997         { .dma_req = -1 }
1998 };
1999
2000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2001         { .role = "pad_fck", .clk = "pad_clks_ck" },
2002         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2003 };
2004
2005 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006         .name           = "mcbsp2",
2007         .class          = &omap44xx_mcbsp_hwmod_class,
2008         .clkdm_name     = "abe_clkdm",
2009         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2010         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2011         .main_clk       = "mcbsp2_fck",
2012         .prcm = {
2013                 .omap4 = {
2014                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2015                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2016                         .modulemode   = MODULEMODE_SWCTRL,
2017                 },
2018         },
2019         .opt_clks       = mcbsp2_opt_clks,
2020         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2021 };
2022
2023 /* mcbsp3 */
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2025         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2026         { .irq = -1 }
2027 };
2028
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2030         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2031         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2032         { .dma_req = -1 }
2033 };
2034
2035 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2036         { .role = "pad_fck", .clk = "pad_clks_ck" },
2037         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2038 };
2039
2040 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041         .name           = "mcbsp3",
2042         .class          = &omap44xx_mcbsp_hwmod_class,
2043         .clkdm_name     = "abe_clkdm",
2044         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2045         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2046         .main_clk       = "mcbsp3_fck",
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2050                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_SWCTRL,
2052                 },
2053         },
2054         .opt_clks       = mcbsp3_opt_clks,
2055         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2056 };
2057
2058 /* mcbsp4 */
2059 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2060         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2061         { .irq = -1 }
2062 };
2063
2064 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2065         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2066         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2067         { .dma_req = -1 }
2068 };
2069
2070 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2071         { .role = "pad_fck", .clk = "pad_clks_ck" },
2072         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2073 };
2074
2075 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076         .name           = "mcbsp4",
2077         .class          = &omap44xx_mcbsp_hwmod_class,
2078         .clkdm_name     = "l4_per_clkdm",
2079         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2080         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2081         .main_clk       = "mcbsp4_fck",
2082         .prcm = {
2083                 .omap4 = {
2084                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2085                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2086                         .modulemode   = MODULEMODE_SWCTRL,
2087                 },
2088         },
2089         .opt_clks       = mcbsp4_opt_clks,
2090         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2091 };
2092
2093 /*
2094  * 'mcpdm' class
2095  * multi channel pdm controller (proprietary interface with phoenix power
2096  * ic)
2097  */
2098
2099 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2100         .rev_offs       = 0x0000,
2101         .sysc_offs      = 0x0010,
2102         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2105                            SIDLE_SMART_WKUP),
2106         .sysc_fields    = &omap_hwmod_sysc_type2,
2107 };
2108
2109 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2110         .name   = "mcpdm",
2111         .sysc   = &omap44xx_mcpdm_sysc,
2112 };
2113
2114 /* mcpdm */
2115 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2116         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2117         { .irq = -1 }
2118 };
2119
2120 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2121         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2122         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2123         { .dma_req = -1 }
2124 };
2125
2126 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127         .name           = "mcpdm",
2128         .class          = &omap44xx_mcpdm_hwmod_class,
2129         .clkdm_name     = "abe_clkdm",
2130         /*
2131          * It's suspected that the McPDM requires an off-chip main
2132          * functional clock, controlled via I2C.  This IP block is
2133          * currently reset very early during boot, before I2C is
2134          * available, so it doesn't seem that we have any choice in
2135          * the kernel other than to avoid resetting it.
2136          */
2137         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2138         .mpu_irqs       = omap44xx_mcpdm_irqs,
2139         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2140         .main_clk       = "mcpdm_fck",
2141         .prcm = {
2142                 .omap4 = {
2143                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2144                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2145                         .modulemode   = MODULEMODE_SWCTRL,
2146                 },
2147         },
2148 };
2149
2150 /*
2151  * 'mcspi' class
2152  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2153  * bus
2154  */
2155
2156 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2157         .rev_offs       = 0x0000,
2158         .sysc_offs      = 0x0010,
2159         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2160                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2161         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2162                            SIDLE_SMART_WKUP),
2163         .sysc_fields    = &omap_hwmod_sysc_type2,
2164 };
2165
2166 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2167         .name   = "mcspi",
2168         .sysc   = &omap44xx_mcspi_sysc,
2169         .rev    = OMAP4_MCSPI_REV,
2170 };
2171
2172 /* mcspi1 */
2173 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2174         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2175         { .irq = -1 }
2176 };
2177
2178 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2179         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2180         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2181         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2182         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2183         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2184         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2185         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2186         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2187         { .dma_req = -1 }
2188 };
2189
2190 /* mcspi1 dev_attr */
2191 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2192         .num_chipselect = 4,
2193 };
2194
2195 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2196         .name           = "mcspi1",
2197         .class          = &omap44xx_mcspi_hwmod_class,
2198         .clkdm_name     = "l4_per_clkdm",
2199         .mpu_irqs       = omap44xx_mcspi1_irqs,
2200         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2201         .main_clk       = "mcspi1_fck",
2202         .prcm = {
2203                 .omap4 = {
2204                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2205                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2206                         .modulemode   = MODULEMODE_SWCTRL,
2207                 },
2208         },
2209         .dev_attr       = &mcspi1_dev_attr,
2210 };
2211
2212 /* mcspi2 */
2213 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2214         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2215         { .irq = -1 }
2216 };
2217
2218 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2219         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2220         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2221         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2222         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2223         { .dma_req = -1 }
2224 };
2225
2226 /* mcspi2 dev_attr */
2227 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2228         .num_chipselect = 2,
2229 };
2230
2231 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2232         .name           = "mcspi2",
2233         .class          = &omap44xx_mcspi_hwmod_class,
2234         .clkdm_name     = "l4_per_clkdm",
2235         .mpu_irqs       = omap44xx_mcspi2_irqs,
2236         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2237         .main_clk       = "mcspi2_fck",
2238         .prcm = {
2239                 .omap4 = {
2240                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2241                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2242                         .modulemode   = MODULEMODE_SWCTRL,
2243                 },
2244         },
2245         .dev_attr       = &mcspi2_dev_attr,
2246 };
2247
2248 /* mcspi3 */
2249 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2250         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2251         { .irq = -1 }
2252 };
2253
2254 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2255         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2256         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2257         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2258         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2259         { .dma_req = -1 }
2260 };
2261
2262 /* mcspi3 dev_attr */
2263 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2264         .num_chipselect = 2,
2265 };
2266
2267 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2268         .name           = "mcspi3",
2269         .class          = &omap44xx_mcspi_hwmod_class,
2270         .clkdm_name     = "l4_per_clkdm",
2271         .mpu_irqs       = omap44xx_mcspi3_irqs,
2272         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2273         .main_clk       = "mcspi3_fck",
2274         .prcm = {
2275                 .omap4 = {
2276                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2277                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2278                         .modulemode   = MODULEMODE_SWCTRL,
2279                 },
2280         },
2281         .dev_attr       = &mcspi3_dev_attr,
2282 };
2283
2284 /* mcspi4 */
2285 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2286         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2287         { .irq = -1 }
2288 };
2289
2290 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2291         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2292         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2293         { .dma_req = -1 }
2294 };
2295
2296 /* mcspi4 dev_attr */
2297 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2298         .num_chipselect = 1,
2299 };
2300
2301 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2302         .name           = "mcspi4",
2303         .class          = &omap44xx_mcspi_hwmod_class,
2304         .clkdm_name     = "l4_per_clkdm",
2305         .mpu_irqs       = omap44xx_mcspi4_irqs,
2306         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2307         .main_clk       = "mcspi4_fck",
2308         .prcm = {
2309                 .omap4 = {
2310                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2311                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2312                         .modulemode   = MODULEMODE_SWCTRL,
2313                 },
2314         },
2315         .dev_attr       = &mcspi4_dev_attr,
2316 };
2317
2318 /*
2319  * 'mmc' class
2320  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2321  */
2322
2323 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2324         .rev_offs       = 0x0000,
2325         .sysc_offs      = 0x0010,
2326         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2327                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2328                            SYSC_HAS_SOFTRESET),
2329         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2330                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2331                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2332         .sysc_fields    = &omap_hwmod_sysc_type2,
2333 };
2334
2335 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2336         .name   = "mmc",
2337         .sysc   = &omap44xx_mmc_sysc,
2338 };
2339
2340 /* mmc1 */
2341 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2342         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2343         { .irq = -1 }
2344 };
2345
2346 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2347         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2348         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2349         { .dma_req = -1 }
2350 };
2351
2352 /* mmc1 dev_attr */
2353 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2354         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2355 };
2356
2357 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2358         .name           = "mmc1",
2359         .class          = &omap44xx_mmc_hwmod_class,
2360         .clkdm_name     = "l3_init_clkdm",
2361         .mpu_irqs       = omap44xx_mmc1_irqs,
2362         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2363         .main_clk       = "mmc1_fck",
2364         .prcm = {
2365                 .omap4 = {
2366                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2367                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2368                         .modulemode   = MODULEMODE_SWCTRL,
2369                 },
2370         },
2371         .dev_attr       = &mmc1_dev_attr,
2372 };
2373
2374 /* mmc2 */
2375 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2376         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2377         { .irq = -1 }
2378 };
2379
2380 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2381         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2382         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2383         { .dma_req = -1 }
2384 };
2385
2386 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2387         .name           = "mmc2",
2388         .class          = &omap44xx_mmc_hwmod_class,
2389         .clkdm_name     = "l3_init_clkdm",
2390         .mpu_irqs       = omap44xx_mmc2_irqs,
2391         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2392         .main_clk       = "mmc2_fck",
2393         .prcm = {
2394                 .omap4 = {
2395                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2396                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2397                         .modulemode   = MODULEMODE_SWCTRL,
2398                 },
2399         },
2400 };
2401
2402 /* mmc3 */
2403 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2404         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2405         { .irq = -1 }
2406 };
2407
2408 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2409         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2410         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2411         { .dma_req = -1 }
2412 };
2413
2414 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2415         .name           = "mmc3",
2416         .class          = &omap44xx_mmc_hwmod_class,
2417         .clkdm_name     = "l4_per_clkdm",
2418         .mpu_irqs       = omap44xx_mmc3_irqs,
2419         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2420         .main_clk       = "mmc3_fck",
2421         .prcm = {
2422                 .omap4 = {
2423                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2424                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2425                         .modulemode   = MODULEMODE_SWCTRL,
2426                 },
2427         },
2428 };
2429
2430 /* mmc4 */
2431 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2432         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2433         { .irq = -1 }
2434 };
2435
2436 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2437         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2438         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2439         { .dma_req = -1 }
2440 };
2441
2442 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2443         .name           = "mmc4",
2444         .class          = &omap44xx_mmc_hwmod_class,
2445         .clkdm_name     = "l4_per_clkdm",
2446         .mpu_irqs       = omap44xx_mmc4_irqs,
2447         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2448         .main_clk       = "mmc4_fck",
2449         .prcm = {
2450                 .omap4 = {
2451                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2452                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2453                         .modulemode   = MODULEMODE_SWCTRL,
2454                 },
2455         },
2456 };
2457
2458 /* mmc5 */
2459 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2460         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2461         { .irq = -1 }
2462 };
2463
2464 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2465         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2466         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2467         { .dma_req = -1 }
2468 };
2469
2470 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2471         .name           = "mmc5",
2472         .class          = &omap44xx_mmc_hwmod_class,
2473         .clkdm_name     = "l4_per_clkdm",
2474         .mpu_irqs       = omap44xx_mmc5_irqs,
2475         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2476         .main_clk       = "mmc5_fck",
2477         .prcm = {
2478                 .omap4 = {
2479                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2480                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2481                         .modulemode   = MODULEMODE_SWCTRL,
2482                 },
2483         },
2484 };
2485
2486 /*
2487  * 'mmu' class
2488  * The memory management unit performs virtual to physical address translation
2489  * for its requestors.
2490  */
2491
2492 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2493         .rev_offs       = 0x000,
2494         .sysc_offs      = 0x010,
2495         .syss_offs      = 0x014,
2496         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2497                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2498         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2499         .sysc_fields    = &omap_hwmod_sysc_type1,
2500 };
2501
2502 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2503         .name = "mmu",
2504         .sysc = &mmu_sysc,
2505 };
2506
2507 /* mmu ipu */
2508
2509 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2510         .da_start       = 0x0,
2511         .da_end         = 0xfffff000,
2512         .nr_tlb_entries = 32,
2513 };
2514
2515 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2516 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2517         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2518         { .irq = -1 }
2519 };
2520
2521 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2522         { .name = "mmu_cache", .rst_shift = 2 },
2523 };
2524
2525 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2526         {
2527                 .pa_start       = 0x55082000,
2528                 .pa_end         = 0x550820ff,
2529                 .flags          = ADDR_TYPE_RT,
2530         },
2531         { }
2532 };
2533
2534 /* l3_main_2 -> mmu_ipu */
2535 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2536         .master         = &omap44xx_l3_main_2_hwmod,
2537         .slave          = &omap44xx_mmu_ipu_hwmod,
2538         .clk            = "l3_div_ck",
2539         .addr           = omap44xx_mmu_ipu_addrs,
2540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2541 };
2542
2543 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2544         .name           = "mmu_ipu",
2545         .class          = &omap44xx_mmu_hwmod_class,
2546         .clkdm_name     = "ducati_clkdm",
2547         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2548         .rst_lines      = omap44xx_mmu_ipu_resets,
2549         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2550         .main_clk       = "ducati_clk_mux_ck",
2551         .prcm = {
2552                 .omap4 = {
2553                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2554                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2555                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2556                         .modulemode   = MODULEMODE_HWCTRL,
2557                 },
2558         },
2559         .dev_attr       = &mmu_ipu_dev_attr,
2560 };
2561
2562 /* mmu dsp */
2563
2564 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2565         .da_start       = 0x0,
2566         .da_end         = 0xfffff000,
2567         .nr_tlb_entries = 32,
2568 };
2569
2570 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2571 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2572         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2573         { .irq = -1 }
2574 };
2575
2576 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2577         { .name = "mmu_cache", .rst_shift = 1 },
2578 };
2579
2580 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2581         {
2582                 .pa_start       = 0x4a066000,
2583                 .pa_end         = 0x4a0660ff,
2584                 .flags          = ADDR_TYPE_RT,
2585         },
2586         { }
2587 };
2588
2589 /* l4_cfg -> dsp */
2590 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2591         .master         = &omap44xx_l4_cfg_hwmod,
2592         .slave          = &omap44xx_mmu_dsp_hwmod,
2593         .clk            = "l4_div_ck",
2594         .addr           = omap44xx_mmu_dsp_addrs,
2595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2596 };
2597
2598 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2599         .name           = "mmu_dsp",
2600         .class          = &omap44xx_mmu_hwmod_class,
2601         .clkdm_name     = "tesla_clkdm",
2602         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2603         .rst_lines      = omap44xx_mmu_dsp_resets,
2604         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2605         .main_clk       = "dpll_iva_m4x2_ck",
2606         .prcm = {
2607                 .omap4 = {
2608                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2609                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2610                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2611                         .modulemode   = MODULEMODE_HWCTRL,
2612                 },
2613         },
2614         .dev_attr       = &mmu_dsp_dev_attr,
2615 };
2616
2617 /*
2618  * 'mpu' class
2619  * mpu sub-system
2620  */
2621
2622 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2623         .name   = "mpu",
2624 };
2625
2626 /* mpu */
2627 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2628         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2629         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2630         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2631         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2632         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2633         { .irq = -1 }
2634 };
2635
2636 static struct omap_hwmod omap44xx_mpu_hwmod = {
2637         .name           = "mpu",
2638         .class          = &omap44xx_mpu_hwmod_class,
2639         .clkdm_name     = "mpuss_clkdm",
2640         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2641         .mpu_irqs       = omap44xx_mpu_irqs,
2642         .main_clk       = "dpll_mpu_m2_ck",
2643         .prcm = {
2644                 .omap4 = {
2645                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2646                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2647                 },
2648         },
2649 };
2650
2651 /*
2652  * 'ocmc_ram' class
2653  * top-level core on-chip ram
2654  */
2655
2656 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2657         .name   = "ocmc_ram",
2658 };
2659
2660 /* ocmc_ram */
2661 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2662         .name           = "ocmc_ram",
2663         .class          = &omap44xx_ocmc_ram_hwmod_class,
2664         .clkdm_name     = "l3_2_clkdm",
2665         .prcm = {
2666                 .omap4 = {
2667                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2668                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2669                 },
2670         },
2671 };
2672
2673 /*
2674  * 'ocp2scp' class
2675  * bridge to transform ocp interface protocol to scp (serial control port)
2676  * protocol
2677  */
2678
2679 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2680         .rev_offs       = 0x0000,
2681         .sysc_offs      = 0x0010,
2682         .syss_offs      = 0x0014,
2683         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2684                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2685         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2686         .sysc_fields    = &omap_hwmod_sysc_type1,
2687 };
2688
2689 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2690         .name   = "ocp2scp",
2691         .sysc   = &omap44xx_ocp2scp_sysc,
2692 };
2693
2694 /* ocp2scp dev_attr */
2695 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2696         {
2697                 .name           = "usb_phy",
2698                 .start          = 0x4a0ad080,
2699                 .end            = 0x4a0ae000,
2700                 .flags          = IORESOURCE_MEM,
2701         },
2702         {
2703                 /* XXX: Remove this once control module driver is in place */
2704                 .name           = "ctrl_dev",
2705                 .start          = 0x4a002300,
2706                 .end            = 0x4a002303,
2707                 .flags          = IORESOURCE_MEM,
2708         },
2709         { }
2710 };
2711
2712 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2713         {
2714                 .drv_name       = "omap-usb2",
2715                 .res            = omap44xx_usb_phy_and_pll_addrs,
2716         },
2717         { }
2718 };
2719
2720 /* ocp2scp_usb_phy */
2721 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2722         .name           = "ocp2scp_usb_phy",
2723         .class          = &omap44xx_ocp2scp_hwmod_class,
2724         .clkdm_name     = "l3_init_clkdm",
2725         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2726         .prcm = {
2727                 .omap4 = {
2728                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2729                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2730                         .modulemode   = MODULEMODE_HWCTRL,
2731                 },
2732         },
2733         .dev_attr       = ocp2scp_dev_attr,
2734 };
2735
2736 /*
2737  * 'prcm' class
2738  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2739  * + clock manager 1 (in always on power domain) + local prm in mpu
2740  */
2741
2742 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2743         .name   = "prcm",
2744 };
2745
2746 /* prcm_mpu */
2747 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2748         .name           = "prcm_mpu",
2749         .class          = &omap44xx_prcm_hwmod_class,
2750         .clkdm_name     = "l4_wkup_clkdm",
2751         .flags          = HWMOD_NO_IDLEST,
2752         .prcm = {
2753                 .omap4 = {
2754                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2755                 },
2756         },
2757 };
2758
2759 /* cm_core_aon */
2760 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2761         .name           = "cm_core_aon",
2762         .class          = &omap44xx_prcm_hwmod_class,
2763         .flags          = HWMOD_NO_IDLEST,
2764         .prcm = {
2765                 .omap4 = {
2766                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2767                 },
2768         },
2769 };
2770
2771 /* cm_core */
2772 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2773         .name           = "cm_core",
2774         .class          = &omap44xx_prcm_hwmod_class,
2775         .flags          = HWMOD_NO_IDLEST,
2776         .prcm = {
2777                 .omap4 = {
2778                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2779                 },
2780         },
2781 };
2782
2783 /* prm */
2784 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2785         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2786         { .irq = -1 }
2787 };
2788
2789 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2790         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2791         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2792 };
2793
2794 static struct omap_hwmod omap44xx_prm_hwmod = {
2795         .name           = "prm",
2796         .class          = &omap44xx_prcm_hwmod_class,
2797         .mpu_irqs       = omap44xx_prm_irqs,
2798         .rst_lines      = omap44xx_prm_resets,
2799         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2800 };
2801
2802 /*
2803  * 'scrm' class
2804  * system clock and reset manager
2805  */
2806
2807 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2808         .name   = "scrm",
2809 };
2810
2811 /* scrm */
2812 static struct omap_hwmod omap44xx_scrm_hwmod = {
2813         .name           = "scrm",
2814         .class          = &omap44xx_scrm_hwmod_class,
2815         .clkdm_name     = "l4_wkup_clkdm",
2816         .prcm = {
2817                 .omap4 = {
2818                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2819                 },
2820         },
2821 };
2822
2823 /*
2824  * 'sl2if' class
2825  * shared level 2 memory interface
2826  */
2827
2828 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2829         .name   = "sl2if",
2830 };
2831
2832 /* sl2if */
2833 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2834         .name           = "sl2if",
2835         .class          = &omap44xx_sl2if_hwmod_class,
2836         .clkdm_name     = "ivahd_clkdm",
2837         .prcm = {
2838                 .omap4 = {
2839                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2840                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2841                         .modulemode   = MODULEMODE_HWCTRL,
2842                 },
2843         },
2844 };
2845
2846 /*
2847  * 'slimbus' class
2848  * bidirectional, multi-drop, multi-channel two-line serial interface between
2849  * the device and external components
2850  */
2851
2852 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2853         .rev_offs       = 0x0000,
2854         .sysc_offs      = 0x0010,
2855         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2856                            SYSC_HAS_SOFTRESET),
2857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2858                            SIDLE_SMART_WKUP),
2859         .sysc_fields    = &omap_hwmod_sysc_type2,
2860 };
2861
2862 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2863         .name   = "slimbus",
2864         .sysc   = &omap44xx_slimbus_sysc,
2865 };
2866
2867 /* slimbus1 */
2868 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2869         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2870         { .irq = -1 }
2871 };
2872
2873 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2874         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2875         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2876         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2877         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2878         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2879         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2880         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2881         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2882         { .dma_req = -1 }
2883 };
2884
2885 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2886         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2887         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2888         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2889         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2890 };
2891
2892 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2893         .name           = "slimbus1",
2894         .class          = &omap44xx_slimbus_hwmod_class,
2895         .clkdm_name     = "abe_clkdm",
2896         .mpu_irqs       = omap44xx_slimbus1_irqs,
2897         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2898         .prcm = {
2899                 .omap4 = {
2900                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2901                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2902                         .modulemode   = MODULEMODE_SWCTRL,
2903                 },
2904         },
2905         .opt_clks       = slimbus1_opt_clks,
2906         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2907 };
2908
2909 /* slimbus2 */
2910 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2911         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2912         { .irq = -1 }
2913 };
2914
2915 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2916         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2917         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2918         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2919         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2920         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2921         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2922         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2923         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2924         { .dma_req = -1 }
2925 };
2926
2927 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2928         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2929         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2930         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2931 };
2932
2933 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2934         .name           = "slimbus2",
2935         .class          = &omap44xx_slimbus_hwmod_class,
2936         .clkdm_name     = "l4_per_clkdm",
2937         .mpu_irqs       = omap44xx_slimbus2_irqs,
2938         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2939         .prcm = {
2940                 .omap4 = {
2941                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2942                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2943                         .modulemode   = MODULEMODE_SWCTRL,
2944                 },
2945         },
2946         .opt_clks       = slimbus2_opt_clks,
2947         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2948 };
2949
2950 /*
2951  * 'smartreflex' class
2952  * smartreflex module (monitor silicon performance and outputs a measure of
2953  * performance error)
2954  */
2955
2956 /* The IP is not compliant to type1 / type2 scheme */
2957 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2958         .sidle_shift    = 24,
2959         .enwkup_shift   = 26,
2960 };
2961
2962 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2963         .sysc_offs      = 0x0038,
2964         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2965         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2966                            SIDLE_SMART_WKUP),
2967         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2968 };
2969
2970 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2971         .name   = "smartreflex",
2972         .sysc   = &omap44xx_smartreflex_sysc,
2973         .rev    = 2,
2974 };
2975
2976 /* smartreflex_core */
2977 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2978         .sensor_voltdm_name   = "core",
2979 };
2980
2981 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2982         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2983         { .irq = -1 }
2984 };
2985
2986 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2987         .name           = "smartreflex_core",
2988         .class          = &omap44xx_smartreflex_hwmod_class,
2989         .clkdm_name     = "l4_ao_clkdm",
2990         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2991
2992         .main_clk       = "smartreflex_core_fck",
2993         .prcm = {
2994                 .omap4 = {
2995                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2996                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2997                         .modulemode   = MODULEMODE_SWCTRL,
2998                 },
2999         },
3000         .dev_attr       = &smartreflex_core_dev_attr,
3001 };
3002
3003 /* smartreflex_iva */
3004 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3005         .sensor_voltdm_name     = "iva",
3006 };
3007
3008 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3009         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3010         { .irq = -1 }
3011 };
3012
3013 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3014         .name           = "smartreflex_iva",
3015         .class          = &omap44xx_smartreflex_hwmod_class,
3016         .clkdm_name     = "l4_ao_clkdm",
3017         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3018         .main_clk       = "smartreflex_iva_fck",
3019         .prcm = {
3020                 .omap4 = {
3021                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3022                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3023                         .modulemode   = MODULEMODE_SWCTRL,
3024                 },
3025         },
3026         .dev_attr       = &smartreflex_iva_dev_attr,
3027 };
3028
3029 /* smartreflex_mpu */
3030 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3031         .sensor_voltdm_name     = "mpu",
3032 };
3033
3034 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3035         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3036         { .irq = -1 }
3037 };
3038
3039 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3040         .name           = "smartreflex_mpu",
3041         .class          = &omap44xx_smartreflex_hwmod_class,
3042         .clkdm_name     = "l4_ao_clkdm",
3043         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3044         .main_clk       = "smartreflex_mpu_fck",
3045         .prcm = {
3046                 .omap4 = {
3047                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3048                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3049                         .modulemode   = MODULEMODE_SWCTRL,
3050                 },
3051         },
3052         .dev_attr       = &smartreflex_mpu_dev_attr,
3053 };
3054
3055 /*
3056  * 'spinlock' class
3057  * spinlock provides hardware assistance for synchronizing the processes
3058  * running on multiple processors
3059  */
3060
3061 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3062         .rev_offs       = 0x0000,
3063         .sysc_offs      = 0x0010,
3064         .syss_offs      = 0x0014,
3065         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3066                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3067                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3068         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3069                            SIDLE_SMART_WKUP),
3070         .sysc_fields    = &omap_hwmod_sysc_type1,
3071 };
3072
3073 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3074         .name   = "spinlock",
3075         .sysc   = &omap44xx_spinlock_sysc,
3076 };
3077
3078 /* spinlock */
3079 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3080         .name           = "spinlock",
3081         .class          = &omap44xx_spinlock_hwmod_class,
3082         .clkdm_name     = "l4_cfg_clkdm",
3083         .prcm = {
3084                 .omap4 = {
3085                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3086                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3087                 },
3088         },
3089 };
3090
3091 /*
3092  * 'timer' class
3093  * general purpose timer module with accurate 1ms tick
3094  * This class contains several variants: ['timer_1ms', 'timer']
3095  */
3096
3097 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3098         .rev_offs       = 0x0000,
3099         .sysc_offs      = 0x0010,
3100         .syss_offs      = 0x0014,
3101         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3102                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3104                            SYSS_HAS_RESET_STATUS),
3105         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3106         .clockact       = CLOCKACT_TEST_ICLK,
3107         .sysc_fields    = &omap_hwmod_sysc_type1,
3108 };
3109
3110 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3111         .name   = "timer",
3112         .sysc   = &omap44xx_timer_1ms_sysc,
3113 };
3114
3115 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3116         .rev_offs       = 0x0000,
3117         .sysc_offs      = 0x0010,
3118         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3119                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3120         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3121                            SIDLE_SMART_WKUP),
3122         .sysc_fields    = &omap_hwmod_sysc_type2,
3123 };
3124
3125 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3126         .name   = "timer",
3127         .sysc   = &omap44xx_timer_sysc,
3128 };
3129
3130 /* always-on timers dev attribute */
3131 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3132         .timer_capability       = OMAP_TIMER_ALWON,
3133 };
3134
3135 /* pwm timers dev attribute */
3136 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3137         .timer_capability       = OMAP_TIMER_HAS_PWM,
3138 };
3139
3140 /* timers with DSP interrupt dev attribute */
3141 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3142         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3143 };
3144
3145 /* pwm timers with DSP interrupt dev attribute */
3146 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3147         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3148 };
3149
3150 /* timer1 */
3151 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3152         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3153         { .irq = -1 }
3154 };
3155
3156 static struct omap_hwmod omap44xx_timer1_hwmod = {
3157         .name           = "timer1",
3158         .class          = &omap44xx_timer_1ms_hwmod_class,
3159         .clkdm_name     = "l4_wkup_clkdm",
3160         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3161         .mpu_irqs       = omap44xx_timer1_irqs,
3162         .main_clk       = "timer1_fck",
3163         .prcm = {
3164                 .omap4 = {
3165                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3166                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3167                         .modulemode   = MODULEMODE_SWCTRL,
3168                 },
3169         },
3170         .dev_attr       = &capability_alwon_dev_attr,
3171 };
3172
3173 /* timer2 */
3174 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3175         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3176         { .irq = -1 }
3177 };
3178
3179 static struct omap_hwmod omap44xx_timer2_hwmod = {
3180         .name           = "timer2",
3181         .class          = &omap44xx_timer_1ms_hwmod_class,
3182         .clkdm_name     = "l4_per_clkdm",
3183         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3184         .mpu_irqs       = omap44xx_timer2_irqs,
3185         .main_clk       = "timer2_fck",
3186         .prcm = {
3187                 .omap4 = {
3188                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3189                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3190                         .modulemode   = MODULEMODE_SWCTRL,
3191                 },
3192         },
3193 };
3194
3195 /* timer3 */
3196 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3197         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3198         { .irq = -1 }
3199 };
3200
3201 static struct omap_hwmod omap44xx_timer3_hwmod = {
3202         .name           = "timer3",
3203         .class          = &omap44xx_timer_hwmod_class,
3204         .clkdm_name     = "l4_per_clkdm",
3205         .mpu_irqs       = omap44xx_timer3_irqs,
3206         .main_clk       = "timer3_fck",
3207         .prcm = {
3208                 .omap4 = {
3209                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,