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ARM: omap: fix typo on timer cleanup
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1 /*
2  * linux/arch/arm/mach-omap2/timer.c
3  *
4  * OMAP2 GP timer support.
5  *
6  * Copyright (C) 2009 Nokia Corporation
7  *
8  * Update to use new clocksource/clockevent layers
9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10  * Copyright (C) 2007 MontaVista Software, Inc.
11  *
12  * Original driver:
13  * Copyright (C) 2005 Nokia Corporation
14  * Author: Paul Mundt <paul.mundt@nokia.com>
15  *         Juha Yrjölä <juha.yrjola@nokia.com>
16  * OMAP Dual-mode timer framework support by Timo Teras
17  *
18  * Some parts based off of TI's 24xx code:
19  *
20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
21  *
22  * Roughly modelled after the OMAP1 MPU timer code.
23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24  *
25  * This file is subject to the terms and conditions of the GNU General Public
26  * License. See the file "COPYING" in the main directory of this archive
27  * for more details.
28  */
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
39 #include <linux/of.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
44
45 #include <asm/mach/time.h>
46 #include <asm/smp_twd.h>
47 #include <asm/sched_clock.h>
48
49 #include <asm/arch_timer.h>
50 #include "omap_hwmod.h"
51 #include "omap_device.h"
52 #include <plat/counter-32k.h>
53 #include <plat/dmtimer.h>
54 #include "omap-pm.h"
55
56 #include "soc.h"
57 #include "common.h"
58 #include "powerdomain.h"
59
60 /* Parent clocks, eventually these will come from the clock framework */
61
62 #define OMAP2_MPU_SOURCE        "sys_ck"
63 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
64 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
65 #define OMAP2_32K_SOURCE        "func_32k_ck"
66 #define OMAP3_32K_SOURCE        "omap_32k_fck"
67 #define OMAP4_32K_SOURCE        "sys_32k_ck"
68
69 #define REALTIME_COUNTER_BASE                           0x48243200
70 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
71 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
72 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
73
74 /* Clockevent code */
75
76 static struct omap_dm_timer clkev;
77 static struct clock_event_device clockevent_gpt;
78
79 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
80 {
81         struct clock_event_device *evt = &clockevent_gpt;
82
83         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
84
85         evt->event_handler(evt);
86         return IRQ_HANDLED;
87 }
88
89 static struct irqaction omap2_gp_timer_irq = {
90         .name           = "gp_timer",
91         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
92         .handler        = omap2_gp_timer_interrupt,
93 };
94
95 static int omap2_gp_timer_set_next_event(unsigned long cycles,
96                                          struct clock_event_device *evt)
97 {
98         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
99                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
100
101         return 0;
102 }
103
104 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
105                                     struct clock_event_device *evt)
106 {
107         u32 period;
108
109         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
110
111         switch (mode) {
112         case CLOCK_EVT_MODE_PERIODIC:
113                 period = clkev.rate / HZ;
114                 period -= 1;
115                 /* Looks like we need to first set the load value separately */
116                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
117                                       0xffffffff - period, OMAP_TIMER_POSTED);
118                 __omap_dm_timer_load_start(&clkev,
119                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
120                                         0xffffffff - period, OMAP_TIMER_POSTED);
121                 break;
122         case CLOCK_EVT_MODE_ONESHOT:
123                 break;
124         case CLOCK_EVT_MODE_UNUSED:
125         case CLOCK_EVT_MODE_SHUTDOWN:
126         case CLOCK_EVT_MODE_RESUME:
127                 break;
128         }
129 }
130
131 static struct clock_event_device clockevent_gpt = {
132         .name           = "gp_timer",
133         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
134         .shift          = 32,
135         .rating         = 300,
136         .set_next_event = omap2_gp_timer_set_next_event,
137         .set_mode       = omap2_gp_timer_set_mode,
138 };
139
140 static struct property device_disabled = {
141         .name = "status",
142         .length = sizeof("disabled"),
143         .value = "disabled",
144 };
145
146 static struct of_device_id omap_timer_match[] __initdata = {
147         { .compatible = "ti,omap2-timer", },
148         { }
149 };
150
151 /**
152  * omap_get_timer_dt - get a timer using device-tree
153  * @match       - device-tree match structure for matching a device type
154  * @property    - optional timer property to match
155  *
156  * Helper function to get a timer during early boot using device-tree for use
157  * as kernel system timer. Optionally, the property argument can be used to
158  * select a timer with a specific property. Once a timer is found then mark
159  * the timer node in device-tree as disabled, to prevent the kernel from
160  * registering this timer as a platform device and so no one else can use it.
161  */
162 static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
163                                                      const char *property)
164 {
165         struct device_node *np;
166
167         for_each_matching_node(np, match) {
168                 if (!of_device_is_available(np)) {
169                         of_node_put(np);
170                         continue;
171                 }
172
173                 if (property && !of_get_property(np, property, NULL)) {
174                         of_node_put(np);
175                         continue;
176                 }
177
178                 prom_add_property(np, &device_disabled);
179                 return np;
180         }
181
182         return NULL;
183 }
184
185 /**
186  * omap_dmtimer_init - initialisation function when device tree is used
187  *
188  * For secure OMAP3 devices, timers with device type "timer-secure" cannot
189  * be used by the kernel as they are reserved. Therefore, to prevent the
190  * kernel registering these devices remove them dynamically from the device
191  * tree on boot.
192  */
193 void __init omap_dmtimer_init(void)
194 {
195         struct device_node *np;
196
197         if (!cpu_is_omap34xx())
198                 return;
199
200         /* If we are a secure device, remove any secure timer nodes */
201         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
202                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
203                 if (np)
204                         of_node_put(np);
205         }
206 }
207
208 /**
209  * omap_dm_timer_get_errata - get errata flags for a timer
210  *
211  * Get the timer errata flags that are specific to the OMAP device being used.
212  */
213 u32 __init omap_dm_timer_get_errata(void)
214 {
215         if (cpu_is_omap24xx())
216                 return 0;
217
218         return OMAP_TIMER_ERRATA_I103_I767;
219 }
220
221 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
222                                                 int gptimer_id,
223                                                 const char *fck_source,
224                                                 const char *property,
225                                                 int posted)
226 {
227         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
228         const char *oh_name;
229         struct device_node *np;
230         struct omap_hwmod *oh;
231         struct resource irq, mem;
232         int r = 0;
233
234         if (of_have_populated_dt()) {
235                 np = omap_get_timer_dt(omap_timer_match, NULL);
236                 if (!np)
237                         return -ENODEV;
238
239                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
240                 if (!oh_name)
241                         return -ENODEV;
242
243                 timer->irq = irq_of_parse_and_map(np, 0);
244                 if (!timer->irq)
245                         return -ENXIO;
246
247                 timer->io_base = of_iomap(np, 0);
248
249                 of_node_put(np);
250         } else {
251                 if (omap_dm_timer_reserve_systimer(gptimer_id))
252                         return -ENODEV;
253
254                 sprintf(name, "timer%d", gptimer_id);
255                 oh_name = name;
256         }
257
258         oh = omap_hwmod_lookup(oh_name);
259         if (!oh)
260                 return -ENODEV;
261
262         if (!of_have_populated_dt()) {
263                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
264                                                    &irq);
265                 if (r)
266                         return -ENXIO;
267                 timer->irq = irq.start;
268
269                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
270                                                    &mem);
271                 if (r)
272                         return -ENXIO;
273
274                 /* Static mapping, never released */
275                 timer->io_base = ioremap(mem.start, mem.end - mem.start);
276         }
277
278         if (!timer->io_base)
279                 return -ENXIO;
280
281         /* After the dmtimer is using hwmod these clocks won't be needed */
282         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
283         if (IS_ERR(timer->fclk))
284                 return -ENODEV;
285
286         /* FIXME: Need to remove hard-coded test on timer ID */
287         if (gptimer_id != 12) {
288                 struct clk *src;
289
290                 src = clk_get(NULL, fck_source);
291                 if (IS_ERR(src)) {
292                         r = -EINVAL;
293                 } else {
294                         r = clk_set_parent(timer->fclk, src);
295                         if (IS_ERR_VALUE(r))
296                                 pr_warn("%s: %s cannot set source\n",
297                                         __func__, oh->name);
298                         clk_put(src);
299                 }
300         }
301
302         omap_hwmod_setup_one(oh_name);
303         omap_hwmod_enable(oh);
304         __omap_dm_timer_init_regs(timer);
305
306         if (posted)
307                 __omap_dm_timer_enable_posted(timer);
308
309         /* Check that the intended posted configuration matches the actual */
310         if (posted != timer->posted)
311                 return -EINVAL;
312
313         timer->rate = clk_get_rate(timer->fclk);
314         timer->reserved = 1;
315
316         return r;
317 }
318
319 static void __init omap2_gp_clockevent_init(int gptimer_id,
320                                                 const char *fck_source,
321                                                 const char *property)
322 {
323         int res;
324
325         clkev.errata = omap_dm_timer_get_errata();
326
327         /*
328          * For clock-event timers we never read the timer counter and
329          * so we are not impacted by errata i103 and i767. Therefore,
330          * we can safely ignore this errata for clock-event timers.
331          */
332         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
333
334         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
335                                      OMAP_TIMER_POSTED);
336         BUG_ON(res);
337
338         omap2_gp_timer_irq.dev_id = &clkev;
339         setup_irq(clkev.irq, &omap2_gp_timer_irq);
340
341         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
342
343         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
344                                      clockevent_gpt.shift);
345         clockevent_gpt.max_delta_ns =
346                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
347         clockevent_gpt.min_delta_ns =
348                 clockevent_delta2ns(3, &clockevent_gpt);
349                 /* Timer internal resynch latency. */
350
351         clockevent_gpt.cpumask = cpu_possible_mask;
352         clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
353         clockevents_register_device(&clockevent_gpt);
354
355         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
356                 gptimer_id, clkev.rate);
357 }
358
359 /* Clocksource code */
360 static struct omap_dm_timer clksrc;
361 static bool use_gptimer_clksrc;
362
363 /*
364  * clocksource
365  */
366 static cycle_t clocksource_read_cycles(struct clocksource *cs)
367 {
368         return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
369                                                      OMAP_TIMER_NONPOSTED);
370 }
371
372 static struct clocksource clocksource_gpt = {
373         .name           = "gp_timer",
374         .rating         = 300,
375         .read           = clocksource_read_cycles,
376         .mask           = CLOCKSOURCE_MASK(32),
377         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
378 };
379
380 static u32 notrace dmtimer_read_sched_clock(void)
381 {
382         if (clksrc.reserved)
383                 return __omap_dm_timer_read_counter(&clksrc,
384                                                     OMAP_TIMER_NONPOSTED);
385
386         return 0;
387 }
388
389 static struct of_device_id omap_counter_match[] __initdata = {
390         { .compatible = "ti,omap-counter32k", },
391         { }
392 };
393
394 /* Setup free-running counter for clocksource */
395 static int __init omap2_sync32k_clocksource_init(void)
396 {
397         int ret;
398         struct device_node *np = NULL;
399         struct omap_hwmod *oh;
400         void __iomem *vbase;
401         const char *oh_name = "counter_32k";
402
403         /*
404          * If device-tree is present, then search the DT blob
405          * to see if the 32kHz counter is supported.
406          */
407         if (of_have_populated_dt()) {
408                 np = omap_get_timer_dt(omap_counter_match, NULL);
409                 if (!np)
410                         return -ENODEV;
411
412                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
413                 if (!oh_name)
414                         return -ENODEV;
415         }
416
417         /*
418          * First check hwmod data is available for sync32k counter
419          */
420         oh = omap_hwmod_lookup(oh_name);
421         if (!oh || oh->slaves_cnt == 0)
422                 return -ENODEV;
423
424         omap_hwmod_setup_one(oh_name);
425
426         if (np) {
427                 vbase = of_iomap(np, 0);
428                 of_node_put(np);
429         } else {
430                 vbase = omap_hwmod_get_mpu_rt_va(oh);
431         }
432
433         if (!vbase) {
434                 pr_warn("%s: failed to get counter_32k resource\n", __func__);
435                 return -ENXIO;
436         }
437
438         ret = omap_hwmod_enable(oh);
439         if (ret) {
440                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
441                                                         __func__, ret);
442                 return ret;
443         }
444
445         ret = omap_init_clocksource_32k(vbase);
446         if (ret) {
447                 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
448                                                         __func__, ret);
449                 omap_hwmod_idle(oh);
450         }
451
452         return ret;
453 }
454
455 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
456                                                 const char *fck_source)
457 {
458         int res;
459
460         clksrc.errata = omap_dm_timer_get_errata();
461
462         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
463                                      OMAP_TIMER_NONPOSTED);
464         BUG_ON(res);
465
466         __omap_dm_timer_load_start(&clksrc,
467                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
468                                    OMAP_TIMER_NONPOSTED);
469         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
470
471         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
472                 pr_err("Could not register clocksource %s\n",
473                         clocksource_gpt.name);
474         else
475                 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
476                         gptimer_id, clksrc.rate);
477 }
478
479 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
480 /*
481  * The realtime counter also called master counter, is a free-running
482  * counter, which is related to real time. It produces the count used
483  * by the CPU local timer peripherals in the MPU cluster. The timer counts
484  * at a rate of 6.144 MHz. Because the device operates on different clocks
485  * in different power modes, the master counter shifts operation between
486  * clocks, adjusting the increment per clock in hardware accordingly to
487  * maintain a constant count rate.
488  */
489 static void __init realtime_counter_init(void)
490 {
491         void __iomem *base;
492         static struct clk *sys_clk;
493         unsigned long rate;
494         unsigned int reg, num, den;
495
496         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
497         if (!base) {
498                 pr_err("%s: ioremap failed\n", __func__);
499                 return;
500         }
501         sys_clk = clk_get(NULL, "sys_clkin_ck");
502         if (IS_ERR(sys_clk)) {
503                 pr_err("%s: failed to get system clock handle\n", __func__);
504                 iounmap(base);
505                 return;
506         }
507
508         rate = clk_get_rate(sys_clk);
509         /* Numerator/denumerator values refer TRM Realtime Counter section */
510         switch (rate) {
511         case 1200000:
512                 num = 64;
513                 den = 125;
514                 break;
515         case 1300000:
516                 num = 768;
517                 den = 1625;
518                 break;
519         case 19200000:
520                 num = 8;
521                 den = 25;
522                 break;
523         case 2600000:
524                 num = 384;
525                 den = 1625;
526                 break;
527         case 2700000:
528                 num = 256;
529                 den = 1125;
530                 break;
531         case 38400000:
532         default:
533                 /* Program it for 38.4 MHz */
534                 num = 4;
535                 den = 25;
536                 break;
537         }
538
539         /* Program numerator and denumerator registers */
540         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
541                         NUMERATOR_DENUMERATOR_MASK;
542         reg |= num;
543         __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
544
545         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
546                         NUMERATOR_DENUMERATOR_MASK;
547         reg |= den;
548         __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
549
550         iounmap(base);
551 }
552 #else
553 static inline void __init realtime_counter_init(void)
554 {}
555 #endif
556
557 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
558                                clksrc_nr, clksrc_src)                   \
559 static void __init omap##name##_gptimer_timer_init(void)                \
560 {                                                                       \
561         omap_dmtimer_init();                                            \
562         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
563         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
564 }
565
566 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
567                                 clksrc_nr, clksrc_src)                  \
568 static void __init omap##name##_sync32k_timer_init(void)                \
569 {                                                                       \
570         omap_dmtimer_init();                                            \
571         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
572         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
573         if (use_gptimer_clksrc)                                         \
574                 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
575         else                                                            \
576                 omap2_sync32k_clocksource_init();                       \
577 }
578
579 #define OMAP_SYS_TIMER(name, clksrc)                                    \
580 struct sys_timer omap##name##_timer = {                                 \
581         .init   = omap##name##_##clksrc##_timer_init,                   \
582 };
583
584 #ifdef CONFIG_ARCH_OMAP2
585 OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
586                         2, OMAP2_MPU_SOURCE);
587 OMAP_SYS_TIMER(2, sync32k);
588 #endif /* CONFIG_ARCH_OMAP2 */
589
590 #ifdef CONFIG_ARCH_OMAP3
591 OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
592                         2, OMAP3_MPU_SOURCE);
593 OMAP_SYS_TIMER(3, sync32k);
594 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
595                         2, OMAP3_MPU_SOURCE);
596 OMAP_SYS_TIMER(3_secure, sync32k);
597 OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
598                        2, OMAP3_MPU_SOURCE);
599 OMAP_SYS_TIMER(3_gp, gptimer);
600 #endif /* CONFIG_ARCH_OMAP3 */
601
602 #ifdef CONFIG_SOC_AM33XX
603 OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
604                        2, OMAP4_MPU_SOURCE);
605 OMAP_SYS_TIMER(3_am33xx, gptimer);
606 #endif /* CONFIG_SOC_AM33XX */
607
608 #ifdef CONFIG_ARCH_OMAP4
609 OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
610                         2, OMAP4_MPU_SOURCE);
611 #ifdef CONFIG_LOCAL_TIMERS
612 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
613 static void __init omap4_local_timer_init(void)
614 {
615         omap4_sync32k_timer_init();
616         /* Local timers are not supprted on OMAP4430 ES1.0 */
617         if (omap_rev() != OMAP4430_REV_ES1_0) {
618                 int err;
619
620                 if (of_have_populated_dt()) {
621                         twd_local_timer_of_register();
622                         return;
623                 }
624
625                 err = twd_local_timer_register(&twd_local_timer);
626                 if (err)
627                         pr_err("twd_local_timer_register failed %d\n", err);
628         }
629 }
630 #else /* CONFIG_LOCAL_TIMERS */
631 static void __init omap4_local_timer_init(void)
632 {
633         omap4_sync32k_timer_init();
634 }
635 #endif /* CONFIG_LOCAL_TIMERS */
636 OMAP_SYS_TIMER(4, local);
637 #endif /* CONFIG_ARCH_OMAP4 */
638
639 #ifdef CONFIG_SOC_OMAP5
640 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
641                         2, OMAP4_MPU_SOURCE);
642 static void __init omap5_realtime_timer_init(void)
643 {
644         int err;
645
646         omap5_sync32k_timer_init();
647         realtime_counter_init();
648
649         err = arch_timer_of_register();
650         if (err)
651                 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
652 }
653 OMAP_SYS_TIMER(5, realtime);
654 #endif /* CONFIG_SOC_OMAP5 */
655
656 /**
657  * omap_timer_init - build and register timer device with an
658  * associated timer hwmod
659  * @oh: timer hwmod pointer to be used to build timer device
660  * @user:       parameter that can be passed from calling hwmod API
661  *
662  * Called by omap_hwmod_for_each_by_class to register each of the timer
663  * devices present in the system. The number of timer devices is known
664  * by parsing through the hwmod database for a given class name. At the
665  * end of function call memory is allocated for timer device and it is
666  * registered to the framework ready to be proved by the driver.
667  */
668 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
669 {
670         int id;
671         int ret = 0;
672         char *name = "omap_timer";
673         struct dmtimer_platform_data *pdata;
674         struct platform_device *pdev;
675         struct omap_timer_capability_dev_attr *timer_dev_attr;
676
677         pr_debug("%s: %s\n", __func__, oh->name);
678
679         /* on secure device, do not register secure timer */
680         timer_dev_attr = oh->dev_attr;
681         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
682                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
683                         return ret;
684
685         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
686         if (!pdata) {
687                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
688                 return -ENOMEM;
689         }
690
691         /*
692          * Extract the IDs from name field in hwmod database
693          * and use the same for constructing ids' for the
694          * timer devices. In a way, we are avoiding usage of
695          * static variable witin the function to do the same.
696          * CAUTION: We have to be careful and make sure the
697          * name in hwmod database does not change in which case
698          * we might either make corresponding change here or
699          * switch back static variable mechanism.
700          */
701         sscanf(oh->name, "timer%2d", &id);
702
703         if (timer_dev_attr)
704                 pdata->timer_capability = timer_dev_attr->timer_capability;
705
706         pdata->timer_errata = omap_dm_timer_get_errata();
707         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
708
709         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
710                                  NULL, 0, 0);
711
712         if (IS_ERR(pdev)) {
713                 pr_err("%s: Can't build omap_device for %s: %s.\n",
714                         __func__, name, oh->name);
715                 ret = -EINVAL;
716         }
717
718         kfree(pdata);
719
720         return ret;
721 }
722
723 /**
724  * omap2_dm_timer_init - top level regular device initialization
725  *
726  * Uses dedicated hwmod api to parse through hwmod database for
727  * given class name and then build and register the timer device.
728  */
729 static int __init omap2_dm_timer_init(void)
730 {
731         int ret;
732
733         /* If dtb is there, the devices will be created dynamically */
734         if (of_have_populated_dt())
735                 return -ENODEV;
736
737         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
738         if (unlikely(ret)) {
739                 pr_err("%s: device registration failed.\n", __func__);
740                 return -EINVAL;
741         }
742
743         return 0;
744 }
745 arch_initcall(omap2_dm_timer_init);
746
747 /**
748  * omap2_override_clocksource - clocksource override with user configuration
749  *
750  * Allows user to override default clocksource, using kernel parameter
751  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
752  *
753  * Note that, here we are using same standard kernel parameter "clocksource=",
754  * and not introducing any OMAP specific interface.
755  */
756 static int __init omap2_override_clocksource(char *str)
757 {
758         if (!str)
759                 return 0;
760         /*
761          * For OMAP architecture, we only have two options
762          *    - sync_32k (default)
763          *    - gp_timer (sys_clk based)
764          */
765         if (!strcmp(str, "gp_timer"))
766                 use_gptimer_clksrc = true;
767
768         return 0;
769 }
770 early_param("clocksource", omap2_override_clocksource);