d8a455ede5a751c8dc31604526e425fb50167ee0
[~shefty/rdma-dev.git] / arch / openrisc / kernel / entry.S
1 /*
2  * OpenRISC entry.S
3  *
4  * Linux architectural port borrowing liberally from similar works of
5  * others.  All original copyrights apply as per the original source
6  * declaration.
7  *
8  * Modifications for the OpenRISC architecture:
9  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10  * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
11  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
12  *
13  *      This program is free software; you can redistribute it and/or
14  *      modify it under the terms of the GNU General Public License
15  *      as published by the Free Software Foundation; either version
16  *      2 of the License, or (at your option) any later version.
17  */
18
19 #include <linux/linkage.h>
20
21 #include <asm/processor.h>
22 #include <asm/unistd.h>
23 #include <asm/thread_info.h>
24 #include <asm/errno.h>
25 #include <asm/spr_defs.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/pgtable.h>
29 #include <asm/asm-offsets.h>
30
31 #define DISABLE_INTERRUPTS(t1,t2)                       \
32         l.mfspr t2,r0,SPR_SR                            ;\
33         l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE))         ;\
34         l.ori   t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE))      ;\
35         l.and   t2,t2,t1                                ;\
36         l.mtspr r0,t2,SPR_SR
37
38 #define ENABLE_INTERRUPTS(t1)                           \
39         l.mfspr t1,r0,SPR_SR                            ;\
40         l.ori   t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE)         ;\
41         l.mtspr r0,t1,SPR_SR
42
43 /* =========================================================[ macros ]=== */
44
45 /*
46  * We need to disable interrupts at beginning of RESTORE_ALL
47  * since interrupt might come in after we've loaded EPC return address
48  * and overwrite EPC with address somewhere in RESTORE_ALL
49  * which is of course wrong!
50  */
51
52 #define RESTORE_ALL                                             \
53         DISABLE_INTERRUPTS(r3,r4)                               ;\
54         l.lwz   r3,PT_PC(r1)                                    ;\
55         l.mtspr r0,r3,SPR_EPCR_BASE                             ;\
56         l.lwz   r3,PT_SR(r1)                                    ;\
57         l.mtspr r0,r3,SPR_ESR_BASE                              ;\
58         l.lwz   r2,PT_GPR2(r1)                                  ;\
59         l.lwz   r3,PT_GPR3(r1)                                  ;\
60         l.lwz   r4,PT_GPR4(r1)                                  ;\
61         l.lwz   r5,PT_GPR5(r1)                                  ;\
62         l.lwz   r6,PT_GPR6(r1)                                  ;\
63         l.lwz   r7,PT_GPR7(r1)                                  ;\
64         l.lwz   r8,PT_GPR8(r1)                                  ;\
65         l.lwz   r9,PT_GPR9(r1)                                  ;\
66         l.lwz   r10,PT_GPR10(r1)                                        ;\
67         l.lwz   r11,PT_GPR11(r1)                                        ;\
68         l.lwz   r12,PT_GPR12(r1)                                        ;\
69         l.lwz   r13,PT_GPR13(r1)                                        ;\
70         l.lwz   r14,PT_GPR14(r1)                                        ;\
71         l.lwz   r15,PT_GPR15(r1)                                        ;\
72         l.lwz   r16,PT_GPR16(r1)                                        ;\
73         l.lwz   r17,PT_GPR17(r1)                                        ;\
74         l.lwz   r18,PT_GPR18(r1)                                        ;\
75         l.lwz   r19,PT_GPR19(r1)                                        ;\
76         l.lwz   r20,PT_GPR20(r1)                                        ;\
77         l.lwz   r21,PT_GPR21(r1)                                        ;\
78         l.lwz   r22,PT_GPR22(r1)                                        ;\
79         l.lwz   r23,PT_GPR23(r1)                                        ;\
80         l.lwz   r24,PT_GPR24(r1)                                        ;\
81         l.lwz   r25,PT_GPR25(r1)                                        ;\
82         l.lwz   r26,PT_GPR26(r1)                                        ;\
83         l.lwz   r27,PT_GPR27(r1)                                        ;\
84         l.lwz   r28,PT_GPR28(r1)                                        ;\
85         l.lwz   r29,PT_GPR29(r1)                                        ;\
86         l.lwz   r30,PT_GPR30(r1)                                        ;\
87         l.lwz   r31,PT_GPR31(r1)                                        ;\
88         l.lwz   r1,PT_SP(r1)                                    ;\
89         l.rfe
90
91
92 #define EXCEPTION_ENTRY(handler)                                \
93         .global handler                                         ;\
94 handler:                                                        ;\
95         /* r1, EPCR, ESR a already saved */                     ;\
96         l.sw    PT_GPR2(r1),r2                                  ;\
97         l.sw    PT_GPR3(r1),r3                                  ;\
98         /* r4 already save */                                   ;\
99         l.sw    PT_GPR5(r1),r5                                  ;\
100         l.sw    PT_GPR6(r1),r6                                  ;\
101         l.sw    PT_GPR7(r1),r7                                  ;\
102         l.sw    PT_GPR8(r1),r8                                  ;\
103         l.sw    PT_GPR9(r1),r9                                  ;\
104         /* r10 already saved */                                 ;\
105         l.sw    PT_GPR11(r1),r11                                        ;\
106         /* r12 already saved */                                 ;\
107         l.sw    PT_GPR13(r1),r13                                        ;\
108         l.sw    PT_GPR14(r1),r14                                        ;\
109         l.sw    PT_GPR15(r1),r15                                        ;\
110         l.sw    PT_GPR16(r1),r16                                        ;\
111         l.sw    PT_GPR17(r1),r17                                        ;\
112         l.sw    PT_GPR18(r1),r18                                        ;\
113         l.sw    PT_GPR19(r1),r19                                        ;\
114         l.sw    PT_GPR20(r1),r20                                        ;\
115         l.sw    PT_GPR21(r1),r21                                        ;\
116         l.sw    PT_GPR22(r1),r22                                        ;\
117         l.sw    PT_GPR23(r1),r23                                        ;\
118         l.sw    PT_GPR24(r1),r24                                        ;\
119         l.sw    PT_GPR25(r1),r25                                        ;\
120         l.sw    PT_GPR26(r1),r26                                        ;\
121         l.sw    PT_GPR27(r1),r27                                        ;\
122         l.sw    PT_GPR28(r1),r28                                        ;\
123         l.sw    PT_GPR29(r1),r29                                        ;\
124         /* r30 already save */                                  ;\
125 /*        l.sw    PT_GPR30(r1),r30*/                                    ;\
126         l.sw    PT_GPR31(r1),r31                                        ;\
127         /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
128         l.addi  r30,r0,-1                                       ;\
129         l.sw    PT_ORIG_GPR11(r1),r30
130
131 #define UNHANDLED_EXCEPTION(handler,vector)                     \
132         .global handler                                         ;\
133 handler:                                                        ;\
134         /* r1, EPCR, ESR already saved */                       ;\
135         l.sw    PT_GPR2(r1),r2                                  ;\
136         l.sw    PT_GPR3(r1),r3                                  ;\
137         l.sw    PT_GPR5(r1),r5                                  ;\
138         l.sw    PT_GPR6(r1),r6                                  ;\
139         l.sw    PT_GPR7(r1),r7                                  ;\
140         l.sw    PT_GPR8(r1),r8                                  ;\
141         l.sw    PT_GPR9(r1),r9                                  ;\
142         /* r10 already saved */                                 ;\
143         l.sw    PT_GPR11(r1),r11                                        ;\
144         /* r12 already saved */                                 ;\
145         l.sw    PT_GPR13(r1),r13                                        ;\
146         l.sw    PT_GPR14(r1),r14                                        ;\
147         l.sw    PT_GPR15(r1),r15                                        ;\
148         l.sw    PT_GPR16(r1),r16                                        ;\
149         l.sw    PT_GPR17(r1),r17                                        ;\
150         l.sw    PT_GPR18(r1),r18                                        ;\
151         l.sw    PT_GPR19(r1),r19                                        ;\
152         l.sw    PT_GPR20(r1),r20                                        ;\
153         l.sw    PT_GPR21(r1),r21                                        ;\
154         l.sw    PT_GPR22(r1),r22                                        ;\
155         l.sw    PT_GPR23(r1),r23                                        ;\
156         l.sw    PT_GPR24(r1),r24                                        ;\
157         l.sw    PT_GPR25(r1),r25                                        ;\
158         l.sw    PT_GPR26(r1),r26                                        ;\
159         l.sw    PT_GPR27(r1),r27                                        ;\
160         l.sw    PT_GPR28(r1),r28                                        ;\
161         l.sw    PT_GPR29(r1),r29                                        ;\
162         /* r31 already saved */                                 ;\
163         l.sw    PT_GPR30(r1),r30                                        ;\
164 /*        l.sw    PT_GPR31(r1),r31      */                              ;\
165         /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
166         l.addi  r30,r0,-1                                       ;\
167         l.sw    PT_ORIG_GPR11(r1),r30                           ;\
168         l.addi  r3,r1,0                                         ;\
169         /* r4 is exception EA */                                ;\
170         l.addi  r5,r0,vector                                    ;\
171         l.jal   unhandled_exception                             ;\
172          l.nop                                                  ;\
173         l.j     _ret_from_exception                             ;\
174          l.nop
175
176 /*
177  * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
178  *       contain the same values as when exception we're handling
179  *       occured. in fact they never do. if you need them use
180  *       values saved on stack (for SPR_EPC, SPR_ESR) or content
181  *       of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
182  *       in 'arch/or32/kernel/head.S'
183  */
184
185 /* =====================================================[ exceptions] === */
186
187 /* ---[ 0x100: RESET exception ]----------------------------------------- */
188
189 EXCEPTION_ENTRY(_tng_kernel_start)
190         l.jal   _start
191          l.andi r0,r0,0
192
193 /* ---[ 0x200: BUS exception ]------------------------------------------- */
194
195 EXCEPTION_ENTRY(_bus_fault_handler)
196         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
197         l.jal   do_bus_fault
198          l.addi  r3,r1,0 /* pt_regs */
199
200         l.j     _ret_from_exception
201          l.nop
202
203 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
204 EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
205         l.and   r5,r5,r0
206         l.j     1f
207          l.nop
208
209 EXCEPTION_ENTRY(_data_page_fault_handler)
210         /* set up parameters for do_page_fault */
211         l.ori   r5,r0,0x300                // exception vector
212 1:
213         l.addi  r3,r1,0                    // pt_regs
214         /* r4 set be EXCEPTION_HANDLE */   // effective address of fault
215
216         /*
217          * __PHX__: TODO
218          *
219          * all this can be written much simpler. look at
220          * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
221          */
222 #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
223         l.lwz   r6,PT_PC(r3)                  // address of an offending insn
224         l.lwz   r6,0(r6)                   // instruction that caused pf
225
226         l.srli  r6,r6,26                   // check opcode for jump insn
227         l.sfeqi r6,0                       // l.j
228         l.bf    8f
229         l.sfeqi r6,1                       // l.jal
230         l.bf    8f
231         l.sfeqi r6,3                       // l.bnf
232         l.bf    8f
233         l.sfeqi r6,4                       // l.bf
234         l.bf    8f
235         l.sfeqi r6,0x11                    // l.jr
236         l.bf    8f
237         l.sfeqi r6,0x12                    // l.jalr
238         l.bf    8f
239
240         l.nop
241
242         l.j     9f
243         l.nop
244 8:
245
246         l.lwz   r6,PT_PC(r3)                  // address of an offending insn
247         l.addi  r6,r6,4
248         l.lwz   r6,0(r6)                   // instruction that caused pf
249         l.srli  r6,r6,26                   // get opcode
250 9:
251
252 #else
253
254         l.mfspr r6,r0,SPR_SR               // SR
255 //      l.lwz   r6,PT_SR(r3)               // ESR
256         l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
257         l.sfeqi r6,0x1                     // exception happened in delay slot
258         l.bnf   7f
259         l.lwz   r6,PT_PC(r3)               // address of an offending insn
260
261         l.addi  r6,r6,4                    // offending insn is in delay slot
262 7:
263         l.lwz   r6,0(r6)                   // instruction that caused pf
264         l.srli  r6,r6,26                   // check opcode for write access
265 #endif
266
267         l.sfgeui r6,0x34                   // check opcode for write access
268         l.bnf   1f
269         l.sfleui r6,0x37
270         l.bnf   1f
271         l.ori   r6,r0,0x1                  // write access
272         l.j     2f
273         l.nop
274 1:      l.ori   r6,r0,0x0                  // !write access
275 2:
276
277         /* call fault.c handler in or32/mm/fault.c */
278         l.jal   do_page_fault
279         l.nop
280         l.j     _ret_from_exception
281         l.nop
282
283 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
284 EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
285         l.and   r5,r5,r0
286         l.j     1f
287          l.nop
288
289 EXCEPTION_ENTRY(_insn_page_fault_handler)
290         /* set up parameters for do_page_fault */
291         l.ori   r5,r0,0x400                // exception vector
292 1:
293         l.addi  r3,r1,0                    // pt_regs
294         /* r4 set be EXCEPTION_HANDLE */   // effective address of fault
295         l.ori   r6,r0,0x0                  // !write access
296
297         /* call fault.c handler in or32/mm/fault.c */
298         l.jal   do_page_fault
299         l.nop
300         l.j     _ret_from_exception
301         l.nop
302
303
304 /* ---[ 0x500: Timer exception ]----------------------------------------- */
305
306 EXCEPTION_ENTRY(_timer_handler)
307         l.jal   timer_interrupt
308          l.addi r3,r1,0 /* pt_regs */
309
310         l.j    _ret_from_intr
311          l.nop
312
313 /* ---[ 0x600: Aligment exception ]-------------------------------------- */
314
315 EXCEPTION_ENTRY(_alignment_handler)
316         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
317         l.jal   do_unaligned_access
318          l.addi  r3,r1,0 /* pt_regs */
319
320         l.j     _ret_from_exception
321          l.nop
322
323 #if 0
324 EXCEPTION_ENTRY(_aligment_handler)
325 //        l.mfspr r2,r0,SPR_EEAR_BASE     /* Load the efective addres */
326         l.addi  r2,r4,0
327 //        l.mfspr r5,r0,SPR_EPCR_BASE     /* Load the insn address */
328         l.lwz   r5,PT_PC(r1)
329
330         l.lwz   r3,0(r5)                /* Load insn */
331         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
332
333         l.sfeqi r4,0x00                 /* Check if the load/store insn is in delay slot */
334         l.bf    jmp
335         l.sfeqi r4,0x01
336         l.bf    jmp
337         l.sfeqi r4,0x03
338         l.bf    jmp
339         l.sfeqi r4,0x04
340         l.bf    jmp
341         l.sfeqi r4,0x11
342         l.bf    jr
343         l.sfeqi r4,0x12
344         l.bf    jr
345         l.nop
346         l.j     1f
347         l.addi  r5,r5,4                 /* Increment PC to get return insn address */
348
349 jmp:
350         l.slli  r4,r3,6                 /* Get the signed extended jump length */
351         l.srai  r4,r4,4
352
353         l.lwz   r3,4(r5)                /* Load the real load/store insn */
354
355         l.add   r5,r5,r4                /* Calculate jump target address */
356
357         l.j     1f
358         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
359
360 jr:
361         l.slli  r4,r3,9                 /* Shift to get the reg nb */
362         l.andi  r4,r4,0x7c
363
364         l.lwz   r3,4(r5)                /* Load the real load/store insn */
365
366         l.add   r4,r4,r1                /* Load the jump register value from the stack */
367         l.lwz   r5,0(r4)
368
369         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
370
371
372 1:
373 //        l.mtspr r0,r5,SPR_EPCR_BASE
374         l.sw    PT_PC(r1),r5
375
376         l.sfeqi r4,0x26
377         l.bf    lhs
378         l.sfeqi r4,0x25
379         l.bf    lhz
380         l.sfeqi r4,0x22
381         l.bf    lws
382         l.sfeqi r4,0x21
383         l.bf    lwz
384         l.sfeqi r4,0x37
385         l.bf    sh
386         l.sfeqi r4,0x35
387         l.bf    sw
388         l.nop
389
390 1:      l.j     1b                      /* I don't know what to do */
391         l.nop
392
393 lhs:    l.lbs   r5,0(r2)
394         l.slli  r5,r5,8
395         l.lbz   r6,1(r2)
396         l.or    r5,r5,r6
397         l.srli  r4,r3,19
398         l.andi  r4,r4,0x7c
399         l.add   r4,r4,r1
400         l.j     align_end
401         l.sw    0(r4),r5
402
403 lhz:    l.lbz   r5,0(r2)
404         l.slli  r5,r5,8
405         l.lbz   r6,1(r2)
406         l.or    r5,r5,r6
407         l.srli  r4,r3,19
408         l.andi  r4,r4,0x7c
409         l.add   r4,r4,r1
410         l.j     align_end
411         l.sw    0(r4),r5
412
413 lws:    l.lbs   r5,0(r2)
414         l.slli  r5,r5,24
415         l.lbz   r6,1(r2)
416         l.slli  r6,r6,16
417         l.or    r5,r5,r6
418         l.lbz   r6,2(r2)
419         l.slli  r6,r6,8
420         l.or    r5,r5,r6
421         l.lbz   r6,3(r2)
422         l.or    r5,r5,r6
423         l.srli  r4,r3,19
424         l.andi  r4,r4,0x7c
425         l.add   r4,r4,r1
426         l.j     align_end
427         l.sw    0(r4),r5
428
429 lwz:    l.lbz   r5,0(r2)
430         l.slli  r5,r5,24
431         l.lbz   r6,1(r2)
432         l.slli  r6,r6,16
433         l.or    r5,r5,r6
434         l.lbz   r6,2(r2)
435         l.slli  r6,r6,8
436         l.or    r5,r5,r6
437         l.lbz   r6,3(r2)
438         l.or    r5,r5,r6
439         l.srli  r4,r3,19
440         l.andi  r4,r4,0x7c
441         l.add   r4,r4,r1
442         l.j     align_end
443         l.sw    0(r4),r5
444
445 sh:
446         l.srli  r4,r3,9
447         l.andi  r4,r4,0x7c
448         l.add   r4,r4,r1
449         l.lwz   r5,0(r4)
450         l.sb    1(r2),r5
451         l.srli  r5,r5,8
452         l.j     align_end
453         l.sb    0(r2),r5
454
455 sw:
456         l.srli  r4,r3,9
457         l.andi  r4,r4,0x7c
458         l.add   r4,r4,r1
459         l.lwz   r5,0(r4)
460         l.sb    3(r2),r5
461         l.srli  r5,r5,8
462         l.sb    2(r2),r5
463         l.srli  r5,r5,8
464         l.sb    1(r2),r5
465         l.srli  r5,r5,8
466         l.j     align_end
467         l.sb    0(r2),r5
468
469 align_end:
470         l.j    _ret_from_intr
471         l.nop
472 #endif
473
474 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
475
476 EXCEPTION_ENTRY(_illegal_instruction_handler)
477         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
478         l.jal   do_illegal_instruction
479          l.addi  r3,r1,0 /* pt_regs */
480
481         l.j     _ret_from_exception
482          l.nop
483
484 /* ---[ 0x800: External interrupt exception ]---------------------------- */
485
486 EXCEPTION_ENTRY(_external_irq_handler)
487 #ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
488         l.lwz   r4,PT_SR(r1)            // were interrupts enabled ?
489         l.andi  r4,r4,SPR_SR_IEE
490         l.sfeqi r4,0
491         l.bnf   1f                      // ext irq enabled, all ok.
492         l.nop
493
494         l.addi  r1,r1,-0x8
495         l.movhi r3,hi(42f)
496         l.ori   r3,r3,lo(42f)
497         l.sw    0x0(r1),r3
498         l.jal   printk
499         l.sw    0x4(r1),r4
500         l.addi  r1,r1,0x8
501
502         .section .rodata, "a"
503 42:
504                 .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
505                 .align 4
506         .previous
507
508         l.ori   r4,r4,SPR_SR_IEE        // fix the bug
509 //      l.sw    PT_SR(r1),r4
510 1:
511 #endif
512         l.addi  r3,r1,0
513         l.movhi r8,hi(do_IRQ)
514         l.ori   r8,r8,lo(do_IRQ)
515         l.jalr r8
516         l.nop
517         l.j    _ret_from_intr
518         l.nop
519
520 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
521
522
523 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
524
525
526 /* ---[ 0xb00: Range exception ]----------------------------------------- */
527
528 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
529
530 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
531
532 /*
533  * Syscalls are a special type of exception in that they are
534  * _explicitly_ invoked by userspace and can therefore be
535  * held to conform to the same ABI as normal functions with
536  * respect to whether registers are preserved across the call
537  * or not.
538  */
539
540 /* Upon syscall entry we just save the callee-saved registers
541  * and not the call-clobbered ones.
542  */
543
544 _string_syscall_return:
545         .string "syscall return %ld \n\r\0"
546         .align 4
547
548 ENTRY(_sys_call_handler)
549         /* syscalls run with interrupts enabled */
550         ENABLE_INTERRUPTS(r29)          // enable interrupts, r29 is temp
551
552         /* r1, EPCR, ESR a already saved */
553         l.sw    PT_GPR2(r1),r2
554         /* r3-r8 must be saved because syscall restart relies
555          * on us being able to restart the syscall args... technically
556          * they should be clobbered, otherwise
557          */
558         l.sw    PT_GPR3(r1),r3
559         /* r4 already saved */
560         /* r4 holds the EEAR address of the fault, load the original r4 */
561         l.lwz   r4,PT_GPR4(r1)
562         l.sw    PT_GPR5(r1),r5
563         l.sw    PT_GPR6(r1),r6
564         l.sw    PT_GPR7(r1),r7
565         l.sw    PT_GPR8(r1),r8
566         l.sw    PT_GPR9(r1),r9
567         /* r10 already saved */
568         l.sw    PT_GPR11(r1),r11
569         /* orig_gpr11 must be set for syscalls */
570         l.sw    PT_ORIG_GPR11(r1),r11
571         /* r12,r13 already saved */
572
573         /* r14-r28 (even) aren't touched by the syscall fast path below
574          * so we don't need to save them.  However, the functions that return
575          * to userspace via a call to switch() DO need to save these because
576          * switch() effectively clobbers them... saving these registers for
577          * such functions is handled in their syscall wrappers (see fork, vfork,
578          * and clone, below).
579
580         /* r30 is the only register we clobber in the fast path */
581         /* r30 already saved */
582 /*      l.sw    PT_GPR30(r1),r30 */
583
584 _syscall_check_trace_enter:
585         /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
586         l.lwz   r30,TI_FLAGS(r10)
587         l.andi  r30,r30,_TIF_SYSCALL_TRACE
588         l.sfne  r30,r0
589         l.bf    _syscall_trace_enter
590          l.nop
591
592 _syscall_check:
593         /* Ensure that the syscall number is reasonable */
594         l.sfgeui r11,__NR_syscalls
595         l.bf    _syscall_badsys
596          l.nop
597
598 _syscall_call:
599         l.movhi r29,hi(sys_call_table)
600         l.ori   r29,r29,lo(sys_call_table)
601         l.slli  r11,r11,2
602         l.add   r29,r29,r11
603         l.lwz   r29,0(r29)
604
605         l.jalr  r29
606          l.nop
607
608 _syscall_return:
609         /* All syscalls return here... just pay attention to ret_from_fork
610          * which does it in a round-about way.
611          */
612         l.sw    PT_GPR11(r1),r11           // save return value
613
614 #if 0
615 _syscall_debug:
616         l.movhi r3,hi(_string_syscall_return)
617         l.ori   r3,r3,lo(_string_syscall_return)
618         l.ori   r27,r0,1
619         l.sw    -4(r1),r27
620         l.sw    -8(r1),r11
621         l.addi  r1,r1,-8
622         l.movhi r27,hi(printk)
623         l.ori   r27,r27,lo(printk)
624         l.jalr  r27
625          l.nop
626         l.addi  r1,r1,8
627 #endif
628
629 _syscall_check_trace_leave:
630         /* r30 is a callee-saved register so this should still hold the
631          * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
632          * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
633          */
634         l.sfne  r30,r0
635         l.bf    _syscall_trace_leave
636          l.nop
637
638 /* This is where the exception-return code begins... interrupts need to be
639  * disabled the rest of the way here because we can't afford to miss any
640  * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
641
642 _syscall_check_work:
643         /* Here we need to disable interrupts */
644         DISABLE_INTERRUPTS(r27,r29)
645         l.lwz   r30,TI_FLAGS(r10)
646         l.andi  r30,r30,_TIF_WORK_MASK
647         l.sfne  r30,r0
648
649         l.bnf   _syscall_resume_userspace
650          l.nop
651
652         /* Work pending follows a different return path, so we need to
653          * make sure that all the call-saved registers get into pt_regs
654          * before branching...
655          */
656         l.sw    PT_GPR14(r1),r14
657         l.sw    PT_GPR16(r1),r16
658         l.sw    PT_GPR18(r1),r18
659         l.sw    PT_GPR20(r1),r20
660         l.sw    PT_GPR22(r1),r22
661         l.sw    PT_GPR24(r1),r24
662         l.sw    PT_GPR26(r1),r26
663         l.sw    PT_GPR28(r1),r28
664
665         /* _work_pending needs to be called with interrupts disabled */
666         l.j     _work_pending
667          l.nop
668
669 _syscall_resume_userspace:
670 //      ENABLE_INTERRUPTS(r29)
671
672
673 /* This is the hot path for returning to userspace from a syscall.  If there's
674  * work to be done and the branch to _work_pending was taken above, then the
675  * return to userspace will be done via the normal exception return path...
676  * that path restores _all_ registers and will overwrite the "clobbered"
677  * registers with whatever garbage is in pt_regs -- that's OK because those
678  * registers are clobbered anyway and because the extra work is insignificant
679  * in the context of the extra work that _work_pending is doing.
680
681 /* Once again, syscalls are special and only guarantee to preserve the
682  * same registers as a normal function call */
683
684 /* The assumption here is that the registers r14-r28 (even) are untouched and
685  * don't need to be restored... be sure that that's really the case!
686  */
687
688 /* This is still too much... we should only be restoring what we actually
689  * clobbered... we should even be using 'scratch' (odd) regs above so that
690  * we don't need to restore anything, hardly...
691  */
692
693         l.lwz   r2,PT_GPR2(r1)
694
695         /* Restore args */
696         /* r3-r8 are technically clobbered, but syscall restart needs these
697          * to be restored...
698          */
699         l.lwz   r3,PT_GPR3(r1)
700         l.lwz   r4,PT_GPR4(r1)
701         l.lwz   r5,PT_GPR5(r1)
702         l.lwz   r6,PT_GPR6(r1)
703         l.lwz   r7,PT_GPR7(r1)
704         l.lwz   r8,PT_GPR8(r1)
705
706         l.lwz   r9,PT_GPR9(r1)
707         l.lwz   r10,PT_GPR10(r1)
708         l.lwz   r11,PT_GPR11(r1)
709
710         /* r30 is the only register we clobber in the fast path */
711         l.lwz   r30,PT_GPR30(r1)
712
713         /* Here we use r13-r19 (odd) as scratch regs */
714         l.lwz   r13,PT_PC(r1)
715         l.lwz   r15,PT_SR(r1)
716         l.lwz   r1,PT_SP(r1)
717         /* Interrupts need to be disabled for setting EPCR and ESR
718          * so that another interrupt doesn't come in here and clobber
719          * them before we can use them for our l.rfe */
720         DISABLE_INTERRUPTS(r17,r19)
721         l.mtspr r0,r13,SPR_EPCR_BASE
722         l.mtspr r0,r15,SPR_ESR_BASE
723         l.rfe
724
725 /* End of hot path!
726  * Keep the below tracing and error handling out of the hot path...
727 */
728
729 _syscall_trace_enter:
730         /* Here we pass pt_regs to do_syscall_trace_enter.  Make sure
731          * that function is really getting all the info it needs as
732          * pt_regs isn't a complete set of userspace regs, just the
733          * ones relevant to the syscall...
734          *
735          * Note use of delay slot for setting argument.
736          */
737         l.jal   do_syscall_trace_enter
738          l.addi r3,r1,0
739
740         /* Restore arguments (not preserved across do_syscall_trace_enter)
741          * so that we can do the syscall for real and return to the syscall
742          * hot path.
743          */
744         l.lwz   r11,PT_GPR11(r1)
745         l.lwz   r3,PT_GPR3(r1)
746         l.lwz   r4,PT_GPR4(r1)
747         l.lwz   r5,PT_GPR5(r1)
748         l.lwz   r6,PT_GPR6(r1)
749         l.lwz   r7,PT_GPR7(r1)
750
751         l.j     _syscall_check
752          l.lwz  r8,PT_GPR8(r1)
753
754 _syscall_trace_leave:
755         l.jal   do_syscall_trace_leave
756          l.addi r3,r1,0
757
758         l.j     _syscall_check_work
759          l.nop
760
761 _syscall_badsys:
762         /* Here we effectively pretend to have executed an imaginary
763          * syscall that returns -ENOSYS and then return to the regular
764          * syscall hot path.
765          * Note that "return value" is set in the delay slot...
766          */
767         l.j     _syscall_return
768          l.addi r11,r0,-ENOSYS
769
770 /******* END SYSCALL HANDLING *******/
771
772 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
773
774 UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
775
776 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
777
778 EXCEPTION_ENTRY(_trap_handler)
779         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
780         l.jal   do_trap
781          l.addi  r3,r1,0 /* pt_regs */
782
783         l.j     _ret_from_exception
784          l.nop
785
786 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
787
788 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
789
790 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
791
792 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
793
794 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
795
796 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
797
798 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
799
800 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
801
802 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
803
804 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
805
806 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
807
808 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
809
810 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
811
812 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
813
814 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
815
816 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
817
818 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
819
820 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
821
822 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
823
824 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
825
826 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
827
828 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
829
830 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
831
832 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
833
834 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
835
836 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
837
838 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
839
840 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
841
842 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
843
844 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
845
846 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
847
848 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
849
850 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
851
852 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
853
854 /* ========================================================[ return ] === */
855
856 _work_pending:
857         /*
858          * if (current_thread_info->flags & _TIF_NEED_RESCHED)
859          *     schedule();
860          */
861         l.lwz   r5,TI_FLAGS(r10)
862         l.andi  r3,r5,_TIF_NEED_RESCHED
863         l.sfnei r3,0
864         l.bnf   _work_notifysig
865          l.nop
866         l.jal   schedule
867          l.nop
868         l.j     _resume_userspace
869          l.nop
870
871 /* Handle pending signals and notify-resume requests.
872  * do_notify_resume must be passed the latest pushed pt_regs, not
873  * necessarily the "userspace" ones.  Also, pt_regs->syscallno
874  * must be set so that the syscall restart functionality works.
875  */
876 _work_notifysig:
877         l.jal   do_notify_resume
878          l.ori  r3,r1,0           /* pt_regs */
879
880 _resume_userspace:
881         DISABLE_INTERRUPTS(r3,r4)
882         l.lwz   r3,TI_FLAGS(r10)
883         l.andi  r3,r3,_TIF_WORK_MASK
884         l.sfnei r3,0
885         l.bf    _work_pending
886          l.nop
887
888 _restore_all:
889         RESTORE_ALL
890         /* This returns to userspace code */
891
892
893 ENTRY(_ret_from_intr)
894 ENTRY(_ret_from_exception)
895         l.lwz   r4,PT_SR(r1)
896         l.andi  r3,r4,SPR_SR_SM
897         l.sfeqi r3,0
898         l.bnf   _restore_all
899          l.nop
900         l.j     _resume_userspace
901          l.nop
902
903 ENTRY(ret_from_fork)
904         l.jal   schedule_tail
905          l.nop
906
907         /* Check if we are a kernel thread */
908         l.sfeqi r20,0
909         l.bf    1f
910          l.nop
911
912         /* ...we are a kernel thread so invoke the requested callback */
913         l.jalr  r20
914          l.or   r3,r22,r0
915
916 1:
917         /* _syscall_returns expect r11 to contain return value */
918         l.lwz   r11,PT_GPR11(r1)
919
920         /* The syscall fast path return expects call-saved registers
921          * r12-r28 to be untouched, so we restore them here as they
922          * will have been effectively clobbered when arriving here
923          * via the call to switch()
924          */
925         l.lwz   r12,PT_GPR12(r1)
926         l.lwz   r14,PT_GPR14(r1)
927         l.lwz   r16,PT_GPR16(r1)
928         l.lwz   r18,PT_GPR18(r1)
929         l.lwz   r20,PT_GPR20(r1)
930         l.lwz   r22,PT_GPR22(r1)
931         l.lwz   r24,PT_GPR24(r1)
932         l.lwz   r26,PT_GPR26(r1)
933         l.lwz   r28,PT_GPR28(r1)
934
935         l.j     _syscall_return
936          l.nop
937
938 /* ========================================================[ switch ] === */
939
940 /*
941  * This routine switches between two different tasks.  The process
942  * state of one is saved on its kernel stack.  Then the state
943  * of the other is restored from its kernel stack.  The memory
944  * management hardware is updated to the second process's state.
945  * Finally, we can return to the second process, via the 'return'.
946  *
947  * Note: there are two ways to get to the "going out" portion
948  * of this code; either by coming in via the entry (_switch)
949  * or via "fork" which must set up an environment equivalent
950  * to the "_switch" path.  If you change this (or in particular, the
951  * SAVE_REGS macro), you'll have to change the fork code also.
952  */
953
954
955 /* _switch MUST never lay on page boundry, cause it runs from
956  * effective addresses and beeing interrupted by iTLB miss would kill it.
957  * dTLB miss seams to never accour in the bad place since data accesses
958  * are from task structures which are always page aligned.
959  *
960  * The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
961  * register, then load the previous register values and only at the end call
962  * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
963  * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
964  * holds for ESR)
965  *
966  * To avoid this problems it is sufficient to align _switch to
967  * some nice round number smaller than it's size...
968  */
969
970 /* ABI rules apply here... we either enter _switch via schedule() or via
971  * an imaginary call to which we shall return at return_from_fork.  Either
972  * way, we are a function call and only need to preserve the callee-saved
973  * registers when we return.  As such, we don't need to save the registers
974  * on the stack that we won't be returning as they were...
975  */
976
977         .align 0x400
978 ENTRY(_switch)
979         /* We don't store SR as _switch only gets called in a context where
980          * the SR will be the same going in and coming out... */
981
982         /* Set up new pt_regs struct for saving task state */
983         l.addi  r1,r1,-(INT_FRAME_SIZE)
984
985         /* No need to store r1/PT_SP as it goes into KSP below */
986         l.sw    PT_GPR2(r1),r2
987         l.sw    PT_GPR9(r1),r9
988         /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
989          * and expects r12 to be callee-saved... */
990         l.sw    PT_GPR12(r1),r12
991         l.sw    PT_GPR14(r1),r14
992         l.sw    PT_GPR16(r1),r16
993         l.sw    PT_GPR18(r1),r18
994         l.sw    PT_GPR20(r1),r20
995         l.sw    PT_GPR22(r1),r22
996         l.sw    PT_GPR24(r1),r24
997         l.sw    PT_GPR26(r1),r26
998         l.sw    PT_GPR28(r1),r28
999         l.sw    PT_GPR30(r1),r30
1000
1001         l.addi  r11,r10,0                       /* Save old 'current' to 'last' return value*/
1002
1003         /* We use thread_info->ksp for storing the address of the above
1004          * structure so that we can get back to it later... we don't want
1005          * to lose the value of thread_info->ksp, though, so store it as
1006          * pt_regs->sp so that we can easily restore it when we are made
1007          * live again...
1008          */
1009
1010         /* Save the old value of thread_info->ksp as pt_regs->sp */
1011         l.lwz   r29,TI_KSP(r10)
1012         l.sw    PT_SP(r1),r29
1013
1014         /* Swap kernel stack pointers */
1015         l.sw    TI_KSP(r10),r1                  /* Save old stack pointer */
1016         l.or    r10,r4,r0                       /* Set up new current_thread_info */
1017         l.lwz   r1,TI_KSP(r10)                  /* Load new stack pointer */
1018
1019         /* Restore the old value of thread_info->ksp */
1020         l.lwz   r29,PT_SP(r1)
1021         l.sw    TI_KSP(r10),r29
1022
1023         /* ...and restore the registers, except r11 because the return value
1024          * has already been set above.
1025          */
1026         l.lwz   r2,PT_GPR2(r1)
1027         l.lwz   r9,PT_GPR9(r1)
1028         /* No need to restore r10 */
1029         /* ...and do not restore r11 */
1030
1031         /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1032          * and expects r12 to be callee-saved... */
1033         l.lwz   r12,PT_GPR12(r1)
1034         l.lwz   r14,PT_GPR14(r1)
1035         l.lwz   r16,PT_GPR16(r1)
1036         l.lwz   r18,PT_GPR18(r1)
1037         l.lwz   r20,PT_GPR20(r1)
1038         l.lwz   r22,PT_GPR22(r1)
1039         l.lwz   r24,PT_GPR24(r1)
1040         l.lwz   r26,PT_GPR26(r1)
1041         l.lwz   r28,PT_GPR28(r1)
1042         l.lwz   r30,PT_GPR30(r1)
1043
1044         /* Unwind stack to pre-switch state */
1045         l.addi  r1,r1,(INT_FRAME_SIZE)
1046
1047         /* Return via the link-register back to where we 'came from', where
1048          * that may be either schedule(), ret_from_fork(), or
1049          * ret_from_kernel_thread().  If we are returning to a new thread,
1050          * we are expected to have set up the arg to schedule_tail already,
1051          * hence we do so here unconditionally:
1052          */
1053         l.lwz   r3,TI_TASK(r3)          /* Load 'prev' as schedule_tail arg */
1054         l.jr    r9
1055          l.nop
1056
1057 /* ==================================================================== */
1058
1059 /* These all use the delay slot for setting the argument register, so the
1060  * jump is always happening after the l.addi instruction.
1061  *
1062  * These are all just wrappers that don't touch the link-register r9, so the
1063  * return from the "real" syscall function will return back to the syscall
1064  * code that did the l.jal that brought us here.
1065  */
1066
1067 /* fork requires that we save all the callee-saved registers because they
1068  * are all effectively clobbered by the call to _switch.  Here we store
1069  * all the registers that aren't touched by the syscall fast path and thus
1070  * weren't saved there.
1071  */
1072
1073 _fork_save_extra_regs_and_call:
1074         l.sw    PT_GPR14(r1),r14
1075         l.sw    PT_GPR16(r1),r16
1076         l.sw    PT_GPR18(r1),r18
1077         l.sw    PT_GPR20(r1),r20
1078         l.sw    PT_GPR22(r1),r22
1079         l.sw    PT_GPR24(r1),r24
1080         l.sw    PT_GPR26(r1),r26
1081         l.jr    r29
1082          l.sw    PT_GPR28(r1),r28
1083
1084 ENTRY(__sys_clone)
1085         l.movhi r29,hi(sys_clone)
1086         l.ori   r29,r29,lo(sys_clone)
1087         l.j     _fork_save_extra_regs_and_call
1088          l.addi r7,r1,0
1089
1090 ENTRY(__sys_fork)
1091         l.movhi r29,hi(sys_fork)
1092         l.ori   r29,r29,lo(sys_fork)
1093         l.j     _fork_save_extra_regs_and_call
1094          l.addi r3,r1,0
1095
1096 ENTRY(sys_rt_sigreturn)
1097         l.j     _sys_rt_sigreturn
1098          l.addi r3,r1,0
1099
1100 /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1101  * The functions takes a variable number of parameters depending on which
1102  * particular flavour of atomic you want... parameter 1 is a flag identifying
1103  * the atomic in question.  Currently, this function implements the
1104  * following variants:
1105  *
1106  * XCHG:
1107  *  @flag: 1
1108  *  @ptr1:
1109  *  @ptr2:
1110  * Atomically exchange the values in pointers 1 and 2.
1111  *
1112  */
1113
1114 ENTRY(sys_or1k_atomic)
1115         /* FIXME: This ignores r3 and always does an XCHG */
1116         DISABLE_INTERRUPTS(r17,r19)
1117         l.lwz   r29,0(r4)
1118         l.lwz   r27,0(r5)
1119         l.sw    0(r4),r27
1120         l.sw    0(r5),r29
1121         ENABLE_INTERRUPTS(r17)
1122         l.jr    r9
1123          l.or   r11,r0,r0
1124
1125 /* ============================================================[ EOF ]=== */