sh: intc: Fix up initializers for gcc 4.5.
[~shefty/rdma-dev.git] / arch / sh / include / asm / io.h
1 #ifndef __ASM_SH_IO_H
2 #define __ASM_SH_IO_H
3 /*
4  * Convention:
5  *    read{b,w,l,q}/write{b,w,l,q} are for PCI,
6  *    while in{b,w,l}/out{b,w,l} are for ISA
7  *
8  * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
9  * and 'string' versions: ins{b,w,l}/outs{b,w,l}
10  *
11  * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
12  * automatically, there are also __raw versions, which do not.
13  *
14  * Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for
15  * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
16  * these have the same semantics as the __raw variants, and as such, all
17  * new code should be using the __raw versions.
18  *
19  * All ISA I/O routines are wrapped through the machine vector. If a
20  * board does not provide overrides, a generic set that are copied in
21  * from the default machine vector are used instead. These are largely
22  * for old compat code for I/O offseting to SuperIOs, all of which are
23  * better handled through the machvec ioport mapping routines these days.
24  */
25 #include <linux/errno.h>
26 #include <asm/cache.h>
27 #include <asm/system.h>
28 #include <asm/addrspace.h>
29 #include <asm/machvec.h>
30 #include <asm/pgtable.h>
31 #include <asm-generic/iomap.h>
32
33 #ifdef __KERNEL__
34 /*
35  * Depending on which platform we are running on, we need different
36  * I/O functions.
37  */
38 #define __IO_PREFIX     generic
39 #include <asm/io_generic.h>
40 #include <asm/io_trapped.h>
41
42 #ifdef CONFIG_HAS_IOPORT
43
44 #define inb(p)                  sh_mv.mv_inb((p))
45 #define inw(p)                  sh_mv.mv_inw((p))
46 #define inl(p)                  sh_mv.mv_inl((p))
47 #define outb(x,p)               sh_mv.mv_outb((x),(p))
48 #define outw(x,p)               sh_mv.mv_outw((x),(p))
49 #define outl(x,p)               sh_mv.mv_outl((x),(p))
50
51 #define inb_p(p)                sh_mv.mv_inb_p((p))
52 #define inw_p(p)                sh_mv.mv_inw_p((p))
53 #define inl_p(p)                sh_mv.mv_inl_p((p))
54 #define outb_p(x,p)             sh_mv.mv_outb_p((x),(p))
55 #define outw_p(x,p)             sh_mv.mv_outw_p((x),(p))
56 #define outl_p(x,p)             sh_mv.mv_outl_p((x),(p))
57
58 #define insb(p,b,c)             sh_mv.mv_insb((p), (b), (c))
59 #define insw(p,b,c)             sh_mv.mv_insw((p), (b), (c))
60 #define insl(p,b,c)             sh_mv.mv_insl((p), (b), (c))
61 #define outsb(p,b,c)            sh_mv.mv_outsb((p), (b), (c))
62 #define outsw(p,b,c)            sh_mv.mv_outsw((p), (b), (c))
63 #define outsl(p,b,c)            sh_mv.mv_outsl((p), (b), (c))
64
65 #endif
66
67 #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile u8  __force *)(a) = (v))
68 #define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
69 #define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
70 #define __raw_writeq(v,a)       (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
71
72 #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile u8  __force *)(a))
73 #define __raw_readw(a)          (__chk_io_ptr(a), *(volatile u16 __force *)(a))
74 #define __raw_readl(a)          (__chk_io_ptr(a), *(volatile u32 __force *)(a))
75 #define __raw_readq(a)          (__chk_io_ptr(a), *(volatile u64 __force *)(a))
76
77 #define readb(a)                ({ u8  r_ = __raw_readb(a); mb(); r_; })
78 #define readw(a)                ({ u16 r_ = __raw_readw(a); mb(); r_; })
79 #define readl(a)                ({ u32 r_ = __raw_readl(a); mb(); r_; })
80 #define readq(a)                ({ u64 r_ = __raw_readq(a); mb(); r_; })
81
82 #define writeb(v,a)             ({ __raw_writeb((v),(a)); mb(); })
83 #define writew(v,a)             ({ __raw_writew((v),(a)); mb(); })
84 #define writel(v,a)             ({ __raw_writel((v),(a)); mb(); })
85 #define writeq(v,a)             ({ __raw_writeq((v),(a)); mb(); })
86
87 /*
88  * Legacy SuperH on-chip I/O functions
89  *
90  * These are all deprecated, all new (and especially cross-platform) code
91  * should be using the __raw_xxx() routines directly.
92  */
93 static inline u8 __deprecated ctrl_inb(unsigned long addr)
94 {
95         return __raw_readb(addr);
96 }
97
98 static inline u16 __deprecated ctrl_inw(unsigned long addr)
99 {
100         return __raw_readw(addr);
101 }
102
103 static inline u32 __deprecated ctrl_inl(unsigned long addr)
104 {
105         return __raw_readl(addr);
106 }
107
108 static inline u64 __deprecated ctrl_inq(unsigned long addr)
109 {
110         return __raw_readq(addr);
111 }
112
113 static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
114 {
115         __raw_writeb(v, addr);
116 }
117
118 static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
119 {
120         __raw_writew(v, addr);
121 }
122
123 static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
124 {
125         __raw_writel(v, addr);
126 }
127
128 static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
129 {
130         __raw_writeq(v, addr);
131 }
132
133 extern unsigned long generic_io_base;
134
135 static inline void ctrl_delay(void)
136 {
137         __raw_readw(generic_io_base);
138 }
139
140 #define __BUILD_UNCACHED_IO(bwlq, type)                                 \
141 static inline type read##bwlq##_uncached(unsigned long addr)            \
142 {                                                                       \
143         type ret;                                                       \
144         jump_to_uncached();                                             \
145         ret = __raw_read##bwlq(addr);                                   \
146         back_to_cached();                                               \
147         return ret;                                                     \
148 }                                                                       \
149                                                                         \
150 static inline void write##bwlq##_uncached(type v, unsigned long addr)   \
151 {                                                                       \
152         jump_to_uncached();                                             \
153         __raw_write##bwlq(v, addr);                                     \
154         back_to_cached();                                               \
155 }
156
157 __BUILD_UNCACHED_IO(b, u8)
158 __BUILD_UNCACHED_IO(w, u16)
159 __BUILD_UNCACHED_IO(l, u32)
160 __BUILD_UNCACHED_IO(q, u64)
161
162 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
163                                                                         \
164 static inline void __raw_writes##bwlq(volatile void __iomem *mem,       \
165                                 const void *addr, unsigned int count)   \
166 {                                                                       \
167         const volatile type *__addr = addr;                             \
168                                                                         \
169         while (count--) {                                               \
170                 __raw_write##bwlq(*__addr, mem);                        \
171                 __addr++;                                               \
172         }                                                               \
173 }                                                                       \
174                                                                         \
175 static inline void __raw_reads##bwlq(volatile void __iomem *mem,        \
176                                void *addr, unsigned int count)          \
177 {                                                                       \
178         volatile type *__addr = addr;                                   \
179                                                                         \
180         while (count--) {                                               \
181                 *__addr = __raw_read##bwlq(mem);                        \
182                 __addr++;                                               \
183         }                                                               \
184 }
185
186 __BUILD_MEMORY_STRING(b, u8)
187 __BUILD_MEMORY_STRING(w, u16)
188
189 #ifdef CONFIG_SUPERH32
190 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
191 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
192 #else
193 __BUILD_MEMORY_STRING(l, u32)
194 #endif
195
196 __BUILD_MEMORY_STRING(q, u64)
197
198 #define writesb                 __raw_writesb
199 #define writesw                 __raw_writesw
200 #define writesl                 __raw_writesl
201
202 #define readsb                  __raw_readsb
203 #define readsw                  __raw_readsw
204 #define readsl                  __raw_readsl
205
206 #define readb_relaxed(a)        readb(a)
207 #define readw_relaxed(a)        readw(a)
208 #define readl_relaxed(a)        readl(a)
209 #define readq_relaxed(a)        readq(a)
210
211 #ifndef CONFIG_GENERIC_IOMAP
212 /* Simple MMIO */
213 #define ioread8(a)              __raw_readb(a)
214 #define ioread16(a)             __raw_readw(a)
215 #define ioread16be(a)           be16_to_cpu(__raw_readw((a)))
216 #define ioread32(a)             __raw_readl(a)
217 #define ioread32be(a)           be32_to_cpu(__raw_readl((a)))
218
219 #define iowrite8(v,a)           __raw_writeb((v),(a))
220 #define iowrite16(v,a)          __raw_writew((v),(a))
221 #define iowrite16be(v,a)        __raw_writew(cpu_to_be16((v)),(a))
222 #define iowrite32(v,a)          __raw_writel((v),(a))
223 #define iowrite32be(v,a)        __raw_writel(cpu_to_be32((v)),(a))
224
225 #define ioread8_rep(a, d, c)    __raw_readsb((a), (d), (c))
226 #define ioread16_rep(a, d, c)   __raw_readsw((a), (d), (c))
227 #define ioread32_rep(a, d, c)   __raw_readsl((a), (d), (c))
228
229 #define iowrite8_rep(a, s, c)   __raw_writesb((a), (s), (c))
230 #define iowrite16_rep(a, s, c)  __raw_writesw((a), (s), (c))
231 #define iowrite32_rep(a, s, c)  __raw_writesl((a), (s), (c))
232 #endif
233
234 #define mmio_insb(p,d,c)        __raw_readsb(p,d,c)
235 #define mmio_insw(p,d,c)        __raw_readsw(p,d,c)
236 #define mmio_insl(p,d,c)        __raw_readsl(p,d,c)
237
238 #define mmio_outsb(p,s,c)       __raw_writesb(p,s,c)
239 #define mmio_outsw(p,s,c)       __raw_writesw(p,s,c)
240 #define mmio_outsl(p,s,c)       __raw_writesl(p,s,c)
241
242 /* synco on SH-4A, otherwise a nop */
243 #define mmiowb()                wmb()
244
245 #define IO_SPACE_LIMIT 0xffffffff
246
247 #ifdef CONFIG_HAS_IOPORT
248
249 /*
250  * This function provides a method for the generic case where a
251  * board-specific ioport_map simply needs to return the port + some
252  * arbitrary port base.
253  *
254  * We use this at board setup time to implicitly set the port base, and
255  * as a result, we can use the generic ioport_map.
256  */
257 static inline void __set_io_port_base(unsigned long pbase)
258 {
259         generic_io_base = pbase;
260 }
261
262 #define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
263
264 #endif
265
266 /* We really want to try and get these to memcpy etc */
267 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
268 void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
269 void memset_io(volatile void __iomem *, int, unsigned long);
270
271 /* Quad-word real-mode I/O, don't ask.. */
272 unsigned long long peek_real_address_q(unsigned long long addr);
273 unsigned long long poke_real_address_q(unsigned long long addr,
274                                        unsigned long long val);
275
276 #if !defined(CONFIG_MMU)
277 #define virt_to_phys(address)   ((unsigned long)(address))
278 #define phys_to_virt(address)   ((void *)(address))
279 #else
280 #define virt_to_phys(address)   (__pa(address))
281 #define phys_to_virt(address)   (__va(address))
282 #endif
283
284 /*
285  * On 32-bit SH, we traditionally have the whole physical address space
286  * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
287  * not need to do anything but place the address in the proper segment.
288  * This is true for P1 and P2 addresses, as well as some P3 ones.
289  * However, most of the P3 addresses and newer cores using extended
290  * addressing need to map through page tables, so the ioremap()
291  * implementation becomes a bit more complicated.
292  *
293  * See arch/sh/mm/ioremap.c for additional notes on this.
294  *
295  * We cheat a bit and always return uncachable areas until we've fixed
296  * the drivers to handle caching properly.
297  *
298  * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
299  * doesn't exist, so everything must go through page tables.
300  */
301 #ifdef CONFIG_MMU
302 void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
303                                pgprot_t prot, void *caller);
304 void __iounmap(void __iomem *addr);
305
306 static inline void __iomem *
307 __ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
308 {
309         return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
310 }
311
312 static inline void __iomem *
313 __ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
314 {
315 #ifdef CONFIG_29BIT
316         phys_addr_t last_addr = offset + size - 1;
317
318         /*
319          * For P1 and P2 space this is trivial, as everything is already
320          * mapped. Uncached access for P1 addresses are done through P2.
321          * In the P3 case or for addresses outside of the 29-bit space,
322          * mapping must be done by the PMB or by using page tables.
323          */
324         if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
325                 if (unlikely(pgprot_val(prot) & _PAGE_CACHABLE))
326                         return (void __iomem *)P1SEGADDR(offset);
327
328                 return (void __iomem *)P2SEGADDR(offset);
329         }
330
331         /* P4 above the store queues are always mapped. */
332         if (unlikely(offset >= P3_ADDR_MAX))
333                 return (void __iomem *)P4SEGADDR(offset);
334 #endif
335
336         return NULL;
337 }
338
339 static inline void __iomem *
340 __ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
341 {
342         void __iomem *ret;
343
344         ret = __ioremap_trapped(offset, size);
345         if (ret)
346                 return ret;
347
348         ret = __ioremap_29bit(offset, size, prot);
349         if (ret)
350                 return ret;
351
352         return __ioremap(offset, size, prot);
353 }
354 #else
355 #define __ioremap(offset, size, prot)           ((void __iomem *)(offset))
356 #define __ioremap_mode(offset, size, prot)      ((void __iomem *)(offset))
357 #define __iounmap(addr)                         do { } while (0)
358 #endif /* CONFIG_MMU */
359
360 static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
361 {
362         return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
363 }
364
365 static inline void __iomem *
366 ioremap_cache(phys_addr_t offset, unsigned long size)
367 {
368         return __ioremap_mode(offset, size, PAGE_KERNEL);
369 }
370
371 #ifdef CONFIG_HAVE_IOREMAP_PROT
372 static inline void __iomem *
373 ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
374 {
375         return __ioremap_mode(offset, size, __pgprot(flags));
376 }
377 #endif
378
379 #ifdef CONFIG_IOREMAP_FIXED
380 extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
381 extern int iounmap_fixed(void __iomem *);
382 extern void ioremap_fixed_init(void);
383 #else
384 static inline void __iomem *
385 ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
386 {
387         BUG();
388         return NULL;
389 }
390
391 static inline void ioremap_fixed_init(void) { }
392 static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
393 #endif
394
395 #define ioremap_nocache ioremap
396 #define iounmap         __iounmap
397
398 #define maybebadio(port) \
399         printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
400                __func__, __LINE__, (port), (u32)__builtin_return_address(0))
401
402 /*
403  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
404  * access
405  */
406 #define xlate_dev_mem_ptr(p)    __va(p)
407
408 /*
409  * Convert a virtual cached pointer to an uncached pointer
410  */
411 #define xlate_dev_kmem_ptr(p)   p
412
413 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
414 int valid_phys_addr_range(unsigned long addr, size_t size);
415 int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
416
417 #endif /* __KERNEL__ */
418
419 #endif /* __ASM_SH_IO_H */