9ee4b3667ddfe9218b657d5f94fc9a01ca04925b
[~shefty/rdma-dev.git] / arch / sh / kernel / cpu / sh4a / clock-sh7724.c
1 /*
2  * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
3  *
4  * SH7724 clock framework support
5  *
6  * Copyright (C) 2009 Magnus Damm
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/clkdev.h>
26 #include <asm/clock.h>
27 #include <asm/hwblk.h>
28 #include <cpu/sh7724.h>
29
30 /* SH7724 registers */
31 #define FRQCRA          0xa4150000
32 #define FRQCRB          0xa4150004
33 #define VCLKCR          0xa4150048
34 #define FCLKACR         0xa4150008
35 #define FCLKBCR         0xa415000c
36 #define IRDACLKCR       0xa4150018
37 #define PLLCR           0xa4150024
38 #define SPUCLKCR        0xa415003c
39 #define FLLFRQ          0xa4150050
40 #define LSTATS          0xa4150060
41
42 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
43 static struct clk r_clk = {
44         .rate           = 32768,
45 };
46
47 /*
48  * Default rate for the root input clock, reset this with clk_set_rate()
49  * from the platform code.
50  */
51 static struct clk extal_clk = {
52         .rate           = 33333333,
53 };
54
55 /* The fll multiplies the 32khz r_clk, may be used instead of extal */
56 static unsigned long fll_recalc(struct clk *clk)
57 {
58         unsigned long mult = 0;
59         unsigned long div = 1;
60
61         if (__raw_readl(PLLCR) & 0x1000)
62                 mult = __raw_readl(FLLFRQ) & 0x3ff;
63
64         if (__raw_readl(FLLFRQ) & 0x4000)
65                 div = 2;
66
67         return (clk->parent->rate * mult) / div;
68 }
69
70 static struct clk_ops fll_clk_ops = {
71         .recalc         = fll_recalc,
72 };
73
74 static struct clk fll_clk = {
75         .ops            = &fll_clk_ops,
76         .parent         = &r_clk,
77         .flags          = CLK_ENABLE_ON_INIT,
78 };
79
80 static unsigned long pll_recalc(struct clk *clk)
81 {
82         unsigned long mult = 1;
83
84         if (__raw_readl(PLLCR) & 0x4000)
85                 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
86
87         return clk->parent->rate * mult;
88 }
89
90 static struct clk_ops pll_clk_ops = {
91         .recalc         = pll_recalc,
92 };
93
94 static struct clk pll_clk = {
95         .ops            = &pll_clk_ops,
96         .flags          = CLK_ENABLE_ON_INIT,
97 };
98
99 /* A fixed divide-by-3 block use by the div6 clocks */
100 static unsigned long div3_recalc(struct clk *clk)
101 {
102         return clk->parent->rate / 3;
103 }
104
105 static struct clk_ops div3_clk_ops = {
106         .recalc         = div3_recalc,
107 };
108
109 static struct clk div3_clk = {
110         .ops            = &div3_clk_ops,
111         .parent         = &pll_clk,
112 };
113
114 /* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */
115 struct clk sh7724_fsimcka_clk = {
116 };
117
118 struct clk sh7724_fsimckb_clk = {
119 };
120
121 struct clk sh7724_dv_clki = {
122 };
123
124 static struct clk *main_clks[] = {
125         &r_clk,
126         &extal_clk,
127         &fll_clk,
128         &pll_clk,
129         &div3_clk,
130         &sh7724_fsimcka_clk,
131         &sh7724_fsimckb_clk,
132         &sh7724_dv_clki,
133 };
134
135 static void div4_kick(struct clk *clk)
136 {
137         unsigned long value;
138
139         /* set KICK bit in FRQCRA to update hardware setting */
140         value = __raw_readl(FRQCRA);
141         value |= (1 << 31);
142         __raw_writel(value, FRQCRA);
143 }
144
145 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
146
147 static struct clk_div_mult_table div4_div_mult_table = {
148         .divisors = divisors,
149         .nr_divisors = ARRAY_SIZE(divisors),
150 };
151
152 static struct clk_div4_table div4_table = {
153         .div_mult_table = &div4_div_mult_table,
154         .kick = div4_kick,
155 };
156
157 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
158
159 #define DIV4(_reg, _bit, _mask, _flags) \
160   SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
161
162 struct clk div4_clks[DIV4_NR] = {
163         [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
164         [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
165         [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
166         [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
167         [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
168 };
169
170 enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR };
171
172 /* Indices are important - they are the actual src selecting values */
173 static struct clk *common_parent[] = {
174         [0] = &div3_clk,
175         [1] = NULL,
176 };
177
178 static struct clk *vclkcr_parent[8] = {
179         [0] = &div3_clk,
180         [2] = &sh7724_dv_clki,
181         [4] = &extal_clk,
182 };
183
184 static struct clk *fclkacr_parent[] = {
185         [0] = &div3_clk,
186         [1] = NULL,
187         [2] = &sh7724_fsimcka_clk,
188         [3] = NULL,
189 };
190
191 static struct clk *fclkbcr_parent[] = {
192         [0] = &div3_clk,
193         [1] = NULL,
194         [2] = &sh7724_fsimckb_clk,
195         [3] = NULL,
196 };
197
198 static struct clk div6_clks[DIV6_NR] = {
199         [DIV6_V] = SH_CLK_DIV6_EXT(VCLKCR, 0,
200                         vclkcr_parent, ARRAY_SIZE(vclkcr_parent), 12, 3),
201         [DIV6_I] = SH_CLK_DIV6_EXT(IRDACLKCR, 0,
202                         common_parent, ARRAY_SIZE(common_parent), 6, 1),
203         [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT,
204                         common_parent, ARRAY_SIZE(common_parent), 6, 1),
205         [DIV6_FA] = SH_CLK_DIV6_EXT(FCLKACR, 0,
206                                       fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
207         [DIV6_FB] = SH_CLK_DIV6_EXT(FCLKBCR, 0,
208                                       fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
209 };
210
211 static struct clk mstp_clks[HWBLK_NR] = {
212         SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
213         SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
214         SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
215         SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
216         SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
217         SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
218         SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
219         SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
220         SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
221         SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
222         SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
223         SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
224         SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
225         SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
226         SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
227         SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
228         SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
229         SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
230         SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
231         SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
232         SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
233         SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
234         SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
235         SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
236         SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
237
238         SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
239         SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
240         SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
241         SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
242
243         SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
244         SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
245         SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
246         SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
247         SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
248         SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
249         SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
250         SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
251         SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
252         SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
253         SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
254         SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
255         SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
256         SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
257         SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
258         SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
259         SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
260         SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
261         SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
262         SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
263         SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
264         SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
265         SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
266 };
267
268 static struct clk_lookup lookups[] = {
269         /* main clocks */
270         CLKDEV_CON_ID("rclk", &r_clk),
271         CLKDEV_CON_ID("extal", &extal_clk),
272         CLKDEV_CON_ID("fll_clk", &fll_clk),
273         CLKDEV_CON_ID("pll_clk", &pll_clk),
274         CLKDEV_CON_ID("div3_clk", &div3_clk),
275
276         /* DIV4 clocks */
277         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
278         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
279         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
280         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
281         CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
282
283         /* DIV6 clocks */
284         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
285         CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
286         CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
287         CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
288         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
289
290         /* MSTP clocks */
291         CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
292         CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
293         CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
294         CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
295         CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
296         CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
297         CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
298         CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
299         CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
300         CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
301         CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
302         CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
303
304         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
305         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
306         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]),
307         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
308
309         CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
310         CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
311         CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
312
313         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
314         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
315         CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
316         CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
317         CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
318         CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
319         CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
320         CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
321
322         CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
323         CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
324         CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
325         CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
326         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
327         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
328         CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
329         CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
330         CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
331         CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
332         CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
333         CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
334         CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
335         CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
336         CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
337         CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
338         CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
339         CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
340         CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
341         CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
342         CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
343         CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
344         CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
345         CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
346         CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
347         CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
348         CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
349         CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
350         CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
351 };
352
353 int __init arch_clk_init(void)
354 {
355         int k, ret = 0;
356
357         /* autodetect extal or fll configuration */
358         if (__raw_readl(PLLCR) & 0x1000)
359                 pll_clk.parent = &fll_clk;
360         else
361                 pll_clk.parent = &extal_clk;
362
363         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
364                 ret = clk_register(main_clks[k]);
365
366         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
367
368         if (!ret)
369                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
370
371         if (!ret)
372                 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
373
374         if (!ret)
375                 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
376
377         return ret;
378 }