Merge branch 'common/serial-rework' into sh-latest
[~shefty/rdma-dev.git] / arch / sh / kernel / cpu / sh4a / setup-sh7722.c
1 /*
2  * SH7722 Setup
3  *
4  *  Copyright (C) 2006 - 2008  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/init.h>
11 #include <linux/mm.h>
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
16 #include <linux/uio_driver.h>
17 #include <linux/usb/m66592.h>
18
19 #include <asm/clock.h>
20 #include <asm/mmzone.h>
21 #include <asm/siu.h>
22
23 #include <cpu/dma-register.h>
24 #include <cpu/sh7722.h>
25
26 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
27         {
28                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
29                 .addr           = 0xffe0000c,
30                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
31                 .mid_rid        = 0x21,
32         }, {
33                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
34                 .addr           = 0xffe00014,
35                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
36                 .mid_rid        = 0x22,
37         }, {
38                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
39                 .addr           = 0xffe1000c,
40                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
41                 .mid_rid        = 0x25,
42         }, {
43                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
44                 .addr           = 0xffe10014,
45                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
46                 .mid_rid        = 0x26,
47         }, {
48                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
49                 .addr           = 0xffe2000c,
50                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
51                 .mid_rid        = 0x29,
52         }, {
53                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
54                 .addr           = 0xffe20014,
55                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
56                 .mid_rid        = 0x2a,
57         }, {
58                 .slave_id       = SHDMA_SLAVE_SIUA_TX,
59                 .addr           = 0xa454c098,
60                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
61                 .mid_rid        = 0xb1,
62         }, {
63                 .slave_id       = SHDMA_SLAVE_SIUA_RX,
64                 .addr           = 0xa454c090,
65                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
66                 .mid_rid        = 0xb2,
67         }, {
68                 .slave_id       = SHDMA_SLAVE_SIUB_TX,
69                 .addr           = 0xa454c09c,
70                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
71                 .mid_rid        = 0xb5,
72         }, {
73                 .slave_id       = SHDMA_SLAVE_SIUB_RX,
74                 .addr           = 0xa454c094,
75                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
76                 .mid_rid        = 0xb6,
77         }, {
78                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
79                 .addr           = 0x04ce0030,
80                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
81                 .mid_rid        = 0xc1,
82         }, {
83                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
84                 .addr           = 0x04ce0030,
85                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
86                 .mid_rid        = 0xc2,
87         },
88 };
89
90 static const struct sh_dmae_channel sh7722_dmae_channels[] = {
91         {
92                 .offset = 0,
93                 .dmars = 0,
94                 .dmars_bit = 0,
95         }, {
96                 .offset = 0x10,
97                 .dmars = 0,
98                 .dmars_bit = 8,
99         }, {
100                 .offset = 0x20,
101                 .dmars = 4,
102                 .dmars_bit = 0,
103         }, {
104                 .offset = 0x30,
105                 .dmars = 4,
106                 .dmars_bit = 8,
107         }, {
108                 .offset = 0x50,
109                 .dmars = 8,
110                 .dmars_bit = 0,
111         }, {
112                 .offset = 0x60,
113                 .dmars = 8,
114                 .dmars_bit = 8,
115         }
116 };
117
118 static const unsigned int ts_shift[] = TS_SHIFT;
119
120 static struct sh_dmae_pdata dma_platform_data = {
121         .slave          = sh7722_dmae_slaves,
122         .slave_num      = ARRAY_SIZE(sh7722_dmae_slaves),
123         .channel        = sh7722_dmae_channels,
124         .channel_num    = ARRAY_SIZE(sh7722_dmae_channels),
125         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
126         .ts_low_mask    = CHCR_TS_LOW_MASK,
127         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
128         .ts_high_mask   = CHCR_TS_HIGH_MASK,
129         .ts_shift       = ts_shift,
130         .ts_shift_num   = ARRAY_SIZE(ts_shift),
131         .dmaor_init     = DMAOR_INIT,
132 };
133
134 static struct resource sh7722_dmae_resources[] = {
135         [0] = {
136                 /* Channel registers and DMAOR */
137                 .start  = 0xfe008020,
138                 .end    = 0xfe00808f,
139                 .flags  = IORESOURCE_MEM,
140         },
141         [1] = {
142                 /* DMARSx */
143                 .start  = 0xfe009000,
144                 .end    = 0xfe00900b,
145                 .flags  = IORESOURCE_MEM,
146         },
147         {
148                 /* DMA error IRQ */
149                 .start  = 78,
150                 .end    = 78,
151                 .flags  = IORESOURCE_IRQ,
152         },
153         {
154                 /* IRQ for channels 0-3 */
155                 .start  = 48,
156                 .end    = 51,
157                 .flags  = IORESOURCE_IRQ,
158         },
159         {
160                 /* IRQ for channels 4-5 */
161                 .start  = 76,
162                 .end    = 77,
163                 .flags  = IORESOURCE_IRQ,
164         },
165 };
166
167 struct platform_device dma_device = {
168         .name           = "sh-dma-engine",
169         .id             = -1,
170         .resource       = sh7722_dmae_resources,
171         .num_resources  = ARRAY_SIZE(sh7722_dmae_resources),
172         .dev            = {
173                 .platform_data  = &dma_platform_data,
174         },
175         .archdata = {
176                 .hwblk_id = HWBLK_DMAC,
177         },
178 };
179
180 /* Serial */
181 static struct plat_sci_port scif0_platform_data = {
182         .mapbase        = 0xffe00000,
183         .flags          = UPF_BOOT_AUTOCONF,
184         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185         .scbrr_algo_id  = SCBRR_ALGO_2,
186         .type           = PORT_SCIF,
187         .irqs           = { 80, 80, 80, 80 },
188 };
189
190 static struct platform_device scif0_device = {
191         .name           = "sh-sci",
192         .id             = 0,
193         .dev            = {
194                 .platform_data  = &scif0_platform_data,
195         },
196 };
197
198 static struct plat_sci_port scif1_platform_data = {
199         .mapbase        = 0xffe10000,
200         .flags          = UPF_BOOT_AUTOCONF,
201         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202         .scbrr_algo_id  = SCBRR_ALGO_2,
203         .type           = PORT_SCIF,
204         .irqs           = { 81, 81, 81, 81 },
205 };
206
207 static struct platform_device scif1_device = {
208         .name           = "sh-sci",
209         .id             = 1,
210         .dev            = {
211                 .platform_data  = &scif1_platform_data,
212         },
213 };
214
215 static struct plat_sci_port scif2_platform_data = {
216         .mapbase        = 0xffe20000,
217         .flags          = UPF_BOOT_AUTOCONF,
218         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
219         .scbrr_algo_id  = SCBRR_ALGO_2,
220         .type           = PORT_SCIF,
221         .irqs           = { 82, 82, 82, 82 },
222 };
223
224 static struct platform_device scif2_device = {
225         .name           = "sh-sci",
226         .id             = 2,
227         .dev            = {
228                 .platform_data  = &scif2_platform_data,
229         },
230 };
231
232 static struct resource rtc_resources[] = {
233         [0] = {
234                 .start  = 0xa465fec0,
235                 .end    = 0xa465fec0 + 0x58 - 1,
236                 .flags  = IORESOURCE_IO,
237         },
238         [1] = {
239                 /* Period IRQ */
240                 .start  = 45,
241                 .flags  = IORESOURCE_IRQ,
242         },
243         [2] = {
244                 /* Carry IRQ */
245                 .start  = 46,
246                 .flags  = IORESOURCE_IRQ,
247         },
248         [3] = {
249                 /* Alarm IRQ */
250                 .start  = 44,
251                 .flags  = IORESOURCE_IRQ,
252         },
253 };
254
255 static struct platform_device rtc_device = {
256         .name           = "sh-rtc",
257         .id             = -1,
258         .num_resources  = ARRAY_SIZE(rtc_resources),
259         .resource       = rtc_resources,
260         .archdata = {
261                 .hwblk_id = HWBLK_RTC,
262         },
263 };
264
265 static struct m66592_platdata usbf_platdata = {
266         .on_chip = 1,
267 };
268
269 static struct resource usbf_resources[] = {
270         [0] = {
271                 .name   = "USBF",
272                 .start  = 0x04480000,
273                 .end    = 0x044800FF,
274                 .flags  = IORESOURCE_MEM,
275         },
276         [1] = {
277                 .start  = 65,
278                 .end    = 65,
279                 .flags  = IORESOURCE_IRQ,
280         },
281 };
282
283 static struct platform_device usbf_device = {
284         .name           = "m66592_udc",
285         .id             = 0, /* "usbf0" clock */
286         .dev = {
287                 .dma_mask               = NULL,
288                 .coherent_dma_mask      = 0xffffffff,
289                 .platform_data          = &usbf_platdata,
290         },
291         .num_resources  = ARRAY_SIZE(usbf_resources),
292         .resource       = usbf_resources,
293         .archdata = {
294                 .hwblk_id = HWBLK_USBF,
295         },
296 };
297
298 static struct resource iic_resources[] = {
299         [0] = {
300                 .name   = "IIC",
301                 .start  = 0x04470000,
302                 .end    = 0x04470017,
303                 .flags  = IORESOURCE_MEM,
304         },
305         [1] = {
306                 .start  = 96,
307                 .end    = 99,
308                 .flags  = IORESOURCE_IRQ,
309        },
310 };
311
312 static struct platform_device iic_device = {
313         .name           = "i2c-sh_mobile",
314         .id             = 0, /* "i2c0" clock */
315         .num_resources  = ARRAY_SIZE(iic_resources),
316         .resource       = iic_resources,
317         .archdata = {
318                 .hwblk_id = HWBLK_IIC,
319         },
320 };
321
322 static struct uio_info vpu_platform_data = {
323         .name = "VPU4",
324         .version = "0",
325         .irq = 60,
326 };
327
328 static struct resource vpu_resources[] = {
329         [0] = {
330                 .name   = "VPU",
331                 .start  = 0xfe900000,
332                 .end    = 0xfe9022eb,
333                 .flags  = IORESOURCE_MEM,
334         },
335         [1] = {
336                 /* place holder for contiguous memory */
337         },
338 };
339
340 static struct platform_device vpu_device = {
341         .name           = "uio_pdrv_genirq",
342         .id             = 0,
343         .dev = {
344                 .platform_data  = &vpu_platform_data,
345         },
346         .resource       = vpu_resources,
347         .num_resources  = ARRAY_SIZE(vpu_resources),
348         .archdata = {
349                 .hwblk_id = HWBLK_VPU,
350         },
351 };
352
353 static struct uio_info veu_platform_data = {
354         .name = "VEU",
355         .version = "0",
356         .irq = 54,
357 };
358
359 static struct resource veu_resources[] = {
360         [0] = {
361                 .name   = "VEU",
362                 .start  = 0xfe920000,
363                 .end    = 0xfe9200b7,
364                 .flags  = IORESOURCE_MEM,
365         },
366         [1] = {
367                 /* place holder for contiguous memory */
368         },
369 };
370
371 static struct platform_device veu_device = {
372         .name           = "uio_pdrv_genirq",
373         .id             = 1,
374         .dev = {
375                 .platform_data  = &veu_platform_data,
376         },
377         .resource       = veu_resources,
378         .num_resources  = ARRAY_SIZE(veu_resources),
379         .archdata = {
380                 .hwblk_id = HWBLK_VEU,
381         },
382 };
383
384 static struct uio_info jpu_platform_data = {
385         .name = "JPU",
386         .version = "0",
387         .irq = 27,
388 };
389
390 static struct resource jpu_resources[] = {
391         [0] = {
392                 .name   = "JPU",
393                 .start  = 0xfea00000,
394                 .end    = 0xfea102d3,
395                 .flags  = IORESOURCE_MEM,
396         },
397         [1] = {
398                 /* place holder for contiguous memory */
399         },
400 };
401
402 static struct platform_device jpu_device = {
403         .name           = "uio_pdrv_genirq",
404         .id             = 2,
405         .dev = {
406                 .platform_data  = &jpu_platform_data,
407         },
408         .resource       = jpu_resources,
409         .num_resources  = ARRAY_SIZE(jpu_resources),
410         .archdata = {
411                 .hwblk_id = HWBLK_JPU,
412         },
413 };
414
415 static struct sh_timer_config cmt_platform_data = {
416         .channel_offset = 0x60,
417         .timer_bit = 5,
418         .clockevent_rating = 125,
419         .clocksource_rating = 125,
420 };
421
422 static struct resource cmt_resources[] = {
423         [0] = {
424                 .start  = 0x044a0060,
425                 .end    = 0x044a006b,
426                 .flags  = IORESOURCE_MEM,
427         },
428         [1] = {
429                 .start  = 104,
430                 .flags  = IORESOURCE_IRQ,
431         },
432 };
433
434 static struct platform_device cmt_device = {
435         .name           = "sh_cmt",
436         .id             = 0,
437         .dev = {
438                 .platform_data  = &cmt_platform_data,
439         },
440         .resource       = cmt_resources,
441         .num_resources  = ARRAY_SIZE(cmt_resources),
442         .archdata = {
443                 .hwblk_id = HWBLK_CMT,
444         },
445 };
446
447 static struct sh_timer_config tmu0_platform_data = {
448         .channel_offset = 0x04,
449         .timer_bit = 0,
450         .clockevent_rating = 200,
451 };
452
453 static struct resource tmu0_resources[] = {
454         [0] = {
455                 .start  = 0xffd80008,
456                 .end    = 0xffd80013,
457                 .flags  = IORESOURCE_MEM,
458         },
459         [1] = {
460                 .start  = 16,
461                 .flags  = IORESOURCE_IRQ,
462         },
463 };
464
465 static struct platform_device tmu0_device = {
466         .name           = "sh_tmu",
467         .id             = 0,
468         .dev = {
469                 .platform_data  = &tmu0_platform_data,
470         },
471         .resource       = tmu0_resources,
472         .num_resources  = ARRAY_SIZE(tmu0_resources),
473         .archdata = {
474                 .hwblk_id = HWBLK_TMU,
475         },
476 };
477
478 static struct sh_timer_config tmu1_platform_data = {
479         .channel_offset = 0x10,
480         .timer_bit = 1,
481         .clocksource_rating = 200,
482 };
483
484 static struct resource tmu1_resources[] = {
485         [0] = {
486                 .start  = 0xffd80014,
487                 .end    = 0xffd8001f,
488                 .flags  = IORESOURCE_MEM,
489         },
490         [1] = {
491                 .start  = 17,
492                 .flags  = IORESOURCE_IRQ,
493         },
494 };
495
496 static struct platform_device tmu1_device = {
497         .name           = "sh_tmu",
498         .id             = 1,
499         .dev = {
500                 .platform_data  = &tmu1_platform_data,
501         },
502         .resource       = tmu1_resources,
503         .num_resources  = ARRAY_SIZE(tmu1_resources),
504         .archdata = {
505                 .hwblk_id = HWBLK_TMU,
506         },
507 };
508
509 static struct sh_timer_config tmu2_platform_data = {
510         .channel_offset = 0x1c,
511         .timer_bit = 2,
512 };
513
514 static struct resource tmu2_resources[] = {
515         [0] = {
516                 .start  = 0xffd80020,
517                 .end    = 0xffd8002b,
518                 .flags  = IORESOURCE_MEM,
519         },
520         [1] = {
521                 .start  = 18,
522                 .flags  = IORESOURCE_IRQ,
523         },
524 };
525
526 static struct platform_device tmu2_device = {
527         .name           = "sh_tmu",
528         .id             = 2,
529         .dev = {
530                 .platform_data  = &tmu2_platform_data,
531         },
532         .resource       = tmu2_resources,
533         .num_resources  = ARRAY_SIZE(tmu2_resources),
534         .archdata = {
535                 .hwblk_id = HWBLK_TMU,
536         },
537 };
538
539 static struct siu_platform siu_platform_data = {
540         .dma_dev        = &dma_device.dev,
541         .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
542         .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
543         .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
544         .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
545 };
546
547 static struct resource siu_resources[] = {
548         [0] = {
549                 .start  = 0xa4540000,
550                 .end    = 0xa454c10f,
551                 .flags  = IORESOURCE_MEM,
552         },
553         [1] = {
554                 .start  = 108,
555                 .flags  = IORESOURCE_IRQ,
556         },
557 };
558
559 static struct platform_device siu_device = {
560         .name           = "siu-pcm-audio",
561         .id             = -1,
562         .dev = {
563                 .platform_data  = &siu_platform_data,
564         },
565         .resource       = siu_resources,
566         .num_resources  = ARRAY_SIZE(siu_resources),
567         .archdata = {
568                 .hwblk_id = HWBLK_SIU,
569         },
570 };
571
572 static struct platform_device *sh7722_devices[] __initdata = {
573         &scif0_device,
574         &scif1_device,
575         &scif2_device,
576         &cmt_device,
577         &tmu0_device,
578         &tmu1_device,
579         &tmu2_device,
580         &rtc_device,
581         &usbf_device,
582         &iic_device,
583         &vpu_device,
584         &veu_device,
585         &jpu_device,
586         &siu_device,
587         &dma_device,
588 };
589
590 static int __init sh7722_devices_setup(void)
591 {
592         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
593         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
594         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
595
596         return platform_add_devices(sh7722_devices,
597                                     ARRAY_SIZE(sh7722_devices));
598 }
599 arch_initcall(sh7722_devices_setup);
600
601 static struct platform_device *sh7722_early_devices[] __initdata = {
602         &scif0_device,
603         &scif1_device,
604         &scif2_device,
605         &cmt_device,
606         &tmu0_device,
607         &tmu1_device,
608         &tmu2_device,
609 };
610
611 void __init plat_early_device_setup(void)
612 {
613         early_platform_add_devices(sh7722_early_devices,
614                                    ARRAY_SIZE(sh7722_early_devices));
615 }
616
617 enum {
618         UNUSED=0,
619         ENABLED,
620         DISABLED,
621
622         /* interrupt sources */
623         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
624         HUDI,
625         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
626         RTC_ATI, RTC_PRI, RTC_CUI,
627         DMAC0, DMAC1, DMAC2, DMAC3,
628         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
629         VPU, TPU,
630         USB_USBI0, USB_USBI1,
631         DMAC4, DMAC5, DMAC_DADERR,
632         KEYSC,
633         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
634         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
635         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
636         CMT, TSIF, SIU, TWODG,
637         TMU0, TMU1, TMU2,
638         IRDA, JPU, LCDC,
639
640         /* interrupt groups */
641         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
642 };
643
644 static struct intc_vect vectors[] __initdata = {
645         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
646         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
647         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
648         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
649         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
650         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
651         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
652         INTC_VECT(RTC_CUI, 0x7c0),
653         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
654         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
655         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
656         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
657         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
658         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
659         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
660         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
661         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
662         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
663         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
664         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
665         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
666         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
667         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
668         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
669         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
670         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
671         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
672         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
673         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
674         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
675 };
676
677 static struct intc_group groups[] __initdata = {
678         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
679         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
680         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
681         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
682         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
683         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
684         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
685                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
686         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
687 };
688
689 static struct intc_mask_reg mask_registers[] __initdata = {
690         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
691           { } },
692         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
693           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
694         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
695           { 0, 0, 0, VPU, } },
696         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
697           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
698         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
699           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
700         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
701           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
702         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
703           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
704         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
705           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
706             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
707         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
708           { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
709         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
710           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
711         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
712           { } },
713         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
714           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
715         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
716           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
717 };
718
719 static struct intc_prio_reg prio_registers[] __initdata = {
720         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
721         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
722         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
723         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
724         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
725         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
726         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
727         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
728         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
729         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
730         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
731         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
732         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
733           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
734 };
735
736 static struct intc_sense_reg sense_registers[] __initdata = {
737         { 0xa414001c, 16, 2, /* ICR1 */
738           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
739 };
740
741 static struct intc_mask_reg ack_registers[] __initdata = {
742         { 0xa4140024, 0, 8, /* INTREQ00 */
743           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
744 };
745
746 static struct intc_desc intc_desc __initdata = {
747         .name = "sh7722",
748         .force_enable = ENABLED,
749         .force_disable = DISABLED,
750         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
751                            prio_registers, sense_registers, ack_registers),
752 };
753
754 void __init plat_irq_setup(void)
755 {
756         register_intc_controller(&intc_desc);
757 }
758
759 void __init plat_mem_setup(void)
760 {
761         /* Register the URAM space as Node 1 */
762         setup_bootmem_node(1, 0x055f0000, 0x05610000);
763 }