Merge branch 'common/serial-rework' into sh-latest
[~shefty/rdma-dev.git] / arch / sh / kernel / cpu / sh4a / setup-sh7723.c
1 /*
2  * SH7723 Setup
3  *
4  *  Copyright (C) 2008  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/mm.h>
14 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <linux/usb/r8a66597.h>
17 #include <linux/sh_timer.h>
18 #include <linux/io.h>
19 #include <asm/clock.h>
20 #include <asm/mmzone.h>
21 #include <cpu/sh7723.h>
22
23 /* Serial */
24 static struct plat_sci_port scif0_platform_data = {
25         .mapbase        = 0xffe00000,
26         .flags          = UPF_BOOT_AUTOCONF,
27         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28         .scbrr_algo_id  = SCBRR_ALGO_2,
29         .type           = PORT_SCIF,
30         .irqs           = { 80, 80, 80, 80 },
31 };
32
33 static struct platform_device scif0_device = {
34         .name           = "sh-sci",
35         .id             = 0,
36         .dev            = {
37                 .platform_data  = &scif0_platform_data,
38         },
39 };
40
41 static struct plat_sci_port scif1_platform_data = {
42         .mapbase        = 0xffe10000,
43         .flags          = UPF_BOOT_AUTOCONF,
44         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
45         .scbrr_algo_id  = SCBRR_ALGO_2,
46         .type           = PORT_SCIF,
47         .irqs           = { 81, 81, 81, 81 },
48 };
49
50 static struct platform_device scif1_device = {
51         .name           = "sh-sci",
52         .id             = 1,
53         .dev            = {
54                 .platform_data  = &scif1_platform_data,
55         },
56 };
57
58 static struct plat_sci_port scif2_platform_data = {
59         .mapbase        = 0xffe20000,
60         .flags          = UPF_BOOT_AUTOCONF,
61         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
62         .scbrr_algo_id  = SCBRR_ALGO_2,
63         .type           = PORT_SCIF,
64         .irqs           = { 82, 82, 82, 82 },
65 };
66
67 static struct platform_device scif2_device = {
68         .name           = "sh-sci",
69         .id             = 2,
70         .dev            = {
71                 .platform_data  = &scif2_platform_data,
72         },
73 };
74
75 static struct plat_sci_port scif3_platform_data = {
76         .mapbase        = 0xa4e30000,
77         .flags          = UPF_BOOT_AUTOCONF,
78         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
79         .scbrr_algo_id  = SCBRR_ALGO_3,
80         .type           = PORT_SCIFA,
81         .irqs           = { 56, 56, 56, 56 },
82 };
83
84 static struct platform_device scif3_device = {
85         .name           = "sh-sci",
86         .id             = 3,
87         .dev            = {
88                 .platform_data  = &scif3_platform_data,
89         },
90 };
91
92 static struct plat_sci_port scif4_platform_data = {
93         .mapbase        = 0xa4e40000,
94         .flags          = UPF_BOOT_AUTOCONF,
95         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
96         .scbrr_algo_id  = SCBRR_ALGO_3,
97         .type           = PORT_SCIFA,
98         .irqs           = { 88, 88, 88, 88 },
99 };
100
101 static struct platform_device scif4_device = {
102         .name           = "sh-sci",
103         .id             = 4,
104         .dev            = {
105                 .platform_data  = &scif4_platform_data,
106         },
107 };
108
109 static struct plat_sci_port scif5_platform_data = {
110         .mapbase        = 0xa4e50000,
111         .flags          = UPF_BOOT_AUTOCONF,
112         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
113         .scbrr_algo_id  = SCBRR_ALGO_3,
114         .type           = PORT_SCIFA,
115         .irqs           = { 109, 109, 109, 109 },
116 };
117
118 static struct platform_device scif5_device = {
119         .name           = "sh-sci",
120         .id             = 5,
121         .dev            = {
122                 .platform_data  = &scif5_platform_data,
123         },
124 };
125
126 static struct uio_info vpu_platform_data = {
127         .name = "VPU5",
128         .version = "0",
129         .irq = 60,
130 };
131
132 static struct resource vpu_resources[] = {
133         [0] = {
134                 .name   = "VPU",
135                 .start  = 0xfe900000,
136                 .end    = 0xfe902807,
137                 .flags  = IORESOURCE_MEM,
138         },
139         [1] = {
140                 /* place holder for contiguous memory */
141         },
142 };
143
144 static struct platform_device vpu_device = {
145         .name           = "uio_pdrv_genirq",
146         .id             = 0,
147         .dev = {
148                 .platform_data  = &vpu_platform_data,
149         },
150         .resource       = vpu_resources,
151         .num_resources  = ARRAY_SIZE(vpu_resources),
152         .archdata = {
153                 .hwblk_id = HWBLK_VPU,
154         },
155 };
156
157 static struct uio_info veu0_platform_data = {
158         .name = "VEU2H",
159         .version = "0",
160         .irq = 54,
161 };
162
163 static struct resource veu0_resources[] = {
164         [0] = {
165                 .name   = "VEU2H0",
166                 .start  = 0xfe920000,
167                 .end    = 0xfe92027b,
168                 .flags  = IORESOURCE_MEM,
169         },
170         [1] = {
171                 /* place holder for contiguous memory */
172         },
173 };
174
175 static struct platform_device veu0_device = {
176         .name           = "uio_pdrv_genirq",
177         .id             = 1,
178         .dev = {
179                 .platform_data  = &veu0_platform_data,
180         },
181         .resource       = veu0_resources,
182         .num_resources  = ARRAY_SIZE(veu0_resources),
183         .archdata = {
184                 .hwblk_id = HWBLK_VEU2H0,
185         },
186 };
187
188 static struct uio_info veu1_platform_data = {
189         .name = "VEU2H",
190         .version = "0",
191         .irq = 27,
192 };
193
194 static struct resource veu1_resources[] = {
195         [0] = {
196                 .name   = "VEU2H1",
197                 .start  = 0xfe924000,
198                 .end    = 0xfe92427b,
199                 .flags  = IORESOURCE_MEM,
200         },
201         [1] = {
202                 /* place holder for contiguous memory */
203         },
204 };
205
206 static struct platform_device veu1_device = {
207         .name           = "uio_pdrv_genirq",
208         .id             = 2,
209         .dev = {
210                 .platform_data  = &veu1_platform_data,
211         },
212         .resource       = veu1_resources,
213         .num_resources  = ARRAY_SIZE(veu1_resources),
214         .archdata = {
215                 .hwblk_id = HWBLK_VEU2H1,
216         },
217 };
218
219 static struct sh_timer_config cmt_platform_data = {
220         .channel_offset = 0x60,
221         .timer_bit = 5,
222         .clockevent_rating = 125,
223         .clocksource_rating = 125,
224 };
225
226 static struct resource cmt_resources[] = {
227         [0] = {
228                 .start  = 0x044a0060,
229                 .end    = 0x044a006b,
230                 .flags  = IORESOURCE_MEM,
231         },
232         [1] = {
233                 .start  = 104,
234                 .flags  = IORESOURCE_IRQ,
235         },
236 };
237
238 static struct platform_device cmt_device = {
239         .name           = "sh_cmt",
240         .id             = 0,
241         .dev = {
242                 .platform_data  = &cmt_platform_data,
243         },
244         .resource       = cmt_resources,
245         .num_resources  = ARRAY_SIZE(cmt_resources),
246         .archdata = {
247                 .hwblk_id = HWBLK_CMT,
248         },
249 };
250
251 static struct sh_timer_config tmu0_platform_data = {
252         .channel_offset = 0x04,
253         .timer_bit = 0,
254         .clockevent_rating = 200,
255 };
256
257 static struct resource tmu0_resources[] = {
258         [0] = {
259                 .start  = 0xffd80008,
260                 .end    = 0xffd80013,
261                 .flags  = IORESOURCE_MEM,
262         },
263         [1] = {
264                 .start  = 16,
265                 .flags  = IORESOURCE_IRQ,
266         },
267 };
268
269 static struct platform_device tmu0_device = {
270         .name           = "sh_tmu",
271         .id             = 0,
272         .dev = {
273                 .platform_data  = &tmu0_platform_data,
274         },
275         .resource       = tmu0_resources,
276         .num_resources  = ARRAY_SIZE(tmu0_resources),
277         .archdata = {
278                 .hwblk_id = HWBLK_TMU0,
279         },
280 };
281
282 static struct sh_timer_config tmu1_platform_data = {
283         .channel_offset = 0x10,
284         .timer_bit = 1,
285         .clocksource_rating = 200,
286 };
287
288 static struct resource tmu1_resources[] = {
289         [0] = {
290                 .start  = 0xffd80014,
291                 .end    = 0xffd8001f,
292                 .flags  = IORESOURCE_MEM,
293         },
294         [1] = {
295                 .start  = 17,
296                 .flags  = IORESOURCE_IRQ,
297         },
298 };
299
300 static struct platform_device tmu1_device = {
301         .name           = "sh_tmu",
302         .id             = 1,
303         .dev = {
304                 .platform_data  = &tmu1_platform_data,
305         },
306         .resource       = tmu1_resources,
307         .num_resources  = ARRAY_SIZE(tmu1_resources),
308         .archdata = {
309                 .hwblk_id = HWBLK_TMU0,
310         },
311 };
312
313 static struct sh_timer_config tmu2_platform_data = {
314         .channel_offset = 0x1c,
315         .timer_bit = 2,
316 };
317
318 static struct resource tmu2_resources[] = {
319         [0] = {
320                 .start  = 0xffd80020,
321                 .end    = 0xffd8002b,
322                 .flags  = IORESOURCE_MEM,
323         },
324         [1] = {
325                 .start  = 18,
326                 .flags  = IORESOURCE_IRQ,
327         },
328 };
329
330 static struct platform_device tmu2_device = {
331         .name           = "sh_tmu",
332         .id             = 2,
333         .dev = {
334                 .platform_data  = &tmu2_platform_data,
335         },
336         .resource       = tmu2_resources,
337         .num_resources  = ARRAY_SIZE(tmu2_resources),
338         .archdata = {
339                 .hwblk_id = HWBLK_TMU0,
340         },
341 };
342
343 static struct sh_timer_config tmu3_platform_data = {
344         .channel_offset = 0x04,
345         .timer_bit = 0,
346 };
347
348 static struct resource tmu3_resources[] = {
349         [0] = {
350                 .start  = 0xffd90008,
351                 .end    = 0xffd90013,
352                 .flags  = IORESOURCE_MEM,
353         },
354         [1] = {
355                 .start  = 57,
356                 .flags  = IORESOURCE_IRQ,
357         },
358 };
359
360 static struct platform_device tmu3_device = {
361         .name           = "sh_tmu",
362         .id             = 3,
363         .dev = {
364                 .platform_data  = &tmu3_platform_data,
365         },
366         .resource       = tmu3_resources,
367         .num_resources  = ARRAY_SIZE(tmu3_resources),
368         .archdata = {
369                 .hwblk_id = HWBLK_TMU1,
370         },
371 };
372
373 static struct sh_timer_config tmu4_platform_data = {
374         .channel_offset = 0x10,
375         .timer_bit = 1,
376 };
377
378 static struct resource tmu4_resources[] = {
379         [0] = {
380                 .start  = 0xffd90014,
381                 .end    = 0xffd9001f,
382                 .flags  = IORESOURCE_MEM,
383         },
384         [1] = {
385                 .start  = 58,
386                 .flags  = IORESOURCE_IRQ,
387         },
388 };
389
390 static struct platform_device tmu4_device = {
391         .name           = "sh_tmu",
392         .id             = 4,
393         .dev = {
394                 .platform_data  = &tmu4_platform_data,
395         },
396         .resource       = tmu4_resources,
397         .num_resources  = ARRAY_SIZE(tmu4_resources),
398         .archdata = {
399                 .hwblk_id = HWBLK_TMU1,
400         },
401 };
402
403 static struct sh_timer_config tmu5_platform_data = {
404         .channel_offset = 0x1c,
405         .timer_bit = 2,
406 };
407
408 static struct resource tmu5_resources[] = {
409         [0] = {
410                 .start  = 0xffd90020,
411                 .end    = 0xffd9002b,
412                 .flags  = IORESOURCE_MEM,
413         },
414         [1] = {
415                 .start  = 57,
416                 .flags  = IORESOURCE_IRQ,
417         },
418 };
419
420 static struct platform_device tmu5_device = {
421         .name           = "sh_tmu",
422         .id             = 5,
423         .dev = {
424                 .platform_data  = &tmu5_platform_data,
425         },
426         .resource       = tmu5_resources,
427         .num_resources  = ARRAY_SIZE(tmu5_resources),
428         .archdata = {
429                 .hwblk_id = HWBLK_TMU1,
430         },
431 };
432
433 static struct resource rtc_resources[] = {
434         [0] = {
435                 .start  = 0xa465fec0,
436                 .end    = 0xa465fec0 + 0x58 - 1,
437                 .flags  = IORESOURCE_IO,
438         },
439         [1] = {
440                 /* Period IRQ */
441                 .start  = 69,
442                 .flags  = IORESOURCE_IRQ,
443         },
444         [2] = {
445                 /* Carry IRQ */
446                 .start  = 70,
447                 .flags  = IORESOURCE_IRQ,
448         },
449         [3] = {
450                 /* Alarm IRQ */
451                 .start  = 68,
452                 .flags  = IORESOURCE_IRQ,
453         },
454 };
455
456 static struct platform_device rtc_device = {
457         .name           = "sh-rtc",
458         .id             = -1,
459         .num_resources  = ARRAY_SIZE(rtc_resources),
460         .resource       = rtc_resources,
461         .archdata = {
462                 .hwblk_id = HWBLK_RTC,
463         },
464 };
465
466 static struct r8a66597_platdata r8a66597_data = {
467         .on_chip = 1,
468 };
469
470 static struct resource sh7723_usb_host_resources[] = {
471         [0] = {
472                 .start  = 0xa4d80000,
473                 .end    = 0xa4d800ff,
474                 .flags  = IORESOURCE_MEM,
475         },
476         [1] = {
477                 .start  = 65,
478                 .end    = 65,
479                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
480         },
481 };
482
483 static struct platform_device sh7723_usb_host_device = {
484         .name           = "r8a66597_hcd",
485         .id             = 0,
486         .dev = {
487                 .dma_mask               = NULL,         /*  not use dma */
488                 .coherent_dma_mask      = 0xffffffff,
489                 .platform_data          = &r8a66597_data,
490         },
491         .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
492         .resource       = sh7723_usb_host_resources,
493         .archdata = {
494                 .hwblk_id = HWBLK_USB,
495         },
496 };
497
498 static struct resource iic_resources[] = {
499         [0] = {
500                 .name   = "IIC",
501                 .start  = 0x04470000,
502                 .end    = 0x04470017,
503                 .flags  = IORESOURCE_MEM,
504         },
505         [1] = {
506                 .start  = 96,
507                 .end    = 99,
508                 .flags  = IORESOURCE_IRQ,
509        },
510 };
511
512 static struct platform_device iic_device = {
513         .name           = "i2c-sh_mobile",
514         .id             = 0, /* "i2c0" clock */
515         .num_resources  = ARRAY_SIZE(iic_resources),
516         .resource       = iic_resources,
517         .archdata = {
518                 .hwblk_id = HWBLK_IIC,
519         },
520 };
521
522 static struct platform_device *sh7723_devices[] __initdata = {
523         &scif0_device,
524         &scif1_device,
525         &scif2_device,
526         &scif3_device,
527         &scif4_device,
528         &scif5_device,
529         &cmt_device,
530         &tmu0_device,
531         &tmu1_device,
532         &tmu2_device,
533         &tmu3_device,
534         &tmu4_device,
535         &tmu5_device,
536         &rtc_device,
537         &iic_device,
538         &sh7723_usb_host_device,
539         &vpu_device,
540         &veu0_device,
541         &veu1_device,
542 };
543
544 static int __init sh7723_devices_setup(void)
545 {
546         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
547         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
548         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
549
550         return platform_add_devices(sh7723_devices,
551                                     ARRAY_SIZE(sh7723_devices));
552 }
553 arch_initcall(sh7723_devices_setup);
554
555 static struct platform_device *sh7723_early_devices[] __initdata = {
556         &scif0_device,
557         &scif1_device,
558         &scif2_device,
559         &scif3_device,
560         &scif4_device,
561         &scif5_device,
562         &cmt_device,
563         &tmu0_device,
564         &tmu1_device,
565         &tmu2_device,
566         &tmu3_device,
567         &tmu4_device,
568         &tmu5_device,
569 };
570
571 void __init plat_early_device_setup(void)
572 {
573         early_platform_add_devices(sh7723_early_devices,
574                                    ARRAY_SIZE(sh7723_early_devices));
575 }
576
577 #define RAMCR_CACHE_L2FC        0x0002
578 #define RAMCR_CACHE_L2E         0x0001
579 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
580
581 void l2_cache_init(void)
582 {
583         /* Enable L2 cache */
584         __raw_writel(L2_CACHE_ENABLE, RAMCR);
585 }
586
587 enum {
588         UNUSED=0,
589         ENABLED,
590         DISABLED,
591
592         /* interrupt sources */
593         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
594         HUDI,
595         DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
596         _2DG_TRI,_2DG_INI,_2DG_CEI,
597         DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
598         VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
599         SCIFA_SCIFA0,
600         VPU_VPUI,
601         TPU_TPUI,
602         ADC_ADI,
603         USB_USI0,
604         RTC_ATI,RTC_PRI,RTC_CUI,
605         DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
606         DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
607         KEYSC_KEYI,
608         SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
609         MSIOF_MSIOFI0,MSIOF_MSIOFI1,
610         SCIFA_SCIFA1,
611         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
612         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
613         CMT_CMTI,
614         TSIF_TSIFI,
615         SIU_SIUI,
616         SCIFA_SCIFA2,
617         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
618         IRDA_IRDAI,
619         ATAPI_ATAPII,
620         VEU2H1_VEU2HI,
621         LCDC_LCDCI,
622         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
623
624         /* interrupt groups */
625         DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
626         SDHI1, RTC, DMAC1B, SDHI0,
627 };
628
629 static struct intc_vect vectors[] __initdata = {
630         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
631         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
632         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
633         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
634
635         INTC_VECT(DMAC1A_DEI0,0x700),
636         INTC_VECT(DMAC1A_DEI1,0x720),
637         INTC_VECT(DMAC1A_DEI2,0x740),
638         INTC_VECT(DMAC1A_DEI3,0x760),
639
640         INTC_VECT(_2DG_TRI, 0x780),
641         INTC_VECT(_2DG_INI, 0x7A0),
642         INTC_VECT(_2DG_CEI, 0x7C0),
643
644         INTC_VECT(DMAC0A_DEI0,0x800),
645         INTC_VECT(DMAC0A_DEI1,0x820),
646         INTC_VECT(DMAC0A_DEI2,0x840),
647         INTC_VECT(DMAC0A_DEI3,0x860),
648
649         INTC_VECT(VIO_CEUI,0x880),
650         INTC_VECT(VIO_BEUI,0x8A0),
651         INTC_VECT(VIO_VEU2HI,0x8C0),
652         INTC_VECT(VIO_VOUI,0x8E0),
653
654         INTC_VECT(SCIFA_SCIFA0,0x900),
655         INTC_VECT(VPU_VPUI,0x980),
656         INTC_VECT(TPU_TPUI,0x9A0),
657         INTC_VECT(ADC_ADI,0x9E0),
658         INTC_VECT(USB_USI0,0xA20),
659
660         INTC_VECT(RTC_ATI,0xA80),
661         INTC_VECT(RTC_PRI,0xAA0),
662         INTC_VECT(RTC_CUI,0xAC0),
663
664         INTC_VECT(DMAC1B_DEI4,0xB00),
665         INTC_VECT(DMAC1B_DEI5,0xB20),
666         INTC_VECT(DMAC1B_DADERR,0xB40),
667
668         INTC_VECT(DMAC0B_DEI4,0xB80),
669         INTC_VECT(DMAC0B_DEI5,0xBA0),
670         INTC_VECT(DMAC0B_DADERR,0xBC0),
671
672         INTC_VECT(KEYSC_KEYI,0xBE0),
673         INTC_VECT(SCIF_SCIF0,0xC00),
674         INTC_VECT(SCIF_SCIF1,0xC20),
675         INTC_VECT(SCIF_SCIF2,0xC40),
676         INTC_VECT(MSIOF_MSIOFI0,0xC80),
677         INTC_VECT(MSIOF_MSIOFI1,0xCA0),
678         INTC_VECT(SCIFA_SCIFA1,0xD00),
679
680         INTC_VECT(FLCTL_FLSTEI,0xD80),
681         INTC_VECT(FLCTL_FLTENDI,0xDA0),
682         INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
683         INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
684
685         INTC_VECT(I2C_ALI,0xE00),
686         INTC_VECT(I2C_TACKI,0xE20),
687         INTC_VECT(I2C_WAITI,0xE40),
688         INTC_VECT(I2C_DTEI,0xE60),
689
690         INTC_VECT(SDHI0, 0xE80),
691         INTC_VECT(SDHI0, 0xEA0),
692         INTC_VECT(SDHI0, 0xEC0),
693
694         INTC_VECT(CMT_CMTI,0xF00),
695         INTC_VECT(TSIF_TSIFI,0xF20),
696         INTC_VECT(SIU_SIUI,0xF80),
697         INTC_VECT(SCIFA_SCIFA2,0xFA0),
698
699         INTC_VECT(TMU0_TUNI0,0x400),
700         INTC_VECT(TMU0_TUNI1,0x420),
701         INTC_VECT(TMU0_TUNI2,0x440),
702
703         INTC_VECT(IRDA_IRDAI,0x480),
704         INTC_VECT(ATAPI_ATAPII,0x4A0),
705
706         INTC_VECT(SDHI1, 0x4E0),
707         INTC_VECT(SDHI1, 0x500),
708         INTC_VECT(SDHI1, 0x520),
709
710         INTC_VECT(VEU2H1_VEU2HI,0x560),
711         INTC_VECT(LCDC_LCDCI,0x580),
712
713         INTC_VECT(TMU1_TUNI0,0x920),
714         INTC_VECT(TMU1_TUNI1,0x940),
715         INTC_VECT(TMU1_TUNI2,0x960),
716
717 };
718
719 static struct intc_group groups[] __initdata = {
720         INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
721         INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
722         INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
723         INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
724         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
725         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
726         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
727         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
728         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
729 };
730
731 static struct intc_mask_reg mask_registers[] __initdata = {
732         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
733           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
734             0, ENABLED, ENABLED, ENABLED } },
735         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
736           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
737         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
738           { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
739         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
740           { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
741         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
742           { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
743         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
744           { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
745         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
746           { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
747         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
748           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
749             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
750         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
751           { 0, ENABLED, ENABLED, ENABLED,
752             0, 0, SCIFA_SCIFA2, SIU_SIUI } },
753         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
754           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
755         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
756           { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
757         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
758           { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
759         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
760           { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
761         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
762           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
763 };
764
765 static struct intc_prio_reg prio_registers[] __initdata = {
766         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
767         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
768         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
769         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
770         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
771         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
772         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
773         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
774         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
775         { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
776         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
777         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
778         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
779           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
780 };
781
782 static struct intc_sense_reg sense_registers[] __initdata = {
783         { 0xa414001c, 16, 2, /* ICR1 */
784           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
785 };
786
787 static struct intc_mask_reg ack_registers[] __initdata = {
788         { 0xa4140024, 0, 8, /* INTREQ00 */
789           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
790 };
791
792 static struct intc_desc intc_desc __initdata = {
793         .name = "sh7723",
794         .force_enable = ENABLED,
795         .force_disable = DISABLED,
796         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
797                            prio_registers, sense_registers, ack_registers),
798 };
799
800 void __init plat_irq_setup(void)
801 {
802         register_intc_controller(&intc_desc);
803 }