sh: add a resource name for shdma
[~shefty/rdma-dev.git] / arch / sh / kernel / cpu / sh4a / setup-sh7724.c
1 /*
2  * SH7724 Setup
3  *
4  * Copyright (C) 2009 Renesas Solutions Corp.
5  *
6  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7  *
8  * Based on SH7723 Setup
9  * Copyright (C) 2008  Paul Mundt
10  *
11  * This file is subject to the terms and conditions of the GNU General Public
12  * License.  See the file "COPYING" in the main directory of this archive
13  * for more details.
14  */
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
18 #include <linux/mm.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_dma.h>
22 #include <linux/sh_timer.h>
23 #include <linux/io.h>
24 #include <linux/notifier.h>
25
26 #include <asm/suspend.h>
27 #include <asm/clock.h>
28 #include <asm/mmzone.h>
29
30 #include <cpu/dma-register.h>
31 #include <cpu/sh7724.h>
32
33 /* DMA */
34 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
35         {
36                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
37                 .addr           = 0xffe0000c,
38                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
39                 .mid_rid        = 0x21,
40         }, {
41                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
42                 .addr           = 0xffe00014,
43                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
44                 .mid_rid        = 0x22,
45         }, {
46                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
47                 .addr           = 0xffe1000c,
48                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
49                 .mid_rid        = 0x25,
50         }, {
51                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
52                 .addr           = 0xffe10014,
53                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
54                 .mid_rid        = 0x26,
55         }, {
56                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
57                 .addr           = 0xffe2000c,
58                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
59                 .mid_rid        = 0x29,
60         }, {
61                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
62                 .addr           = 0xffe20014,
63                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
64                 .mid_rid        = 0x2a,
65         }, {
66                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
67                 .addr           = 0xa4e30020,
68                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
69                 .mid_rid        = 0x2d,
70         }, {
71                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
72                 .addr           = 0xa4e30024,
73                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
74                 .mid_rid        = 0x2e,
75         }, {
76                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
77                 .addr           = 0xa4e40020,
78                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
79                 .mid_rid        = 0x31,
80         }, {
81                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
82                 .addr           = 0xa4e40024,
83                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
84                 .mid_rid        = 0x32,
85         }, {
86                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
87                 .addr           = 0xa4e50020,
88                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
89                 .mid_rid        = 0x35,
90         }, {
91                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
92                 .addr           = 0xa4e50024,
93                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
94                 .mid_rid        = 0x36,
95         }, {
96                 .slave_id       = SHDMA_SLAVE_USB0D0_TX,
97                 .addr           = 0xA4D80100,
98                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
99                 .mid_rid        = 0x73,
100         }, {
101                 .slave_id       = SHDMA_SLAVE_USB0D0_RX,
102                 .addr           = 0xA4D80100,
103                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
104                 .mid_rid        = 0x73,
105         }, {
106                 .slave_id       = SHDMA_SLAVE_USB0D1_TX,
107                 .addr           = 0xA4D80120,
108                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
109                 .mid_rid        = 0x77,
110         }, {
111                 .slave_id       = SHDMA_SLAVE_USB0D1_RX,
112                 .addr           = 0xA4D80120,
113                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
114                 .mid_rid        = 0x77,
115         }, {
116                 .slave_id       = SHDMA_SLAVE_USB1D0_TX,
117                 .addr           = 0xA4D90100,
118                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
119                 .mid_rid        = 0xab,
120         }, {
121                 .slave_id       = SHDMA_SLAVE_USB1D0_RX,
122                 .addr           = 0xA4D90100,
123                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
124                 .mid_rid        = 0xab,
125         }, {
126                 .slave_id       = SHDMA_SLAVE_USB1D1_TX,
127                 .addr           = 0xA4D90120,
128                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
129                 .mid_rid        = 0xaf,
130         }, {
131                 .slave_id       = SHDMA_SLAVE_USB1D1_RX,
132                 .addr           = 0xA4D90120,
133                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
134                 .mid_rid        = 0xaf,
135         }, {
136                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
137                 .addr           = 0x04ce0030,
138                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
139                 .mid_rid        = 0xc1,
140         }, {
141                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
142                 .addr           = 0x04ce0030,
143                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
144                 .mid_rid        = 0xc2,
145         }, {
146                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
147                 .addr           = 0x04cf0030,
148                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
149                 .mid_rid        = 0xc9,
150         }, {
151                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
152                 .addr           = 0x04cf0030,
153                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
154                 .mid_rid        = 0xca,
155         },
156 };
157
158 static const struct sh_dmae_channel sh7724_dmae_channels[] = {
159         {
160                 .offset = 0,
161                 .dmars = 0,
162                 .dmars_bit = 0,
163         }, {
164                 .offset = 0x10,
165                 .dmars = 0,
166                 .dmars_bit = 8,
167         }, {
168                 .offset = 0x20,
169                 .dmars = 4,
170                 .dmars_bit = 0,
171         }, {
172                 .offset = 0x30,
173                 .dmars = 4,
174                 .dmars_bit = 8,
175         }, {
176                 .offset = 0x50,
177                 .dmars = 8,
178                 .dmars_bit = 0,
179         }, {
180                 .offset = 0x60,
181                 .dmars = 8,
182                 .dmars_bit = 8,
183         }
184 };
185
186 static const unsigned int ts_shift[] = TS_SHIFT;
187
188 static struct sh_dmae_pdata dma_platform_data = {
189         .slave          = sh7724_dmae_slaves,
190         .slave_num      = ARRAY_SIZE(sh7724_dmae_slaves),
191         .channel        = sh7724_dmae_channels,
192         .channel_num    = ARRAY_SIZE(sh7724_dmae_channels),
193         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
194         .ts_low_mask    = CHCR_TS_LOW_MASK,
195         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
196         .ts_high_mask   = CHCR_TS_HIGH_MASK,
197         .ts_shift       = ts_shift,
198         .ts_shift_num   = ARRAY_SIZE(ts_shift),
199         .dmaor_init     = DMAOR_INIT,
200 };
201
202 /* Resource order important! */
203 static struct resource sh7724_dmae0_resources[] = {
204         {
205                 /* Channel registers and DMAOR */
206                 .start  = 0xfe008020,
207                 .end    = 0xfe00808f,
208                 .flags  = IORESOURCE_MEM,
209         },
210         {
211                 /* DMARSx */
212                 .start  = 0xfe009000,
213                 .end    = 0xfe00900b,
214                 .flags  = IORESOURCE_MEM,
215         },
216         {
217                 .name   = "error_irq",
218                 .start  = 78,
219                 .end    = 78,
220                 .flags  = IORESOURCE_IRQ,
221         },
222         {
223                 /* IRQ for channels 0-3 */
224                 .start  = 48,
225                 .end    = 51,
226                 .flags  = IORESOURCE_IRQ,
227         },
228         {
229                 /* IRQ for channels 4-5 */
230                 .start  = 76,
231                 .end    = 77,
232                 .flags  = IORESOURCE_IRQ,
233         },
234 };
235
236 /* Resource order important! */
237 static struct resource sh7724_dmae1_resources[] = {
238         {
239                 /* Channel registers and DMAOR */
240                 .start  = 0xfdc08020,
241                 .end    = 0xfdc0808f,
242                 .flags  = IORESOURCE_MEM,
243         },
244         {
245                 /* DMARSx */
246                 .start  = 0xfdc09000,
247                 .end    = 0xfdc0900b,
248                 .flags  = IORESOURCE_MEM,
249         },
250         {
251                 .name   = "error_irq",
252                 .start  = 74,
253                 .end    = 74,
254                 .flags  = IORESOURCE_IRQ,
255         },
256         {
257                 /* IRQ for channels 0-3 */
258                 .start  = 40,
259                 .end    = 43,
260                 .flags  = IORESOURCE_IRQ,
261         },
262         {
263                 /* IRQ for channels 4-5 */
264                 .start  = 72,
265                 .end    = 73,
266                 .flags  = IORESOURCE_IRQ,
267         },
268 };
269
270 static struct platform_device dma0_device = {
271         .name           = "sh-dma-engine",
272         .id             = 0,
273         .resource       = sh7724_dmae0_resources,
274         .num_resources  = ARRAY_SIZE(sh7724_dmae0_resources),
275         .dev            = {
276                 .platform_data  = &dma_platform_data,
277         },
278         .archdata = {
279                 .hwblk_id = HWBLK_DMAC0,
280         },
281 };
282
283 static struct platform_device dma1_device = {
284         .name           = "sh-dma-engine",
285         .id             = 1,
286         .resource       = sh7724_dmae1_resources,
287         .num_resources  = ARRAY_SIZE(sh7724_dmae1_resources),
288         .dev            = {
289                 .platform_data  = &dma_platform_data,
290         },
291         .archdata = {
292                 .hwblk_id = HWBLK_DMAC1,
293         },
294 };
295
296 /* Serial */
297 static struct plat_sci_port scif0_platform_data = {
298         .mapbase        = 0xffe00000,
299         .port_reg       = SCIx_NOT_SUPPORTED,
300         .flags          = UPF_BOOT_AUTOCONF,
301         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
302         .scbrr_algo_id  = SCBRR_ALGO_2,
303         .type           = PORT_SCIF,
304         .irqs           = { 80, 80, 80, 80 },
305         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
306 };
307
308 static struct platform_device scif0_device = {
309         .name           = "sh-sci",
310         .id             = 0,
311         .dev            = {
312                 .platform_data  = &scif0_platform_data,
313         },
314 };
315
316 static struct plat_sci_port scif1_platform_data = {
317         .mapbase        = 0xffe10000,
318         .port_reg       = SCIx_NOT_SUPPORTED,
319         .flags          = UPF_BOOT_AUTOCONF,
320         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
321         .scbrr_algo_id  = SCBRR_ALGO_2,
322         .type           = PORT_SCIF,
323         .irqs           = { 81, 81, 81, 81 },
324         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
325 };
326
327 static struct platform_device scif1_device = {
328         .name           = "sh-sci",
329         .id             = 1,
330         .dev            = {
331                 .platform_data  = &scif1_platform_data,
332         },
333 };
334
335 static struct plat_sci_port scif2_platform_data = {
336         .mapbase        = 0xffe20000,
337         .port_reg       = SCIx_NOT_SUPPORTED,
338         .flags          = UPF_BOOT_AUTOCONF,
339         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
340         .scbrr_algo_id  = SCBRR_ALGO_2,
341         .type           = PORT_SCIF,
342         .irqs           = { 82, 82, 82, 82 },
343         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
344 };
345
346 static struct platform_device scif2_device = {
347         .name           = "sh-sci",
348         .id             = 2,
349         .dev            = {
350                 .platform_data  = &scif2_platform_data,
351         },
352 };
353
354 static struct plat_sci_port scif3_platform_data = {
355         .mapbase        = 0xa4e30000,
356         .port_reg       = SCIx_NOT_SUPPORTED,
357         .flags          = UPF_BOOT_AUTOCONF,
358         .scscr          = SCSCR_RE | SCSCR_TE,
359         .scbrr_algo_id  = SCBRR_ALGO_3,
360         .type           = PORT_SCIFA,
361         .irqs           = { 56, 56, 56, 56 },
362 };
363
364 static struct platform_device scif3_device = {
365         .name           = "sh-sci",
366         .id             = 3,
367         .dev            = {
368                 .platform_data  = &scif3_platform_data,
369         },
370 };
371
372 static struct plat_sci_port scif4_platform_data = {
373         .mapbase        = 0xa4e40000,
374         .port_reg       = SCIx_NOT_SUPPORTED,
375         .flags          = UPF_BOOT_AUTOCONF,
376         .scscr          = SCSCR_RE | SCSCR_TE,
377         .scbrr_algo_id  = SCBRR_ALGO_3,
378         .type           = PORT_SCIFA,
379         .irqs           = { 88, 88, 88, 88 },
380 };
381
382 static struct platform_device scif4_device = {
383         .name           = "sh-sci",
384         .id             = 4,
385         .dev            = {
386                 .platform_data  = &scif4_platform_data,
387         },
388 };
389
390 static struct plat_sci_port scif5_platform_data = {
391         .mapbase        = 0xa4e50000,
392         .port_reg       = SCIx_NOT_SUPPORTED,
393         .flags          = UPF_BOOT_AUTOCONF,
394         .scscr          = SCSCR_RE | SCSCR_TE,
395         .scbrr_algo_id  = SCBRR_ALGO_3,
396         .type           = PORT_SCIFA,
397         .irqs           = { 109, 109, 109, 109 },
398 };
399
400 static struct platform_device scif5_device = {
401         .name           = "sh-sci",
402         .id             = 5,
403         .dev            = {
404                 .platform_data  = &scif5_platform_data,
405         },
406 };
407
408 /* RTC */
409 static struct resource rtc_resources[] = {
410         [0] = {
411                 .start  = 0xa465fec0,
412                 .end    = 0xa465fec0 + 0x58 - 1,
413                 .flags  = IORESOURCE_IO,
414         },
415         [1] = {
416                 /* Period IRQ */
417                 .start  = 69,
418                 .flags  = IORESOURCE_IRQ,
419         },
420         [2] = {
421                 /* Carry IRQ */
422                 .start  = 70,
423                 .flags  = IORESOURCE_IRQ,
424         },
425         [3] = {
426                 /* Alarm IRQ */
427                 .start  = 68,
428                 .flags  = IORESOURCE_IRQ,
429         },
430 };
431
432 static struct platform_device rtc_device = {
433         .name           = "sh-rtc",
434         .id             = -1,
435         .num_resources  = ARRAY_SIZE(rtc_resources),
436         .resource       = rtc_resources,
437         .archdata = {
438                 .hwblk_id = HWBLK_RTC,
439         },
440 };
441
442 /* I2C0 */
443 static struct resource iic0_resources[] = {
444         [0] = {
445                 .name   = "IIC0",
446                 .start  = 0x04470000,
447                 .end    = 0x04470018 - 1,
448                 .flags  = IORESOURCE_MEM,
449         },
450         [1] = {
451                 .start  = 96,
452                 .end    = 99,
453                 .flags  = IORESOURCE_IRQ,
454         },
455 };
456
457 static struct platform_device iic0_device = {
458         .name           = "i2c-sh_mobile",
459         .id             = 0, /* "i2c0" clock */
460         .num_resources  = ARRAY_SIZE(iic0_resources),
461         .resource       = iic0_resources,
462         .archdata = {
463                 .hwblk_id = HWBLK_IIC0,
464         },
465 };
466
467 /* I2C1 */
468 static struct resource iic1_resources[] = {
469         [0] = {
470                 .name   = "IIC1",
471                 .start  = 0x04750000,
472                 .end    = 0x04750018 - 1,
473                 .flags  = IORESOURCE_MEM,
474         },
475         [1] = {
476                 .start  = 92,
477                 .end    = 95,
478                 .flags  = IORESOURCE_IRQ,
479         },
480 };
481
482 static struct platform_device iic1_device = {
483         .name           = "i2c-sh_mobile",
484         .id             = 1, /* "i2c1" clock */
485         .num_resources  = ARRAY_SIZE(iic1_resources),
486         .resource       = iic1_resources,
487         .archdata = {
488                 .hwblk_id = HWBLK_IIC1,
489         },
490 };
491
492 /* VPU */
493 static struct uio_info vpu_platform_data = {
494         .name = "VPU5F",
495         .version = "0",
496         .irq = 60,
497 };
498
499 static struct resource vpu_resources[] = {
500         [0] = {
501                 .name   = "VPU",
502                 .start  = 0xfe900000,
503                 .end    = 0xfe902807,
504                 .flags  = IORESOURCE_MEM,
505         },
506         [1] = {
507                 /* place holder for contiguous memory */
508         },
509 };
510
511 static struct platform_device vpu_device = {
512         .name           = "uio_pdrv_genirq",
513         .id             = 0,
514         .dev = {
515                 .platform_data  = &vpu_platform_data,
516         },
517         .resource       = vpu_resources,
518         .num_resources  = ARRAY_SIZE(vpu_resources),
519         .archdata = {
520                 .hwblk_id = HWBLK_VPU,
521         },
522 };
523
524 /* VEU0 */
525 static struct uio_info veu0_platform_data = {
526         .name = "VEU3F0",
527         .version = "0",
528         .irq = 83,
529 };
530
531 static struct resource veu0_resources[] = {
532         [0] = {
533                 .name   = "VEU3F0",
534                 .start  = 0xfe920000,
535                 .end    = 0xfe9200cb,
536                 .flags  = IORESOURCE_MEM,
537         },
538         [1] = {
539                 /* place holder for contiguous memory */
540         },
541 };
542
543 static struct platform_device veu0_device = {
544         .name           = "uio_pdrv_genirq",
545         .id             = 1,
546         .dev = {
547                 .platform_data  = &veu0_platform_data,
548         },
549         .resource       = veu0_resources,
550         .num_resources  = ARRAY_SIZE(veu0_resources),
551         .archdata = {
552                 .hwblk_id = HWBLK_VEU0,
553         },
554 };
555
556 /* VEU1 */
557 static struct uio_info veu1_platform_data = {
558         .name = "VEU3F1",
559         .version = "0",
560         .irq = 54,
561 };
562
563 static struct resource veu1_resources[] = {
564         [0] = {
565                 .name   = "VEU3F1",
566                 .start  = 0xfe924000,
567                 .end    = 0xfe9240cb,
568                 .flags  = IORESOURCE_MEM,
569         },
570         [1] = {
571                 /* place holder for contiguous memory */
572         },
573 };
574
575 static struct platform_device veu1_device = {
576         .name           = "uio_pdrv_genirq",
577         .id             = 2,
578         .dev = {
579                 .platform_data  = &veu1_platform_data,
580         },
581         .resource       = veu1_resources,
582         .num_resources  = ARRAY_SIZE(veu1_resources),
583         .archdata = {
584                 .hwblk_id = HWBLK_VEU1,
585         },
586 };
587
588 /* BEU0 */
589 static struct uio_info beu0_platform_data = {
590         .name = "BEU0",
591         .version = "0",
592         .irq = evt2irq(0x8A0),
593 };
594
595 static struct resource beu0_resources[] = {
596         [0] = {
597                 .name   = "BEU0",
598                 .start  = 0xfe930000,
599                 .end    = 0xfe933400,
600                 .flags  = IORESOURCE_MEM,
601         },
602         [1] = {
603                 /* place holder for contiguous memory */
604         },
605 };
606
607 static struct platform_device beu0_device = {
608         .name           = "uio_pdrv_genirq",
609         .id             = 6,
610         .dev = {
611                 .platform_data  = &beu0_platform_data,
612         },
613         .resource       = beu0_resources,
614         .num_resources  = ARRAY_SIZE(beu0_resources),
615         .archdata = {
616                 .hwblk_id = HWBLK_BEU0,
617         },
618 };
619
620 /* BEU1 */
621 static struct uio_info beu1_platform_data = {
622         .name = "BEU1",
623         .version = "0",
624         .irq = evt2irq(0xA00),
625 };
626
627 static struct resource beu1_resources[] = {
628         [0] = {
629                 .name   = "BEU1",
630                 .start  = 0xfe940000,
631                 .end    = 0xfe943400,
632                 .flags  = IORESOURCE_MEM,
633         },
634         [1] = {
635                 /* place holder for contiguous memory */
636         },
637 };
638
639 static struct platform_device beu1_device = {
640         .name           = "uio_pdrv_genirq",
641         .id             = 7,
642         .dev = {
643                 .platform_data  = &beu1_platform_data,
644         },
645         .resource       = beu1_resources,
646         .num_resources  = ARRAY_SIZE(beu1_resources),
647         .archdata = {
648                 .hwblk_id = HWBLK_BEU1,
649         },
650 };
651
652 static struct sh_timer_config cmt_platform_data = {
653         .channel_offset = 0x60,
654         .timer_bit = 5,
655         .clockevent_rating = 125,
656         .clocksource_rating = 200,
657 };
658
659 static struct resource cmt_resources[] = {
660         [0] = {
661                 .start  = 0x044a0060,
662                 .end    = 0x044a006b,
663                 .flags  = IORESOURCE_MEM,
664         },
665         [1] = {
666                 .start  = 104,
667                 .flags  = IORESOURCE_IRQ,
668         },
669 };
670
671 static struct platform_device cmt_device = {
672         .name           = "sh_cmt",
673         .id             = 0,
674         .dev = {
675                 .platform_data  = &cmt_platform_data,
676         },
677         .resource       = cmt_resources,
678         .num_resources  = ARRAY_SIZE(cmt_resources),
679         .archdata = {
680                 .hwblk_id = HWBLK_CMT,
681         },
682 };
683
684 static struct sh_timer_config tmu0_platform_data = {
685         .channel_offset = 0x04,
686         .timer_bit = 0,
687         .clockevent_rating = 200,
688 };
689
690 static struct resource tmu0_resources[] = {
691         [0] = {
692                 .start  = 0xffd80008,
693                 .end    = 0xffd80013,
694                 .flags  = IORESOURCE_MEM,
695         },
696         [1] = {
697                 .start  = 16,
698                 .flags  = IORESOURCE_IRQ,
699         },
700 };
701
702 static struct platform_device tmu0_device = {
703         .name           = "sh_tmu",
704         .id             = 0,
705         .dev = {
706                 .platform_data  = &tmu0_platform_data,
707         },
708         .resource       = tmu0_resources,
709         .num_resources  = ARRAY_SIZE(tmu0_resources),
710         .archdata = {
711                 .hwblk_id = HWBLK_TMU0,
712         },
713 };
714
715 static struct sh_timer_config tmu1_platform_data = {
716         .channel_offset = 0x10,
717         .timer_bit = 1,
718         .clocksource_rating = 200,
719 };
720
721 static struct resource tmu1_resources[] = {
722         [0] = {
723                 .start  = 0xffd80014,
724                 .end    = 0xffd8001f,
725                 .flags  = IORESOURCE_MEM,
726         },
727         [1] = {
728                 .start  = 17,
729                 .flags  = IORESOURCE_IRQ,
730         },
731 };
732
733 static struct platform_device tmu1_device = {
734         .name           = "sh_tmu",
735         .id             = 1,
736         .dev = {
737                 .platform_data  = &tmu1_platform_data,
738         },
739         .resource       = tmu1_resources,
740         .num_resources  = ARRAY_SIZE(tmu1_resources),
741         .archdata = {
742                 .hwblk_id = HWBLK_TMU0,
743         },
744 };
745
746 static struct sh_timer_config tmu2_platform_data = {
747         .channel_offset = 0x1c,
748         .timer_bit = 2,
749 };
750
751 static struct resource tmu2_resources[] = {
752         [0] = {
753                 .start  = 0xffd80020,
754                 .end    = 0xffd8002b,
755                 .flags  = IORESOURCE_MEM,
756         },
757         [1] = {
758                 .start  = 18,
759                 .flags  = IORESOURCE_IRQ,
760         },
761 };
762
763 static struct platform_device tmu2_device = {
764         .name           = "sh_tmu",
765         .id             = 2,
766         .dev = {
767                 .platform_data  = &tmu2_platform_data,
768         },
769         .resource       = tmu2_resources,
770         .num_resources  = ARRAY_SIZE(tmu2_resources),
771         .archdata = {
772                 .hwblk_id = HWBLK_TMU0,
773         },
774 };
775
776
777 static struct sh_timer_config tmu3_platform_data = {
778         .channel_offset = 0x04,
779         .timer_bit = 0,
780 };
781
782 static struct resource tmu3_resources[] = {
783         [0] = {
784                 .start  = 0xffd90008,
785                 .end    = 0xffd90013,
786                 .flags  = IORESOURCE_MEM,
787         },
788         [1] = {
789                 .start  = 57,
790                 .flags  = IORESOURCE_IRQ,
791         },
792 };
793
794 static struct platform_device tmu3_device = {
795         .name           = "sh_tmu",
796         .id             = 3,
797         .dev = {
798                 .platform_data  = &tmu3_platform_data,
799         },
800         .resource       = tmu3_resources,
801         .num_resources  = ARRAY_SIZE(tmu3_resources),
802         .archdata = {
803                 .hwblk_id = HWBLK_TMU1,
804         },
805 };
806
807 static struct sh_timer_config tmu4_platform_data = {
808         .channel_offset = 0x10,
809         .timer_bit = 1,
810 };
811
812 static struct resource tmu4_resources[] = {
813         [0] = {
814                 .start  = 0xffd90014,
815                 .end    = 0xffd9001f,
816                 .flags  = IORESOURCE_MEM,
817         },
818         [1] = {
819                 .start  = 58,
820                 .flags  = IORESOURCE_IRQ,
821         },
822 };
823
824 static struct platform_device tmu4_device = {
825         .name           = "sh_tmu",
826         .id             = 4,
827         .dev = {
828                 .platform_data  = &tmu4_platform_data,
829         },
830         .resource       = tmu4_resources,
831         .num_resources  = ARRAY_SIZE(tmu4_resources),
832         .archdata = {
833                 .hwblk_id = HWBLK_TMU1,
834         },
835 };
836
837 static struct sh_timer_config tmu5_platform_data = {
838         .channel_offset = 0x1c,
839         .timer_bit = 2,
840 };
841
842 static struct resource tmu5_resources[] = {
843         [0] = {
844                 .start  = 0xffd90020,
845                 .end    = 0xffd9002b,
846                 .flags  = IORESOURCE_MEM,
847         },
848         [1] = {
849                 .start  = 57,
850                 .flags  = IORESOURCE_IRQ,
851         },
852 };
853
854 static struct platform_device tmu5_device = {
855         .name           = "sh_tmu",
856         .id             = 5,
857         .dev = {
858                 .platform_data  = &tmu5_platform_data,
859         },
860         .resource       = tmu5_resources,
861         .num_resources  = ARRAY_SIZE(tmu5_resources),
862         .archdata = {
863                 .hwblk_id = HWBLK_TMU1,
864         },
865 };
866
867 /* JPU */
868 static struct uio_info jpu_platform_data = {
869         .name = "JPU",
870         .version = "0",
871         .irq = 27,
872 };
873
874 static struct resource jpu_resources[] = {
875         [0] = {
876                 .name   = "JPU",
877                 .start  = 0xfe980000,
878                 .end    = 0xfe9902d3,
879                 .flags  = IORESOURCE_MEM,
880         },
881         [1] = {
882                 /* place holder for contiguous memory */
883         },
884 };
885
886 static struct platform_device jpu_device = {
887         .name           = "uio_pdrv_genirq",
888         .id             = 3,
889         .dev = {
890                 .platform_data  = &jpu_platform_data,
891         },
892         .resource       = jpu_resources,
893         .num_resources  = ARRAY_SIZE(jpu_resources),
894         .archdata = {
895                 .hwblk_id = HWBLK_JPU,
896         },
897 };
898
899 /* SPU2DSP0 */
900 static struct uio_info spu0_platform_data = {
901         .name = "SPU2DSP0",
902         .version = "0",
903         .irq = 86,
904 };
905
906 static struct resource spu0_resources[] = {
907         [0] = {
908                 .name   = "SPU2DSP0",
909                 .start  = 0xFE200000,
910                 .end    = 0xFE2FFFFF,
911                 .flags  = IORESOURCE_MEM,
912         },
913         [1] = {
914                 /* place holder for contiguous memory */
915         },
916 };
917
918 static struct platform_device spu0_device = {
919         .name           = "uio_pdrv_genirq",
920         .id             = 4,
921         .dev = {
922                 .platform_data  = &spu0_platform_data,
923         },
924         .resource       = spu0_resources,
925         .num_resources  = ARRAY_SIZE(spu0_resources),
926         .archdata = {
927                 .hwblk_id = HWBLK_SPU,
928         },
929 };
930
931 /* SPU2DSP1 */
932 static struct uio_info spu1_platform_data = {
933         .name = "SPU2DSP1",
934         .version = "0",
935         .irq = 87,
936 };
937
938 static struct resource spu1_resources[] = {
939         [0] = {
940                 .name   = "SPU2DSP1",
941                 .start  = 0xFE300000,
942                 .end    = 0xFE3FFFFF,
943                 .flags  = IORESOURCE_MEM,
944         },
945         [1] = {
946                 /* place holder for contiguous memory */
947         },
948 };
949
950 static struct platform_device spu1_device = {
951         .name           = "uio_pdrv_genirq",
952         .id             = 5,
953         .dev = {
954                 .platform_data  = &spu1_platform_data,
955         },
956         .resource       = spu1_resources,
957         .num_resources  = ARRAY_SIZE(spu1_resources),
958         .archdata = {
959                 .hwblk_id = HWBLK_SPU,
960         },
961 };
962
963 static struct platform_device *sh7724_devices[] __initdata = {
964         &scif0_device,
965         &scif1_device,
966         &scif2_device,
967         &scif3_device,
968         &scif4_device,
969         &scif5_device,
970         &cmt_device,
971         &tmu0_device,
972         &tmu1_device,
973         &tmu2_device,
974         &tmu3_device,
975         &tmu4_device,
976         &tmu5_device,
977         &dma0_device,
978         &dma1_device,
979         &rtc_device,
980         &iic0_device,
981         &iic1_device,
982         &vpu_device,
983         &veu0_device,
984         &veu1_device,
985         &beu0_device,
986         &beu1_device,
987         &jpu_device,
988         &spu0_device,
989         &spu1_device,
990 };
991
992 static int __init sh7724_devices_setup(void)
993 {
994         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
995         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
996         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
997         platform_resource_setup_memory(&jpu_device,  "jpu",  2 << 20);
998         platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
999         platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
1000
1001         return platform_add_devices(sh7724_devices,
1002                                     ARRAY_SIZE(sh7724_devices));
1003 }
1004 arch_initcall(sh7724_devices_setup);
1005
1006 static struct platform_device *sh7724_early_devices[] __initdata = {
1007         &scif0_device,
1008         &scif1_device,
1009         &scif2_device,
1010         &scif3_device,
1011         &scif4_device,
1012         &scif5_device,
1013         &cmt_device,
1014         &tmu0_device,
1015         &tmu1_device,
1016         &tmu2_device,
1017         &tmu3_device,
1018         &tmu4_device,
1019         &tmu5_device,
1020 };
1021
1022 void __init plat_early_device_setup(void)
1023 {
1024         early_platform_add_devices(sh7724_early_devices,
1025                                    ARRAY_SIZE(sh7724_early_devices));
1026 }
1027
1028 #define RAMCR_CACHE_L2FC        0x0002
1029 #define RAMCR_CACHE_L2E         0x0001
1030 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
1031
1032 void l2_cache_init(void)
1033 {
1034         /* Enable L2 cache */
1035         __raw_writel(L2_CACHE_ENABLE, RAMCR);
1036 }
1037
1038 enum {
1039         UNUSED = 0,
1040         ENABLED,
1041         DISABLED,
1042
1043         /* interrupt sources */
1044         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
1045         HUDI,
1046         DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
1047         _2DG_TRI, _2DG_INI, _2DG_CEI,
1048         DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
1049         VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
1050         SCIFA3,
1051         VPU,
1052         TPU,
1053         CEU1,
1054         BEU1,
1055         USB0, USB1,
1056         ATAPI,
1057         RTC_ATI, RTC_PRI, RTC_CUI,
1058         DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
1059         DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
1060         KEYSC,
1061         SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
1062         VEU0,
1063         MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1064         SPU_SPUI0, SPU_SPUI1,
1065         SCIFA4,
1066         ICB,
1067         ETHI,
1068         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
1069         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
1070         CMT,
1071         TSIF,
1072         FSI,
1073         SCIFA5,
1074         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
1075         IRDA,
1076         JPU,
1077         _2DDMAC,
1078         MMC_MMC2I, MMC_MMC3I,
1079         LCDC,
1080         TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
1081
1082         /* interrupt groups */
1083         DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
1084         DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
1085 };
1086
1087 static struct intc_vect vectors[] __initdata = {
1088         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
1089         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
1090         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
1091         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
1092
1093         INTC_VECT(DMAC1A_DEI0, 0x700),
1094         INTC_VECT(DMAC1A_DEI1, 0x720),
1095         INTC_VECT(DMAC1A_DEI2, 0x740),
1096         INTC_VECT(DMAC1A_DEI3, 0x760),
1097
1098         INTC_VECT(_2DG_TRI, 0x780),
1099         INTC_VECT(_2DG_INI, 0x7A0),
1100         INTC_VECT(_2DG_CEI, 0x7C0),
1101
1102         INTC_VECT(DMAC0A_DEI0, 0x800),
1103         INTC_VECT(DMAC0A_DEI1, 0x820),
1104         INTC_VECT(DMAC0A_DEI2, 0x840),
1105         INTC_VECT(DMAC0A_DEI3, 0x860),
1106
1107         INTC_VECT(VIO_CEU0, 0x880),
1108         INTC_VECT(VIO_BEU0, 0x8A0),
1109         INTC_VECT(VIO_VEU1, 0x8C0),
1110         INTC_VECT(VIO_VOU,  0x8E0),
1111
1112         INTC_VECT(SCIFA3, 0x900),
1113         INTC_VECT(VPU,    0x980),
1114         INTC_VECT(TPU,    0x9A0),
1115         INTC_VECT(CEU1,   0x9E0),
1116         INTC_VECT(BEU1,   0xA00),
1117         INTC_VECT(USB0,   0xA20),
1118         INTC_VECT(USB1,   0xA40),
1119         INTC_VECT(ATAPI,  0xA60),
1120
1121         INTC_VECT(RTC_ATI, 0xA80),
1122         INTC_VECT(RTC_PRI, 0xAA0),
1123         INTC_VECT(RTC_CUI, 0xAC0),
1124
1125         INTC_VECT(DMAC1B_DEI4, 0xB00),
1126         INTC_VECT(DMAC1B_DEI5, 0xB20),
1127         INTC_VECT(DMAC1B_DADERR, 0xB40),
1128
1129         INTC_VECT(DMAC0B_DEI4, 0xB80),
1130         INTC_VECT(DMAC0B_DEI5, 0xBA0),
1131         INTC_VECT(DMAC0B_DADERR, 0xBC0),
1132
1133         INTC_VECT(KEYSC,      0xBE0),
1134         INTC_VECT(SCIF_SCIF0, 0xC00),
1135         INTC_VECT(SCIF_SCIF1, 0xC20),
1136         INTC_VECT(SCIF_SCIF2, 0xC40),
1137         INTC_VECT(VEU0,       0xC60),
1138         INTC_VECT(MSIOF_MSIOFI0, 0xC80),
1139         INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
1140         INTC_VECT(SPU_SPUI0, 0xCC0),
1141         INTC_VECT(SPU_SPUI1, 0xCE0),
1142         INTC_VECT(SCIFA4,    0xD00),
1143
1144         INTC_VECT(ICB,  0xD20),
1145         INTC_VECT(ETHI, 0xD60),
1146
1147         INTC_VECT(I2C1_ALI, 0xD80),
1148         INTC_VECT(I2C1_TACKI, 0xDA0),
1149         INTC_VECT(I2C1_WAITI, 0xDC0),
1150         INTC_VECT(I2C1_DTEI, 0xDE0),
1151
1152         INTC_VECT(I2C0_ALI, 0xE00),
1153         INTC_VECT(I2C0_TACKI, 0xE20),
1154         INTC_VECT(I2C0_WAITI, 0xE40),
1155         INTC_VECT(I2C0_DTEI, 0xE60),
1156
1157         INTC_VECT(SDHI0, 0xE80),
1158         INTC_VECT(SDHI0, 0xEA0),
1159         INTC_VECT(SDHI0, 0xEC0),
1160         INTC_VECT(SDHI0, 0xEE0),
1161
1162         INTC_VECT(CMT,    0xF00),
1163         INTC_VECT(TSIF,   0xF20),
1164         INTC_VECT(FSI,    0xF80),
1165         INTC_VECT(SCIFA5, 0xFA0),
1166
1167         INTC_VECT(TMU0_TUNI0, 0x400),
1168         INTC_VECT(TMU0_TUNI1, 0x420),
1169         INTC_VECT(TMU0_TUNI2, 0x440),
1170
1171         INTC_VECT(IRDA,    0x480),
1172
1173         INTC_VECT(SDHI1, 0x4E0),
1174         INTC_VECT(SDHI1, 0x500),
1175         INTC_VECT(SDHI1, 0x520),
1176
1177         INTC_VECT(JPU, 0x560),
1178         INTC_VECT(_2DDMAC, 0x4A0),
1179
1180         INTC_VECT(MMC_MMC2I, 0x5A0),
1181         INTC_VECT(MMC_MMC3I, 0x5C0),
1182
1183         INTC_VECT(LCDC, 0xF40),
1184
1185         INTC_VECT(TMU1_TUNI0, 0x920),
1186         INTC_VECT(TMU1_TUNI1, 0x940),
1187         INTC_VECT(TMU1_TUNI2, 0x960),
1188 };
1189
1190 static struct intc_group groups[] __initdata = {
1191         INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1192         INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1193         INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1194         INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1195         INTC_GROUP(USB, USB0, USB1),
1196         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1197         INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1198         INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1199         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1200         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1201         INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1202         INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1203 };
1204
1205 static struct intc_mask_reg mask_registers[] __initdata = {
1206         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1207           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1208             0, ENABLED, ENABLED, ENABLED } },
1209         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1210           { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1211             DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1212         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1213           { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1214         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1215           { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1216             SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1217         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1218           { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1219             JPU, 0, 0, LCDC } },
1220         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1221           { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1222             VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1223         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1224           { 0, 0, ICB, SCIFA4,
1225             CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1226         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1227           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1228             I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1229         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1230           { DISABLED, ENABLED, ENABLED, ENABLED,
1231             0, 0, SCIFA5, FSI } },
1232         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1233           { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1234         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1235           { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1236             0, RTC_CUI, RTC_PRI, RTC_ATI } },
1237         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1238           { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1239             0, TPU, 0, TSIF } },
1240         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1241           { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1242         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1243           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1244 };
1245
1246 static struct intc_prio_reg prio_registers[] __initdata = {
1247         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1248                                              TMU0_TUNI2, IRDA } },
1249         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1250         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1251                                              TMU1_TUNI2, SPU } },
1252         { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1253         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1254         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1255         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1256                                              SCIF_SCIF2, VEU0 } },
1257         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1258                                              I2C1, I2C0 } },
1259         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1260         { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1261         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1262         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1263         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1264           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1265 };
1266
1267 static struct intc_sense_reg sense_registers[] __initdata = {
1268         { 0xa414001c, 16, 2, /* ICR1 */
1269           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1270 };
1271
1272 static struct intc_mask_reg ack_registers[] __initdata = {
1273         { 0xa4140024, 0, 8, /* INTREQ00 */
1274           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1275 };
1276
1277 static struct intc_desc intc_desc __initdata = {
1278         .name = "sh7724",
1279         .force_enable = ENABLED,
1280         .force_disable = DISABLED,
1281         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1282                            prio_registers, sense_registers, ack_registers),
1283 };
1284
1285 void __init plat_irq_setup(void)
1286 {
1287         register_intc_controller(&intc_desc);
1288 }
1289
1290 static struct {
1291         /* BSC */
1292         unsigned long mmselr;
1293         unsigned long cs0bcr;
1294         unsigned long cs4bcr;
1295         unsigned long cs5abcr;
1296         unsigned long cs5bbcr;
1297         unsigned long cs6abcr;
1298         unsigned long cs6bbcr;
1299         unsigned long cs4wcr;
1300         unsigned long cs5awcr;
1301         unsigned long cs5bwcr;
1302         unsigned long cs6awcr;
1303         unsigned long cs6bwcr;
1304         /* INTC */
1305         unsigned short ipra;
1306         unsigned short iprb;
1307         unsigned short iprc;
1308         unsigned short iprd;
1309         unsigned short ipre;
1310         unsigned short iprf;
1311         unsigned short iprg;
1312         unsigned short iprh;
1313         unsigned short ipri;
1314         unsigned short iprj;
1315         unsigned short iprk;
1316         unsigned short iprl;
1317         unsigned char imr0;
1318         unsigned char imr1;
1319         unsigned char imr2;
1320         unsigned char imr3;
1321         unsigned char imr4;
1322         unsigned char imr5;
1323         unsigned char imr6;
1324         unsigned char imr7;
1325         unsigned char imr8;
1326         unsigned char imr9;
1327         unsigned char imr10;
1328         unsigned char imr11;
1329         unsigned char imr12;
1330         /* RWDT */
1331         unsigned short rwtcnt;
1332         unsigned short rwtcsr;
1333         /* CPG */
1334         unsigned long irdaclk;
1335         unsigned long spuclk;
1336 } sh7724_rstandby_state;
1337
1338 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1339                                           unsigned long flags, void *unused)
1340 {
1341         if (!(flags & SUSP_SH_RSTANDBY))
1342                 return NOTIFY_DONE;
1343
1344         /* BCR */
1345         sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1346         sh7724_rstandby_state.mmselr |= 0xa5a50000;
1347         sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1348         sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1349         sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1350         sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1351         sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1352         sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1353         sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1354         sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1355         sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1356         sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1357         sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1358
1359         /* INTC */
1360         sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1361         sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1362         sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1363         sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1364         sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1365         sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1366         sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1367         sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1368         sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1369         sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1370         sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1371         sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1372         sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1373         sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1374         sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1375         sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1376         sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1377         sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1378         sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1379         sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1380         sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1381         sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1382         sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1383         sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1384         sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1385
1386         /* RWDT */
1387         sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1388         sh7724_rstandby_state.rwtcnt |= 0x5a00;
1389         sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1390         sh7724_rstandby_state.rwtcsr |= 0xa500;
1391         __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1392
1393         /* CPG */
1394         sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1395         sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1396
1397         return NOTIFY_DONE;
1398 }
1399
1400 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1401                                            unsigned long flags, void *unused)
1402 {
1403         if (!(flags & SUSP_SH_RSTANDBY))
1404                 return NOTIFY_DONE;
1405
1406         /* BCR */
1407         __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1408         __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1409         __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1410         __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1411         __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1412         __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1413         __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1414         __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1415         __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1416         __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1417         __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1418         __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1419
1420         /* INTC */
1421         __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1422         __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1423         __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1424         __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1425         __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1426         __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1427         __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1428         __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1429         __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1430         __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1431         __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1432         __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1433         __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1434         __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1435         __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1436         __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1437         __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1438         __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1439         __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1440         __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1441         __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1442         __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1443         __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1444         __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1445         __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1446
1447         /* RWDT */
1448         __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1449         __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1450
1451         /* CPG */
1452         __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1453         __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1454
1455         return NOTIFY_DONE;
1456 }
1457
1458 static struct notifier_block sh7724_pre_sleep_notifier = {
1459         .notifier_call = sh7724_pre_sleep_notifier_call,
1460         .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1461 };
1462
1463 static struct notifier_block sh7724_post_sleep_notifier = {
1464         .notifier_call = sh7724_post_sleep_notifier_call,
1465         .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1466 };
1467
1468 static int __init sh7724_sleep_setup(void)
1469 {
1470         atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1471                                        &sh7724_pre_sleep_notifier);
1472
1473         atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1474                                        &sh7724_post_sleep_notifier);
1475         return 0;
1476 }
1477 arch_initcall(sh7724_sleep_setup);
1478