]> git.openfabrics.org - ~shefty/rdma-dev.git/blob - arch/sh/kernel/cpu/sh4a/setup-sh7757.c
05559295d2ca8e8fa184e50bcca0a4b224e9d308
[~shefty/rdma-dev.git] / arch / sh / kernel / cpu / sh4a / setup-sh7757.c
1 /*
2  * SH7757 Setup
3  *
4  * Copyright (C) 2009, 2011  Renesas Solutions Corp.
5  *
6  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
7  *
8  * This file is subject to the terms and conditions of the GNU General Public
9  * License.  See the file "COPYING" in the main directory of this archive
10  * for more details.
11  */
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
16 #include <linux/io.h>
17 #include <linux/mm.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/sh_timer.h>
20 #include <linux/sh_dma.h>
21
22 #include <cpu/dma-register.h>
23 #include <cpu/sh7757.h>
24
25 static struct plat_sci_port scif2_platform_data = {
26         .mapbase        = 0xfe4b0000,           /* SCIF2 */
27         .flags          = UPF_BOOT_AUTOCONF,
28         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29         .scbrr_algo_id  = SCBRR_ALGO_2,
30         .type           = PORT_SCIF,
31         .irqs           = { 40, 40, 40, 40 },
32 };
33
34 static struct platform_device scif2_device = {
35         .name           = "sh-sci",
36         .id             = 0,
37         .dev            = {
38                 .platform_data  = &scif2_platform_data,
39         },
40 };
41
42 static struct plat_sci_port scif3_platform_data = {
43         .mapbase        = 0xfe4c0000,           /* SCIF3 */
44         .flags          = UPF_BOOT_AUTOCONF,
45         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
46         .scbrr_algo_id  = SCBRR_ALGO_2,
47         .type           = PORT_SCIF,
48         .irqs           = { 76, 76, 76, 76 },
49 };
50
51 static struct platform_device scif3_device = {
52         .name           = "sh-sci",
53         .id             = 1,
54         .dev            = {
55                 .platform_data  = &scif3_platform_data,
56         },
57 };
58
59 static struct plat_sci_port scif4_platform_data = {
60         .mapbase        = 0xfe4d0000,           /* SCIF4 */
61         .flags          = UPF_BOOT_AUTOCONF,
62         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
63         .scbrr_algo_id  = SCBRR_ALGO_2,
64         .type           = PORT_SCIF,
65         .irqs           = { 104, 104, 104, 104 },
66 };
67
68 static struct platform_device scif4_device = {
69         .name           = "sh-sci",
70         .id             = 2,
71         .dev            = {
72                 .platform_data  = &scif4_platform_data,
73         },
74 };
75
76 static struct sh_timer_config tmu0_platform_data = {
77         .channel_offset = 0x04,
78         .timer_bit = 0,
79         .clockevent_rating = 200,
80 };
81
82 static struct resource tmu0_resources[] = {
83         [0] = {
84                 .start  = 0xfe430008,
85                 .end    = 0xfe430013,
86                 .flags  = IORESOURCE_MEM,
87         },
88         [1] = {
89                 .start  = 28,
90                 .flags  = IORESOURCE_IRQ,
91         },
92 };
93
94 static struct platform_device tmu0_device = {
95         .name           = "sh_tmu",
96         .id             = 0,
97         .dev = {
98                 .platform_data  = &tmu0_platform_data,
99         },
100         .resource       = tmu0_resources,
101         .num_resources  = ARRAY_SIZE(tmu0_resources),
102 };
103
104 static struct sh_timer_config tmu1_platform_data = {
105         .channel_offset = 0x10,
106         .timer_bit = 1,
107         .clocksource_rating = 200,
108 };
109
110 static struct resource tmu1_resources[] = {
111         [0] = {
112                 .start  = 0xfe430014,
113                 .end    = 0xfe43001f,
114                 .flags  = IORESOURCE_MEM,
115         },
116         [1] = {
117                 .start  = 29,
118                 .flags  = IORESOURCE_IRQ,
119         },
120 };
121
122 static struct platform_device tmu1_device = {
123         .name           = "sh_tmu",
124         .id             = 1,
125         .dev = {
126                 .platform_data  = &tmu1_platform_data,
127         },
128         .resource       = tmu1_resources,
129         .num_resources  = ARRAY_SIZE(tmu1_resources),
130 };
131
132 static struct resource spi0_resources[] = {
133         [0] = {
134                 .start  = 0xfe002000,
135                 .end    = 0xfe0020ff,
136                 .flags  = IORESOURCE_MEM,
137         },
138         [1] = {
139                 .start  = 86,
140                 .flags  = IORESOURCE_IRQ,
141         },
142 };
143
144 /* DMA */
145 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
146         {
147                 .slave_id       = SHDMA_SLAVE_SDHI_TX,
148                 .addr           = 0x1fe50030,
149                 .chcr           = SM_INC | 0x800 | 0x40000000 |
150                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
151                 .mid_rid        = 0xc5,
152         },
153         {
154                 .slave_id       = SHDMA_SLAVE_SDHI_RX,
155                 .addr           = 0x1fe50030,
156                 .chcr           = DM_INC | 0x800 | 0x40000000 |
157                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
158                 .mid_rid        = 0xc6,
159         },
160         {
161                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
162                 .addr           = 0x1fcb0034,
163                 .chcr           = SM_INC | 0x800 | 0x40000000 |
164                                   TS_INDEX2VAL(XMIT_SZ_32BIT),
165                 .mid_rid        = 0xd3,
166         },
167         {
168                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
169                 .addr           = 0x1fcb0034,
170                 .chcr           = DM_INC | 0x800 | 0x40000000 |
171                                   TS_INDEX2VAL(XMIT_SZ_32BIT),
172                 .mid_rid        = 0xd7,
173         },
174 };
175
176 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
177         {
178                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
179                 .addr           = 0x1f4b000c,
180                 .chcr           = SM_INC | 0x800 | 0x40000000 |
181                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
182                 .mid_rid        = 0x21,
183         },
184         {
185                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
186                 .addr           = 0x1f4b0014,
187                 .chcr           = DM_INC | 0x800 | 0x40000000 |
188                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
189                 .mid_rid        = 0x22,
190         },
191         {
192                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
193                 .addr           = 0x1f4c000c,
194                 .chcr           = SM_INC | 0x800 | 0x40000000 |
195                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
196                 .mid_rid        = 0x29,
197         },
198         {
199                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
200                 .addr           = 0x1f4c0014,
201                 .chcr           = DM_INC | 0x800 | 0x40000000 |
202                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
203                 .mid_rid        = 0x2a,
204         },
205         {
206                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
207                 .addr           = 0x1f4d000c,
208                 .chcr           = SM_INC | 0x800 | 0x40000000 |
209                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
210                 .mid_rid        = 0x41,
211         },
212         {
213                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
214                 .addr           = 0x1f4d0014,
215                 .chcr           = DM_INC | 0x800 | 0x40000000 |
216                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
217                 .mid_rid        = 0x42,
218         },
219 };
220
221 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
222         {
223                 .slave_id       = SHDMA_SLAVE_RIIC0_TX,
224                 .addr           = 0x1e500012,
225                 .chcr           = SM_INC | 0x800 | 0x40000000 |
226                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
227                 .mid_rid        = 0x21,
228         },
229         {
230                 .slave_id       = SHDMA_SLAVE_RIIC0_RX,
231                 .addr           = 0x1e500013,
232                 .chcr           = DM_INC | 0x800 | 0x40000000 |
233                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
234                 .mid_rid        = 0x22,
235         },
236         {
237                 .slave_id       = SHDMA_SLAVE_RIIC1_TX,
238                 .addr           = 0x1e510012,
239                 .chcr           = SM_INC | 0x800 | 0x40000000 |
240                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
241                 .mid_rid        = 0x29,
242         },
243         {
244                 .slave_id       = SHDMA_SLAVE_RIIC1_RX,
245                 .addr           = 0x1e510013,
246                 .chcr           = DM_INC | 0x800 | 0x40000000 |
247                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
248                 .mid_rid        = 0x2a,
249         },
250         {
251                 .slave_id       = SHDMA_SLAVE_RIIC2_TX,
252                 .addr           = 0x1e520012,
253                 .chcr           = SM_INC | 0x800 | 0x40000000 |
254                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
255                 .mid_rid        = 0xa1,
256         },
257         {
258                 .slave_id       = SHDMA_SLAVE_RIIC2_RX,
259                 .addr           = 0x1e520013,
260                 .chcr           = DM_INC | 0x800 | 0x40000000 |
261                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
262                 .mid_rid        = 0xa2,
263         },
264         {
265                 .slave_id       = SHDMA_SLAVE_RIIC3_TX,
266                 .addr           = 0x1e530012,
267                 .chcr           = SM_INC | 0x800 | 0x40000000 |
268                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
269                 .mid_rid        = 0xa9,
270         },
271         {
272                 .slave_id       = SHDMA_SLAVE_RIIC3_RX,
273                 .addr           = 0x1e530013,
274                 .chcr           = DM_INC | 0x800 | 0x40000000 |
275                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
276                 .mid_rid        = 0xaf,
277         },
278         {
279                 .slave_id       = SHDMA_SLAVE_RIIC4_TX,
280                 .addr           = 0x1e540012,
281                 .chcr           = SM_INC | 0x800 | 0x40000000 |
282                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
283                 .mid_rid        = 0xc5,
284         },
285         {
286                 .slave_id       = SHDMA_SLAVE_RIIC4_RX,
287                 .addr           = 0x1e540013,
288                 .chcr           = DM_INC | 0x800 | 0x40000000 |
289                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
290                 .mid_rid        = 0xc6,
291         },
292 };
293
294 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
295         {
296                 .slave_id       = SHDMA_SLAVE_RIIC5_TX,
297                 .addr           = 0x1e550012,
298                 .chcr           = SM_INC | 0x800 | 0x40000000 |
299                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
300                 .mid_rid        = 0x21,
301         },
302         {
303                 .slave_id       = SHDMA_SLAVE_RIIC5_RX,
304                 .addr           = 0x1e550013,
305                 .chcr           = DM_INC | 0x800 | 0x40000000 |
306                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
307                 .mid_rid        = 0x22,
308         },
309         {
310                 .slave_id       = SHDMA_SLAVE_RIIC6_TX,
311                 .addr           = 0x1e560012,
312                 .chcr           = SM_INC | 0x800 | 0x40000000 |
313                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
314                 .mid_rid        = 0x29,
315         },
316         {
317                 .slave_id       = SHDMA_SLAVE_RIIC6_RX,
318                 .addr           = 0x1e560013,
319                 .chcr           = DM_INC | 0x800 | 0x40000000 |
320                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
321                 .mid_rid        = 0x2a,
322         },
323         {
324                 .slave_id       = SHDMA_SLAVE_RIIC7_TX,
325                 .addr           = 0x1e570012,
326                 .chcr           = SM_INC | 0x800 | 0x40000000 |
327                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
328                 .mid_rid        = 0x41,
329         },
330         {
331                 .slave_id       = SHDMA_SLAVE_RIIC7_RX,
332                 .addr           = 0x1e570013,
333                 .chcr           = DM_INC | 0x800 | 0x40000000 |
334                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
335                 .mid_rid        = 0x42,
336         },
337         {
338                 .slave_id       = SHDMA_SLAVE_RIIC8_TX,
339                 .addr           = 0x1e580012,
340                 .chcr           = SM_INC | 0x800 | 0x40000000 |
341                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
342                 .mid_rid        = 0x45,
343         },
344         {
345                 .slave_id       = SHDMA_SLAVE_RIIC8_RX,
346                 .addr           = 0x1e580013,
347                 .chcr           = DM_INC | 0x800 | 0x40000000 |
348                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
349                 .mid_rid        = 0x46,
350         },
351         {
352                 .slave_id       = SHDMA_SLAVE_RIIC9_TX,
353                 .addr           = 0x1e590012,
354                 .chcr           = SM_INC | 0x800 | 0x40000000 |
355                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
356                 .mid_rid        = 0x51,
357         },
358         {
359                 .slave_id       = SHDMA_SLAVE_RIIC9_RX,
360                 .addr           = 0x1e590013,
361                 .chcr           = DM_INC | 0x800 | 0x40000000 |
362                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
363                 .mid_rid        = 0x52,
364         },
365 };
366
367 static const struct sh_dmae_channel sh7757_dmae_channels[] = {
368         {
369                 .offset = 0,
370                 .dmars = 0,
371                 .dmars_bit = 0,
372         }, {
373                 .offset = 0x10,
374                 .dmars = 0,
375                 .dmars_bit = 8,
376         }, {
377                 .offset = 0x20,
378                 .dmars = 4,
379                 .dmars_bit = 0,
380         }, {
381                 .offset = 0x30,
382                 .dmars = 4,
383                 .dmars_bit = 8,
384         }, {
385                 .offset = 0x50,
386                 .dmars = 8,
387                 .dmars_bit = 0,
388         }, {
389                 .offset = 0x60,
390                 .dmars = 8,
391                 .dmars_bit = 8,
392         }
393 };
394
395 static const unsigned int ts_shift[] = TS_SHIFT;
396
397 static struct sh_dmae_pdata dma0_platform_data = {
398         .slave          = sh7757_dmae0_slaves,
399         .slave_num      = ARRAY_SIZE(sh7757_dmae0_slaves),
400         .channel        = sh7757_dmae_channels,
401         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
402         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
403         .ts_low_mask    = CHCR_TS_LOW_MASK,
404         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
405         .ts_high_mask   = CHCR_TS_HIGH_MASK,
406         .ts_shift       = ts_shift,
407         .ts_shift_num   = ARRAY_SIZE(ts_shift),
408         .dmaor_init     = DMAOR_INIT,
409 };
410
411 static struct sh_dmae_pdata dma1_platform_data = {
412         .slave          = sh7757_dmae1_slaves,
413         .slave_num      = ARRAY_SIZE(sh7757_dmae1_slaves),
414         .channel        = sh7757_dmae_channels,
415         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
416         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
417         .ts_low_mask    = CHCR_TS_LOW_MASK,
418         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
419         .ts_high_mask   = CHCR_TS_HIGH_MASK,
420         .ts_shift       = ts_shift,
421         .ts_shift_num   = ARRAY_SIZE(ts_shift),
422         .dmaor_init     = DMAOR_INIT,
423 };
424
425 static struct sh_dmae_pdata dma2_platform_data = {
426         .slave          = sh7757_dmae2_slaves,
427         .slave_num      = ARRAY_SIZE(sh7757_dmae2_slaves),
428         .channel        = sh7757_dmae_channels,
429         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
430         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
431         .ts_low_mask    = CHCR_TS_LOW_MASK,
432         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
433         .ts_high_mask   = CHCR_TS_HIGH_MASK,
434         .ts_shift       = ts_shift,
435         .ts_shift_num   = ARRAY_SIZE(ts_shift),
436         .dmaor_init     = DMAOR_INIT,
437 };
438
439 static struct sh_dmae_pdata dma3_platform_data = {
440         .slave          = sh7757_dmae3_slaves,
441         .slave_num      = ARRAY_SIZE(sh7757_dmae3_slaves),
442         .channel        = sh7757_dmae_channels,
443         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
444         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
445         .ts_low_mask    = CHCR_TS_LOW_MASK,
446         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
447         .ts_high_mask   = CHCR_TS_HIGH_MASK,
448         .ts_shift       = ts_shift,
449         .ts_shift_num   = ARRAY_SIZE(ts_shift),
450         .dmaor_init     = DMAOR_INIT,
451 };
452
453 /* channel 0 to 5 */
454 static struct resource sh7757_dmae0_resources[] = {
455         [0] = {
456                 /* Channel registers and DMAOR */
457                 .start  = 0xff608020,
458                 .end    = 0xff60808f,
459                 .flags  = IORESOURCE_MEM,
460         },
461         [1] = {
462                 /* DMARSx */
463                 .start  = 0xff609000,
464                 .end    = 0xff60900b,
465                 .flags  = IORESOURCE_MEM,
466         },
467         {
468                 .start  = 34,
469                 .end    = 34,
470                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
471         },
472 };
473
474 /* channel 6 to 11 */
475 static struct resource sh7757_dmae1_resources[] = {
476         [0] = {
477                 /* Channel registers and DMAOR */
478                 .start  = 0xff618020,
479                 .end    = 0xff61808f,
480                 .flags  = IORESOURCE_MEM,
481         },
482         [1] = {
483                 /* DMARSx */
484                 .start  = 0xff619000,
485                 .end    = 0xff61900b,
486                 .flags  = IORESOURCE_MEM,
487         },
488         {
489                 /* DMA error */
490                 .start  = 34,
491                 .end    = 34,
492                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
493         },
494         {
495                 /* IRQ for channels 4 */
496                 .start  = 46,
497                 .end    = 46,
498                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
499         },
500         {
501                 /* IRQ for channels 5 */
502                 .start  = 46,
503                 .end    = 46,
504                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
505         },
506         {
507                 /* IRQ for channels 6 */
508                 .start  = 88,
509                 .end    = 88,
510                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
511         },
512         {
513                 /* IRQ for channels 7 */
514                 .start  = 88,
515                 .end    = 88,
516                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
517         },
518         {
519                 /* IRQ for channels 8 */
520                 .start  = 88,
521                 .end    = 88,
522                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
523         },
524         {
525                 /* IRQ for channels 9 */
526                 .start  = 88,
527                 .end    = 88,
528                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
529         },
530         {
531                 /* IRQ for channels 10 */
532                 .start  = 88,
533                 .end    = 88,
534                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
535         },
536         {
537                 /* IRQ for channels 11 */
538                 .start  = 88,
539                 .end    = 88,
540                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
541         },
542 };
543
544 /* channel 12 to 17 */
545 static struct resource sh7757_dmae2_resources[] = {
546         [0] = {
547                 /* Channel registers and DMAOR */
548                 .start  = 0xff708020,
549                 .end    = 0xff70808f,
550                 .flags  = IORESOURCE_MEM,
551         },
552         [1] = {
553                 /* DMARSx */
554                 .start  = 0xff709000,
555                 .end    = 0xff70900b,
556                 .flags  = IORESOURCE_MEM,
557         },
558         {
559                 /* DMA error */
560                 .start  = 323,
561                 .end    = 323,
562                 .flags  = IORESOURCE_IRQ,
563         },
564         {
565                 /* IRQ for channels 12 to 16 */
566                 .start  = 272,
567                 .end    = 276,
568                 .flags  = IORESOURCE_IRQ,
569         },
570         {
571                 /* IRQ for channel 17 */
572                 .start  = 279,
573                 .end    = 279,
574                 .flags  = IORESOURCE_IRQ,
575         },
576 };
577
578 /* channel 18 to 23 */
579 static struct resource sh7757_dmae3_resources[] = {
580         [0] = {
581                 /* Channel registers and DMAOR */
582                 .start  = 0xff718020,
583                 .end    = 0xff71808f,
584                 .flags  = IORESOURCE_MEM,
585         },
586         [1] = {
587                 /* DMARSx */
588                 .start  = 0xff719000,
589                 .end    = 0xff71900b,
590                 .flags  = IORESOURCE_MEM,
591         },
592         {
593                 /* DMA error */
594                 .start  = 324,
595                 .end    = 324,
596                 .flags  = IORESOURCE_IRQ,
597         },
598         {
599                 /* IRQ for channels 18 to 22 */
600                 .start  = 280,
601                 .end    = 284,
602                 .flags  = IORESOURCE_IRQ,
603         },
604         {
605                 /* IRQ for channel 23 */
606                 .start  = 288,
607                 .end    = 288,
608                 .flags  = IORESOURCE_IRQ,
609         },
610 };
611
612 static struct platform_device dma0_device = {
613         .name           = "sh-dma-engine",
614         .id             = 0,
615         .resource       = sh7757_dmae0_resources,
616         .num_resources  = ARRAY_SIZE(sh7757_dmae0_resources),
617         .dev            = {
618                 .platform_data  = &dma0_platform_data,
619         },
620 };
621
622 static struct platform_device dma1_device = {
623         .name           = "sh-dma-engine",
624         .id             = 1,
625         .resource       = sh7757_dmae1_resources,
626         .num_resources  = ARRAY_SIZE(sh7757_dmae1_resources),
627         .dev            = {
628                 .platform_data  = &dma1_platform_data,
629         },
630 };
631
632 static struct platform_device dma2_device = {
633         .name           = "sh-dma-engine",
634         .id             = 2,
635         .resource       = sh7757_dmae2_resources,
636         .num_resources  = ARRAY_SIZE(sh7757_dmae2_resources),
637         .dev            = {
638                 .platform_data  = &dma2_platform_data,
639         },
640 };
641
642 static struct platform_device dma3_device = {
643         .name           = "sh-dma-engine",
644         .id             = 3,
645         .resource       = sh7757_dmae3_resources,
646         .num_resources  = ARRAY_SIZE(sh7757_dmae3_resources),
647         .dev            = {
648                 .platform_data  = &dma3_platform_data,
649         },
650 };
651
652 static struct platform_device spi0_device = {
653         .name   = "sh_spi",
654         .id     = 0,
655         .dev    = {
656                 .dma_mask               = NULL,
657                 .coherent_dma_mask      = 0xffffffff,
658         },
659         .num_resources  = ARRAY_SIZE(spi0_resources),
660         .resource       = spi0_resources,
661 };
662
663 static struct resource usb_ehci_resources[] = {
664         [0] = {
665                 .start  = 0xfe4f1000,
666                 .end    = 0xfe4f10ff,
667                 .flags  = IORESOURCE_MEM,
668         },
669         [1] = {
670                 .start  = 57,
671                 .end    = 57,
672                 .flags  = IORESOURCE_IRQ,
673         },
674 };
675
676 static struct platform_device usb_ehci_device = {
677         .name           = "sh_ehci",
678         .id             = -1,
679         .dev = {
680                 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
681                 .coherent_dma_mask = DMA_BIT_MASK(32),
682         },
683         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
684         .resource       = usb_ehci_resources,
685 };
686
687 static struct resource usb_ohci_resources[] = {
688         [0] = {
689                 .start  = 0xfe4f1800,
690                 .end    = 0xfe4f18ff,
691                 .flags  = IORESOURCE_MEM,
692         },
693         [1] = {
694                 .start  = 57,
695                 .end    = 57,
696                 .flags  = IORESOURCE_IRQ,
697         },
698 };
699
700 static struct platform_device usb_ohci_device = {
701         .name           = "sh_ohci",
702         .id             = -1,
703         .dev = {
704                 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
705                 .coherent_dma_mask = DMA_BIT_MASK(32),
706         },
707         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
708         .resource       = usb_ohci_resources,
709 };
710
711 static struct platform_device *sh7757_devices[] __initdata = {
712         &scif2_device,
713         &scif3_device,
714         &scif4_device,
715         &tmu0_device,
716         &tmu1_device,
717         &dma0_device,
718         &dma1_device,
719         &dma2_device,
720         &dma3_device,
721         &spi0_device,
722         &usb_ehci_device,
723         &usb_ohci_device,
724 };
725
726 static int __init sh7757_devices_setup(void)
727 {
728         return platform_add_devices(sh7757_devices,
729                                     ARRAY_SIZE(sh7757_devices));
730 }
731 arch_initcall(sh7757_devices_setup);
732
733 static struct platform_device *sh7757_early_devices[] __initdata = {
734         &scif2_device,
735         &scif3_device,
736         &scif4_device,
737         &tmu0_device,
738         &tmu1_device,
739 };
740
741 void __init plat_early_device_setup(void)
742 {
743         early_platform_add_devices(sh7757_early_devices,
744                                    ARRAY_SIZE(sh7757_early_devices));
745 }
746
747 enum {
748         UNUSED = 0,
749
750         /* interrupt sources */
751
752         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
753         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
754         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
755         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
756
757         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
758         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
759         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
760         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
761         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
762
763         SDHI, DVC,
764         IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
765         TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
766         HUDI,
767         ARC4,
768         DMAC0_5, DMAC6_7, DMAC8_11,
769         SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
770         USB0, USB1,
771         JMC,
772         SPI0, SPI1,
773         TMR01, TMR23, TMR45,
774         FRT,
775         LPC, LPC5, LPC6, LPC7, LPC8,
776         PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
777         ETHERC,
778         ADC0, ADC1,
779         SIM,
780         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
781         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
782         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
783         IIC3_0, IIC3_1, IIC3_2, IIC3_3,
784         IIC4_0, IIC4_1, IIC4_2, IIC4_3,
785         IIC5_0, IIC5_1, IIC5_2, IIC5_3,
786         IIC6_0, IIC6_1, IIC6_2, IIC6_3,
787         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
788         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
789         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
790         ONFICTL,
791         MMC1, MMC2,
792         ECCU,
793         PCIC,
794         G200,
795         RSPI,
796         SGPIO,
797         DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
798         DMINT20, DMINT21, DMINT22, DMINT23,
799         DDRECC,
800         TSIP,
801         PCIE_BRIDGE,
802         WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
803         GETHER0, GETHER1, GETHER2,
804         PBIA, PBIB, PBIC,
805         DMAE2, DMAE3,
806         SERMUX2, SERMUX3,
807
808         /* interrupt groups */
809
810         TMU012, TMU345,
811 };
812
813 static struct intc_vect vectors[] __initdata = {
814         INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
815         INTC_VECT(SDHI, 0x4c0),
816         INTC_VECT(DVC, 0x4e0),
817         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
818         INTC_VECT(IRQ10, 0x540),
819         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
820         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
821         INTC_VECT(HUDI, 0x600),
822         INTC_VECT(ARC4, 0x620),
823         INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
824         INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
825         INTC_VECT(DMAC0_5, 0x6c0),
826         INTC_VECT(IRQ11, 0x6e0),
827         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
828         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
829         INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
830         INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
831         INTC_VECT(USB0, 0x840),
832         INTC_VECT(IRQ12, 0x880),
833         INTC_VECT(JMC, 0x8a0),
834         INTC_VECT(SPI1, 0x8c0),
835         INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
836         INTC_VECT(USB1, 0x920),
837         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
838         INTC_VECT(TMR45, 0xa40),
839         INTC_VECT(FRT, 0xa80),
840         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
841         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
842         INTC_VECT(LPC, 0xb20),
843         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
844         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
845         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
846         INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
847         INTC_VECT(PECI2, 0xc40),
848         INTC_VECT(IRQ15, 0xc60),
849         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
850         INTC_VECT(SPI0, 0xcc0),
851         INTC_VECT(ADC1, 0xce0),
852         INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
853         INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
854         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
855         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
856         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
857         INTC_VECT(TMU5, 0xe40),
858         INTC_VECT(ADC0, 0xe60),
859         INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
860         INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
861         INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
862         INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
863         INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
864         INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
865         INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
866         INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
867         INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
868         INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
869         INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
870         INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
871         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
872         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
873         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
874         INTC_VECT(IIC6_2, 0x1920),
875         INTC_VECT(ONFICTL, 0x1960),
876         INTC_VECT(IIC6_3, 0x1980),
877         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
878         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
879         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
880         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
881         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
882         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
883         INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
884         INTC_VECT(ECCU, 0x1cc0),
885         INTC_VECT(PCIC, 0x1ce0),
886         INTC_VECT(G200, 0x1d00),
887         INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
888         INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
889         INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
890         INTC_VECT(PECI5, 0x1f00),
891         INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
892         INTC_VECT(SGPIO, 0x1fc0),
893         INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
894         INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
895         INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
896         INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
897         INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
898         INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
899         INTC_VECT(DDRECC, 0x2620),
900         INTC_VECT(TSIP, 0x2640),
901         INTC_VECT(PCIE_BRIDGE, 0x27c0),
902         INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
903         INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
904         INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
905         INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
906         INTC_VECT(WDT8B, 0x2900),
907         INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
908         INTC_VECT(GETHER2, 0x29a0),
909         INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
910         INTC_VECT(PBIC, 0x2a40),
911         INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
912         INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
913         INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
914         INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
915 };
916
917 static struct intc_group groups[] __initdata = {
918         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
919         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
920 };
921
922 static struct intc_mask_reg mask_registers[] __initdata = {
923         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
924           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
925
926         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
927           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
928             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
929             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
930             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
931             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
932             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
933             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
934             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
935
936         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
937           { 0, 0, 0, 0, 0, 0, 0, 0,
938             0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
939             TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
940             HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
941              } },
942
943         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
944           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
945             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
946             ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
947             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
948              } },
949
950         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
951           { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
952             0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
953             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
954             IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
955              } },
956
957         { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
958           { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
959             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
960             PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
961             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
962              } },
963
964         { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
965           { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
966             0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
967             PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
968             DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
969              } },
970
971         { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
972           { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
973             DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
974             0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
975             DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
976              } },
977 };
978
979 #define INTPRI          0xffd00010
980 #define INT2PRI0        0xffd40000
981 #define INT2PRI1        0xffd40004
982 #define INT2PRI2        0xffd40008
983 #define INT2PRI3        0xffd4000c
984 #define INT2PRI4        0xffd40010
985 #define INT2PRI5        0xffd40014
986 #define INT2PRI6        0xffd40018
987 #define INT2PRI7        0xffd4001c
988 #define INT2PRI8        0xffd400a0
989 #define INT2PRI9        0xffd400a4
990 #define INT2PRI10       0xffd400a8
991 #define INT2PRI11       0xffd400ac
992 #define INT2PRI12       0xffd400b0
993 #define INT2PRI13       0xffd400b4
994 #define INT2PRI14       0xffd400b8
995 #define INT2PRI15       0xffd400bc
996 #define INT2PRI16       0xffd10000
997 #define INT2PRI17       0xffd10004
998 #define INT2PRI18       0xffd10008
999 #define INT2PRI19       0xffd1000c
1000 #define INT2PRI20       0xffd10010
1001 #define INT2PRI21       0xffd10014
1002 #define INT2PRI22       0xffd10018
1003 #define INT2PRI23       0xffd1001c
1004 #define INT2PRI24       0xffd100a0
1005 #define INT2PRI25       0xffd100a4
1006 #define INT2PRI26       0xffd100a8
1007 #define INT2PRI27       0xffd100ac
1008 #define INT2PRI28       0xffd100b0
1009 #define INT2PRI29       0xffd100b4
1010 #define INT2PRI30       0xffd100b8
1011 #define INT2PRI31       0xffd100bc
1012 #define INT2PRI32       0xffd20000
1013 #define INT2PRI33       0xffd20004
1014 #define INT2PRI34       0xffd20008
1015 #define INT2PRI35       0xffd2000c
1016 #define INT2PRI36       0xffd20010
1017 #define INT2PRI37       0xffd20014
1018 #define INT2PRI38       0xffd20018
1019 #define INT2PRI39       0xffd2001c
1020 #define INT2PRI40       0xffd200a0
1021 #define INT2PRI41       0xffd200a4
1022 #define INT2PRI42       0xffd200a8
1023 #define INT2PRI43       0xffd200ac
1024 #define INT2PRI44       0xffd200b0
1025 #define INT2PRI45       0xffd200b4
1026 #define INT2PRI46       0xffd200b8
1027 #define INT2PRI47       0xffd200bc
1028
1029 static struct intc_prio_reg prio_registers[] __initdata = {
1030         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
1031                               IRQ4, IRQ5, IRQ6, IRQ7 } },
1032
1033         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
1034         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
1035         { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
1036         { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
1037         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
1038         { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
1039         { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
1040         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
1041         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
1042         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
1043         { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
1044         { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
1045         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
1046         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
1047
1048         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
1049         { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
1050         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1051         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1052         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1053         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
1054         { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1055         { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1056         { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
1057         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
1058         { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1059         { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1060         { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
1061         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
1062         { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
1063         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1064         { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1065         { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1066         { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1067         { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1068         { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1069         { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1070         { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1071         { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1072         { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1073         { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1074         { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1075         { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1076         { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1077         { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1078         { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1079         { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1080 };
1081
1082 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1083         { 0xffd100f8, 32, 2, /* ICR2 */   { IRQ15, IRQ14, IRQ13, IRQ12,
1084                                             IRQ11, IRQ10, IRQ9, IRQ8 } },
1085 };
1086
1087 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
1088                          mask_registers, prio_registers,
1089                          sense_registers_irq8to15);
1090
1091 /* Support for external interrupt pins in IRQ mode */
1092 static struct intc_vect vectors_irq0123[] __initdata = {
1093         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
1094         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
1095 };
1096
1097 static struct intc_vect vectors_irq4567[] __initdata = {
1098         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
1099         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
1100 };
1101
1102 static struct intc_sense_reg sense_registers[] __initdata = {
1103         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
1104                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
1105 };
1106
1107 static struct intc_mask_reg ack_registers[] __initdata = {
1108         { 0xffd00024, 0, 32, /* INTREQ */
1109           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1110 };
1111
1112 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
1113                              vectors_irq0123, NULL, mask_registers,
1114                              prio_registers, sense_registers, ack_registers);
1115
1116 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
1117                              vectors_irq4567, NULL, mask_registers,
1118                              prio_registers, sense_registers, ack_registers);
1119
1120 /* External interrupt pins in IRL mode */
1121 static struct intc_vect vectors_irl0123[] __initdata = {
1122         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1123         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1124         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1125         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1126         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1127         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1128         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1129         INTC_VECT(IRL0_HHHL, 0x3c0),
1130 };
1131
1132 static struct intc_vect vectors_irl4567[] __initdata = {
1133         INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
1134         INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
1135         INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
1136         INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
1137         INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
1138         INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
1139         INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
1140         INTC_VECT(IRL4_HHHL, 0x3c0),
1141 };
1142
1143 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
1144                          NULL, mask_registers, NULL, NULL);
1145
1146 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
1147                          NULL, mask_registers, NULL, NULL);
1148
1149 #define INTC_ICR0       0xffd00000
1150 #define INTC_INTMSK0    0xffd00044
1151 #define INTC_INTMSK1    0xffd00048
1152 #define INTC_INTMSK2    0xffd40080
1153 #define INTC_INTMSKCLR1 0xffd00068
1154 #define INTC_INTMSKCLR2 0xffd40084
1155
1156 void __init plat_irq_setup(void)
1157 {
1158         /* disable IRQ3-0 + IRQ7-4 */
1159         __raw_writel(0xff000000, INTC_INTMSK0);
1160
1161         /* disable IRL3-0 + IRL7-4 */
1162         __raw_writel(0xc0000000, INTC_INTMSK1);
1163         __raw_writel(0xfffefffe, INTC_INTMSK2);
1164
1165         /* select IRL mode for IRL3-0 + IRL7-4 */
1166         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
1167
1168         /* disable holding function, ie enable "SH-4 Mode" */
1169         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
1170
1171         register_intc_controller(&intc_desc);
1172 }
1173
1174 void __init plat_irq_setup_pins(int mode)
1175 {
1176         switch (mode) {
1177         case IRQ_MODE_IRQ7654:
1178                 /* select IRQ mode for IRL7-4 */
1179                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
1180                 register_intc_controller(&intc_desc_irq4567);
1181                 break;
1182         case IRQ_MODE_IRQ3210:
1183                 /* select IRQ mode for IRL3-0 */
1184                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
1185                 register_intc_controller(&intc_desc_irq0123);
1186                 break;
1187         case IRQ_MODE_IRL7654:
1188                 /* enable IRL7-4 but don't provide any masking */
1189                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1190                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1191                 break;
1192         case IRQ_MODE_IRL3210:
1193                 /* enable IRL0-3 but don't provide any masking */
1194                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1195                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1196                 break;
1197         case IRQ_MODE_IRL7654_MASK:
1198                 /* enable IRL7-4 and mask using cpu intc controller */
1199                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1200                 register_intc_controller(&intc_desc_irl4567);
1201                 break;
1202         case IRQ_MODE_IRL3210_MASK:
1203                 /* enable IRL0-3 and mask using cpu intc controller */
1204                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1205                 register_intc_controller(&intc_desc_irl0123);
1206                 break;
1207         default:
1208                 BUG();
1209         }
1210 }
1211
1212 void __init plat_mem_setup(void)
1213 {
1214 }