Merge branch 'common/serial-rework' into sh-latest
[~shefty/rdma-dev.git] / arch / sh / kernel / cpu / sh4a / setup-sh7785.c
1 /*
2  * SH7785 Setup
3  *
4  *  Copyright (C) 2007  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/io.h>
15 #include <linux/mm.h>
16 #include <linux/sh_dma.h>
17 #include <linux/sh_timer.h>
18
19 #include <asm/mmzone.h>
20
21 #include <cpu/dma-register.h>
22
23 static struct plat_sci_port scif0_platform_data = {
24         .mapbase        = 0xffea0000,
25         .flags          = UPF_BOOT_AUTOCONF,
26         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
27         .scbrr_algo_id  = SCBRR_ALGO_1,
28         .type           = PORT_SCIF,
29         .irqs           = { 40, 40, 40, 40 },
30 };
31
32 static struct platform_device scif0_device = {
33         .name           = "sh-sci",
34         .id             = 0,
35         .dev            = {
36                 .platform_data  = &scif0_platform_data,
37         },
38 };
39
40 static struct plat_sci_port scif1_platform_data = {
41         .mapbase        = 0xffeb0000,
42         .flags          = UPF_BOOT_AUTOCONF,
43         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44         .scbrr_algo_id  = SCBRR_ALGO_1,
45         .type           = PORT_SCIF,
46         .irqs           = { 44, 44, 44, 44 },
47 };
48
49 static struct platform_device scif1_device = {
50         .name           = "sh-sci",
51         .id             = 1,
52         .dev            = {
53                 .platform_data  = &scif1_platform_data,
54         },
55 };
56
57 static struct plat_sci_port scif2_platform_data = {
58         .mapbase        = 0xffec0000,
59         .flags          = UPF_BOOT_AUTOCONF,
60         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
61         .scbrr_algo_id  = SCBRR_ALGO_1,
62         .type           = PORT_SCIF,
63         .irqs           = { 60, 60, 60, 60 },
64 };
65
66 static struct platform_device scif2_device = {
67         .name           = "sh-sci",
68         .id             = 2,
69         .dev            = {
70                 .platform_data  = &scif2_platform_data,
71         },
72 };
73
74 static struct plat_sci_port scif3_platform_data = {
75         .mapbase        = 0xffed0000,
76         .flags          = UPF_BOOT_AUTOCONF,
77         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
78         .scbrr_algo_id  = SCBRR_ALGO_1,
79         .type           = PORT_SCIF,
80         .irqs           = { 61, 61, 61, 61 },
81 };
82
83 static struct platform_device scif3_device = {
84         .name           = "sh-sci",
85         .id             = 3,
86         .dev            = {
87                 .platform_data  = &scif3_platform_data,
88         },
89 };
90
91 static struct plat_sci_port scif4_platform_data = {
92         .mapbase        = 0xffee0000,
93         .flags          = UPF_BOOT_AUTOCONF,
94         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
95         .scbrr_algo_id  = SCBRR_ALGO_1,
96         .type           = PORT_SCIF,
97         .irqs           = { 62, 62, 62, 62 },
98 };
99
100 static struct platform_device scif4_device = {
101         .name           = "sh-sci",
102         .id             = 4,
103         .dev            = {
104                 .platform_data  = &scif4_platform_data,
105         },
106 };
107
108 static struct plat_sci_port scif5_platform_data = {
109         .mapbase        = 0xffef0000,
110         .flags          = UPF_BOOT_AUTOCONF,
111         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
112         .scbrr_algo_id  = SCBRR_ALGO_1,
113         .type           = PORT_SCIF,
114         .irqs           = { 63, 63, 63, 63 },
115 };
116
117 static struct platform_device scif5_device = {
118         .name           = "sh-sci",
119         .id             = 5,
120         .dev            = {
121                 .platform_data  = &scif5_platform_data,
122         },
123 };
124
125 static struct sh_timer_config tmu0_platform_data = {
126         .channel_offset = 0x04,
127         .timer_bit = 0,
128         .clockevent_rating = 200,
129 };
130
131 static struct resource tmu0_resources[] = {
132         [0] = {
133                 .start  = 0xffd80008,
134                 .end    = 0xffd80013,
135                 .flags  = IORESOURCE_MEM,
136         },
137         [1] = {
138                 .start  = 28,
139                 .flags  = IORESOURCE_IRQ,
140         },
141 };
142
143 static struct platform_device tmu0_device = {
144         .name           = "sh_tmu",
145         .id             = 0,
146         .dev = {
147                 .platform_data  = &tmu0_platform_data,
148         },
149         .resource       = tmu0_resources,
150         .num_resources  = ARRAY_SIZE(tmu0_resources),
151 };
152
153 static struct sh_timer_config tmu1_platform_data = {
154         .channel_offset = 0x10,
155         .timer_bit = 1,
156         .clocksource_rating = 200,
157 };
158
159 static struct resource tmu1_resources[] = {
160         [0] = {
161                 .start  = 0xffd80014,
162                 .end    = 0xffd8001f,
163                 .flags  = IORESOURCE_MEM,
164         },
165         [1] = {
166                 .start  = 29,
167                 .flags  = IORESOURCE_IRQ,
168         },
169 };
170
171 static struct platform_device tmu1_device = {
172         .name           = "sh_tmu",
173         .id             = 1,
174         .dev = {
175                 .platform_data  = &tmu1_platform_data,
176         },
177         .resource       = tmu1_resources,
178         .num_resources  = ARRAY_SIZE(tmu1_resources),
179 };
180
181 static struct sh_timer_config tmu2_platform_data = {
182         .channel_offset = 0x1c,
183         .timer_bit = 2,
184 };
185
186 static struct resource tmu2_resources[] = {
187         [0] = {
188                 .start  = 0xffd80020,
189                 .end    = 0xffd8002f,
190                 .flags  = IORESOURCE_MEM,
191         },
192         [1] = {
193                 .start  = 30,
194                 .flags  = IORESOURCE_IRQ,
195         },
196 };
197
198 static struct platform_device tmu2_device = {
199         .name           = "sh_tmu",
200         .id             = 2,
201         .dev = {
202                 .platform_data  = &tmu2_platform_data,
203         },
204         .resource       = tmu2_resources,
205         .num_resources  = ARRAY_SIZE(tmu2_resources),
206 };
207
208 static struct sh_timer_config tmu3_platform_data = {
209         .channel_offset = 0x04,
210         .timer_bit = 0,
211 };
212
213 static struct resource tmu3_resources[] = {
214         [0] = {
215                 .start  = 0xffdc0008,
216                 .end    = 0xffdc0013,
217                 .flags  = IORESOURCE_MEM,
218         },
219         [1] = {
220                 .start  = 96,
221                 .flags  = IORESOURCE_IRQ,
222         },
223 };
224
225 static struct platform_device tmu3_device = {
226         .name           = "sh_tmu",
227         .id             = 3,
228         .dev = {
229                 .platform_data  = &tmu3_platform_data,
230         },
231         .resource       = tmu3_resources,
232         .num_resources  = ARRAY_SIZE(tmu3_resources),
233 };
234
235 static struct sh_timer_config tmu4_platform_data = {
236         .channel_offset = 0x10,
237         .timer_bit = 1,
238 };
239
240 static struct resource tmu4_resources[] = {
241         [0] = {
242                 .start  = 0xffdc0014,
243                 .end    = 0xffdc001f,
244                 .flags  = IORESOURCE_MEM,
245         },
246         [1] = {
247                 .start  = 97,
248                 .flags  = IORESOURCE_IRQ,
249         },
250 };
251
252 static struct platform_device tmu4_device = {
253         .name           = "sh_tmu",
254         .id             = 4,
255         .dev = {
256                 .platform_data  = &tmu4_platform_data,
257         },
258         .resource       = tmu4_resources,
259         .num_resources  = ARRAY_SIZE(tmu4_resources),
260 };
261
262 static struct sh_timer_config tmu5_platform_data = {
263         .channel_offset = 0x1c,
264         .timer_bit = 2,
265 };
266
267 static struct resource tmu5_resources[] = {
268         [0] = {
269                 .start  = 0xffdc0020,
270                 .end    = 0xffdc002b,
271                 .flags  = IORESOURCE_MEM,
272         },
273         [1] = {
274                 .start  = 98,
275                 .flags  = IORESOURCE_IRQ,
276         },
277 };
278
279 static struct platform_device tmu5_device = {
280         .name           = "sh_tmu",
281         .id             = 5,
282         .dev = {
283                 .platform_data  = &tmu5_platform_data,
284         },
285         .resource       = tmu5_resources,
286         .num_resources  = ARRAY_SIZE(tmu5_resources),
287 };
288
289 /* DMA */
290 static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
291         {
292                 .offset = 0,
293                 .dmars = 0,
294                 .dmars_bit = 0,
295         }, {
296                 .offset = 0x10,
297                 .dmars = 0,
298                 .dmars_bit = 8,
299         }, {
300                 .offset = 0x20,
301                 .dmars = 4,
302                 .dmars_bit = 0,
303         }, {
304                 .offset = 0x30,
305                 .dmars = 4,
306                 .dmars_bit = 8,
307         }, {
308                 .offset = 0x50,
309                 .dmars = 8,
310                 .dmars_bit = 0,
311         }, {
312                 .offset = 0x60,
313                 .dmars = 8,
314                 .dmars_bit = 8,
315         }
316 };
317
318 static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
319         {
320                 .offset = 0,
321         }, {
322                 .offset = 0x10,
323         }, {
324                 .offset = 0x20,
325         }, {
326                 .offset = 0x30,
327         }, {
328                 .offset = 0x50,
329         }, {
330                 .offset = 0x60,
331         }
332 };
333
334 static const unsigned int ts_shift[] = TS_SHIFT;
335
336 static struct sh_dmae_pdata dma0_platform_data = {
337         .channel        = sh7785_dmae0_channels,
338         .channel_num    = ARRAY_SIZE(sh7785_dmae0_channels),
339         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
340         .ts_low_mask    = CHCR_TS_LOW_MASK,
341         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
342         .ts_high_mask   = CHCR_TS_HIGH_MASK,
343         .ts_shift       = ts_shift,
344         .ts_shift_num   = ARRAY_SIZE(ts_shift),
345         .dmaor_init     = DMAOR_INIT,
346 };
347
348 static struct sh_dmae_pdata dma1_platform_data = {
349         .channel        = sh7785_dmae1_channels,
350         .channel_num    = ARRAY_SIZE(sh7785_dmae1_channels),
351         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
352         .ts_low_mask    = CHCR_TS_LOW_MASK,
353         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
354         .ts_high_mask   = CHCR_TS_HIGH_MASK,
355         .ts_shift       = ts_shift,
356         .ts_shift_num   = ARRAY_SIZE(ts_shift),
357         .dmaor_init     = DMAOR_INIT,
358 };
359
360 static struct resource sh7785_dmae0_resources[] = {
361         [0] = {
362                 /* Channel registers and DMAOR */
363                 .start  = 0xfc808020,
364                 .end    = 0xfc80808f,
365                 .flags  = IORESOURCE_MEM,
366         },
367         [1] = {
368                 /* DMARSx */
369                 .start  = 0xfc809000,
370                 .end    = 0xfc80900b,
371                 .flags  = IORESOURCE_MEM,
372         },
373         {
374                 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
375                 .start  = 33,
376                 .end    = 33,
377                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
378         },
379 };
380
381 static struct resource sh7785_dmae1_resources[] = {
382         [0] = {
383                 /* Channel registers and DMAOR */
384                 .start  = 0xfcc08020,
385                 .end    = 0xfcc0808f,
386                 .flags  = IORESOURCE_MEM,
387         },
388         /* DMAC1 has no DMARS */
389         {
390                 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
391                 .start  = 52,
392                 .end    = 52,
393                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
394         },
395 };
396
397 static struct platform_device dma0_device = {
398         .name           = "sh-dma-engine",
399         .id             = 0,
400         .resource       = sh7785_dmae0_resources,
401         .num_resources  = ARRAY_SIZE(sh7785_dmae0_resources),
402         .dev            = {
403                 .platform_data  = &dma0_platform_data,
404         },
405 };
406
407 static struct platform_device dma1_device = {
408         .name           = "sh-dma-engine",
409         .id             = 1,
410         .resource       = sh7785_dmae1_resources,
411         .num_resources  = ARRAY_SIZE(sh7785_dmae1_resources),
412         .dev            = {
413                 .platform_data  = &dma1_platform_data,
414         },
415 };
416
417 static struct platform_device *sh7785_devices[] __initdata = {
418         &scif0_device,
419         &scif1_device,
420         &scif2_device,
421         &scif3_device,
422         &scif4_device,
423         &scif5_device,
424         &tmu0_device,
425         &tmu1_device,
426         &tmu2_device,
427         &tmu3_device,
428         &tmu4_device,
429         &tmu5_device,
430         &dma0_device,
431         &dma1_device,
432 };
433
434 static int __init sh7785_devices_setup(void)
435 {
436         return platform_add_devices(sh7785_devices,
437                                     ARRAY_SIZE(sh7785_devices));
438 }
439 arch_initcall(sh7785_devices_setup);
440
441 static struct platform_device *sh7785_early_devices[] __initdata = {
442         &scif0_device,
443         &scif1_device,
444         &scif2_device,
445         &scif3_device,
446         &scif4_device,
447         &scif5_device,
448         &tmu0_device,
449         &tmu1_device,
450         &tmu2_device,
451         &tmu3_device,
452         &tmu4_device,
453         &tmu5_device,
454 };
455
456 void __init plat_early_device_setup(void)
457 {
458         early_platform_add_devices(sh7785_early_devices,
459                                    ARRAY_SIZE(sh7785_early_devices));
460 }
461
462 enum {
463         UNUSED = 0,
464
465         /* interrupt sources */
466
467         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
468         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
469         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
470         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
471
472         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
473         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
474         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
475         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
476
477         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
478         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
479         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
480         SCIF2, SCIF3, SCIF4, SCIF5,
481         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
482         SIOF, MMCIF, DU, GDTA,
483         TMU3, TMU4, TMU5,
484         SSI0, SSI1,
485         HAC0, HAC1,
486         FLCTL, GPIO,
487
488         /* interrupt groups */
489
490         TMU012, TMU345
491 };
492
493 static struct intc_vect vectors[] __initdata = {
494         INTC_VECT(WDT, 0x560),
495         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
496         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
497         INTC_VECT(HUDI, 0x600),
498         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
499         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
500         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
501         INTC_VECT(DMAC0, 0x6e0),
502         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
503         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
504         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
505         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
506         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
507         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
508         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
509         INTC_VECT(DMAC1, 0x940),
510         INTC_VECT(HSPI, 0x960),
511         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
512         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
513         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
514         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
515         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
516         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
517         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
518         INTC_VECT(SIOF, 0xc00),
519         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
520         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
521         INTC_VECT(DU, 0xd80),
522         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
523         INTC_VECT(GDTA, 0xde0),
524         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
525         INTC_VECT(TMU5, 0xe40),
526         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
527         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
528         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
529         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
530         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
531         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
532 };
533
534 static struct intc_group groups[] __initdata = {
535         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
536         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
537 };
538
539 static struct intc_mask_reg mask_registers[] __initdata = {
540         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
541           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
542
543         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
544           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
545             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
546             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
547             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
548             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
549             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
550             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
551             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
552
553         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
554           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
555             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
556             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
557             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
558 };
559
560 static struct intc_prio_reg prio_registers[] __initdata = {
561         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
562                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
563         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
564                                                  TMU2, TMU2_TICPI } },
565         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
566         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
567                                                  SCIF2, SCIF3 } },
568         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
569         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
570         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
571                                                  PCISERR, PCIINTA } },
572         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
573                                                  PCIINTD, PCIC5 } },
574         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
575         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
576         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
577 };
578
579 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
580                          mask_registers, prio_registers, NULL);
581
582 /* Support for external interrupt pins in IRQ mode */
583
584 static struct intc_vect vectors_irq0123[] __initdata = {
585         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
586         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
587 };
588
589 static struct intc_vect vectors_irq4567[] __initdata = {
590         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
591         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
592 };
593
594 static struct intc_sense_reg sense_registers[] __initdata = {
595         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
596                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
597 };
598
599 static struct intc_mask_reg ack_registers[] __initdata = {
600         { 0xffd00024, 0, 32, /* INTREQ */
601           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
602 };
603
604 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
605                              vectors_irq0123, NULL, mask_registers,
606                              prio_registers, sense_registers, ack_registers);
607
608 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
609                              vectors_irq4567, NULL, mask_registers,
610                              prio_registers, sense_registers, ack_registers);
611
612 /* External interrupt pins in IRL mode */
613
614 static struct intc_vect vectors_irl0123[] __initdata = {
615         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
616         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
617         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
618         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
619         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
620         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
621         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
622         INTC_VECT(IRL0_HHHL, 0x3c0),
623 };
624
625 static struct intc_vect vectors_irl4567[] __initdata = {
626         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
627         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
628         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
629         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
630         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
631         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
632         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
633         INTC_VECT(IRL4_HHHL, 0xcc0),
634 };
635
636 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
637                          NULL, mask_registers, NULL, NULL);
638
639 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
640                          NULL, mask_registers, NULL, NULL);
641
642 #define INTC_ICR0       0xffd00000
643 #define INTC_INTMSK0    0xffd00044
644 #define INTC_INTMSK1    0xffd00048
645 #define INTC_INTMSK2    0xffd40080
646 #define INTC_INTMSKCLR1 0xffd00068
647 #define INTC_INTMSKCLR2 0xffd40084
648
649 void __init plat_irq_setup(void)
650 {
651         /* disable IRQ3-0 + IRQ7-4 */
652         __raw_writel(0xff000000, INTC_INTMSK0);
653
654         /* disable IRL3-0 + IRL7-4 */
655         __raw_writel(0xc0000000, INTC_INTMSK1);
656         __raw_writel(0xfffefffe, INTC_INTMSK2);
657
658         /* select IRL mode for IRL3-0 + IRL7-4 */
659         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
660
661         /* disable holding function, ie enable "SH-4 Mode" */
662         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
663
664         register_intc_controller(&intc_desc);
665 }
666
667 void __init plat_irq_setup_pins(int mode)
668 {
669         switch (mode) {
670         case IRQ_MODE_IRQ7654:
671                 /* select IRQ mode for IRL7-4 */
672                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
673                 register_intc_controller(&intc_desc_irq4567);
674                 break;
675         case IRQ_MODE_IRQ3210:
676                 /* select IRQ mode for IRL3-0 */
677                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
678                 register_intc_controller(&intc_desc_irq0123);
679                 break;
680         case IRQ_MODE_IRL7654:
681                 /* enable IRL7-4 but don't provide any masking */
682                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
683                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
684                 break;
685         case IRQ_MODE_IRL3210:
686                 /* enable IRL0-3 but don't provide any masking */
687                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
688                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
689                 break;
690         case IRQ_MODE_IRL7654_MASK:
691                 /* enable IRL7-4 and mask using cpu intc controller */
692                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
693                 register_intc_controller(&intc_desc_irl4567);
694                 break;
695         case IRQ_MODE_IRL3210_MASK:
696                 /* enable IRL0-3 and mask using cpu intc controller */
697                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
698                 register_intc_controller(&intc_desc_irl0123);
699                 break;
700         default:
701                 BUG();
702         }
703 }
704
705 void __init plat_mem_setup(void)
706 {
707         /* Register the URAM space as Node 1 */
708         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
709 }