sh: sh7372 SH4AL-DSP probe support
[~shefty/rdma-dev.git] / arch / sh / kernel / cpu / sh4a / setup-sh7785.c
1 /*
2  * SH7785 Setup
3  *
4  *  Copyright (C) 2007  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/io.h>
15 #include <linux/mm.h>
16 #include <linux/sh_dma.h>
17 #include <linux/sh_timer.h>
18
19 #include <asm/mmzone.h>
20
21 #include <cpu/dma-register.h>
22
23 static struct plat_sci_port scif0_platform_data = {
24         .mapbase        = 0xffea0000,
25         .flags          = UPF_BOOT_AUTOCONF,
26         .type           = PORT_SCIF,
27         .irqs           = { 40, 40, 40, 40 },
28 };
29
30 static struct platform_device scif0_device = {
31         .name           = "sh-sci",
32         .id             = 0,
33         .dev            = {
34                 .platform_data  = &scif0_platform_data,
35         },
36 };
37
38 static struct plat_sci_port scif1_platform_data = {
39         .mapbase        = 0xffeb0000,
40         .flags          = UPF_BOOT_AUTOCONF,
41         .type           = PORT_SCIF,
42         .irqs           = { 44, 44, 44, 44 },
43 };
44
45 static struct platform_device scif1_device = {
46         .name           = "sh-sci",
47         .id             = 1,
48         .dev            = {
49                 .platform_data  = &scif1_platform_data,
50         },
51 };
52
53 static struct plat_sci_port scif2_platform_data = {
54         .mapbase        = 0xffec0000,
55         .flags          = UPF_BOOT_AUTOCONF,
56         .type           = PORT_SCIF,
57         .irqs           = { 60, 60, 60, 60 },
58 };
59
60 static struct platform_device scif2_device = {
61         .name           = "sh-sci",
62         .id             = 2,
63         .dev            = {
64                 .platform_data  = &scif2_platform_data,
65         },
66 };
67
68 static struct plat_sci_port scif3_platform_data = {
69         .mapbase        = 0xffed0000,
70         .flags          = UPF_BOOT_AUTOCONF,
71         .type           = PORT_SCIF,
72         .irqs           = { 61, 61, 61, 61 },
73 };
74
75 static struct platform_device scif3_device = {
76         .name           = "sh-sci",
77         .id             = 3,
78         .dev            = {
79                 .platform_data  = &scif3_platform_data,
80         },
81 };
82
83 static struct plat_sci_port scif4_platform_data = {
84         .mapbase        = 0xffee0000,
85         .flags          = UPF_BOOT_AUTOCONF,
86         .type           = PORT_SCIF,
87         .irqs           = { 62, 62, 62, 62 },
88 };
89
90 static struct platform_device scif4_device = {
91         .name           = "sh-sci",
92         .id             = 4,
93         .dev            = {
94                 .platform_data  = &scif4_platform_data,
95         },
96 };
97
98 static struct plat_sci_port scif5_platform_data = {
99         .mapbase        = 0xffef0000,
100         .flags          = UPF_BOOT_AUTOCONF,
101         .type           = PORT_SCIF,
102         .irqs           = { 63, 63, 63, 63 },
103 };
104
105 static struct platform_device scif5_device = {
106         .name           = "sh-sci",
107         .id             = 5,
108         .dev            = {
109                 .platform_data  = &scif5_platform_data,
110         },
111 };
112
113 static struct sh_timer_config tmu0_platform_data = {
114         .channel_offset = 0x04,
115         .timer_bit = 0,
116         .clockevent_rating = 200,
117 };
118
119 static struct resource tmu0_resources[] = {
120         [0] = {
121                 .start  = 0xffd80008,
122                 .end    = 0xffd80013,
123                 .flags  = IORESOURCE_MEM,
124         },
125         [1] = {
126                 .start  = 28,
127                 .flags  = IORESOURCE_IRQ,
128         },
129 };
130
131 static struct platform_device tmu0_device = {
132         .name           = "sh_tmu",
133         .id             = 0,
134         .dev = {
135                 .platform_data  = &tmu0_platform_data,
136         },
137         .resource       = tmu0_resources,
138         .num_resources  = ARRAY_SIZE(tmu0_resources),
139 };
140
141 static struct sh_timer_config tmu1_platform_data = {
142         .channel_offset = 0x10,
143         .timer_bit = 1,
144         .clocksource_rating = 200,
145 };
146
147 static struct resource tmu1_resources[] = {
148         [0] = {
149                 .start  = 0xffd80014,
150                 .end    = 0xffd8001f,
151                 .flags  = IORESOURCE_MEM,
152         },
153         [1] = {
154                 .start  = 29,
155                 .flags  = IORESOURCE_IRQ,
156         },
157 };
158
159 static struct platform_device tmu1_device = {
160         .name           = "sh_tmu",
161         .id             = 1,
162         .dev = {
163                 .platform_data  = &tmu1_platform_data,
164         },
165         .resource       = tmu1_resources,
166         .num_resources  = ARRAY_SIZE(tmu1_resources),
167 };
168
169 static struct sh_timer_config tmu2_platform_data = {
170         .channel_offset = 0x1c,
171         .timer_bit = 2,
172 };
173
174 static struct resource tmu2_resources[] = {
175         [0] = {
176                 .start  = 0xffd80020,
177                 .end    = 0xffd8002f,
178                 .flags  = IORESOURCE_MEM,
179         },
180         [1] = {
181                 .start  = 30,
182                 .flags  = IORESOURCE_IRQ,
183         },
184 };
185
186 static struct platform_device tmu2_device = {
187         .name           = "sh_tmu",
188         .id             = 2,
189         .dev = {
190                 .platform_data  = &tmu2_platform_data,
191         },
192         .resource       = tmu2_resources,
193         .num_resources  = ARRAY_SIZE(tmu2_resources),
194 };
195
196 static struct sh_timer_config tmu3_platform_data = {
197         .channel_offset = 0x04,
198         .timer_bit = 0,
199 };
200
201 static struct resource tmu3_resources[] = {
202         [0] = {
203                 .start  = 0xffdc0008,
204                 .end    = 0xffdc0013,
205                 .flags  = IORESOURCE_MEM,
206         },
207         [1] = {
208                 .start  = 96,
209                 .flags  = IORESOURCE_IRQ,
210         },
211 };
212
213 static struct platform_device tmu3_device = {
214         .name           = "sh_tmu",
215         .id             = 3,
216         .dev = {
217                 .platform_data  = &tmu3_platform_data,
218         },
219         .resource       = tmu3_resources,
220         .num_resources  = ARRAY_SIZE(tmu3_resources),
221 };
222
223 static struct sh_timer_config tmu4_platform_data = {
224         .channel_offset = 0x10,
225         .timer_bit = 1,
226 };
227
228 static struct resource tmu4_resources[] = {
229         [0] = {
230                 .start  = 0xffdc0014,
231                 .end    = 0xffdc001f,
232                 .flags  = IORESOURCE_MEM,
233         },
234         [1] = {
235                 .start  = 97,
236                 .flags  = IORESOURCE_IRQ,
237         },
238 };
239
240 static struct platform_device tmu4_device = {
241         .name           = "sh_tmu",
242         .id             = 4,
243         .dev = {
244                 .platform_data  = &tmu4_platform_data,
245         },
246         .resource       = tmu4_resources,
247         .num_resources  = ARRAY_SIZE(tmu4_resources),
248 };
249
250 static struct sh_timer_config tmu5_platform_data = {
251         .channel_offset = 0x1c,
252         .timer_bit = 2,
253 };
254
255 static struct resource tmu5_resources[] = {
256         [0] = {
257                 .start  = 0xffdc0020,
258                 .end    = 0xffdc002b,
259                 .flags  = IORESOURCE_MEM,
260         },
261         [1] = {
262                 .start  = 98,
263                 .flags  = IORESOURCE_IRQ,
264         },
265 };
266
267 static struct platform_device tmu5_device = {
268         .name           = "sh_tmu",
269         .id             = 5,
270         .dev = {
271                 .platform_data  = &tmu5_platform_data,
272         },
273         .resource       = tmu5_resources,
274         .num_resources  = ARRAY_SIZE(tmu5_resources),
275 };
276
277 /* DMA */
278 static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
279         {
280                 .offset = 0,
281                 .dmars = 0,
282                 .dmars_bit = 0,
283         }, {
284                 .offset = 0x10,
285                 .dmars = 0,
286                 .dmars_bit = 8,
287         }, {
288                 .offset = 0x20,
289                 .dmars = 4,
290                 .dmars_bit = 0,
291         }, {
292                 .offset = 0x30,
293                 .dmars = 4,
294                 .dmars_bit = 8,
295         }, {
296                 .offset = 0x50,
297                 .dmars = 8,
298                 .dmars_bit = 0,
299         }, {
300                 .offset = 0x60,
301                 .dmars = 8,
302                 .dmars_bit = 8,
303         }
304 };
305
306 static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
307         {
308                 .offset = 0,
309         }, {
310                 .offset = 0x10,
311         }, {
312                 .offset = 0x20,
313         }, {
314                 .offset = 0x30,
315         }, {
316                 .offset = 0x50,
317         }, {
318                 .offset = 0x60,
319         }
320 };
321
322 static const unsigned int ts_shift[] = TS_SHIFT;
323
324 static struct sh_dmae_pdata dma0_platform_data = {
325         .channel        = sh7785_dmae0_channels,
326         .channel_num    = ARRAY_SIZE(sh7785_dmae0_channels),
327         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
328         .ts_low_mask    = CHCR_TS_LOW_MASK,
329         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
330         .ts_high_mask   = CHCR_TS_HIGH_MASK,
331         .ts_shift       = ts_shift,
332         .ts_shift_num   = ARRAY_SIZE(ts_shift),
333         .dmaor_init     = DMAOR_INIT,
334 };
335
336 static struct sh_dmae_pdata dma1_platform_data = {
337         .channel        = sh7785_dmae1_channels,
338         .channel_num    = ARRAY_SIZE(sh7785_dmae1_channels),
339         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
340         .ts_low_mask    = CHCR_TS_LOW_MASK,
341         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
342         .ts_high_mask   = CHCR_TS_HIGH_MASK,
343         .ts_shift       = ts_shift,
344         .ts_shift_num   = ARRAY_SIZE(ts_shift),
345         .dmaor_init     = DMAOR_INIT,
346 };
347
348 static struct resource sh7785_dmae0_resources[] = {
349         [0] = {
350                 /* Channel registers and DMAOR */
351                 .start  = 0xfc808020,
352                 .end    = 0xfc80808f,
353                 .flags  = IORESOURCE_MEM,
354         },
355         [1] = {
356                 /* DMARSx */
357                 .start  = 0xfc809000,
358                 .end    = 0xfc80900b,
359                 .flags  = IORESOURCE_MEM,
360         },
361         {
362                 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
363                 .start  = 33,
364                 .end    = 33,
365                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
366         },
367 };
368
369 static struct resource sh7785_dmae1_resources[] = {
370         [0] = {
371                 /* Channel registers and DMAOR */
372                 .start  = 0xfcc08020,
373                 .end    = 0xfcc0808f,
374                 .flags  = IORESOURCE_MEM,
375         },
376         /* DMAC1 has no DMARS */
377         {
378                 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
379                 .start  = 52,
380                 .end    = 52,
381                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
382         },
383 };
384
385 static struct platform_device dma0_device = {
386         .name           = "sh-dma-engine",
387         .id             = 0,
388         .resource       = sh7785_dmae0_resources,
389         .num_resources  = ARRAY_SIZE(sh7785_dmae0_resources),
390         .dev            = {
391                 .platform_data  = &dma0_platform_data,
392         },
393 };
394
395 static struct platform_device dma1_device = {
396         .name           = "sh-dma-engine",
397         .id             = 1,
398         .resource       = sh7785_dmae1_resources,
399         .num_resources  = ARRAY_SIZE(sh7785_dmae1_resources),
400         .dev            = {
401                 .platform_data  = &dma1_platform_data,
402         },
403 };
404
405 static struct platform_device *sh7785_devices[] __initdata = {
406         &scif0_device,
407         &scif1_device,
408         &scif2_device,
409         &scif3_device,
410         &scif4_device,
411         &scif5_device,
412         &tmu0_device,
413         &tmu1_device,
414         &tmu2_device,
415         &tmu3_device,
416         &tmu4_device,
417         &tmu5_device,
418         &dma0_device,
419         &dma1_device,
420 };
421
422 static int __init sh7785_devices_setup(void)
423 {
424         return platform_add_devices(sh7785_devices,
425                                     ARRAY_SIZE(sh7785_devices));
426 }
427 arch_initcall(sh7785_devices_setup);
428
429 static struct platform_device *sh7785_early_devices[] __initdata = {
430         &scif0_device,
431         &scif1_device,
432         &scif2_device,
433         &scif3_device,
434         &scif4_device,
435         &scif5_device,
436         &tmu0_device,
437         &tmu1_device,
438         &tmu2_device,
439         &tmu3_device,
440         &tmu4_device,
441         &tmu5_device,
442 };
443
444 void __init plat_early_device_setup(void)
445 {
446         early_platform_add_devices(sh7785_early_devices,
447                                    ARRAY_SIZE(sh7785_early_devices));
448 }
449
450 enum {
451         UNUSED = 0,
452
453         /* interrupt sources */
454
455         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
456         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
457         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
458         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
459
460         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
461         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
462         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
463         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
464
465         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
466         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
467         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
468         SCIF2, SCIF3, SCIF4, SCIF5,
469         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
470         SIOF, MMCIF, DU, GDTA,
471         TMU3, TMU4, TMU5,
472         SSI0, SSI1,
473         HAC0, HAC1,
474         FLCTL, GPIO,
475
476         /* interrupt groups */
477
478         TMU012, TMU345
479 };
480
481 static struct intc_vect vectors[] __initdata = {
482         INTC_VECT(WDT, 0x560),
483         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
484         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
485         INTC_VECT(HUDI, 0x600),
486         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
487         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
488         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
489         INTC_VECT(DMAC0, 0x6e0),
490         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
491         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
492         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
493         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
494         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
495         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
496         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
497         INTC_VECT(DMAC1, 0x940),
498         INTC_VECT(HSPI, 0x960),
499         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
500         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
501         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
502         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
503         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
504         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
505         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
506         INTC_VECT(SIOF, 0xc00),
507         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
508         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
509         INTC_VECT(DU, 0xd80),
510         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
511         INTC_VECT(GDTA, 0xde0),
512         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
513         INTC_VECT(TMU5, 0xe40),
514         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
515         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
516         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
517         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
518         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
519         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
520 };
521
522 static struct intc_group groups[] __initdata = {
523         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
524         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
525 };
526
527 static struct intc_mask_reg mask_registers[] __initdata = {
528         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
529           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
530
531         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
532           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
533             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
534             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
535             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
536             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
537             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
538             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
539             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
540
541         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
542           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
543             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
544             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
545             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
546 };
547
548 static struct intc_prio_reg prio_registers[] __initdata = {
549         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
550                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
551         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
552                                                  TMU2, TMU2_TICPI } },
553         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
554         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
555                                                  SCIF2, SCIF3 } },
556         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
557         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
558         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
559                                                  PCISERR, PCIINTA } },
560         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
561                                                  PCIINTD, PCIC5 } },
562         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
563         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
564         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
565 };
566
567 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
568                          mask_registers, prio_registers, NULL);
569
570 /* Support for external interrupt pins in IRQ mode */
571
572 static struct intc_vect vectors_irq0123[] __initdata = {
573         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
574         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
575 };
576
577 static struct intc_vect vectors_irq4567[] __initdata = {
578         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
579         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
580 };
581
582 static struct intc_sense_reg sense_registers[] __initdata = {
583         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
584                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
585 };
586
587 static struct intc_mask_reg ack_registers[] __initdata = {
588         { 0xffd00024, 0, 32, /* INTREQ */
589           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
590 };
591
592 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
593                              vectors_irq0123, NULL, mask_registers,
594                              prio_registers, sense_registers, ack_registers);
595
596 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
597                              vectors_irq4567, NULL, mask_registers,
598                              prio_registers, sense_registers, ack_registers);
599
600 /* External interrupt pins in IRL mode */
601
602 static struct intc_vect vectors_irl0123[] __initdata = {
603         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
604         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
605         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
606         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
607         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
608         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
609         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
610         INTC_VECT(IRL0_HHHL, 0x3c0),
611 };
612
613 static struct intc_vect vectors_irl4567[] __initdata = {
614         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
615         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
616         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
617         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
618         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
619         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
620         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
621         INTC_VECT(IRL4_HHHL, 0xcc0),
622 };
623
624 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
625                          NULL, mask_registers, NULL, NULL);
626
627 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
628                          NULL, mask_registers, NULL, NULL);
629
630 #define INTC_ICR0       0xffd00000
631 #define INTC_INTMSK0    0xffd00044
632 #define INTC_INTMSK1    0xffd00048
633 #define INTC_INTMSK2    0xffd40080
634 #define INTC_INTMSKCLR1 0xffd00068
635 #define INTC_INTMSKCLR2 0xffd40084
636
637 void __init plat_irq_setup(void)
638 {
639         /* disable IRQ3-0 + IRQ7-4 */
640         __raw_writel(0xff000000, INTC_INTMSK0);
641
642         /* disable IRL3-0 + IRL7-4 */
643         __raw_writel(0xc0000000, INTC_INTMSK1);
644         __raw_writel(0xfffefffe, INTC_INTMSK2);
645
646         /* select IRL mode for IRL3-0 + IRL7-4 */
647         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
648
649         /* disable holding function, ie enable "SH-4 Mode" */
650         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
651
652         register_intc_controller(&intc_desc);
653 }
654
655 void __init plat_irq_setup_pins(int mode)
656 {
657         switch (mode) {
658         case IRQ_MODE_IRQ7654:
659                 /* select IRQ mode for IRL7-4 */
660                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
661                 register_intc_controller(&intc_desc_irq4567);
662                 break;
663         case IRQ_MODE_IRQ3210:
664                 /* select IRQ mode for IRL3-0 */
665                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
666                 register_intc_controller(&intc_desc_irq0123);
667                 break;
668         case IRQ_MODE_IRL7654:
669                 /* enable IRL7-4 but don't provide any masking */
670                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
671                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
672                 break;
673         case IRQ_MODE_IRL3210:
674                 /* enable IRL0-3 but don't provide any masking */
675                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
676                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
677                 break;
678         case IRQ_MODE_IRL7654_MASK:
679                 /* enable IRL7-4 and mask using cpu intc controller */
680                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
681                 register_intc_controller(&intc_desc_irl4567);
682                 break;
683         case IRQ_MODE_IRL3210_MASK:
684                 /* enable IRL0-3 and mask using cpu intc controller */
685                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
686                 register_intc_controller(&intc_desc_irl0123);
687                 break;
688         default:
689                 BUG();
690         }
691 }
692
693 void __init plat_mem_setup(void)
694 {
695         /* Register the URAM space as Node 1 */
696         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
697 }