Merge branch 'common/serial-rework' into sh-latest
[~shefty/rdma-dev.git] / arch / sh / kernel / cpu / sh4a / setup-sh7786.c
1 /*
2  * SH7786 Setup
3  *
4  * Copyright (C) 2009 - 2010  Renesas Solutions Corp.
5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6  * Paul Mundt <paul.mundt@renesas.com>
7  *
8  * Based on SH7785 Setup
9  *
10  *  Copyright (C) 2007  Paul Mundt
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file "COPYING" in the main directory of this archive
14  * for more details.
15  */
16 #include <linux/platform_device.h>
17 #include <linux/init.h>
18 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/io.h>
21 #include <linux/mm.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/sh_timer.h>
24 #include <linux/sh_dma.h>
25 #include <linux/sh_intc.h>
26 #include <cpu/dma-register.h>
27 #include <asm/mmzone.h>
28
29 static struct plat_sci_port scif0_platform_data = {
30         .mapbase        = 0xffea0000,
31         .flags          = UPF_BOOT_AUTOCONF,
32         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
33         .scbrr_algo_id  = SCBRR_ALGO_1,
34         .type           = PORT_SCIF,
35         .irqs           = { 40, 41, 43, 42 },
36 };
37
38 static struct platform_device scif0_device = {
39         .name           = "sh-sci",
40         .id             = 0,
41         .dev            = {
42                 .platform_data  = &scif0_platform_data,
43         },
44 };
45
46 /*
47  * The rest of these all have multiplexed IRQs
48  */
49 static struct plat_sci_port scif1_platform_data = {
50         .mapbase        = 0xffeb0000,
51         .flags          = UPF_BOOT_AUTOCONF,
52         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
53         .scbrr_algo_id  = SCBRR_ALGO_1,
54         .type           = PORT_SCIF,
55         .irqs           = { 44, 44, 44, 44 },
56 };
57
58 static struct platform_device scif1_device = {
59         .name           = "sh-sci",
60         .id             = 1,
61         .dev            = {
62                 .platform_data  = &scif1_platform_data,
63         },
64 };
65
66 static struct plat_sci_port scif2_platform_data = {
67         .mapbase        = 0xffec0000,
68         .flags          = UPF_BOOT_AUTOCONF,
69         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
70         .scbrr_algo_id  = SCBRR_ALGO_1,
71         .type           = PORT_SCIF,
72         .irqs           = { 50, 50, 50, 50 },
73 };
74
75 static struct platform_device scif2_device = {
76         .name           = "sh-sci",
77         .id             = 2,
78         .dev            = {
79                 .platform_data  = &scif2_platform_data,
80         },
81 };
82
83 static struct plat_sci_port scif3_platform_data = {
84         .mapbase        = 0xffed0000,
85         .flags          = UPF_BOOT_AUTOCONF,
86         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
87         .scbrr_algo_id  = SCBRR_ALGO_1,
88         .type           = PORT_SCIF,
89         .irqs           = { 51, 51, 51, 51 },
90 };
91
92 static struct platform_device scif3_device = {
93         .name           = "sh-sci",
94         .id             = 3,
95         .dev            = {
96                 .platform_data  = &scif3_platform_data,
97         },
98 };
99
100 static struct plat_sci_port scif4_platform_data = {
101         .mapbase        = 0xffee0000,
102         .flags          = UPF_BOOT_AUTOCONF,
103         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
104         .scbrr_algo_id  = SCBRR_ALGO_1,
105         .type           = PORT_SCIF,
106         .irqs           = { 52, 52, 52, 52 },
107 };
108
109 static struct platform_device scif4_device = {
110         .name           = "sh-sci",
111         .id             = 4,
112         .dev            = {
113                 .platform_data  = &scif4_platform_data,
114         },
115 };
116
117 static struct plat_sci_port scif5_platform_data = {
118         .mapbase        = 0xffef0000,
119         .flags          = UPF_BOOT_AUTOCONF,
120         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
121         .scbrr_algo_id  = SCBRR_ALGO_1,
122         .type           = PORT_SCIF,
123         .irqs           = { 53, 53, 53, 53 },
124 };
125
126 static struct platform_device scif5_device = {
127         .name           = "sh-sci",
128         .id             = 5,
129         .dev            = {
130                 .platform_data  = &scif5_platform_data,
131         },
132 };
133
134 static struct sh_timer_config tmu0_platform_data = {
135         .channel_offset = 0x04,
136         .timer_bit = 0,
137         .clockevent_rating = 200,
138 };
139
140 static struct resource tmu0_resources[] = {
141         [0] = {
142                 .start  = 0xffd80008,
143                 .end    = 0xffd80013,
144                 .flags  = IORESOURCE_MEM,
145         },
146         [1] = {
147                 .start  = 16,
148                 .flags  = IORESOURCE_IRQ,
149         },
150 };
151
152 static struct platform_device tmu0_device = {
153         .name           = "sh_tmu",
154         .id             = 0,
155         .dev = {
156                 .platform_data  = &tmu0_platform_data,
157         },
158         .resource       = tmu0_resources,
159         .num_resources  = ARRAY_SIZE(tmu0_resources),
160 };
161
162 static struct sh_timer_config tmu1_platform_data = {
163         .channel_offset = 0x10,
164         .timer_bit = 1,
165         .clocksource_rating = 200,
166 };
167
168 static struct resource tmu1_resources[] = {
169         [0] = {
170                 .start  = 0xffd80014,
171                 .end    = 0xffd8001f,
172                 .flags  = IORESOURCE_MEM,
173         },
174         [1] = {
175                 .start  = 17,
176                 .flags  = IORESOURCE_IRQ,
177         },
178 };
179
180 static struct platform_device tmu1_device = {
181         .name           = "sh_tmu",
182         .id             = 1,
183         .dev = {
184                 .platform_data  = &tmu1_platform_data,
185         },
186         .resource       = tmu1_resources,
187         .num_resources  = ARRAY_SIZE(tmu1_resources),
188 };
189
190 static struct sh_timer_config tmu2_platform_data = {
191         .channel_offset = 0x1c,
192         .timer_bit = 2,
193 };
194
195 static struct resource tmu2_resources[] = {
196         [0] = {
197                 .start  = 0xffd80020,
198                 .end    = 0xffd8002f,
199                 .flags  = IORESOURCE_MEM,
200         },
201         [1] = {
202                 .start  = 18,
203                 .flags  = IORESOURCE_IRQ,
204         },
205 };
206
207 static struct platform_device tmu2_device = {
208         .name           = "sh_tmu",
209         .id             = 2,
210         .dev = {
211                 .platform_data  = &tmu2_platform_data,
212         },
213         .resource       = tmu2_resources,
214         .num_resources  = ARRAY_SIZE(tmu2_resources),
215 };
216
217 static struct sh_timer_config tmu3_platform_data = {
218         .channel_offset = 0x04,
219         .timer_bit = 0,
220 };
221
222 static struct resource tmu3_resources[] = {
223         [0] = {
224                 .start  = 0xffda0008,
225                 .end    = 0xffda0013,
226                 .flags  = IORESOURCE_MEM,
227         },
228         [1] = {
229                 .start  = 20,
230                 .flags  = IORESOURCE_IRQ,
231         },
232 };
233
234 static struct platform_device tmu3_device = {
235         .name           = "sh_tmu",
236         .id             = 3,
237         .dev = {
238                 .platform_data  = &tmu3_platform_data,
239         },
240         .resource       = tmu3_resources,
241         .num_resources  = ARRAY_SIZE(tmu3_resources),
242 };
243
244 static struct sh_timer_config tmu4_platform_data = {
245         .channel_offset = 0x10,
246         .timer_bit = 1,
247 };
248
249 static struct resource tmu4_resources[] = {
250         [0] = {
251                 .start  = 0xffda0014,
252                 .end    = 0xffda001f,
253                 .flags  = IORESOURCE_MEM,
254         },
255         [1] = {
256                 .start  = 21,
257                 .flags  = IORESOURCE_IRQ,
258         },
259 };
260
261 static struct platform_device tmu4_device = {
262         .name           = "sh_tmu",
263         .id             = 4,
264         .dev = {
265                 .platform_data  = &tmu4_platform_data,
266         },
267         .resource       = tmu4_resources,
268         .num_resources  = ARRAY_SIZE(tmu4_resources),
269 };
270
271 static struct sh_timer_config tmu5_platform_data = {
272         .channel_offset = 0x1c,
273         .timer_bit = 2,
274 };
275
276 static struct resource tmu5_resources[] = {
277         [0] = {
278                 .start  = 0xffda0020,
279                 .end    = 0xffda002b,
280                 .flags  = IORESOURCE_MEM,
281         },
282         [1] = {
283                 .start  = 22,
284                 .flags  = IORESOURCE_IRQ,
285         },
286 };
287
288 static struct platform_device tmu5_device = {
289         .name           = "sh_tmu",
290         .id             = 5,
291         .dev = {
292                 .platform_data  = &tmu5_platform_data,
293         },
294         .resource       = tmu5_resources,
295         .num_resources  = ARRAY_SIZE(tmu5_resources),
296 };
297
298 static struct sh_timer_config tmu6_platform_data = {
299         .channel_offset = 0x04,
300         .timer_bit = 0,
301 };
302
303 static struct resource tmu6_resources[] = {
304         [0] = {
305                 .start  = 0xffdc0008,
306                 .end    = 0xffdc0013,
307                 .flags  = IORESOURCE_MEM,
308         },
309         [1] = {
310                 .start  = 45,
311                 .flags  = IORESOURCE_IRQ,
312         },
313 };
314
315 static struct platform_device tmu6_device = {
316         .name           = "sh_tmu",
317         .id             = 6,
318         .dev = {
319                 .platform_data  = &tmu6_platform_data,
320         },
321         .resource       = tmu6_resources,
322         .num_resources  = ARRAY_SIZE(tmu6_resources),
323 };
324
325 static struct sh_timer_config tmu7_platform_data = {
326         .channel_offset = 0x10,
327         .timer_bit = 1,
328 };
329
330 static struct resource tmu7_resources[] = {
331         [0] = {
332                 .start  = 0xffdc0014,
333                 .end    = 0xffdc001f,
334                 .flags  = IORESOURCE_MEM,
335         },
336         [1] = {
337                 .start  = 45,
338                 .flags  = IORESOURCE_IRQ,
339         },
340 };
341
342 static struct platform_device tmu7_device = {
343         .name           = "sh_tmu",
344         .id             = 7,
345         .dev = {
346                 .platform_data  = &tmu7_platform_data,
347         },
348         .resource       = tmu7_resources,
349         .num_resources  = ARRAY_SIZE(tmu7_resources),
350 };
351
352 static struct sh_timer_config tmu8_platform_data = {
353         .channel_offset = 0x1c,
354         .timer_bit = 2,
355 };
356
357 static struct resource tmu8_resources[] = {
358         [0] = {
359                 .start  = 0xffdc0020,
360                 .end    = 0xffdc002b,
361                 .flags  = IORESOURCE_MEM,
362         },
363         [1] = {
364                 .start  = 45,
365                 .flags  = IORESOURCE_IRQ,
366         },
367 };
368
369 static struct platform_device tmu8_device = {
370         .name           = "sh_tmu",
371         .id             = 8,
372         .dev = {
373                 .platform_data  = &tmu8_platform_data,
374         },
375         .resource       = tmu8_resources,
376         .num_resources  = ARRAY_SIZE(tmu8_resources),
377 };
378
379 static struct sh_timer_config tmu9_platform_data = {
380         .channel_offset = 0x04,
381         .timer_bit = 0,
382 };
383
384 static struct resource tmu9_resources[] = {
385         [0] = {
386                 .start  = 0xffde0008,
387                 .end    = 0xffde0013,
388                 .flags  = IORESOURCE_MEM,
389         },
390         [1] = {
391                 .start  = 46,
392                 .flags  = IORESOURCE_IRQ,
393         },
394 };
395
396 static struct platform_device tmu9_device = {
397         .name           = "sh_tmu",
398         .id             = 9,
399         .dev = {
400                 .platform_data  = &tmu9_platform_data,
401         },
402         .resource       = tmu9_resources,
403         .num_resources  = ARRAY_SIZE(tmu9_resources),
404 };
405
406 static struct sh_timer_config tmu10_platform_data = {
407         .channel_offset = 0x10,
408         .timer_bit = 1,
409 };
410
411 static struct resource tmu10_resources[] = {
412         [0] = {
413                 .start  = 0xffde0014,
414                 .end    = 0xffde001f,
415                 .flags  = IORESOURCE_MEM,
416         },
417         [1] = {
418                 .start  = 46,
419                 .flags  = IORESOURCE_IRQ,
420         },
421 };
422
423 static struct platform_device tmu10_device = {
424         .name           = "sh_tmu",
425         .id             = 10,
426         .dev = {
427                 .platform_data  = &tmu10_platform_data,
428         },
429         .resource       = tmu10_resources,
430         .num_resources  = ARRAY_SIZE(tmu10_resources),
431 };
432
433 static struct sh_timer_config tmu11_platform_data = {
434         .channel_offset = 0x1c,
435         .timer_bit = 2,
436 };
437
438 static struct resource tmu11_resources[] = {
439         [0] = {
440                 .start  = 0xffde0020,
441                 .end    = 0xffde002b,
442                 .flags  = IORESOURCE_MEM,
443         },
444         [1] = {
445                 .start  = 46,
446                 .flags  = IORESOURCE_IRQ,
447         },
448 };
449
450 static struct platform_device tmu11_device = {
451         .name           = "sh_tmu",
452         .id             = 11,
453         .dev = {
454                 .platform_data  = &tmu11_platform_data,
455         },
456         .resource       = tmu11_resources,
457         .num_resources  = ARRAY_SIZE(tmu11_resources),
458 };
459
460 static const struct sh_dmae_channel dmac0_channels[] = {
461         {
462                 .offset = 0,
463                 .dmars = 0,
464                 .dmars_bit = 0,
465         }, {
466                 .offset = 0x10,
467                 .dmars = 0,
468                 .dmars_bit = 8,
469         }, {
470                 .offset = 0x20,
471                 .dmars = 4,
472                 .dmars_bit = 0,
473         }, {
474                 .offset = 0x30,
475                 .dmars = 4,
476                 .dmars_bit = 8,
477         }, {
478                 .offset = 0x50,
479                 .dmars = 8,
480                 .dmars_bit = 0,
481         }, {
482                 .offset = 0x60,
483                 .dmars = 8,
484                 .dmars_bit = 8,
485         }
486 };
487
488 static const unsigned int ts_shift[] = TS_SHIFT;
489
490 static struct sh_dmae_pdata dma0_platform_data = {
491         .channel        = dmac0_channels,
492         .channel_num    = ARRAY_SIZE(dmac0_channels),
493         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
494         .ts_low_mask    = CHCR_TS_LOW_MASK,
495         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
496         .ts_high_mask   = CHCR_TS_HIGH_MASK,
497         .ts_shift       = ts_shift,
498         .ts_shift_num   = ARRAY_SIZE(ts_shift),
499         .dmaor_init     = DMAOR_INIT,
500 };
501
502 /* Resource order important! */
503 static struct resource dmac0_resources[] = {
504         {
505                 /* Channel registers and DMAOR */
506                 .start  = 0xfe008020,
507                 .end    = 0xfe00808f,
508                 .flags  = IORESOURCE_MEM,
509         }, {
510                 /* DMARSx */
511                 .start  = 0xfe009000,
512                 .end    = 0xfe00900b,
513                 .flags  = IORESOURCE_MEM,
514         }, {
515                 /* DMA error IRQ */
516                 .start  = evt2irq(0x5c0),
517                 .end    = evt2irq(0x5c0),
518                 .flags  = IORESOURCE_IRQ,
519         }, {
520                 /* IRQ for channels 0-5 */
521                 .start  = evt2irq(0x500),
522                 .end    = evt2irq(0x5a0),
523                 .flags  = IORESOURCE_IRQ,
524         },
525 };
526
527 static struct platform_device dma0_device = {
528         .name           = "sh-dma-engine",
529         .id             = 0,
530         .resource       = dmac0_resources,
531         .num_resources  = ARRAY_SIZE(dmac0_resources),
532         .dev            = {
533                 .platform_data  = &dma0_platform_data,
534         },
535 };
536
537 #define USB_EHCI_START 0xffe70000
538 #define USB_OHCI_START 0xffe70400
539
540 static struct resource usb_ehci_resources[] = {
541         [0] = {
542                 .start  = USB_EHCI_START,
543                 .end    = USB_EHCI_START + 0x3ff,
544                 .flags  = IORESOURCE_MEM,
545         },
546         [1] = {
547                 .start  = 77,
548                 .end    = 77,
549                 .flags  = IORESOURCE_IRQ,
550         },
551 };
552
553 static struct platform_device usb_ehci_device = {
554         .name           = "sh_ehci",
555         .id             = -1,
556         .dev = {
557                 .dma_mask               = &usb_ehci_device.dev.coherent_dma_mask,
558                 .coherent_dma_mask      = DMA_BIT_MASK(32),
559         },
560         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
561         .resource       = usb_ehci_resources,
562 };
563
564 static struct resource usb_ohci_resources[] = {
565         [0] = {
566                 .start  = USB_OHCI_START,
567                 .end    = USB_OHCI_START + 0x3ff,
568                 .flags  = IORESOURCE_MEM,
569         },
570         [1] = {
571                 .start  = 77,
572                 .end    = 77,
573                 .flags  = IORESOURCE_IRQ,
574         },
575 };
576
577 static struct platform_device usb_ohci_device = {
578         .name           = "sh_ohci",
579         .id             = -1,
580         .dev = {
581                 .dma_mask               = &usb_ohci_device.dev.coherent_dma_mask,
582                 .coherent_dma_mask      = DMA_BIT_MASK(32),
583         },
584         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
585         .resource       = usb_ohci_resources,
586 };
587
588 static struct platform_device *sh7786_early_devices[] __initdata = {
589         &scif0_device,
590         &scif1_device,
591         &scif2_device,
592         &scif3_device,
593         &scif4_device,
594         &scif5_device,
595         &tmu0_device,
596         &tmu1_device,
597         &tmu2_device,
598         &tmu3_device,
599         &tmu4_device,
600         &tmu5_device,
601         &tmu6_device,
602         &tmu7_device,
603         &tmu8_device,
604         &tmu9_device,
605         &tmu10_device,
606         &tmu11_device,
607 };
608
609 static struct platform_device *sh7786_devices[] __initdata = {
610         &dma0_device,
611         &usb_ehci_device,
612         &usb_ohci_device,
613 };
614
615 /*
616  * Please call this function if your platform board
617  * use external clock for USB
618  * */
619 #define USBCTL0         0xffe70858
620 #define CLOCK_MODE_MASK 0xffffff7f
621 #define EXT_CLOCK_MODE  0x00000080
622
623 void __init sh7786_usb_use_exclock(void)
624 {
625         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
626         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
627 }
628
629 #define USBINITREG1     0xffe70094
630 #define USBINITREG2     0xffe7009c
631 #define USBINITVAL1     0x00ff0040
632 #define USBINITVAL2     0x00000001
633
634 #define USBPCTL1        0xffe70804
635 #define USBST           0xffe70808
636 #define PHY_ENB         0x00000001
637 #define PLL_ENB         0x00000002
638 #define PHY_RST         0x00000004
639 #define ACT_PLL_STATUS  0xc0000000
640
641 static void __init sh7786_usb_setup(void)
642 {
643         int i = 1000000;
644
645         /*
646          * USB initial settings
647          *
648          * The following settings are necessary
649          * for using the USB modules.
650          *
651          * see "USB Inital Settings" for detail
652          */
653         __raw_writel(USBINITVAL1, USBINITREG1);
654         __raw_writel(USBINITVAL2, USBINITREG2);
655
656         /*
657          * Set the PHY and PLL enable bit
658          */
659         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
660         while (i--) {
661                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
662                         /* Set the PHY RST bit */
663                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
664                         printk(KERN_INFO "sh7786 usb setup done\n");
665                         break;
666                 }
667                 cpu_relax();
668         }
669 }
670
671 enum {
672         UNUSED = 0,
673
674         /* interrupt sources */
675         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
676         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
677         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
678         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
679
680         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
681         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
682         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
683         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
684
685         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
686         WDT,
687         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
688         TMU1_0, TMU1_1, TMU1_2,
689         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
690         HUDI1, HUDI0,
691         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
692         HPB_0, HPB_1, HPB_2,
693         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
694         SCIF1,
695         TMU2, TMU3,
696         SCIF2, SCIF3, SCIF4, SCIF5,
697         Eth_0, Eth_1,
698         PCIeC0_0, PCIeC0_1, PCIeC0_2,
699         PCIeC1_0, PCIeC1_1, PCIeC1_2,
700         USB,
701         I2C0, I2C1,
702         DU,
703         SSI0, SSI1, SSI2, SSI3,
704         PCIeC2_0, PCIeC2_1, PCIeC2_2,
705         HAC0, HAC1,
706         FLCTL,
707         HSPI,
708         GPIO0, GPIO1,
709         Thermal,
710         INTICI0, INTICI1, INTICI2, INTICI3,
711         INTICI4, INTICI5, INTICI6, INTICI7,
712
713         /* Muxed sub-events */
714         TXI1, BRI1, RXI1, ERI1,
715 };
716
717 static struct intc_vect sh7786_vectors[] __initdata = {
718         INTC_VECT(WDT, 0x3e0),
719         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
720         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
721         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
722         INTC_VECT(TMU1_2, 0x4c0),
723         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
724         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
725         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
726         INTC_VECT(DMAC0_6, 0x5c0),
727         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
728         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
729         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
730         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
731         INTC_VECT(HPB_2, 0x6e0),
732         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
733         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
734         INTC_VECT(SCIF1, 0x780),
735         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
736         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
737         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
738         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
739         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
740         INTC_VECT(PCIeC0_2, 0xb20),
741         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
742         INTC_VECT(PCIeC1_2, 0xb80),
743         INTC_VECT(USB, 0xba0),
744         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
745         INTC_VECT(DU, 0xd00),
746         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
747         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
748         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
749         INTC_VECT(PCIeC2_2, 0xde0),
750         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
751         INTC_VECT(FLCTL, 0xe40),
752         INTC_VECT(HSPI, 0xe80),
753         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
754         INTC_VECT(Thermal, 0xee0),
755         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
756         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
757         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
758         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
759 };
760
761 #define CnINTMSK0       0xfe410030
762 #define CnINTMSK1       0xfe410040
763 #define CnINTMSKCLR0    0xfe410050
764 #define CnINTMSKCLR1    0xfe410060
765 #define CnINT2MSKR0     0xfe410a20
766 #define CnINT2MSKR1     0xfe410a24
767 #define CnINT2MSKR2     0xfe410a28
768 #define CnINT2MSKR3     0xfe410a2c
769 #define CnINT2MSKCR0    0xfe410a30
770 #define CnINT2MSKCR1    0xfe410a34
771 #define CnINT2MSKCR2    0xfe410a38
772 #define CnINT2MSKCR3    0xfe410a3c
773 #define INTMSK2         0xfe410068
774 #define INTMSKCLR2      0xfe41006c
775
776 #define INTDISTCR0      0xfe4100b0
777 #define INTDISTCR1      0xfe4100b4
778 #define INT2DISTCR0     0xfe410900
779 #define INT2DISTCR1     0xfe410904
780 #define INT2DISTCR2     0xfe410908
781 #define INT2DISTCR3     0xfe41090c
782
783 static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
784         { CnINTMSK0, CnINTMSKCLR0, 32,
785           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
786             INTC_SMP_BALANCING(INTDISTCR0) },
787         { INTMSK2, INTMSKCLR2, 32,
788           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
789             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
790             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
791             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
792             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
793             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
794             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
795             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
796         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
797           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
798             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
799             INTC_SMP_BALANCING(INT2DISTCR0) },
800         { CnINT2MSKR1, CnINT2MSKCR1, 32,
801           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
802             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
803             HUDI1, HUDI0,
804             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
805             HPB_0, HPB_1, HPB_2,
806             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
807             SCIF1,
808             TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
809         { CnINT2MSKR2, CnINT2MSKCR2, 32,
810           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
811             Eth_0, Eth_1,
812             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
813             PCIeC0_0, PCIeC0_1, PCIeC0_2,
814             PCIeC1_0, PCIeC1_1, PCIeC1_2,
815             USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
816         { CnINT2MSKR3, CnINT2MSKCR3, 32,
817           { 0, 0, 0, 0, 0, 0,
818             I2C0, I2C1,
819             DU, SSI0, SSI1, SSI2, SSI3,
820             PCIeC2_0, PCIeC2_1, PCIeC2_2,
821             HAC0, HAC1,
822             FLCTL, 0,
823             HSPI, GPIO0, GPIO1, Thermal,
824             0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
825 };
826
827 static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
828         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
829                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
830         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
831         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
832                                                  TMU0_2, TMU0_3 } },
833         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
834                                                  TMU1_2, 0 } },
835         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
836                                                  DMAC0_2, DMAC0_3 } },
837         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
838                                                  DMAC0_6, HUDI1 } },
839         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
840                                                  DMAC1_1, DMAC1_2 } },
841         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
842                                                  HPB_1, HPB_2 } },
843         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
844                                                  SCIF0_2, SCIF0_3 } },
845         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
846         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
847         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
848                                                   Eth_0, Eth_1 } },
849         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
850         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
851         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
852         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
853         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
854                                                   PCIeC1_0, PCIeC1_1 } },
855         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
856         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
857         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
858         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
859         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
860                                                   PCIeC2_1, PCIeC2_2 } },
861         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
862         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
863                                                   GPIO1, Thermal } },
864         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
865         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
866         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
867           { INTICI7, INTICI6, INTICI5, INTICI4,
868             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
869 };
870
871 static struct intc_subgroup sh7786_subgroups[] __initdata = {
872         { 0xfe410c20, 32, SCIF1,
873           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
874             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
875 };
876
877 static struct intc_desc sh7786_intc_desc __initdata = {
878         .name           = "sh7786",
879         .hw             = {
880                 .vectors        = sh7786_vectors,
881                 .nr_vectors     = ARRAY_SIZE(sh7786_vectors),
882                 .mask_regs      = sh7786_mask_registers,
883                 .nr_mask_regs   = ARRAY_SIZE(sh7786_mask_registers),
884                 .subgroups      = sh7786_subgroups,
885                 .nr_subgroups   = ARRAY_SIZE(sh7786_subgroups),
886                 .prio_regs      = sh7786_prio_registers,
887                 .nr_prio_regs   = ARRAY_SIZE(sh7786_prio_registers),
888         },
889 };
890
891 /* Support for external interrupt pins in IRQ mode */
892 static struct intc_vect vectors_irq0123[] __initdata = {
893         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
894         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
895 };
896
897 static struct intc_vect vectors_irq4567[] __initdata = {
898         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
899         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
900 };
901
902 static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
903         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
904                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
905 };
906
907 static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
908         { 0xfe410024, 0, 32, /* INTREQ */
909           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
910 };
911
912 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
913                              vectors_irq0123, NULL, sh7786_mask_registers,
914                              sh7786_prio_registers, sh7786_sense_registers,
915                              sh7786_ack_registers);
916
917 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
918                              vectors_irq4567, NULL, sh7786_mask_registers,
919                              sh7786_prio_registers, sh7786_sense_registers,
920                              sh7786_ack_registers);
921
922 /* External interrupt pins in IRL mode */
923
924 static struct intc_vect vectors_irl0123[] __initdata = {
925         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
926         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
927         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
928         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
929         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
930         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
931         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
932         INTC_VECT(IRL0_HHHL, 0x3c0),
933 };
934
935 static struct intc_vect vectors_irl4567[] __initdata = {
936         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
937         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
938         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
939         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
940         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
941         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
942         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
943         INTC_VECT(IRL4_HHHL, 0xac0),
944 };
945
946 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
947                          NULL, sh7786_mask_registers, NULL, NULL);
948
949 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
950                          NULL, sh7786_mask_registers, NULL, NULL);
951
952 #define INTC_ICR0       0xfe410000
953 #define INTC_INTMSK0    CnINTMSK0
954 #define INTC_INTMSK1    CnINTMSK1
955 #define INTC_INTMSK2    INTMSK2
956 #define INTC_INTMSKCLR1 CnINTMSKCLR1
957 #define INTC_INTMSKCLR2 INTMSKCLR2
958
959 void __init plat_irq_setup(void)
960 {
961         /* disable IRQ3-0 + IRQ7-4 */
962         __raw_writel(0xff000000, INTC_INTMSK0);
963
964         /* disable IRL3-0 + IRL7-4 */
965         __raw_writel(0xc0000000, INTC_INTMSK1);
966         __raw_writel(0xfffefffe, INTC_INTMSK2);
967
968         /* select IRL mode for IRL3-0 + IRL7-4 */
969         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
970
971         register_intc_controller(&sh7786_intc_desc);
972 }
973
974 void __init plat_irq_setup_pins(int mode)
975 {
976         switch (mode) {
977         case IRQ_MODE_IRQ7654:
978                 /* select IRQ mode for IRL7-4 */
979                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
980                 register_intc_controller(&intc_desc_irq4567);
981                 break;
982         case IRQ_MODE_IRQ3210:
983                 /* select IRQ mode for IRL3-0 */
984                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
985                 register_intc_controller(&intc_desc_irq0123);
986                 break;
987         case IRQ_MODE_IRL7654:
988                 /* enable IRL7-4 but don't provide any masking */
989                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
990                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
991                 break;
992         case IRQ_MODE_IRL3210:
993                 /* enable IRL0-3 but don't provide any masking */
994                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
995                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
996                 break;
997         case IRQ_MODE_IRL7654_MASK:
998                 /* enable IRL7-4 and mask using cpu intc controller */
999                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1000                 register_intc_controller(&intc_desc_irl4567);
1001                 break;
1002         case IRQ_MODE_IRL3210_MASK:
1003                 /* enable IRL0-3 and mask using cpu intc controller */
1004                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1005                 register_intc_controller(&intc_desc_irl0123);
1006                 break;
1007         default:
1008                 BUG();
1009         }
1010 }
1011
1012 void __init plat_mem_setup(void)
1013 {
1014 }
1015
1016 static int __init sh7786_devices_setup(void)
1017 {
1018         int ret, irq;
1019
1020         sh7786_usb_setup();
1021
1022         /*
1023          * De-mux SCIF1 IRQs if possible
1024          */
1025         irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1026         if (irq > 0) {
1027                 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
1028                 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1029                         intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1030                 scif1_platform_data.irqs[SCIx_BRI_IRQ] =
1031                         intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1032                 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1033                         intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1034         }
1035
1036         ret = platform_add_devices(sh7786_early_devices,
1037                                    ARRAY_SIZE(sh7786_early_devices));
1038         if (unlikely(ret != 0))
1039                 return ret;
1040
1041         return platform_add_devices(sh7786_devices,
1042                                     ARRAY_SIZE(sh7786_devices));
1043 }
1044 arch_initcall(sh7786_devices_setup);
1045
1046 void __init plat_early_device_setup(void)
1047 {
1048         early_platform_add_devices(sh7786_early_devices,
1049                                    ARRAY_SIZE(sh7786_early_devices));
1050 }