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sparc64: Validate linear D-TLB misses.
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1 /*
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7  
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
28 #include <linux/mmzone.h>
29
30 #include <asm/head.h>
31 #include <asm/system.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/irq.h>
52
53 #include "init_64.h"
54
55 unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57 /* A bitmap, one bit for every 256MB of physical memory.  If the bit
58  * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59  * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60  */
61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65  * Space is allocated for this right after the trap table
66  * in arch/sparc64/kernel/head.S
67  */
68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 #endif
70
71 #define MAX_BANKS       32
72
73 static struct linux_prom64_registers pavail[MAX_BANKS] __devinitdata;
74 static int pavail_ents __devinitdata;
75
76 static int cmp_p64(const void *a, const void *b)
77 {
78         const struct linux_prom64_registers *x = a, *y = b;
79
80         if (x->phys_addr > y->phys_addr)
81                 return 1;
82         if (x->phys_addr < y->phys_addr)
83                 return -1;
84         return 0;
85 }
86
87 static void __init read_obp_memory(const char *property,
88                                    struct linux_prom64_registers *regs,
89                                    int *num_ents)
90 {
91         int node = prom_finddevice("/memory");
92         int prop_size = prom_getproplen(node, property);
93         int ents, ret, i;
94
95         ents = prop_size / sizeof(struct linux_prom64_registers);
96         if (ents > MAX_BANKS) {
97                 prom_printf("The machine has more %s property entries than "
98                             "this kernel can support (%d).\n",
99                             property, MAX_BANKS);
100                 prom_halt();
101         }
102
103         ret = prom_getproperty(node, property, (char *) regs, prop_size);
104         if (ret == -1) {
105                 prom_printf("Couldn't get %s property from /memory.\n");
106                 prom_halt();
107         }
108
109         /* Sanitize what we got from the firmware, by page aligning
110          * everything.
111          */
112         for (i = 0; i < ents; i++) {
113                 unsigned long base, size;
114
115                 base = regs[i].phys_addr;
116                 size = regs[i].reg_size;
117
118                 size &= PAGE_MASK;
119                 if (base & ~PAGE_MASK) {
120                         unsigned long new_base = PAGE_ALIGN(base);
121
122                         size -= new_base - base;
123                         if ((long) size < 0L)
124                                 size = 0UL;
125                         base = new_base;
126                 }
127                 if (size == 0UL) {
128                         /* If it is empty, simply get rid of it.
129                          * This simplifies the logic of the other
130                          * functions that process these arrays.
131                          */
132                         memmove(&regs[i], &regs[i + 1],
133                                 (ents - i - 1) * sizeof(regs[0]));
134                         i--;
135                         ents--;
136                         continue;
137                 }
138                 regs[i].phys_addr = base;
139                 regs[i].reg_size = size;
140         }
141
142         *num_ents = ents;
143
144         sort(regs, ents, sizeof(struct linux_prom64_registers),
145              cmp_p64, NULL);
146 }
147
148 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
149                                         sizeof(unsigned long)];
150 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
151
152 /* Kernel physical address base and size in bytes.  */
153 unsigned long kern_base __read_mostly;
154 unsigned long kern_size __read_mostly;
155
156 /* Initial ramdisk setup */
157 extern unsigned long sparc_ramdisk_image64;
158 extern unsigned int sparc_ramdisk_image;
159 extern unsigned int sparc_ramdisk_size;
160
161 struct page *mem_map_zero __read_mostly;
162 EXPORT_SYMBOL(mem_map_zero);
163
164 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
165
166 unsigned long sparc64_kern_pri_context __read_mostly;
167 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
168 unsigned long sparc64_kern_sec_context __read_mostly;
169
170 int num_kernel_image_mappings;
171
172 #ifdef CONFIG_DEBUG_DCFLUSH
173 atomic_t dcpage_flushes = ATOMIC_INIT(0);
174 #ifdef CONFIG_SMP
175 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
176 #endif
177 #endif
178
179 inline void flush_dcache_page_impl(struct page *page)
180 {
181         BUG_ON(tlb_type == hypervisor);
182 #ifdef CONFIG_DEBUG_DCFLUSH
183         atomic_inc(&dcpage_flushes);
184 #endif
185
186 #ifdef DCACHE_ALIASING_POSSIBLE
187         __flush_dcache_page(page_address(page),
188                             ((tlb_type == spitfire) &&
189                              page_mapping(page) != NULL));
190 #else
191         if (page_mapping(page) != NULL &&
192             tlb_type == spitfire)
193                 __flush_icache_page(__pa(page_address(page)));
194 #endif
195 }
196
197 #define PG_dcache_dirty         PG_arch_1
198 #define PG_dcache_cpu_shift     32UL
199 #define PG_dcache_cpu_mask      \
200         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
201
202 #define dcache_dirty_cpu(page) \
203         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
204
205 static inline void set_dcache_dirty(struct page *page, int this_cpu)
206 {
207         unsigned long mask = this_cpu;
208         unsigned long non_cpu_bits;
209
210         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
211         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
212
213         __asm__ __volatile__("1:\n\t"
214                              "ldx       [%2], %%g7\n\t"
215                              "and       %%g7, %1, %%g1\n\t"
216                              "or        %%g1, %0, %%g1\n\t"
217                              "casx      [%2], %%g7, %%g1\n\t"
218                              "cmp       %%g7, %%g1\n\t"
219                              "bne,pn    %%xcc, 1b\n\t"
220                              " nop"
221                              : /* no outputs */
222                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223                              : "g1", "g7");
224 }
225
226 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227 {
228         unsigned long mask = (1UL << PG_dcache_dirty);
229
230         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231                              "1:\n\t"
232                              "ldx       [%2], %%g7\n\t"
233                              "srlx      %%g7, %4, %%g1\n\t"
234                              "and       %%g1, %3, %%g1\n\t"
235                              "cmp       %%g1, %0\n\t"
236                              "bne,pn    %%icc, 2f\n\t"
237                              " andn     %%g7, %1, %%g1\n\t"
238                              "casx      [%2], %%g7, %%g1\n\t"
239                              "cmp       %%g7, %%g1\n\t"
240                              "bne,pn    %%xcc, 1b\n\t"
241                              " nop\n"
242                              "2:"
243                              : /* no outputs */
244                              : "r" (cpu), "r" (mask), "r" (&page->flags),
245                                "i" (PG_dcache_cpu_mask),
246                                "i" (PG_dcache_cpu_shift)
247                              : "g1", "g7");
248 }
249
250 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
251 {
252         unsigned long tsb_addr = (unsigned long) ent;
253
254         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
255                 tsb_addr = __pa(tsb_addr);
256
257         __tsb_insert(tsb_addr, tag, pte);
258 }
259
260 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
261 unsigned long _PAGE_SZBITS __read_mostly;
262
263 static void flush_dcache(unsigned long pfn)
264 {
265         struct page *page;
266
267         page = pfn_to_page(pfn);
268         if (page && page_mapping(page)) {
269                 unsigned long pg_flags;
270
271                 pg_flags = page->flags;
272                 if (pg_flags & (1UL << PG_dcache_dirty)) {
273                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
274                                    PG_dcache_cpu_mask);
275                         int this_cpu = get_cpu();
276
277                         /* This is just to optimize away some function calls
278                          * in the SMP case.
279                          */
280                         if (cpu == this_cpu)
281                                 flush_dcache_page_impl(page);
282                         else
283                                 smp_flush_dcache_page_impl(page, cpu);
284
285                         clear_dcache_dirty_cpu(page, cpu);
286
287                         put_cpu();
288                 }
289         }
290 }
291
292 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
293 {
294         struct mm_struct *mm;
295         struct tsb *tsb;
296         unsigned long tag, flags;
297         unsigned long tsb_index, tsb_hash_shift;
298
299         if (tlb_type != hypervisor) {
300                 unsigned long pfn = pte_pfn(pte);
301
302                 if (pfn_valid(pfn))
303                         flush_dcache(pfn);
304         }
305
306         mm = vma->vm_mm;
307
308         tsb_index = MM_TSB_BASE;
309         tsb_hash_shift = PAGE_SHIFT;
310
311         spin_lock_irqsave(&mm->context.lock, flags);
312
313 #ifdef CONFIG_HUGETLB_PAGE
314         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
315                 if ((tlb_type == hypervisor &&
316                      (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
317                     (tlb_type != hypervisor &&
318                      (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
319                         tsb_index = MM_TSB_HUGE;
320                         tsb_hash_shift = HPAGE_SHIFT;
321                 }
322         }
323 #endif
324
325         tsb = mm->context.tsb_block[tsb_index].tsb;
326         tsb += ((address >> tsb_hash_shift) &
327                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
328         tag = (address >> 22UL);
329         tsb_insert(tsb, tag, pte_val(pte));
330
331         spin_unlock_irqrestore(&mm->context.lock, flags);
332 }
333
334 void flush_dcache_page(struct page *page)
335 {
336         struct address_space *mapping;
337         int this_cpu;
338
339         if (tlb_type == hypervisor)
340                 return;
341
342         /* Do not bother with the expensive D-cache flush if it
343          * is merely the zero page.  The 'bigcore' testcase in GDB
344          * causes this case to run millions of times.
345          */
346         if (page == ZERO_PAGE(0))
347                 return;
348
349         this_cpu = get_cpu();
350
351         mapping = page_mapping(page);
352         if (mapping && !mapping_mapped(mapping)) {
353                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
354                 if (dirty) {
355                         int dirty_cpu = dcache_dirty_cpu(page);
356
357                         if (dirty_cpu == this_cpu)
358                                 goto out;
359                         smp_flush_dcache_page_impl(page, dirty_cpu);
360                 }
361                 set_dcache_dirty(page, this_cpu);
362         } else {
363                 /* We could delay the flush for the !page_mapping
364                  * case too.  But that case is for exec env/arg
365                  * pages and those are %99 certainly going to get
366                  * faulted into the tlb (and thus flushed) anyways.
367                  */
368                 flush_dcache_page_impl(page);
369         }
370
371 out:
372         put_cpu();
373 }
374 EXPORT_SYMBOL(flush_dcache_page);
375
376 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
377 {
378         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
379         if (tlb_type == spitfire) {
380                 unsigned long kaddr;
381
382                 /* This code only runs on Spitfire cpus so this is
383                  * why we can assume _PAGE_PADDR_4U.
384                  */
385                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
386                         unsigned long paddr, mask = _PAGE_PADDR_4U;
387
388                         if (kaddr >= PAGE_OFFSET)
389                                 paddr = kaddr & mask;
390                         else {
391                                 pgd_t *pgdp = pgd_offset_k(kaddr);
392                                 pud_t *pudp = pud_offset(pgdp, kaddr);
393                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
394                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
395
396                                 paddr = pte_val(*ptep) & mask;
397                         }
398                         __flush_icache_page(paddr);
399                 }
400         }
401 }
402 EXPORT_SYMBOL(flush_icache_range);
403
404 void mmu_info(struct seq_file *m)
405 {
406         if (tlb_type == cheetah)
407                 seq_printf(m, "MMU Type\t: Cheetah\n");
408         else if (tlb_type == cheetah_plus)
409                 seq_printf(m, "MMU Type\t: Cheetah+\n");
410         else if (tlb_type == spitfire)
411                 seq_printf(m, "MMU Type\t: Spitfire\n");
412         else if (tlb_type == hypervisor)
413                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
414         else
415                 seq_printf(m, "MMU Type\t: ???\n");
416
417 #ifdef CONFIG_DEBUG_DCFLUSH
418         seq_printf(m, "DCPageFlushes\t: %d\n",
419                    atomic_read(&dcpage_flushes));
420 #ifdef CONFIG_SMP
421         seq_printf(m, "DCPageFlushesXC\t: %d\n",
422                    atomic_read(&dcpage_flushes_xcall));
423 #endif /* CONFIG_SMP */
424 #endif /* CONFIG_DEBUG_DCFLUSH */
425 }
426
427 struct linux_prom_translation prom_trans[512] __read_mostly;
428 unsigned int prom_trans_ents __read_mostly;
429
430 unsigned long kern_locked_tte_data;
431
432 /* The obp translations are saved based on 8k pagesize, since obp can
433  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
434  * HI_OBP_ADDRESS range are handled in ktlb.S.
435  */
436 static inline int in_obp_range(unsigned long vaddr)
437 {
438         return (vaddr >= LOW_OBP_ADDRESS &&
439                 vaddr < HI_OBP_ADDRESS);
440 }
441
442 static int cmp_ptrans(const void *a, const void *b)
443 {
444         const struct linux_prom_translation *x = a, *y = b;
445
446         if (x->virt > y->virt)
447                 return 1;
448         if (x->virt < y->virt)
449                 return -1;
450         return 0;
451 }
452
453 /* Read OBP translations property into 'prom_trans[]'.  */
454 static void __init read_obp_translations(void)
455 {
456         int n, node, ents, first, last, i;
457
458         node = prom_finddevice("/virtual-memory");
459         n = prom_getproplen(node, "translations");
460         if (unlikely(n == 0 || n == -1)) {
461                 prom_printf("prom_mappings: Couldn't get size.\n");
462                 prom_halt();
463         }
464         if (unlikely(n > sizeof(prom_trans))) {
465                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
466                 prom_halt();
467         }
468
469         if ((n = prom_getproperty(node, "translations",
470                                   (char *)&prom_trans[0],
471                                   sizeof(prom_trans))) == -1) {
472                 prom_printf("prom_mappings: Couldn't get property.\n");
473                 prom_halt();
474         }
475
476         n = n / sizeof(struct linux_prom_translation);
477
478         ents = n;
479
480         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
481              cmp_ptrans, NULL);
482
483         /* Now kick out all the non-OBP entries.  */
484         for (i = 0; i < ents; i++) {
485                 if (in_obp_range(prom_trans[i].virt))
486                         break;
487         }
488         first = i;
489         for (; i < ents; i++) {
490                 if (!in_obp_range(prom_trans[i].virt))
491                         break;
492         }
493         last = i;
494
495         for (i = 0; i < (last - first); i++) {
496                 struct linux_prom_translation *src = &prom_trans[i + first];
497                 struct linux_prom_translation *dest = &prom_trans[i];
498
499                 *dest = *src;
500         }
501         for (; i < ents; i++) {
502                 struct linux_prom_translation *dest = &prom_trans[i];
503                 dest->virt = dest->size = dest->data = 0x0UL;
504         }
505
506         prom_trans_ents = last - first;
507
508         if (tlb_type == spitfire) {
509                 /* Clear diag TTE bits. */
510                 for (i = 0; i < prom_trans_ents; i++)
511                         prom_trans[i].data &= ~0x0003fe0000000000UL;
512         }
513 }
514
515 static void __init hypervisor_tlb_lock(unsigned long vaddr,
516                                        unsigned long pte,
517                                        unsigned long mmu)
518 {
519         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
520
521         if (ret != 0) {
522                 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
523                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
524                 prom_halt();
525         }
526 }
527
528 static unsigned long kern_large_tte(unsigned long paddr);
529
530 static void __init remap_kernel(void)
531 {
532         unsigned long phys_page, tte_vaddr, tte_data;
533         int i, tlb_ent = sparc64_highest_locked_tlbent();
534
535         tte_vaddr = (unsigned long) KERNBASE;
536         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
537         tte_data = kern_large_tte(phys_page);
538
539         kern_locked_tte_data = tte_data;
540
541         /* Now lock us into the TLBs via Hypervisor or OBP. */
542         if (tlb_type == hypervisor) {
543                 for (i = 0; i < num_kernel_image_mappings; i++) {
544                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
545                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
546                         tte_vaddr += 0x400000;
547                         tte_data += 0x400000;
548                 }
549         } else {
550                 for (i = 0; i < num_kernel_image_mappings; i++) {
551                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
552                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
553                         tte_vaddr += 0x400000;
554                         tte_data += 0x400000;
555                 }
556                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
557         }
558         if (tlb_type == cheetah_plus) {
559                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
560                                             CTX_CHEETAH_PLUS_NUC);
561                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
562                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
563         }
564 }
565
566
567 static void __init inherit_prom_mappings(void)
568 {
569         /* Now fixup OBP's idea about where we really are mapped. */
570         printk("Remapping the kernel... ");
571         remap_kernel();
572         printk("done.\n");
573 }
574
575 void prom_world(int enter)
576 {
577         if (!enter)
578                 set_fs((mm_segment_t) { get_thread_current_ds() });
579
580         __asm__ __volatile__("flushw");
581 }
582
583 void __flush_dcache_range(unsigned long start, unsigned long end)
584 {
585         unsigned long va;
586
587         if (tlb_type == spitfire) {
588                 int n = 0;
589
590                 for (va = start; va < end; va += 32) {
591                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
592                         if (++n >= 512)
593                                 break;
594                 }
595         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
596                 start = __pa(start);
597                 end = __pa(end);
598                 for (va = start; va < end; va += 32)
599                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
600                                              "membar #Sync"
601                                              : /* no outputs */
602                                              : "r" (va),
603                                                "i" (ASI_DCACHE_INVALIDATE));
604         }
605 }
606 EXPORT_SYMBOL(__flush_dcache_range);
607
608 /* get_new_mmu_context() uses "cache + 1".  */
609 DEFINE_SPINLOCK(ctx_alloc_lock);
610 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
611 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
612 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
613 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
614
615 /* Caller does TLB context flushing on local CPU if necessary.
616  * The caller also ensures that CTX_VALID(mm->context) is false.
617  *
618  * We must be careful about boundary cases so that we never
619  * let the user have CTX 0 (nucleus) or we ever use a CTX
620  * version of zero (and thus NO_CONTEXT would not be caught
621  * by version mis-match tests in mmu_context.h).
622  *
623  * Always invoked with interrupts disabled.
624  */
625 void get_new_mmu_context(struct mm_struct *mm)
626 {
627         unsigned long ctx, new_ctx;
628         unsigned long orig_pgsz_bits;
629         unsigned long flags;
630         int new_version;
631
632         spin_lock_irqsave(&ctx_alloc_lock, flags);
633         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
634         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
635         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
636         new_version = 0;
637         if (new_ctx >= (1 << CTX_NR_BITS)) {
638                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
639                 if (new_ctx >= ctx) {
640                         int i;
641                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
642                                 CTX_FIRST_VERSION;
643                         if (new_ctx == 1)
644                                 new_ctx = CTX_FIRST_VERSION;
645
646                         /* Don't call memset, for 16 entries that's just
647                          * plain silly...
648                          */
649                         mmu_context_bmap[0] = 3;
650                         mmu_context_bmap[1] = 0;
651                         mmu_context_bmap[2] = 0;
652                         mmu_context_bmap[3] = 0;
653                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
654                                 mmu_context_bmap[i + 0] = 0;
655                                 mmu_context_bmap[i + 1] = 0;
656                                 mmu_context_bmap[i + 2] = 0;
657                                 mmu_context_bmap[i + 3] = 0;
658                         }
659                         new_version = 1;
660                         goto out;
661                 }
662         }
663         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
664         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
665 out:
666         tlb_context_cache = new_ctx;
667         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
668         spin_unlock_irqrestore(&ctx_alloc_lock, flags);
669
670         if (unlikely(new_version))
671                 smp_new_mmu_context_version();
672 }
673
674 static int numa_enabled = 1;
675 static int numa_debug;
676
677 static int __init early_numa(char *p)
678 {
679         if (!p)
680                 return 0;
681
682         if (strstr(p, "off"))
683                 numa_enabled = 0;
684
685         if (strstr(p, "debug"))
686                 numa_debug = 1;
687
688         return 0;
689 }
690 early_param("numa", early_numa);
691
692 #define numadbg(f, a...) \
693 do {    if (numa_debug) \
694                 printk(KERN_INFO f, ## a); \
695 } while (0)
696
697 static void __init find_ramdisk(unsigned long phys_base)
698 {
699 #ifdef CONFIG_BLK_DEV_INITRD
700         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
701                 unsigned long ramdisk_image;
702
703                 /* Older versions of the bootloader only supported a
704                  * 32-bit physical address for the ramdisk image
705                  * location, stored at sparc_ramdisk_image.  Newer
706                  * SILO versions set sparc_ramdisk_image to zero and
707                  * provide a full 64-bit physical address at
708                  * sparc_ramdisk_image64.
709                  */
710                 ramdisk_image = sparc_ramdisk_image;
711                 if (!ramdisk_image)
712                         ramdisk_image = sparc_ramdisk_image64;
713
714                 /* Another bootloader quirk.  The bootloader normalizes
715                  * the physical address to KERNBASE, so we have to
716                  * factor that back out and add in the lowest valid
717                  * physical page address to get the true physical address.
718                  */
719                 ramdisk_image -= KERNBASE;
720                 ramdisk_image += phys_base;
721
722                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
723                         ramdisk_image, sparc_ramdisk_size);
724
725                 initrd_start = ramdisk_image;
726                 initrd_end = ramdisk_image + sparc_ramdisk_size;
727
728                 lmb_reserve(initrd_start, sparc_ramdisk_size);
729
730                 initrd_start += PAGE_OFFSET;
731                 initrd_end += PAGE_OFFSET;
732         }
733 #endif
734 }
735
736 struct node_mem_mask {
737         unsigned long mask;
738         unsigned long val;
739         unsigned long bootmem_paddr;
740 };
741 static struct node_mem_mask node_masks[MAX_NUMNODES];
742 static int num_node_masks;
743
744 int numa_cpu_lookup_table[NR_CPUS];
745 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
746
747 #ifdef CONFIG_NEED_MULTIPLE_NODES
748
749 struct mdesc_mblock {
750         u64     base;
751         u64     size;
752         u64     offset; /* RA-to-PA */
753 };
754 static struct mdesc_mblock *mblocks;
755 static int num_mblocks;
756
757 static unsigned long ra_to_pa(unsigned long addr)
758 {
759         int i;
760
761         for (i = 0; i < num_mblocks; i++) {
762                 struct mdesc_mblock *m = &mblocks[i];
763
764                 if (addr >= m->base &&
765                     addr < (m->base + m->size)) {
766                         addr += m->offset;
767                         break;
768                 }
769         }
770         return addr;
771 }
772
773 static int find_node(unsigned long addr)
774 {
775         int i;
776
777         addr = ra_to_pa(addr);
778         for (i = 0; i < num_node_masks; i++) {
779                 struct node_mem_mask *p = &node_masks[i];
780
781                 if ((addr & p->mask) == p->val)
782                         return i;
783         }
784         return -1;
785 }
786
787 static unsigned long long nid_range(unsigned long long start,
788                                     unsigned long long end, int *nid)
789 {
790         *nid = find_node(start);
791         start += PAGE_SIZE;
792         while (start < end) {
793                 int n = find_node(start);
794
795                 if (n != *nid)
796                         break;
797                 start += PAGE_SIZE;
798         }
799
800         if (start > end)
801                 start = end;
802
803         return start;
804 }
805 #else
806 static unsigned long long nid_range(unsigned long long start,
807                                     unsigned long long end, int *nid)
808 {
809         *nid = 0;
810         return end;
811 }
812 #endif
813
814 /* This must be invoked after performing all of the necessary
815  * add_active_range() calls for 'nid'.  We need to be able to get
816  * correct data from get_pfn_range_for_nid().
817  */
818 static void __init allocate_node_data(int nid)
819 {
820         unsigned long paddr, num_pages, start_pfn, end_pfn;
821         struct pglist_data *p;
822
823 #ifdef CONFIG_NEED_MULTIPLE_NODES
824         paddr = lmb_alloc_nid(sizeof(struct pglist_data),
825                               SMP_CACHE_BYTES, nid, nid_range);
826         if (!paddr) {
827                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
828                 prom_halt();
829         }
830         NODE_DATA(nid) = __va(paddr);
831         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
832
833         NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
834 #endif
835
836         p = NODE_DATA(nid);
837
838         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
839         p->node_start_pfn = start_pfn;
840         p->node_spanned_pages = end_pfn - start_pfn;
841
842         if (p->node_spanned_pages) {
843                 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
844
845                 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
846                                       nid_range);
847                 if (!paddr) {
848                         prom_printf("Cannot allocate bootmap for nid[%d]\n",
849                                   nid);
850                         prom_halt();
851                 }
852                 node_masks[nid].bootmem_paddr = paddr;
853         }
854 }
855
856 static void init_node_masks_nonnuma(void)
857 {
858         int i;
859
860         numadbg("Initializing tables for non-numa.\n");
861
862         node_masks[0].mask = node_masks[0].val = 0;
863         num_node_masks = 1;
864
865         for (i = 0; i < NR_CPUS; i++)
866                 numa_cpu_lookup_table[i] = 0;
867
868         numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
869 }
870
871 #ifdef CONFIG_NEED_MULTIPLE_NODES
872 struct pglist_data *node_data[MAX_NUMNODES];
873
874 EXPORT_SYMBOL(numa_cpu_lookup_table);
875 EXPORT_SYMBOL(numa_cpumask_lookup_table);
876 EXPORT_SYMBOL(node_data);
877
878 struct mdesc_mlgroup {
879         u64     node;
880         u64     latency;
881         u64     match;
882         u64     mask;
883 };
884 static struct mdesc_mlgroup *mlgroups;
885 static int num_mlgroups;
886
887 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
888                                    u32 cfg_handle)
889 {
890         u64 arc;
891
892         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
893                 u64 target = mdesc_arc_target(md, arc);
894                 const u64 *val;
895
896                 val = mdesc_get_property(md, target,
897                                          "cfg-handle", NULL);
898                 if (val && *val == cfg_handle)
899                         return 0;
900         }
901         return -ENODEV;
902 }
903
904 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
905                                     u32 cfg_handle)
906 {
907         u64 arc, candidate, best_latency = ~(u64)0;
908
909         candidate = MDESC_NODE_NULL;
910         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
911                 u64 target = mdesc_arc_target(md, arc);
912                 const char *name = mdesc_node_name(md, target);
913                 const u64 *val;
914
915                 if (strcmp(name, "pio-latency-group"))
916                         continue;
917
918                 val = mdesc_get_property(md, target, "latency", NULL);
919                 if (!val)
920                         continue;
921
922                 if (*val < best_latency) {
923                         candidate = target;
924                         best_latency = *val;
925                 }
926         }
927
928         if (candidate == MDESC_NODE_NULL)
929                 return -ENODEV;
930
931         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
932 }
933
934 int of_node_to_nid(struct device_node *dp)
935 {
936         const struct linux_prom64_registers *regs;
937         struct mdesc_handle *md;
938         u32 cfg_handle;
939         int count, nid;
940         u64 grp;
941
942         /* This is the right thing to do on currently supported
943          * SUN4U NUMA platforms as well, as the PCI controller does
944          * not sit behind any particular memory controller.
945          */
946         if (!mlgroups)
947                 return -1;
948
949         regs = of_get_property(dp, "reg", NULL);
950         if (!regs)
951                 return -1;
952
953         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
954
955         md = mdesc_grab();
956
957         count = 0;
958         nid = -1;
959         mdesc_for_each_node_by_name(md, grp, "group") {
960                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
961                         nid = count;
962                         break;
963                 }
964                 count++;
965         }
966
967         mdesc_release(md);
968
969         return nid;
970 }
971
972 static void __init add_node_ranges(void)
973 {
974         int i;
975
976         for (i = 0; i < lmb.memory.cnt; i++) {
977                 unsigned long size = lmb_size_bytes(&lmb.memory, i);
978                 unsigned long start, end;
979
980                 start = lmb.memory.region[i].base;
981                 end = start + size;
982                 while (start < end) {
983                         unsigned long this_end;
984                         int nid;
985
986                         this_end = nid_range(start, end, &nid);
987
988                         numadbg("Adding active range nid[%d] "
989                                 "start[%lx] end[%lx]\n",
990                                 nid, start, this_end);
991
992                         add_active_range(nid,
993                                          start >> PAGE_SHIFT,
994                                          this_end >> PAGE_SHIFT);
995
996                         start = this_end;
997                 }
998         }
999 }
1000
1001 static int __init grab_mlgroups(struct mdesc_handle *md)
1002 {
1003         unsigned long paddr;
1004         int count = 0;
1005         u64 node;
1006
1007         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1008                 count++;
1009         if (!count)
1010                 return -ENOENT;
1011
1012         paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1013                           SMP_CACHE_BYTES);
1014         if (!paddr)
1015                 return -ENOMEM;
1016
1017         mlgroups = __va(paddr);
1018         num_mlgroups = count;
1019
1020         count = 0;
1021         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1022                 struct mdesc_mlgroup *m = &mlgroups[count++];
1023                 const u64 *val;
1024
1025                 m->node = node;
1026
1027                 val = mdesc_get_property(md, node, "latency", NULL);
1028                 m->latency = *val;
1029                 val = mdesc_get_property(md, node, "address-match", NULL);
1030                 m->match = *val;
1031                 val = mdesc_get_property(md, node, "address-mask", NULL);
1032                 m->mask = *val;
1033
1034                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1035                         "match[%llx] mask[%llx]\n",
1036                         count - 1, m->node, m->latency, m->match, m->mask);
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int __init grab_mblocks(struct mdesc_handle *md)
1043 {
1044         unsigned long paddr;
1045         int count = 0;
1046         u64 node;
1047
1048         mdesc_for_each_node_by_name(md, node, "mblock")
1049                 count++;
1050         if (!count)
1051                 return -ENOENT;
1052
1053         paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1054                           SMP_CACHE_BYTES);
1055         if (!paddr)
1056                 return -ENOMEM;
1057
1058         mblocks = __va(paddr);
1059         num_mblocks = count;
1060
1061         count = 0;
1062         mdesc_for_each_node_by_name(md, node, "mblock") {
1063                 struct mdesc_mblock *m = &mblocks[count++];
1064                 const u64 *val;
1065
1066                 val = mdesc_get_property(md, node, "base", NULL);
1067                 m->base = *val;
1068                 val = mdesc_get_property(md, node, "size", NULL);
1069                 m->size = *val;
1070                 val = mdesc_get_property(md, node,
1071                                          "address-congruence-offset", NULL);
1072                 m->offset = *val;
1073
1074                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1075                         count - 1, m->base, m->size, m->offset);
1076         }
1077
1078         return 0;
1079 }
1080
1081 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1082                                                u64 grp, cpumask_t *mask)
1083 {
1084         u64 arc;
1085
1086         cpus_clear(*mask);
1087
1088         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1089                 u64 target = mdesc_arc_target(md, arc);
1090                 const char *name = mdesc_node_name(md, target);
1091                 const u64 *id;
1092
1093                 if (strcmp(name, "cpu"))
1094                         continue;
1095                 id = mdesc_get_property(md, target, "id", NULL);
1096                 if (*id < nr_cpu_ids)
1097                         cpu_set(*id, *mask);
1098         }
1099 }
1100
1101 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1102 {
1103         int i;
1104
1105         for (i = 0; i < num_mlgroups; i++) {
1106                 struct mdesc_mlgroup *m = &mlgroups[i];
1107                 if (m->node == node)
1108                         return m;
1109         }
1110         return NULL;
1111 }
1112
1113 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1114                                       int index)
1115 {
1116         struct mdesc_mlgroup *candidate = NULL;
1117         u64 arc, best_latency = ~(u64)0;
1118         struct node_mem_mask *n;
1119
1120         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1121                 u64 target = mdesc_arc_target(md, arc);
1122                 struct mdesc_mlgroup *m = find_mlgroup(target);
1123                 if (!m)
1124                         continue;
1125                 if (m->latency < best_latency) {
1126                         candidate = m;
1127                         best_latency = m->latency;
1128                 }
1129         }
1130         if (!candidate)
1131                 return -ENOENT;
1132
1133         if (num_node_masks != index) {
1134                 printk(KERN_ERR "Inconsistent NUMA state, "
1135                        "index[%d] != num_node_masks[%d]\n",
1136                        index, num_node_masks);
1137                 return -EINVAL;
1138         }
1139
1140         n = &node_masks[num_node_masks++];
1141
1142         n->mask = candidate->mask;
1143         n->val = candidate->match;
1144
1145         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1146                 index, n->mask, n->val, candidate->latency);
1147
1148         return 0;
1149 }
1150
1151 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1152                                          int index)
1153 {
1154         cpumask_t mask;
1155         int cpu;
1156
1157         numa_parse_mdesc_group_cpus(md, grp, &mask);
1158
1159         for_each_cpu_mask(cpu, mask)
1160                 numa_cpu_lookup_table[cpu] = index;
1161         numa_cpumask_lookup_table[index] = mask;
1162
1163         if (numa_debug) {
1164                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1165                 for_each_cpu_mask(cpu, mask)
1166                         printk("%d ", cpu);
1167                 printk("]\n");
1168         }
1169
1170         return numa_attach_mlgroup(md, grp, index);
1171 }
1172
1173 static int __init numa_parse_mdesc(void)
1174 {
1175         struct mdesc_handle *md = mdesc_grab();
1176         int i, err, count;
1177         u64 node;
1178
1179         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1180         if (node == MDESC_NODE_NULL) {
1181                 mdesc_release(md);
1182                 return -ENOENT;
1183         }
1184
1185         err = grab_mblocks(md);
1186         if (err < 0)
1187                 goto out;
1188
1189         err = grab_mlgroups(md);
1190         if (err < 0)
1191                 goto out;
1192
1193         count = 0;
1194         mdesc_for_each_node_by_name(md, node, "group") {
1195                 err = numa_parse_mdesc_group(md, node, count);
1196                 if (err < 0)
1197                         break;
1198                 count++;
1199         }
1200
1201         add_node_ranges();
1202
1203         for (i = 0; i < num_node_masks; i++) {
1204                 allocate_node_data(i);
1205                 node_set_online(i);
1206         }
1207
1208         err = 0;
1209 out:
1210         mdesc_release(md);
1211         return err;
1212 }
1213
1214 static int __init numa_parse_jbus(void)
1215 {
1216         unsigned long cpu, index;
1217
1218         /* NUMA node id is encoded in bits 36 and higher, and there is
1219          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1220          */
1221         index = 0;
1222         for_each_present_cpu(cpu) {
1223                 numa_cpu_lookup_table[cpu] = index;
1224                 numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu);
1225                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1226                 node_masks[index].val = cpu << 36UL;
1227
1228                 index++;
1229         }
1230         num_node_masks = index;
1231
1232         add_node_ranges();
1233
1234         for (index = 0; index < num_node_masks; index++) {
1235                 allocate_node_data(index);
1236                 node_set_online(index);
1237         }
1238
1239         return 0;
1240 }
1241
1242 static int __init numa_parse_sun4u(void)
1243 {
1244         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1245                 unsigned long ver;
1246
1247                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1248                 if ((ver >> 32UL) == __JALAPENO_ID ||
1249                     (ver >> 32UL) == __SERRANO_ID)
1250                         return numa_parse_jbus();
1251         }
1252         return -1;
1253 }
1254
1255 static int __init bootmem_init_numa(void)
1256 {
1257         int err = -1;
1258
1259         numadbg("bootmem_init_numa()\n");
1260
1261         if (numa_enabled) {
1262                 if (tlb_type == hypervisor)
1263                         err = numa_parse_mdesc();
1264                 else
1265                         err = numa_parse_sun4u();
1266         }
1267         return err;
1268 }
1269
1270 #else
1271
1272 static int bootmem_init_numa(void)
1273 {
1274         return -1;
1275 }
1276
1277 #endif
1278
1279 static void __init bootmem_init_nonnuma(void)
1280 {
1281         unsigned long top_of_ram = lmb_end_of_DRAM();
1282         unsigned long total_ram = lmb_phys_mem_size();
1283         unsigned int i;
1284
1285         numadbg("bootmem_init_nonnuma()\n");
1286
1287         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1288                top_of_ram, total_ram);
1289         printk(KERN_INFO "Memory hole size: %ldMB\n",
1290                (top_of_ram - total_ram) >> 20);
1291
1292         init_node_masks_nonnuma();
1293
1294         for (i = 0; i < lmb.memory.cnt; i++) {
1295                 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1296                 unsigned long start_pfn, end_pfn;
1297
1298                 if (!size)
1299                         continue;
1300
1301                 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1302                 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1303                 add_active_range(0, start_pfn, end_pfn);
1304         }
1305
1306         allocate_node_data(0);
1307
1308         node_set_online(0);
1309 }
1310
1311 static void __init reserve_range_in_node(int nid, unsigned long start,
1312                                          unsigned long end)
1313 {
1314         numadbg("    reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1315                 nid, start, end);
1316         while (start < end) {
1317                 unsigned long this_end;
1318                 int n;
1319
1320                 this_end = nid_range(start, end, &n);
1321                 if (n == nid) {
1322                         numadbg("      MATCH reserving range [%lx:%lx]\n",
1323                                 start, this_end);
1324                         reserve_bootmem_node(NODE_DATA(nid), start,
1325                                              (this_end - start), BOOTMEM_DEFAULT);
1326                 } else
1327                         numadbg("      NO MATCH, advancing start to %lx\n",
1328                                 this_end);
1329
1330                 start = this_end;
1331         }
1332 }
1333
1334 static void __init trim_reserved_in_node(int nid)
1335 {
1336         int i;
1337
1338         numadbg("  trim_reserved_in_node(%d)\n", nid);
1339
1340         for (i = 0; i < lmb.reserved.cnt; i++) {
1341                 unsigned long start = lmb.reserved.region[i].base;
1342                 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1343                 unsigned long end = start + size;
1344
1345                 reserve_range_in_node(nid, start, end);
1346         }
1347 }
1348
1349 static void __init bootmem_init_one_node(int nid)
1350 {
1351         struct pglist_data *p;
1352
1353         numadbg("bootmem_init_one_node(%d)\n", nid);
1354
1355         p = NODE_DATA(nid);
1356
1357         if (p->node_spanned_pages) {
1358                 unsigned long paddr = node_masks[nid].bootmem_paddr;
1359                 unsigned long end_pfn;
1360
1361                 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1362
1363                 numadbg("  init_bootmem_node(%d, %lx, %lx, %lx)\n",
1364                         nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1365
1366                 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1367                                   p->node_start_pfn, end_pfn);
1368
1369                 numadbg("  free_bootmem_with_active_regions(%d, %lx)\n",
1370                         nid, end_pfn);
1371                 free_bootmem_with_active_regions(nid, end_pfn);
1372
1373                 trim_reserved_in_node(nid);
1374
1375                 numadbg("  sparse_memory_present_with_active_regions(%d)\n",
1376                         nid);
1377                 sparse_memory_present_with_active_regions(nid);
1378         }
1379 }
1380
1381 static unsigned long __init bootmem_init(unsigned long phys_base)
1382 {
1383         unsigned long end_pfn;
1384         int nid;
1385
1386         end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1387         max_pfn = max_low_pfn = end_pfn;
1388         min_low_pfn = (phys_base >> PAGE_SHIFT);
1389
1390         if (bootmem_init_numa() < 0)
1391                 bootmem_init_nonnuma();
1392
1393         /* XXX cpu notifier XXX */
1394
1395         for_each_online_node(nid)
1396                 bootmem_init_one_node(nid);
1397
1398         sparse_init();
1399
1400         return end_pfn;
1401 }
1402
1403 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1404 static int pall_ents __initdata;
1405
1406 #ifdef CONFIG_DEBUG_PAGEALLOC
1407 static unsigned long __ref kernel_map_range(unsigned long pstart,
1408                                             unsigned long pend, pgprot_t prot)
1409 {
1410         unsigned long vstart = PAGE_OFFSET + pstart;
1411         unsigned long vend = PAGE_OFFSET + pend;
1412         unsigned long alloc_bytes = 0UL;
1413
1414         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1415                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1416                             vstart, vend);
1417                 prom_halt();
1418         }
1419
1420         while (vstart < vend) {
1421                 unsigned long this_end, paddr = __pa(vstart);
1422                 pgd_t *pgd = pgd_offset_k(vstart);
1423                 pud_t *pud;
1424                 pmd_t *pmd;
1425                 pte_t *pte;
1426
1427                 pud = pud_offset(pgd, vstart);
1428                 if (pud_none(*pud)) {
1429                         pmd_t *new;
1430
1431                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1432                         alloc_bytes += PAGE_SIZE;
1433                         pud_populate(&init_mm, pud, new);
1434                 }
1435
1436                 pmd = pmd_offset(pud, vstart);
1437                 if (!pmd_present(*pmd)) {
1438                         pte_t *new;
1439
1440                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1441                         alloc_bytes += PAGE_SIZE;
1442                         pmd_populate_kernel(&init_mm, pmd, new);
1443                 }
1444
1445                 pte = pte_offset_kernel(pmd, vstart);
1446                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1447                 if (this_end > vend)
1448                         this_end = vend;
1449
1450                 while (vstart < this_end) {
1451                         pte_val(*pte) = (paddr | pgprot_val(prot));
1452
1453                         vstart += PAGE_SIZE;
1454                         paddr += PAGE_SIZE;
1455                         pte++;
1456                 }
1457         }
1458
1459         return alloc_bytes;
1460 }
1461
1462 extern unsigned int kvmap_linear_patch[1];
1463 #endif /* CONFIG_DEBUG_PAGEALLOC */
1464
1465 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1466 {
1467         const unsigned long shift_256MB = 28;
1468         const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1469         const unsigned long size_256MB = (1UL << shift_256MB);
1470
1471         while (start < end) {
1472                 long remains;
1473
1474                 remains = end - start;
1475                 if (remains < size_256MB)
1476                         break;
1477
1478                 if (start & mask_256MB) {
1479                         start = (start + size_256MB) & ~mask_256MB;
1480                         continue;
1481                 }
1482
1483                 while (remains >= size_256MB) {
1484                         unsigned long index = start >> shift_256MB;
1485
1486                         __set_bit(index, kpte_linear_bitmap);
1487
1488                         start += size_256MB;
1489                         remains -= size_256MB;
1490                 }
1491         }
1492 }
1493
1494 static void __init init_kpte_bitmap(void)
1495 {
1496         unsigned long i;
1497
1498         for (i = 0; i < pall_ents; i++) {
1499                 unsigned long phys_start, phys_end;
1500
1501                 phys_start = pall[i].phys_addr;
1502                 phys_end = phys_start + pall[i].reg_size;
1503
1504                 mark_kpte_bitmap(phys_start, phys_end);
1505         }
1506 }
1507
1508 static void __init kernel_physical_mapping_init(void)
1509 {
1510 #ifdef CONFIG_DEBUG_PAGEALLOC
1511         unsigned long i, mem_alloced = 0UL;
1512
1513         for (i = 0; i < pall_ents; i++) {
1514                 unsigned long phys_start, phys_end;
1515
1516                 phys_start = pall[i].phys_addr;
1517                 phys_end = phys_start + pall[i].reg_size;
1518
1519                 mem_alloced += kernel_map_range(phys_start, phys_end,
1520                                                 PAGE_KERNEL);
1521         }
1522
1523         printk("Allocated %ld bytes for kernel page tables.\n",
1524                mem_alloced);
1525
1526         kvmap_linear_patch[0] = 0x01000000; /* nop */
1527         flushi(&kvmap_linear_patch[0]);
1528
1529         __flush_tlb_all();
1530 #endif
1531 }
1532
1533 #ifdef CONFIG_DEBUG_PAGEALLOC
1534 void kernel_map_pages(struct page *page, int numpages, int enable)
1535 {
1536         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1537         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1538
1539         kernel_map_range(phys_start, phys_end,
1540                          (enable ? PAGE_KERNEL : __pgprot(0)));
1541
1542         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1543                                PAGE_OFFSET + phys_end);
1544
1545         /* we should perform an IPI and flush all tlbs,
1546          * but that can deadlock->flush only current cpu.
1547          */
1548         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1549                                  PAGE_OFFSET + phys_end);
1550 }
1551 #endif
1552
1553 unsigned long __init find_ecache_flush_span(unsigned long size)
1554 {
1555         int i;
1556
1557         for (i = 0; i < pavail_ents; i++) {
1558                 if (pavail[i].reg_size >= size)
1559                         return pavail[i].phys_addr;
1560         }
1561
1562         return ~0UL;
1563 }
1564
1565 static void __init tsb_phys_patch(void)
1566 {
1567         struct tsb_ldquad_phys_patch_entry *pquad;
1568         struct tsb_phys_patch_entry *p;
1569
1570         pquad = &__tsb_ldquad_phys_patch;
1571         while (pquad < &__tsb_ldquad_phys_patch_end) {
1572                 unsigned long addr = pquad->addr;
1573
1574                 if (tlb_type == hypervisor)
1575                         *(unsigned int *) addr = pquad->sun4v_insn;
1576                 else
1577                         *(unsigned int *) addr = pquad->sun4u_insn;
1578                 wmb();
1579                 __asm__ __volatile__("flush     %0"
1580                                      : /* no outputs */
1581                                      : "r" (addr));
1582
1583                 pquad++;
1584         }
1585
1586         p = &__tsb_phys_patch;
1587         while (p < &__tsb_phys_patch_end) {
1588                 unsigned long addr = p->addr;
1589
1590                 *(unsigned int *) addr = p->insn;
1591                 wmb();
1592                 __asm__ __volatile__("flush     %0"
1593                                      : /* no outputs */
1594                                      : "r" (addr));
1595
1596                 p++;
1597         }
1598 }
1599
1600 /* Don't mark as init, we give this to the Hypervisor.  */
1601 #ifndef CONFIG_DEBUG_PAGEALLOC
1602 #define NUM_KTSB_DESCR  2
1603 #else
1604 #define NUM_KTSB_DESCR  1
1605 #endif
1606 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1607 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1608
1609 static void __init sun4v_ktsb_init(void)
1610 {
1611         unsigned long ktsb_pa;
1612
1613         /* First KTSB for PAGE_SIZE mappings.  */
1614         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1615
1616         switch (PAGE_SIZE) {
1617         case 8 * 1024:
1618         default:
1619                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1620                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1621                 break;
1622
1623         case 64 * 1024:
1624                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1625                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1626                 break;
1627
1628         case 512 * 1024:
1629                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1630                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1631                 break;
1632
1633         case 4 * 1024 * 1024:
1634                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1635                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1636                 break;
1637         };
1638
1639         ktsb_descr[0].assoc = 1;
1640         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1641         ktsb_descr[0].ctx_idx = 0;
1642         ktsb_descr[0].tsb_base = ktsb_pa;
1643         ktsb_descr[0].resv = 0;
1644
1645 #ifndef CONFIG_DEBUG_PAGEALLOC
1646         /* Second KTSB for 4MB/256MB mappings.  */
1647         ktsb_pa = (kern_base +
1648                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1649
1650         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1651         ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1652                                    HV_PGSZ_MASK_256MB);
1653         ktsb_descr[1].assoc = 1;
1654         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1655         ktsb_descr[1].ctx_idx = 0;
1656         ktsb_descr[1].tsb_base = ktsb_pa;
1657         ktsb_descr[1].resv = 0;
1658 #endif
1659 }
1660
1661 void __cpuinit sun4v_ktsb_register(void)
1662 {
1663         unsigned long pa, ret;
1664
1665         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1666
1667         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1668         if (ret != 0) {
1669                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1670                             "errors with %lx\n", pa, ret);
1671                 prom_halt();
1672         }
1673 }
1674
1675 /* paging_init() sets up the page tables */
1676
1677 static unsigned long last_valid_pfn;
1678 pgd_t swapper_pg_dir[2048];
1679
1680 static void sun4u_pgprot_init(void);
1681 static void sun4v_pgprot_init(void);
1682
1683 void __init paging_init(void)
1684 {
1685         unsigned long end_pfn, shift, phys_base;
1686         unsigned long real_end, i;
1687
1688         /* These build time checkes make sure that the dcache_dirty_cpu()
1689          * page->flags usage will work.
1690          *
1691          * When a page gets marked as dcache-dirty, we store the
1692          * cpu number starting at bit 32 in the page->flags.  Also,
1693          * functions like clear_dcache_dirty_cpu use the cpu mask
1694          * in 13-bit signed-immediate instruction fields.
1695          */
1696
1697         /*
1698          * Page flags must not reach into upper 32 bits that are used
1699          * for the cpu number
1700          */
1701         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1702
1703         /*
1704          * The bit fields placed in the high range must not reach below
1705          * the 32 bit boundary. Otherwise we cannot place the cpu field
1706          * at the 32 bit boundary.
1707          */
1708         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1709                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1710
1711         BUILD_BUG_ON(NR_CPUS > 4096);
1712
1713         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1714         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1715
1716         /* Invalidate both kernel TSBs.  */
1717         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1718 #ifndef CONFIG_DEBUG_PAGEALLOC
1719         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1720 #endif
1721
1722         if (tlb_type == hypervisor)
1723                 sun4v_pgprot_init();
1724         else
1725                 sun4u_pgprot_init();
1726
1727         if (tlb_type == cheetah_plus ||
1728             tlb_type == hypervisor)
1729                 tsb_phys_patch();
1730
1731         if (tlb_type == hypervisor) {
1732                 sun4v_patch_tlb_handlers();
1733                 sun4v_ktsb_init();
1734         }
1735
1736         lmb_init();
1737
1738         /* Find available physical memory...
1739          *
1740          * Read it twice in order to work around a bug in openfirmware.
1741          * The call to grab this table itself can cause openfirmware to
1742          * allocate memory, which in turn can take away some space from
1743          * the list of available memory.  Reading it twice makes sure
1744          * we really do get the final value.
1745          */
1746         read_obp_translations();
1747         read_obp_memory("reg", &pall[0], &pall_ents);
1748         read_obp_memory("available", &pavail[0], &pavail_ents);
1749         read_obp_memory("available", &pavail[0], &pavail_ents);
1750
1751         phys_base = 0xffffffffffffffffUL;
1752         for (i = 0; i < pavail_ents; i++) {
1753                 phys_base = min(phys_base, pavail[i].phys_addr);
1754                 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1755         }
1756
1757         lmb_reserve(kern_base, kern_size);
1758
1759         find_ramdisk(phys_base);
1760
1761         lmb_enforce_memory_limit(cmdline_memory_size);
1762
1763         lmb_analyze();
1764         lmb_dump_all();
1765
1766         set_bit(0, mmu_context_bmap);
1767
1768         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1769
1770         real_end = (unsigned long)_end;
1771         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1772         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1773                num_kernel_image_mappings);
1774
1775         /* Set kernel pgd to upper alias so physical page computations
1776          * work.
1777          */
1778         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1779         
1780         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1781
1782         /* Now can init the kernel/bad page tables. */
1783         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1784                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1785         
1786         inherit_prom_mappings();
1787         
1788         init_kpte_bitmap();
1789
1790         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1791         setup_tba();
1792
1793         __flush_tlb_all();
1794
1795         if (tlb_type == hypervisor)
1796                 sun4v_ktsb_register();
1797
1798         prom_build_devicetree();
1799         of_populate_present_mask();
1800 #ifndef CONFIG_SMP
1801         of_fill_in_cpu_data();
1802 #endif
1803
1804         if (tlb_type == hypervisor) {
1805                 sun4v_mdesc_init();
1806                 mdesc_populate_present_mask(cpu_all_mask);
1807 #ifndef CONFIG_SMP
1808                 mdesc_fill_in_cpu_data(cpu_all_mask);
1809 #endif
1810         }
1811
1812         /* Once the OF device tree and MDESC have been setup, we know
1813          * the list of possible cpus.  Therefore we can allocate the
1814          * IRQ stacks.
1815          */
1816         for_each_possible_cpu(i) {
1817                 /* XXX Use node local allocations... XXX */
1818                 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1819                 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1820         }
1821
1822         /* Setup bootmem... */
1823         last_valid_pfn = end_pfn = bootmem_init(phys_base);
1824
1825 #ifndef CONFIG_NEED_MULTIPLE_NODES
1826         max_mapnr = last_valid_pfn;
1827 #endif
1828         kernel_physical_mapping_init();
1829
1830         {
1831                 unsigned long max_zone_pfns[MAX_NR_ZONES];
1832
1833                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1834
1835                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1836
1837                 free_area_init_nodes(max_zone_pfns);
1838         }
1839
1840         printk("Booting Linux...\n");
1841 }
1842
1843 int __devinit page_in_phys_avail(unsigned long paddr)
1844 {
1845         int i;
1846
1847         paddr &= PAGE_MASK;
1848
1849         for (i = 0; i < pavail_ents; i++) {
1850                 unsigned long start, end;
1851
1852                 start = pavail[i].phys_addr;
1853                 end = start + pavail[i].reg_size;
1854
1855                 if (paddr >= start && paddr < end)
1856                         return 1;
1857         }
1858         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1859                 return 1;
1860 #ifdef CONFIG_BLK_DEV_INITRD
1861         if (paddr >= __pa(initrd_start) &&
1862             paddr < __pa(PAGE_ALIGN(initrd_end)))
1863                 return 1;
1864 #endif
1865
1866         return 0;
1867 }
1868
1869 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1870 static int pavail_rescan_ents __initdata;
1871
1872 /* Certain OBP calls, such as fetching "available" properties, can
1873  * claim physical memory.  So, along with initializing the valid
1874  * address bitmap, what we do here is refetch the physical available
1875  * memory list again, and make sure it provides at least as much
1876  * memory as 'pavail' does.
1877  */
1878 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1879 {
1880         int i;
1881
1882         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1883
1884         for (i = 0; i < pavail_ents; i++) {
1885                 unsigned long old_start, old_end;
1886
1887                 old_start = pavail[i].phys_addr;
1888                 old_end = old_start + pavail[i].reg_size;
1889                 while (old_start < old_end) {
1890                         int n;
1891
1892                         for (n = 0; n < pavail_rescan_ents; n++) {
1893                                 unsigned long new_start, new_end;
1894
1895                                 new_start = pavail_rescan[n].phys_addr;
1896                                 new_end = new_start +
1897                                         pavail_rescan[n].reg_size;
1898
1899                                 if (new_start <= old_start &&
1900                                     new_end >= (old_start + PAGE_SIZE)) {
1901                                         set_bit(old_start >> 22, bitmap);
1902                                         goto do_next_page;
1903                                 }
1904                         }
1905
1906                         prom_printf("mem_init: Lost memory in pavail\n");
1907                         prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1908                                     pavail[i].phys_addr,
1909                                     pavail[i].reg_size);
1910                         prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1911                                     pavail_rescan[i].phys_addr,
1912                                     pavail_rescan[i].reg_size);
1913                         prom_printf("mem_init: Cannot continue, aborting.\n");
1914                         prom_halt();
1915
1916                 do_next_page:
1917                         old_start += PAGE_SIZE;
1918                 }
1919         }
1920 }
1921
1922 static void __init patch_tlb_miss_handler_bitmap(void)
1923 {
1924         extern unsigned int valid_addr_bitmap_insn[];
1925         extern unsigned int valid_addr_bitmap_patch[];
1926
1927         valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
1928         mb();
1929         valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
1930         flushi(&valid_addr_bitmap_insn[0]);
1931 }
1932
1933 void __init mem_init(void)
1934 {
1935         unsigned long codepages, datapages, initpages;
1936         unsigned long addr, last;
1937
1938         addr = PAGE_OFFSET + kern_base;
1939         last = PAGE_ALIGN(kern_size) + addr;
1940         while (addr < last) {
1941                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1942                 addr += PAGE_SIZE;
1943         }
1944
1945         setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
1946         patch_tlb_miss_handler_bitmap();
1947
1948         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1949
1950 #ifdef CONFIG_NEED_MULTIPLE_NODES
1951         {
1952                 int i;
1953                 for_each_online_node(i) {
1954                         if (NODE_DATA(i)->node_spanned_pages != 0) {
1955                                 totalram_pages +=
1956                                         free_all_bootmem_node(NODE_DATA(i));
1957                         }
1958                 }
1959         }
1960 #else
1961         totalram_pages = free_all_bootmem();
1962 #endif
1963
1964         /* We subtract one to account for the mem_map_zero page
1965          * allocated below.
1966          */
1967         totalram_pages -= 1;
1968         num_physpages = totalram_pages;
1969
1970         /*
1971          * Set up the zero page, mark it reserved, so that page count
1972          * is not manipulated when freeing the page from user ptes.
1973          */
1974         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1975         if (mem_map_zero == NULL) {
1976                 prom_printf("paging_init: Cannot alloc zero page.\n");
1977                 prom_halt();
1978         }
1979         SetPageReserved(mem_map_zero);
1980
1981         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1982         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1983         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1984         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1985         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1986         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1987
1988         printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1989                nr_free_pages() << (PAGE_SHIFT-10),
1990                codepages << (PAGE_SHIFT-10),
1991                datapages << (PAGE_SHIFT-10), 
1992                initpages << (PAGE_SHIFT-10), 
1993                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1994
1995         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1996                 cheetah_ecache_flush_init();
1997 }
1998
1999 void free_initmem(void)
2000 {
2001         unsigned long addr, initend;
2002         int do_free = 1;
2003
2004         /* If the physical memory maps were trimmed by kernel command
2005          * line options, don't even try freeing this initmem stuff up.
2006          * The kernel image could have been in the trimmed out region
2007          * and if so the freeing below will free invalid page structs.
2008          */
2009         if (cmdline_memory_size)
2010                 do_free = 0;
2011
2012         /*
2013          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2014          */
2015         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2016         initend = (unsigned long)(__init_end) & PAGE_MASK;
2017         for (; addr < initend; addr += PAGE_SIZE) {
2018                 unsigned long page;
2019                 struct page *p;
2020
2021                 page = (addr +
2022                         ((unsigned long) __va(kern_base)) -
2023                         ((unsigned long) KERNBASE));
2024                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2025
2026                 if (do_free) {
2027                         p = virt_to_page(page);
2028
2029                         ClearPageReserved(p);
2030                         init_page_count(p);
2031                         __free_page(p);
2032                         num_physpages++;
2033                         totalram_pages++;
2034                 }
2035         }
2036 }
2037
2038 #ifdef CONFIG_BLK_DEV_INITRD
2039 void free_initrd_mem(unsigned long start, unsigned long end)
2040 {
2041         if (start < end)
2042                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2043         for (; start < end; start += PAGE_SIZE) {
2044                 struct page *p = virt_to_page(start);
2045
2046                 ClearPageReserved(p);
2047                 init_page_count(p);
2048                 __free_page(p);
2049                 num_physpages++;
2050                 totalram_pages++;
2051         }
2052 }
2053 #endif
2054
2055 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2056 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2057 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2058 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2059 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2060 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2061
2062 pgprot_t PAGE_KERNEL __read_mostly;
2063 EXPORT_SYMBOL(PAGE_KERNEL);
2064
2065 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2066 pgprot_t PAGE_COPY __read_mostly;
2067
2068 pgprot_t PAGE_SHARED __read_mostly;
2069 EXPORT_SYMBOL(PAGE_SHARED);
2070
2071 unsigned long pg_iobits __read_mostly;
2072
2073 unsigned long _PAGE_IE __read_mostly;
2074 EXPORT_SYMBOL(_PAGE_IE);
2075
2076 unsigned long _PAGE_E __read_mostly;
2077 EXPORT_SYMBOL(_PAGE_E);
2078
2079 unsigned long _PAGE_CACHE __read_mostly;
2080 EXPORT_SYMBOL(_PAGE_CACHE);
2081
2082 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2083 unsigned long vmemmap_table[VMEMMAP_SIZE];
2084
2085 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2086 {
2087         unsigned long vstart = (unsigned long) start;
2088         unsigned long vend = (unsigned long) (start + nr);
2089         unsigned long phys_start = (vstart - VMEMMAP_BASE);
2090         unsigned long phys_end = (vend - VMEMMAP_BASE);
2091         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2092         unsigned long end = VMEMMAP_ALIGN(phys_end);
2093         unsigned long pte_base;
2094
2095         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2096                     _PAGE_CP_4U | _PAGE_CV_4U |
2097                     _PAGE_P_4U | _PAGE_W_4U);
2098         if (tlb_type == hypervisor)
2099                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2100                             _PAGE_CP_4V | _PAGE_CV_4V |
2101                             _PAGE_P_4V | _PAGE_W_4V);
2102
2103         for (; addr < end; addr += VMEMMAP_CHUNK) {
2104                 unsigned long *vmem_pp =
2105                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2106                 void *block;
2107
2108                 if (!(*vmem_pp & _PAGE_VALID)) {
2109                         block = vmemmap_alloc_block(1UL << 22, node);
2110                         if (!block)
2111                                 return -ENOMEM;
2112
2113                         *vmem_pp = pte_base | __pa(block);
2114
2115                         printk(KERN_INFO "[%p-%p] page_structs=%lu "
2116                                "node=%d entry=%lu/%lu\n", start, block, nr,
2117                                node,
2118                                addr >> VMEMMAP_CHUNK_SHIFT,
2119                                VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2120                 }
2121         }
2122         return 0;
2123 }
2124 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2125
2126 static void prot_init_common(unsigned long page_none,
2127                              unsigned long page_shared,
2128                              unsigned long page_copy,
2129                              unsigned long page_readonly,
2130                              unsigned long page_exec_bit)
2131 {
2132         PAGE_COPY = __pgprot(page_copy);
2133         PAGE_SHARED = __pgprot(page_shared);
2134
2135         protection_map[0x0] = __pgprot(page_none);
2136         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2137         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2138         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2139         protection_map[0x4] = __pgprot(page_readonly);
2140         protection_map[0x5] = __pgprot(page_readonly);
2141         protection_map[0x6] = __pgprot(page_copy);
2142         protection_map[0x7] = __pgprot(page_copy);
2143         protection_map[0x8] = __pgprot(page_none);
2144         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2145         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2146         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2147         protection_map[0xc] = __pgprot(page_readonly);
2148         protection_map[0xd] = __pgprot(page_readonly);
2149         protection_map[0xe] = __pgprot(page_shared);
2150         protection_map[0xf] = __pgprot(page_shared);
2151 }
2152
2153 static void __init sun4u_pgprot_init(void)
2154 {
2155         unsigned long page_none, page_shared, page_copy, page_readonly;
2156         unsigned long page_exec_bit;
2157
2158         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2159                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2160                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2161                                 _PAGE_EXEC_4U);
2162         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2163                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2164                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2165                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2166
2167         _PAGE_IE = _PAGE_IE_4U;
2168         _PAGE_E = _PAGE_E_4U;
2169         _PAGE_CACHE = _PAGE_CACHE_4U;
2170
2171         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2172                      __ACCESS_BITS_4U | _PAGE_E_4U);
2173
2174 #ifdef CONFIG_DEBUG_PAGEALLOC
2175         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2176                 0xfffff80000000000UL;
2177 #else
2178         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2179                 0xfffff80000000000UL;
2180 #endif
2181         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2182                                    _PAGE_P_4U | _PAGE_W_4U);
2183
2184         /* XXX Should use 256MB on Panther. XXX */
2185         kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2186
2187         _PAGE_SZBITS = _PAGE_SZBITS_4U;
2188         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2189                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2190                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2191
2192
2193         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2194         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2195                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2196         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2197                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2198         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2199                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2200
2201         page_exec_bit = _PAGE_EXEC_4U;
2202
2203         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2204                          page_exec_bit);
2205 }
2206
2207 static void __init sun4v_pgprot_init(void)
2208 {
2209         unsigned long page_none, page_shared, page_copy, page_readonly;
2210         unsigned long page_exec_bit;
2211
2212         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2213                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2214                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2215                                 _PAGE_EXEC_4V);
2216         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2217
2218         _PAGE_IE = _PAGE_IE_4V;
2219         _PAGE_E = _PAGE_E_4V;
2220         _PAGE_CACHE = _PAGE_CACHE_4V;
2221
2222 #ifdef CONFIG_DEBUG_PAGEALLOC
2223         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2224                 0xfffff80000000000UL;
2225 #else
2226         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2227                 0xfffff80000000000UL;
2228 #endif
2229         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2230                                    _PAGE_P_4V | _PAGE_W_4V);
2231
2232 #ifdef CONFIG_DEBUG_PAGEALLOC
2233         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2234                 0xfffff80000000000UL;
2235 #else
2236         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2237                 0xfffff80000000000UL;
2238 #endif
2239         kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2240                                    _PAGE_P_4V | _PAGE_W_4V);
2241
2242         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2243                      __ACCESS_BITS_4V | _PAGE_E_4V);
2244
2245         _PAGE_SZBITS = _PAGE_SZBITS_4V;
2246         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2247                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2248                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2249                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2250
2251         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2252         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2253                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2254         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2255                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2256         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2257                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2258
2259         page_exec_bit = _PAGE_EXEC_4V;
2260
2261         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2262                          page_exec_bit);
2263 }
2264
2265 unsigned long pte_sz_bits(unsigned long sz)
2266 {
2267         if (tlb_type == hypervisor) {
2268                 switch (sz) {
2269                 case 8 * 1024:
2270                 default:
2271                         return _PAGE_SZ8K_4V;
2272                 case 64 * 1024:
2273                         return _PAGE_SZ64K_4V;
2274                 case 512 * 1024:
2275                         return _PAGE_SZ512K_4V;
2276                 case 4 * 1024 * 1024:
2277                         return _PAGE_SZ4MB_4V;
2278                 };
2279         } else {
2280                 switch (sz) {
2281                 case 8 * 1024:
2282                 default:
2283                         return _PAGE_SZ8K_4U;
2284                 case 64 * 1024:
2285                         return _PAGE_SZ64K_4U;
2286                 case 512 * 1024:
2287                         return _PAGE_SZ512K_4U;
2288                 case 4 * 1024 * 1024:
2289                         return _PAGE_SZ4MB_4U;
2290                 };
2291         }
2292 }
2293
2294 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2295 {
2296         pte_t pte;
2297
2298         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2299         pte_val(pte) |= (((unsigned long)space) << 32);
2300         pte_val(pte) |= pte_sz_bits(page_size);
2301
2302         return pte;
2303 }
2304
2305 static unsigned long kern_large_tte(unsigned long paddr)
2306 {
2307         unsigned long val;
2308
2309         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2310                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2311                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2312         if (tlb_type == hypervisor)
2313                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2314                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2315                        _PAGE_EXEC_4V | _PAGE_W_4V);
2316
2317         return val | paddr;
2318 }
2319
2320 /* If not locked, zap it. */
2321 void __flush_tlb_all(void)
2322 {
2323         unsigned long pstate;
2324         int i;
2325
2326         __asm__ __volatile__("flushw\n\t"
2327                              "rdpr      %%pstate, %0\n\t"
2328                              "wrpr      %0, %1, %%pstate"
2329                              : "=r" (pstate)
2330                              : "i" (PSTATE_IE));
2331         if (tlb_type == hypervisor) {
2332                 sun4v_mmu_demap_all();
2333         } else if (tlb_type == spitfire) {
2334                 for (i = 0; i < 64; i++) {
2335                         /* Spitfire Errata #32 workaround */
2336                         /* NOTE: Always runs on spitfire, so no
2337                          *       cheetah+ page size encodings.
2338                          */
2339                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2340                                              "flush     %%g6"
2341                                              : /* No outputs */
2342                                              : "r" (0),
2343                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2344
2345                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2346                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2347                                                      "membar #Sync"
2348                                                      : /* no outputs */
2349                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2350                                 spitfire_put_dtlb_data(i, 0x0UL);
2351                         }
2352
2353                         /* Spitfire Errata #32 workaround */
2354                         /* NOTE: Always runs on spitfire, so no
2355                          *       cheetah+ page size encodings.
2356                          */
2357                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2358                                              "flush     %%g6"
2359                                              : /* No outputs */
2360                                              : "r" (0),
2361                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2362
2363                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2364                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2365                                                      "membar #Sync"
2366                                                      : /* no outputs */
2367                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2368                                 spitfire_put_itlb_data(i, 0x0UL);
2369                         }
2370                 }
2371         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2372                 cheetah_flush_dtlb_all();
2373                 cheetah_flush_itlb_all();
2374         }
2375         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2376                              : : "r" (pstate));
2377 }