e1fa870ce782203f22741ddd7f32b1e6cb2ecdfe
[~shefty/rdma-dev.git] / arch / x86 / include / asm / uv / uv_mmrs.h
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV MMR definitions
7  *
8  * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
9  */
10
11 #ifndef _ASM_X86_UV_UV_MMRS_H
12 #define _ASM_X86_UV_UV_MMRS_H
13
14 /*
15  * This file contains MMR definitions for all UV hubs types.
16  *
17  * To minimize coding differences between hub types, the symbols are
18  * grouped by architecture types.
19  *
20  * UVH  - definitions common to all UV hub types.
21  * UVXH - definitions common to all UV eXtended hub types (currently 2 & 3).
22  * UV1H - definitions specific to UV type 1 hub.
23  * UV2H - definitions specific to UV type 2 hub.
24  * UV3H - definitions specific to UV type 3 hub.
25  *
26  * So in general, MMR addresses and structures are identical on all hubs types.
27  * These MMRs are identified as:
28  *      #define UVH_xxx         <address>
29  *      union uvh_xxx {
30  *              unsigned long       v;
31  *              struct uvh_int_cmpd_s {
32  *              } s;
33  *      };
34  *
35  * If the MMR exists on all hub types but have different addresses:
36  *      #define UV1Hxxx a
37  *      #define UV2Hxxx b
38  *      #define UV3Hxxx c
39  *      #define UVHxxx  (is_uv1_hub() ? UV1Hxxx :
40  *                      (is_uv2_hub() ? UV2Hxxx :
41  *                                      UV3Hxxx))
42  *
43  * If the MMR exists on all hub types > 1 but have different addresses:
44  *      #define UV2Hxxx b
45  *      #define UV3Hxxx c
46  *      #define UVXHxxx (is_uv2_hub() ? UV2Hxxx :
47  *                                      UV3Hxxx))
48  *
49  *      union uvh_xxx {
50  *              unsigned long       v;
51  *              struct uvh_xxx_s {       # Common fields only
52  *              } s;
53  *              struct uv1h_xxx_s {      # Full UV1 definition (*)
54  *              } s1;
55  *              struct uv2h_xxx_s {      # Full UV2 definition (*)
56  *              } s2;
57  *              struct uv3h_xxx_s {      # Full UV3 definition (*)
58  *              } s3;
59  *      };
60  *              (* - if present and different than the common struct)
61  *
62  * Only essential differences are enumerated. For example, if the address is
63  * the same for all UV's, only a single #define is generated. Likewise,
64  * if the contents is the same for all hubs, only the "s" structure is
65  * generated.
66  *
67  * If the MMR exists on ONLY 1 type of hub, no generic definition is
68  * generated:
69  *      #define UVnH_xxx        <uvn address>
70  *      union uvnh_xxx {
71  *              unsigned long       v;
72  *              struct uvh_int_cmpd_s {
73  *              } sn;
74  *      };
75  *
76  * (GEN Flags: mflags_opt=c undefs=0 UV23=UVXH)
77  */
78
79 #define UV_MMR_ENABLE           (1UL << 63)
80
81 #define UV1_HUB_PART_NUMBER     0x88a5
82 #define UV2_HUB_PART_NUMBER     0x8eb8
83 #define UV2_HUB_PART_NUMBER_X   0x1111
84 #define UV3_HUB_PART_NUMBER     0x9578
85 #define UV3_HUB_PART_NUMBER_X   0x4321
86
87 /* Compat: Indicate which UV Hubs are supported. */
88 #define UV2_HUB_IS_SUPPORTED    1
89 #define UV3_HUB_IS_SUPPORTED    1
90
91 /* ========================================================================= */
92 /*                          UVH_BAU_DATA_BROADCAST                           */
93 /* ========================================================================= */
94 #define UVH_BAU_DATA_BROADCAST 0x61688UL
95 #define UV1H_BAU_DATA_BROADCAST 0x61688UL
96 #define UV2H_BAU_DATA_BROADCAST 0x61688UL
97 #define UV3H_BAU_DATA_BROADCAST 0x61688UL
98 #define UVH_BAU_DATA_BROADCAST_32 0x440
99 #define UV1H_BAU_DATA_BROADCAST_32 0x61688UL
100 #define UV2H_BAU_DATA_BROADCAST_32 0x61688UL
101 #define UV3H_BAU_DATA_BROADCAST_32 0x61688UL
102
103 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT              0
104 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK              0x0000000000000001UL
105
106 #define UV1H_BAU_DATA_BROADCAST_ENABLE_SHFT             0
107 #define UV1H_BAU_DATA_BROADCAST_ENABLE_MASK             0x0000000000000001UL
108
109 #define UVXH_BAU_DATA_BROADCAST_ENABLE_SHFT             0
110 #define UVXH_BAU_DATA_BROADCAST_ENABLE_MASK             0x0000000000000001UL
111
112 #define UV2H_BAU_DATA_BROADCAST_ENABLE_SHFT             0
113 #define UV2H_BAU_DATA_BROADCAST_ENABLE_MASK             0x0000000000000001UL
114
115 #define UV3H_BAU_DATA_BROADCAST_ENABLE_SHFT             0
116 #define UV3H_BAU_DATA_BROADCAST_ENABLE_MASK             0x0000000000000001UL
117
118 union uvh_bau_data_broadcast_u {
119         unsigned long   v;
120         struct uvh_bau_data_broadcast_s {
121                 unsigned long   enable:1;                       /* RW */
122                 unsigned long   rsvd_1_63:63;
123         } s;
124         struct uv1h_bau_data_broadcast_s {
125                 unsigned long   enable:1;                       /* RW */
126                 unsigned long   rsvd_1_63:63;
127         } s1;
128         struct uvxh_bau_data_broadcast_s {
129                 unsigned long   enable:1;                       /* RW */
130                 unsigned long   rsvd_1_63:63;
131         } sx;
132         struct uv2h_bau_data_broadcast_s {
133                 unsigned long   enable:1;                       /* RW */
134                 unsigned long   rsvd_1_63:63;
135         } s2;
136         struct uv3h_bau_data_broadcast_s {
137                 unsigned long   enable:1;                       /* RW */
138                 unsigned long   rsvd_1_63:63;
139         } s3;
140 };
141
142 /* ========================================================================= */
143 /*                           UVH_BAU_DATA_CONFIG                             */
144 /* ========================================================================= */
145 #define UVH_BAU_DATA_CONFIG 0x61680UL
146 #define UV1H_BAU_DATA_CONFIG 0x61680UL
147 #define UV2H_BAU_DATA_CONFIG 0x61680UL
148 #define UV3H_BAU_DATA_CONFIG 0x61680UL
149 #define UVH_BAU_DATA_CONFIG_32 0x438
150 #define UV1H_BAU_DATA_CONFIG_32 0x61680UL
151 #define UV2H_BAU_DATA_CONFIG_32 0x61680UL
152 #define UV3H_BAU_DATA_CONFIG_32 0x61680UL
153
154 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT                 0
155 #define UVH_BAU_DATA_CONFIG_DM_SHFT                     8
156 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT               11
157 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT                 12
158 #define UVH_BAU_DATA_CONFIG_P_SHFT                      13
159 #define UVH_BAU_DATA_CONFIG_T_SHFT                      15
160 #define UVH_BAU_DATA_CONFIG_M_SHFT                      16
161 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT                32
162 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK                 0x00000000000000ffUL
163 #define UVH_BAU_DATA_CONFIG_DM_MASK                     0x0000000000000700UL
164 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK               0x0000000000000800UL
165 #define UVH_BAU_DATA_CONFIG_STATUS_MASK                 0x0000000000001000UL
166 #define UVH_BAU_DATA_CONFIG_P_MASK                      0x0000000000002000UL
167 #define UVH_BAU_DATA_CONFIG_T_MASK                      0x0000000000008000UL
168 #define UVH_BAU_DATA_CONFIG_M_MASK                      0x0000000000010000UL
169 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
170
171 #define UV1H_BAU_DATA_CONFIG_VECTOR_SHFT                0
172 #define UV1H_BAU_DATA_CONFIG_DM_SHFT                    8
173 #define UV1H_BAU_DATA_CONFIG_DESTMODE_SHFT              11
174 #define UV1H_BAU_DATA_CONFIG_STATUS_SHFT                12
175 #define UV1H_BAU_DATA_CONFIG_P_SHFT                     13
176 #define UV1H_BAU_DATA_CONFIG_T_SHFT                     15
177 #define UV1H_BAU_DATA_CONFIG_M_SHFT                     16
178 #define UV1H_BAU_DATA_CONFIG_APIC_ID_SHFT               32
179 #define UV1H_BAU_DATA_CONFIG_VECTOR_MASK                0x00000000000000ffUL
180 #define UV1H_BAU_DATA_CONFIG_DM_MASK                    0x0000000000000700UL
181 #define UV1H_BAU_DATA_CONFIG_DESTMODE_MASK              0x0000000000000800UL
182 #define UV1H_BAU_DATA_CONFIG_STATUS_MASK                0x0000000000001000UL
183 #define UV1H_BAU_DATA_CONFIG_P_MASK                     0x0000000000002000UL
184 #define UV1H_BAU_DATA_CONFIG_T_MASK                     0x0000000000008000UL
185 #define UV1H_BAU_DATA_CONFIG_M_MASK                     0x0000000000010000UL
186 #define UV1H_BAU_DATA_CONFIG_APIC_ID_MASK               0xffffffff00000000UL
187
188 #define UVXH_BAU_DATA_CONFIG_VECTOR_SHFT                0
189 #define UVXH_BAU_DATA_CONFIG_DM_SHFT                    8
190 #define UVXH_BAU_DATA_CONFIG_DESTMODE_SHFT              11
191 #define UVXH_BAU_DATA_CONFIG_STATUS_SHFT                12
192 #define UVXH_BAU_DATA_CONFIG_P_SHFT                     13
193 #define UVXH_BAU_DATA_CONFIG_T_SHFT                     15
194 #define UVXH_BAU_DATA_CONFIG_M_SHFT                     16
195 #define UVXH_BAU_DATA_CONFIG_APIC_ID_SHFT               32
196 #define UVXH_BAU_DATA_CONFIG_VECTOR_MASK                0x00000000000000ffUL
197 #define UVXH_BAU_DATA_CONFIG_DM_MASK                    0x0000000000000700UL
198 #define UVXH_BAU_DATA_CONFIG_DESTMODE_MASK              0x0000000000000800UL
199 #define UVXH_BAU_DATA_CONFIG_STATUS_MASK                0x0000000000001000UL
200 #define UVXH_BAU_DATA_CONFIG_P_MASK                     0x0000000000002000UL
201 #define UVXH_BAU_DATA_CONFIG_T_MASK                     0x0000000000008000UL
202 #define UVXH_BAU_DATA_CONFIG_M_MASK                     0x0000000000010000UL
203 #define UVXH_BAU_DATA_CONFIG_APIC_ID_MASK               0xffffffff00000000UL
204
205 #define UV2H_BAU_DATA_CONFIG_VECTOR_SHFT                0
206 #define UV2H_BAU_DATA_CONFIG_DM_SHFT                    8
207 #define UV2H_BAU_DATA_CONFIG_DESTMODE_SHFT              11
208 #define UV2H_BAU_DATA_CONFIG_STATUS_SHFT                12
209 #define UV2H_BAU_DATA_CONFIG_P_SHFT                     13
210 #define UV2H_BAU_DATA_CONFIG_T_SHFT                     15
211 #define UV2H_BAU_DATA_CONFIG_M_SHFT                     16
212 #define UV2H_BAU_DATA_CONFIG_APIC_ID_SHFT               32
213 #define UV2H_BAU_DATA_CONFIG_VECTOR_MASK                0x00000000000000ffUL
214 #define UV2H_BAU_DATA_CONFIG_DM_MASK                    0x0000000000000700UL
215 #define UV2H_BAU_DATA_CONFIG_DESTMODE_MASK              0x0000000000000800UL
216 #define UV2H_BAU_DATA_CONFIG_STATUS_MASK                0x0000000000001000UL
217 #define UV2H_BAU_DATA_CONFIG_P_MASK                     0x0000000000002000UL
218 #define UV2H_BAU_DATA_CONFIG_T_MASK                     0x0000000000008000UL
219 #define UV2H_BAU_DATA_CONFIG_M_MASK                     0x0000000000010000UL
220 #define UV2H_BAU_DATA_CONFIG_APIC_ID_MASK               0xffffffff00000000UL
221
222 #define UV3H_BAU_DATA_CONFIG_VECTOR_SHFT                0
223 #define UV3H_BAU_DATA_CONFIG_DM_SHFT                    8
224 #define UV3H_BAU_DATA_CONFIG_DESTMODE_SHFT              11
225 #define UV3H_BAU_DATA_CONFIG_STATUS_SHFT                12
226 #define UV3H_BAU_DATA_CONFIG_P_SHFT                     13
227 #define UV3H_BAU_DATA_CONFIG_T_SHFT                     15
228 #define UV3H_BAU_DATA_CONFIG_M_SHFT                     16
229 #define UV3H_BAU_DATA_CONFIG_APIC_ID_SHFT               32
230 #define UV3H_BAU_DATA_CONFIG_VECTOR_MASK                0x00000000000000ffUL
231 #define UV3H_BAU_DATA_CONFIG_DM_MASK                    0x0000000000000700UL
232 #define UV3H_BAU_DATA_CONFIG_DESTMODE_MASK              0x0000000000000800UL
233 #define UV3H_BAU_DATA_CONFIG_STATUS_MASK                0x0000000000001000UL
234 #define UV3H_BAU_DATA_CONFIG_P_MASK                     0x0000000000002000UL
235 #define UV3H_BAU_DATA_CONFIG_T_MASK                     0x0000000000008000UL
236 #define UV3H_BAU_DATA_CONFIG_M_MASK                     0x0000000000010000UL
237 #define UV3H_BAU_DATA_CONFIG_APIC_ID_MASK               0xffffffff00000000UL
238
239 union uvh_bau_data_config_u {
240         unsigned long   v;
241         struct uvh_bau_data_config_s {
242                 unsigned long   vector_:8;                      /* RW */
243                 unsigned long   dm:3;                           /* RW */
244                 unsigned long   destmode:1;                     /* RW */
245                 unsigned long   status:1;                       /* RO */
246                 unsigned long   p:1;                            /* RO */
247                 unsigned long   rsvd_14:1;
248                 unsigned long   t:1;                            /* RO */
249                 unsigned long   m:1;                            /* RW */
250                 unsigned long   rsvd_17_31:15;
251                 unsigned long   apic_id:32;                     /* RW */
252         } s;
253         struct uv1h_bau_data_config_s {
254                 unsigned long   vector_:8;                      /* RW */
255                 unsigned long   dm:3;                           /* RW */
256                 unsigned long   destmode:1;                     /* RW */
257                 unsigned long   status:1;                       /* RO */
258                 unsigned long   p:1;                            /* RO */
259                 unsigned long   rsvd_14:1;
260                 unsigned long   t:1;                            /* RO */
261                 unsigned long   m:1;                            /* RW */
262                 unsigned long   rsvd_17_31:15;
263                 unsigned long   apic_id:32;                     /* RW */
264         } s1;
265         struct uvxh_bau_data_config_s {
266                 unsigned long   vector_:8;                      /* RW */
267                 unsigned long   dm:3;                           /* RW */
268                 unsigned long   destmode:1;                     /* RW */
269                 unsigned long   status:1;                       /* RO */
270                 unsigned long   p:1;                            /* RO */
271                 unsigned long   rsvd_14:1;
272                 unsigned long   t:1;                            /* RO */
273                 unsigned long   m:1;                            /* RW */
274                 unsigned long   rsvd_17_31:15;
275                 unsigned long   apic_id:32;                     /* RW */
276         } sx;
277         struct uv2h_bau_data_config_s {
278                 unsigned long   vector_:8;                      /* RW */
279                 unsigned long   dm:3;                           /* RW */
280                 unsigned long   destmode:1;                     /* RW */
281                 unsigned long   status:1;                       /* RO */
282                 unsigned long   p:1;                            /* RO */
283                 unsigned long   rsvd_14:1;
284                 unsigned long   t:1;                            /* RO */
285                 unsigned long   m:1;                            /* RW */
286                 unsigned long   rsvd_17_31:15;
287                 unsigned long   apic_id:32;                     /* RW */
288         } s2;
289         struct uv3h_bau_data_config_s {
290                 unsigned long   vector_:8;                      /* RW */
291                 unsigned long   dm:3;                           /* RW */
292                 unsigned long   destmode:1;                     /* RW */
293                 unsigned long   status:1;                       /* RO */
294                 unsigned long   p:1;                            /* RO */
295                 unsigned long   rsvd_14:1;
296                 unsigned long   t:1;                            /* RO */
297                 unsigned long   m:1;                            /* RW */
298                 unsigned long   rsvd_17_31:15;
299                 unsigned long   apic_id:32;                     /* RW */
300         } s3;
301 };
302
303 /* ========================================================================= */
304 /*                           UVH_EVENT_OCCURRED0                             */
305 /* ========================================================================= */
306 #define UVH_EVENT_OCCURRED0 0x70000UL
307 #define UV1H_EVENT_OCCURRED0 0x70000UL
308 #define UV2H_EVENT_OCCURRED0 0x70000UL
309 #define UV3H_EVENT_OCCURRED0 0x70000UL
310 #define UVH_EVENT_OCCURRED0_32 0x5e8
311 #define UV1H_EVENT_OCCURRED0_32 0x70000UL
312 #define UV2H_EVENT_OCCURRED0_32 0x70000UL
313 #define UV3H_EVENT_OCCURRED0_32 0x70000UL
314
315 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT               0
316 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT              11
317 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK               0x0000000000000001UL
318 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK              0x0000000000000800UL
319
320 #define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT              0
321 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT             1
322 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT             2
323 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT              3
324 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT              4
325 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT              5
326 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT              6
327 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT             7
328 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT            8
329 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT            9
330 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT             10
331 #define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT             11
332 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT             12
333 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT             13
334 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT             14
335 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            15
336 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            16
337 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT             17
338 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT             18
339 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT             19
340 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT             20
341 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT            21
342 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   22
343 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          23
344 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          24
345 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          25
346 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          26
347 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          27
348 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          28
349 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          29
350 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          30
351 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          31
352 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          32
353 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         33
354 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         34
355 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         35
356 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         36
357 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         37
358 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         38
359 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            39
360 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            40
361 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            41
362 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            42
363 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT               43
364 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        44
365 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT               45
366 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            46
367 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            47
368 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            48
369 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            49
370 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT           50
371 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT                  51
372 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT                  52
373 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT                  53
374 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT                  54
375 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT              55
376 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT  56
377 #define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK              0x0000000000000001UL
378 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000002UL
379 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000004UL
380 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK              0x0000000000000008UL
381 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000010UL
382 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK              0x0000000000000020UL
383 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK              0x0000000000000040UL
384 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000080UL
385 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000000100UL
386 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000000200UL
387 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK             0x0000000000000400UL
388 #define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK             0x0000000000000800UL
389 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK             0x0000000000001000UL
390 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK             0x0000000000002000UL
391 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000004000UL
392 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000000008000UL
393 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000000010000UL
394 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK             0x0000000000020000UL
395 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000040000UL
396 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK             0x0000000000080000UL
397 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK             0x0000000000100000UL
398 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK            0x0000000000200000UL
399 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000000400000UL
400 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000000800000UL
401 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000001000000UL
402 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000002000000UL
403 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000004000000UL
404 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000000008000000UL
405 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000000010000000UL
406 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000000020000000UL
407 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000000040000000UL
408 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000000080000000UL
409 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000000100000000UL
410 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000000200000000UL
411 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000000400000000UL
412 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000000800000000UL
413 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000001000000000UL
414 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000002000000000UL
415 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000004000000000UL
416 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0000008000000000UL
417 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0000010000000000UL
418 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0000020000000000UL
419 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0000040000000000UL
420 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK               0x0000080000000000UL
421 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0000100000000000UL
422 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK               0x0000200000000000UL
423 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0000400000000000UL
424 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0000800000000000UL
425 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0001000000000000UL
426 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0002000000000000UL
427 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0004000000000000UL
428 #define UV1H_EVENT_OCCURRED0_RTC0_MASK                  0x0008000000000000UL
429 #define UV1H_EVENT_OCCURRED0_RTC1_MASK                  0x0010000000000000UL
430 #define UV1H_EVENT_OCCURRED0_RTC2_MASK                  0x0020000000000000UL
431 #define UV1H_EVENT_OCCURRED0_RTC3_MASK                  0x0040000000000000UL
432 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK              0x0080000000000000UL
433 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK  0x0100000000000000UL
434
435 #define UVXH_EVENT_OCCURRED0_LB_HCERR_SHFT              0
436 #define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT              1
437 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT              2
438 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT             3
439 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT             4
440 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT             5
441 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT             6
442 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT             7
443 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT             8
444 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT             9
445 #define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
446 #define UVXH_EVENT_OCCURRED0_RH_AOERR0_SHFT             11
447 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT            12
448 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT            13
449 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT            14
450 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT            15
451 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT             16
452 #define UVXH_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
453 #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
454 #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
455 #define UVXH_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
456 #define UVXH_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
457 #define UVXH_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
458 #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
459 #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
460 #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
461 #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
462 #define UVXH_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
463 #define UVXH_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
464 #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
465 #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
466 #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
467 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
468 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
469 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
470 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
471 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
472 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
473 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
474 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
475 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
476 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
477 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
478 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
479 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
480 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
481 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
482 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
483 #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
484 #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
485 #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
486 #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
487 #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
488 #define UVXH_EVENT_OCCURRED0_IPI_INT_SHFT               53
489 #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
490 #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
491 #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
492 #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
493 #define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
494 #define UVXH_EVENT_OCCURRED0_LB_HCERR_MASK              0x0000000000000001UL
495 #define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
496 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000004UL
497 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK             0x0000000000000008UL
498 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK             0x0000000000000010UL
499 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000020UL
500 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000040UL
501 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK             0x0000000000000080UL
502 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK             0x0000000000000100UL
503 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000200UL
504 #define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
505 #define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK             0x0000000000000800UL
506 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK            0x0000000000001000UL
507 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK            0x0000000000002000UL
508 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000004000UL
509 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000008000UL
510 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK             0x0000000000010000UL
511 #define UVXH_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
512 #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
513 #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
514 #define UVXH_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
515 #define UVXH_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
516 #define UVXH_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
517 #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
518 #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
519 #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
520 #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
521 #define UVXH_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
522 #define UVXH_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
523 #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
524 #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
525 #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
526 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
527 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
528 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
529 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
530 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
531 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
532 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
533 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
534 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
535 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
536 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
537 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
538 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
539 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
540 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
541 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
542 #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
543 #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
544 #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
545 #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
546 #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
547 #define UVXH_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
548 #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
549 #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
550 #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
551 #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
552 #define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
553
554 #define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT              0
555 #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT              1
556 #define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT              2
557 #define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT             3
558 #define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT             4
559 #define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT             5
560 #define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT             6
561 #define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT             7
562 #define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT             8
563 #define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT             9
564 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
565 #define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT             11
566 #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT            12
567 #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT            13
568 #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT            14
569 #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT            15
570 #define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT             16
571 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
572 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
573 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
574 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
575 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
576 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
577 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
578 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
579 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
580 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
581 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
582 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
583 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
584 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
585 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
586 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
587 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
588 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
589 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
590 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
591 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
592 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
593 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
594 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
595 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
596 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
597 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
598 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
599 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
600 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
601 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
602 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
603 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
604 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
605 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
606 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
607 #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT               53
608 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
609 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
610 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
611 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
612 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
613 #define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK              0x0000000000000001UL
614 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
615 #define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000004UL
616 #define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK             0x0000000000000008UL
617 #define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK             0x0000000000000010UL
618 #define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000020UL
619 #define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000040UL
620 #define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK             0x0000000000000080UL
621 #define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK             0x0000000000000100UL
622 #define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000200UL
623 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
624 #define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK             0x0000000000000800UL
625 #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK            0x0000000000001000UL
626 #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK            0x0000000000002000UL
627 #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000004000UL
628 #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000008000UL
629 #define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK             0x0000000000010000UL
630 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
631 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
632 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
633 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
634 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
635 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
636 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
637 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
638 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
639 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
640 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
641 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
642 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
643 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
644 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
645 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
646 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
647 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
648 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
649 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
650 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
651 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
652 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
653 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
654 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
655 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
656 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
657 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
658 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
659 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
660 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
661 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
662 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
663 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
664 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
665 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
666 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
667 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
668 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
669 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
670 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
671 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
672
673 #define UV3H_EVENT_OCCURRED0_LB_HCERR_SHFT              0
674 #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT              1
675 #define UV3H_EVENT_OCCURRED0_RH_HCERR_SHFT              2
676 #define UV3H_EVENT_OCCURRED0_LH0_HCERR_SHFT             3
677 #define UV3H_EVENT_OCCURRED0_LH1_HCERR_SHFT             4
678 #define UV3H_EVENT_OCCURRED0_GR0_HCERR_SHFT             5
679 #define UV3H_EVENT_OCCURRED0_GR1_HCERR_SHFT             6
680 #define UV3H_EVENT_OCCURRED0_NI0_HCERR_SHFT             7
681 #define UV3H_EVENT_OCCURRED0_NI1_HCERR_SHFT             8
682 #define UV3H_EVENT_OCCURRED0_LB_AOERR0_SHFT             9
683 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
684 #define UV3H_EVENT_OCCURRED0_RH_AOERR0_SHFT             11
685 #define UV3H_EVENT_OCCURRED0_LH0_AOERR0_SHFT            12
686 #define UV3H_EVENT_OCCURRED0_LH1_AOERR0_SHFT            13
687 #define UV3H_EVENT_OCCURRED0_GR0_AOERR0_SHFT            14
688 #define UV3H_EVENT_OCCURRED0_GR1_AOERR0_SHFT            15
689 #define UV3H_EVENT_OCCURRED0_XB_AOERR0_SHFT             16
690 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
691 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
692 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
693 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
694 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
695 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
696 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
697 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
698 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
699 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
700 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
701 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
702 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
703 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
704 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
705 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
706 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
707 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
708 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
709 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
710 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
711 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
712 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
713 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
714 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
715 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
716 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
717 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
718 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
719 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
720 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
721 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
722 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
723 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
724 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
725 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
726 #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT               53
727 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
728 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
729 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
730 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
731 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
732 #define UV3H_EVENT_OCCURRED0_LB_HCERR_MASK              0x0000000000000001UL
733 #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
734 #define UV3H_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000004UL
735 #define UV3H_EVENT_OCCURRED0_LH0_HCERR_MASK             0x0000000000000008UL
736 #define UV3H_EVENT_OCCURRED0_LH1_HCERR_MASK             0x0000000000000010UL
737 #define UV3H_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000020UL
738 #define UV3H_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000040UL
739 #define UV3H_EVENT_OCCURRED0_NI0_HCERR_MASK             0x0000000000000080UL
740 #define UV3H_EVENT_OCCURRED0_NI1_HCERR_MASK             0x0000000000000100UL
741 #define UV3H_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000200UL
742 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
743 #define UV3H_EVENT_OCCURRED0_RH_AOERR0_MASK             0x0000000000000800UL
744 #define UV3H_EVENT_OCCURRED0_LH0_AOERR0_MASK            0x0000000000001000UL
745 #define UV3H_EVENT_OCCURRED0_LH1_AOERR0_MASK            0x0000000000002000UL
746 #define UV3H_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000004000UL
747 #define UV3H_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000008000UL
748 #define UV3H_EVENT_OCCURRED0_XB_AOERR0_MASK             0x0000000000010000UL
749 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
750 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
751 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
752 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
753 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
754 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
755 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
756 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
757 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
758 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
759 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
760 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
761 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
762 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
763 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
764 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
765 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
766 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
767 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
768 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
769 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
770 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
771 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
772 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
773 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
774 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
775 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
776 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
777 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
778 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
779 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
780 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
781 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
782 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
783 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
784 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
785 #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
786 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
787 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
788 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
789 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
790 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
791
792 union uvh_event_occurred0_u {
793         unsigned long   v;
794         struct uvh_event_occurred0_s {
795                 unsigned long   lb_hcerr:1;                     /* RW, W1C */
796                 unsigned long   rsvd_1_10:10;
797                 unsigned long   rh_aoerr0:1;                    /* RW, W1C */
798                 unsigned long   rsvd_12_63:52;
799         } s;
800         struct uv1h_event_occurred0_s {
801                 unsigned long   lb_hcerr:1;                     /* RW, W1C */
802                 unsigned long   gr0_hcerr:1;                    /* RW, W1C */
803                 unsigned long   gr1_hcerr:1;                    /* RW, W1C */
804                 unsigned long   lh_hcerr:1;                     /* RW, W1C */
805                 unsigned long   rh_hcerr:1;                     /* RW, W1C */
806                 unsigned long   xn_hcerr:1;                     /* RW, W1C */
807                 unsigned long   si_hcerr:1;                     /* RW, W1C */
808                 unsigned long   lb_aoerr0:1;                    /* RW, W1C */
809                 unsigned long   gr0_aoerr0:1;                   /* RW, W1C */
810                 unsigned long   gr1_aoerr0:1;                   /* RW, W1C */
811                 unsigned long   lh_aoerr0:1;                    /* RW, W1C */
812                 unsigned long   rh_aoerr0:1;                    /* RW, W1C */
813                 unsigned long   xn_aoerr0:1;                    /* RW, W1C */
814                 unsigned long   si_aoerr0:1;                    /* RW, W1C */
815                 unsigned long   lb_aoerr1:1;                    /* RW, W1C */
816                 unsigned long   gr0_aoerr1:1;                   /* RW, W1C */
817                 unsigned long   gr1_aoerr1:1;                   /* RW, W1C */
818                 unsigned long   lh_aoerr1:1;                    /* RW, W1C */
819                 unsigned long   rh_aoerr1:1;                    /* RW, W1C */
820                 unsigned long   xn_aoerr1:1;                    /* RW, W1C */
821                 unsigned long   si_aoerr1:1;                    /* RW, W1C */
822                 unsigned long   rh_vpi_int:1;                   /* RW, W1C */
823                 unsigned long   system_shutdown_int:1;          /* RW, W1C */
824                 unsigned long   lb_irq_int_0:1;                 /* RW, W1C */
825                 unsigned long   lb_irq_int_1:1;                 /* RW, W1C */
826                 unsigned long   lb_irq_int_2:1;                 /* RW, W1C */
827                 unsigned long   lb_irq_int_3:1;                 /* RW, W1C */
828                 unsigned long   lb_irq_int_4:1;                 /* RW, W1C */
829                 unsigned long   lb_irq_int_5:1;                 /* RW, W1C */
830                 unsigned long   lb_irq_int_6:1;                 /* RW, W1C */
831                 unsigned long   lb_irq_int_7:1;                 /* RW, W1C */
832                 unsigned long   lb_irq_int_8:1;                 /* RW, W1C */
833                 unsigned long   lb_irq_int_9:1;                 /* RW, W1C */
834                 unsigned long   lb_irq_int_10:1;                /* RW, W1C */
835                 unsigned long   lb_irq_int_11:1;                /* RW, W1C */
836                 unsigned long   lb_irq_int_12:1;                /* RW, W1C */
837                 unsigned long   lb_irq_int_13:1;                /* RW, W1C */
838                 unsigned long   lb_irq_int_14:1;                /* RW, W1C */
839                 unsigned long   lb_irq_int_15:1;                /* RW, W1C */
840                 unsigned long   l1_nmi_int:1;                   /* RW, W1C */
841                 unsigned long   stop_clock:1;                   /* RW, W1C */
842                 unsigned long   asic_to_l1:1;                   /* RW, W1C */
843                 unsigned long   l1_to_asic:1;                   /* RW, W1C */
844                 unsigned long   ltc_int:1;                      /* RW, W1C */
845                 unsigned long   la_seq_trigger:1;               /* RW, W1C */
846                 unsigned long   ipi_int:1;                      /* RW, W1C */
847                 unsigned long   extio_int0:1;                   /* RW, W1C */
848                 unsigned long   extio_int1:1;                   /* RW, W1C */
849                 unsigned long   extio_int2:1;                   /* RW, W1C */
850                 unsigned long   extio_int3:1;                   /* RW, W1C */
851                 unsigned long   profile_int:1;                  /* RW, W1C */
852                 unsigned long   rtc0:1;                         /* RW, W1C */
853                 unsigned long   rtc1:1;                         /* RW, W1C */
854                 unsigned long   rtc2:1;                         /* RW, W1C */
855                 unsigned long   rtc3:1;                         /* RW, W1C */
856                 unsigned long   bau_data:1;                     /* RW, W1C */
857                 unsigned long   power_management_req:1;         /* RW, W1C */
858                 unsigned long   rsvd_57_63:7;
859         } s1;
860         struct uvxh_event_occurred0_s {
861                 unsigned long   lb_hcerr:1;                     /* RW */
862                 unsigned long   qp_hcerr:1;                     /* RW */
863                 unsigned long   rh_hcerr:1;                     /* RW */
864                 unsigned long   lh0_hcerr:1;                    /* RW */
865                 unsigned long   lh1_hcerr:1;                    /* RW */
866                 unsigned long   gr0_hcerr:1;                    /* RW */
867                 unsigned long   gr1_hcerr:1;                    /* RW */
868                 unsigned long   ni0_hcerr:1;                    /* RW */
869                 unsigned long   ni1_hcerr:1;                    /* RW */
870                 unsigned long   lb_aoerr0:1;                    /* RW */
871                 unsigned long   qp_aoerr0:1;                    /* RW */
872                 unsigned long   rh_aoerr0:1;                    /* RW */
873                 unsigned long   lh0_aoerr0:1;                   /* RW */
874                 unsigned long   lh1_aoerr0:1;                   /* RW */
875                 unsigned long   gr0_aoerr0:1;                   /* RW */
876                 unsigned long   gr1_aoerr0:1;                   /* RW */
877                 unsigned long   xb_aoerr0:1;                    /* RW */
878                 unsigned long   rt_aoerr0:1;                    /* RW */
879                 unsigned long   ni0_aoerr0:1;                   /* RW */
880                 unsigned long   ni1_aoerr0:1;                   /* RW */
881                 unsigned long   lb_aoerr1:1;                    /* RW */
882                 unsigned long   qp_aoerr1:1;                    /* RW */
883                 unsigned long   rh_aoerr1:1;                    /* RW */
884                 unsigned long   lh0_aoerr1:1;                   /* RW */
885                 unsigned long   lh1_aoerr1:1;                   /* RW */
886                 unsigned long   gr0_aoerr1:1;                   /* RW */
887                 unsigned long   gr1_aoerr1:1;                   /* RW */
888                 unsigned long   xb_aoerr1:1;                    /* RW */
889                 unsigned long   rt_aoerr1:1;                    /* RW */
890                 unsigned long   ni0_aoerr1:1;                   /* RW */
891                 unsigned long   ni1_aoerr1:1;                   /* RW */
892                 unsigned long   system_shutdown_int:1;          /* RW */
893                 unsigned long   lb_irq_int_0:1;                 /* RW */
894                 unsigned long   lb_irq_int_1:1;                 /* RW */
895                 unsigned long   lb_irq_int_2:1;                 /* RW */
896                 unsigned long   lb_irq_int_3:1;                 /* RW */
897                 unsigned long   lb_irq_int_4:1;                 /* RW */
898                 unsigned long   lb_irq_int_5:1;                 /* RW */
899                 unsigned long   lb_irq_int_6:1;                 /* RW */
900                 unsigned long   lb_irq_int_7:1;                 /* RW */
901                 unsigned long   lb_irq_int_8:1;                 /* RW */
902                 unsigned long   lb_irq_int_9:1;                 /* RW */
903                 unsigned long   lb_irq_int_10:1;                /* RW */
904                 unsigned long   lb_irq_int_11:1;                /* RW */
905                 unsigned long   lb_irq_int_12:1;                /* RW */
906                 unsigned long   lb_irq_int_13:1;                /* RW */
907                 unsigned long   lb_irq_int_14:1;                /* RW */
908                 unsigned long   lb_irq_int_15:1;                /* RW */
909                 unsigned long   l1_nmi_int:1;                   /* RW */
910                 unsigned long   stop_clock:1;                   /* RW */
911                 unsigned long   asic_to_l1:1;                   /* RW */
912                 unsigned long   l1_to_asic:1;                   /* RW */
913                 unsigned long   la_seq_trigger:1;               /* RW */
914                 unsigned long   ipi_int:1;                      /* RW */
915                 unsigned long   extio_int0:1;                   /* RW */
916                 unsigned long   extio_int1:1;                   /* RW */
917                 unsigned long   extio_int2:1;                   /* RW */
918                 unsigned long   extio_int3:1;                   /* RW */
919                 unsigned long   profile_int:1;                  /* RW */
920                 unsigned long   rsvd_59_63:5;
921         } sx;
922         struct uv2h_event_occurred0_s {
923                 unsigned long   lb_hcerr:1;                     /* RW */
924                 unsigned long   qp_hcerr:1;                     /* RW */
925                 unsigned long   rh_hcerr:1;                     /* RW */
926                 unsigned long   lh0_hcerr:1;                    /* RW */
927                 unsigned long   lh1_hcerr:1;                    /* RW */
928                 unsigned long   gr0_hcerr:1;                    /* RW */
929                 unsigned long   gr1_hcerr:1;                    /* RW */
930                 unsigned long   ni0_hcerr:1;                    /* RW */
931                 unsigned long   ni1_hcerr:1;                    /* RW */
932                 unsigned long   lb_aoerr0:1;                    /* RW */
933                 unsigned long   qp_aoerr0:1;                    /* RW */
934                 unsigned long   rh_aoerr0:1;                    /* RW */
935                 unsigned long   lh0_aoerr0:1;                   /* RW */
936                 unsigned long   lh1_aoerr0:1;                   /* RW */
937                 unsigned long   gr0_aoerr0:1;                   /* RW */
938                 unsigned long   gr1_aoerr0:1;                   /* RW */
939                 unsigned long   xb_aoerr0:1;                    /* RW */
940                 unsigned long   rt_aoerr0:1;                    /* RW */
941                 unsigned long   ni0_aoerr0:1;                   /* RW */
942                 unsigned long   ni1_aoerr0:1;                   /* RW */
943                 unsigned long   lb_aoerr1:1;                    /* RW */
944                 unsigned long   qp_aoerr1:1;                    /* RW */
945                 unsigned long   rh_aoerr1:1;                    /* RW */
946                 unsigned long   lh0_aoerr1:1;                   /* RW */
947                 unsigned long   lh1_aoerr1:1;                   /* RW */
948                 unsigned long   gr0_aoerr1:1;                   /* RW */
949                 unsigned long   gr1_aoerr1:1;                   /* RW */
950                 unsigned long   xb_aoerr1:1;                    /* RW */
951                 unsigned long   rt_aoerr1:1;                    /* RW */
952                 unsigned long   ni0_aoerr1:1;                   /* RW */
953                 unsigned long   ni1_aoerr1:1;                   /* RW */
954                 unsigned long   system_shutdown_int:1;          /* RW */
955                 unsigned long   lb_irq_int_0:1;                 /* RW */
956                 unsigned long   lb_irq_int_1:1;                 /* RW */
957                 unsigned long   lb_irq_int_2:1;                 /* RW */
958                 unsigned long   lb_irq_int_3:1;                 /* RW */
959                 unsigned long   lb_irq_int_4:1;                 /* RW */
960                 unsigned long   lb_irq_int_5:1;                 /* RW */
961                 unsigned long   lb_irq_int_6:1;                 /* RW */
962                 unsigned long   lb_irq_int_7:1;                 /* RW */
963                 unsigned long   lb_irq_int_8:1;                 /* RW */
964                 unsigned long   lb_irq_int_9:1;                 /* RW */
965                 unsigned long   lb_irq_int_10:1;                /* RW */
966                 unsigned long   lb_irq_int_11:1;                /* RW */
967                 unsigned long   lb_irq_int_12:1;                /* RW */
968                 unsigned long   lb_irq_int_13:1;                /* RW */
969                 unsigned long   lb_irq_int_14:1;                /* RW */
970                 unsigned long   lb_irq_int_15:1;                /* RW */
971                 unsigned long   l1_nmi_int:1;                   /* RW */
972                 unsigned long   stop_clock:1;                   /* RW */
973                 unsigned long   asic_to_l1:1;                   /* RW */
974                 unsigned long   l1_to_asic:1;                   /* RW */
975                 unsigned long   la_seq_trigger:1;               /* RW */
976                 unsigned long   ipi_int:1;                      /* RW */
977                 unsigned long   extio_int0:1;                   /* RW */
978                 unsigned long   extio_int1:1;                   /* RW */
979                 unsigned long   extio_int2:1;                   /* RW */
980                 unsigned long   extio_int3:1;                   /* RW */
981                 unsigned long   profile_int:1;                  /* RW */
982                 unsigned long   rsvd_59_63:5;
983         } s2;
984         struct uv3h_event_occurred0_s {
985                 unsigned long   lb_hcerr:1;                     /* RW */
986                 unsigned long   qp_hcerr:1;                     /* RW */
987                 unsigned long   rh_hcerr:1;                     /* RW */
988                 unsigned long   lh0_hcerr:1;                    /* RW */
989                 unsigned long   lh1_hcerr:1;                    /* RW */
990                 unsigned long   gr0_hcerr:1;                    /* RW */
991                 unsigned long   gr1_hcerr:1;                    /* RW */
992                 unsigned long   ni0_hcerr:1;                    /* RW */
993                 unsigned long   ni1_hcerr:1;                    /* RW */
994                 unsigned long   lb_aoerr0:1;                    /* RW */
995                 unsigned long   qp_aoerr0:1;                    /* RW */
996                 unsigned long   rh_aoerr0:1;                    /* RW */
997                 unsigned long   lh0_aoerr0:1;                   /* RW */
998                 unsigned long   lh1_aoerr0:1;                   /* RW */
999                 unsigned long   gr0_aoerr0:1;                   /* RW */
1000                 unsigned long   gr1_aoerr0:1;                   /* RW */
1001                 unsigned long   xb_aoerr0:1;                    /* RW */
1002                 unsigned long   rt_aoerr0:1;                    /* RW */
1003                 unsigned long   ni0_aoerr0:1;                   /* RW */
1004                 unsigned long   ni1_aoerr0:1;                   /* RW */
1005                 unsigned long   lb_aoerr1:1;                    /* RW */
1006                 unsigned long   qp_aoerr1:1;                    /* RW */
1007                 unsigned long   rh_aoerr1:1;                    /* RW */
1008                 unsigned long   lh0_aoerr1:1;                   /* RW */
1009                 unsigned long   lh1_aoerr1:1;                   /* RW */
1010                 unsigned long   gr0_aoerr1:1;                   /* RW */
1011                 unsigned long   gr1_aoerr1:1;                   /* RW */
1012                 unsigned long   xb_aoerr1:1;                    /* RW */
1013                 unsigned long   rt_aoerr1:1;                    /* RW */
1014                 unsigned long   ni0_aoerr1:1;                   /* RW */
1015                 unsigned long   ni1_aoerr1:1;                   /* RW */
1016                 unsigned long   system_shutdown_int:1;          /* RW */
1017                 unsigned long   lb_irq_int_0:1;                 /* RW */
1018                 unsigned long   lb_irq_int_1:1;                 /* RW */
1019                 unsigned long   lb_irq_int_2:1;                 /* RW */
1020                 unsigned long   lb_irq_int_3:1;                 /* RW */
1021                 unsigned long   lb_irq_int_4:1;                 /* RW */
1022                 unsigned long   lb_irq_int_5:1;                 /* RW */
1023                 unsigned long   lb_irq_int_6:1;                 /* RW */
1024                 unsigned long   lb_irq_int_7:1;                 /* RW */
1025                 unsigned long   lb_irq_int_8:1;                 /* RW */
1026                 unsigned long   lb_irq_int_9:1;                 /* RW */
1027                 unsigned long   lb_irq_int_10:1;                /* RW */
1028                 unsigned long   lb_irq_int_11:1;                /* RW */
1029                 unsigned long   lb_irq_int_12:1;                /* RW */
1030                 unsigned long   lb_irq_int_13:1;                /* RW */
1031                 unsigned long   lb_irq_int_14:1;                /* RW */
1032                 unsigned long   lb_irq_int_15:1;                /* RW */
1033                 unsigned long   l1_nmi_int:1;                   /* RW */
1034                 unsigned long   stop_clock:1;                   /* RW */
1035                 unsigned long   asic_to_l1:1;                   /* RW */
1036                 unsigned long   l1_to_asic:1;                   /* RW */
1037                 unsigned long   la_seq_trigger:1;               /* RW */
1038                 unsigned long   ipi_int:1;                      /* RW */
1039                 unsigned long   extio_int0:1;                   /* RW */
1040                 unsigned long   extio_int1:1;                   /* RW */
1041                 unsigned long   extio_int2:1;                   /* RW */
1042                 unsigned long   extio_int3:1;                   /* RW */
1043                 unsigned long   profile_int:1;                  /* RW */
1044                 unsigned long   rsvd_59_63:5;
1045         } s3;
1046 };
1047
1048 /* ========================================================================= */
1049 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
1050 /* ========================================================================= */
1051 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
1052 #define UV1H_EVENT_OCCURRED0_ALIAS 0x70008UL
1053 #define UV2H_EVENT_OCCURRED0_ALIAS 0x70008UL
1054 #define UV3H_EVENT_OCCURRED0_ALIAS 0x70008UL
1055 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
1056 #define UV1H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
1057 #define UV2H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
1058 #define UV3H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
1059
1060
1061 /* ========================================================================= */
1062 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
1063 /* ========================================================================= */
1064 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
1065 #define UV1H_GR0_TLB_INT0_CONFIG 0x61b00UL
1066 #define UV2H_GR0_TLB_INT0_CONFIG 0x61b00UL
1067 #define UV3H_GR0_TLB_INT0_CONFIG 0x61b00UL
1068
1069 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT             0
1070 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT                 8
1071 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT           11
1072 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT             12
1073 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT                  13
1074 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT                  15
1075 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT                  16
1076 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT            32
1077 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK             0x00000000000000ffUL
1078 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK                 0x0000000000000700UL
1079 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK           0x0000000000000800UL
1080 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK             0x0000000000001000UL
1081 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK                  0x0000000000002000UL
1082 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK                  0x0000000000008000UL
1083 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
1084 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
1085
1086 #define UV1H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT            0
1087 #define UV1H_GR0_TLB_INT0_CONFIG_DM_SHFT                8
1088 #define UV1H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT          11
1089 #define UV1H_GR0_TLB_INT0_CONFIG_STATUS_SHFT            12
1090 #define UV1H_GR0_TLB_INT0_CONFIG_P_SHFT                 13
1091 #define UV1H_GR0_TLB_INT0_CONFIG_T_SHFT                 15
1092 #define UV1H_GR0_TLB_INT0_CONFIG_M_SHFT                 16
1093 #define UV1H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT           32
1094 #define UV1H_GR0_TLB_INT0_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1095 #define UV1H_GR0_TLB_INT0_CONFIG_DM_MASK                0x0000000000000700UL
1096 #define UV1H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1097 #define UV1H_GR0_TLB_INT0_CONFIG_STATUS_MASK            0x0000000000001000UL
1098 #define UV1H_GR0_TLB_INT0_CONFIG_P_MASK                 0x0000000000002000UL
1099 #define UV1H_GR0_TLB_INT0_CONFIG_T_MASK                 0x0000000000008000UL
1100 #define UV1H_GR0_TLB_INT0_CONFIG_M_MASK                 0x0000000000010000UL
1101 #define UV1H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1102
1103 #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT            0
1104 #define UVXH_GR0_TLB_INT0_CONFIG_DM_SHFT                8
1105 #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT          11
1106 #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_SHFT            12
1107 #define UVXH_GR0_TLB_INT0_CONFIG_P_SHFT                 13
1108 #define UVXH_GR0_TLB_INT0_CONFIG_T_SHFT                 15
1109 #define UVXH_GR0_TLB_INT0_CONFIG_M_SHFT                 16
1110 #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT           32
1111 #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1112 #define UVXH_GR0_TLB_INT0_CONFIG_DM_MASK                0x0000000000000700UL
1113 #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1114 #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_MASK            0x0000000000001000UL
1115 #define UVXH_GR0_TLB_INT0_CONFIG_P_MASK                 0x0000000000002000UL
1116 #define UVXH_GR0_TLB_INT0_CONFIG_T_MASK                 0x0000000000008000UL
1117 #define UVXH_GR0_TLB_INT0_CONFIG_M_MASK                 0x0000000000010000UL
1118 #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1119
1120 #define UV2H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT            0
1121 #define UV2H_GR0_TLB_INT0_CONFIG_DM_SHFT                8
1122 #define UV2H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT          11
1123 #define UV2H_GR0_TLB_INT0_CONFIG_STATUS_SHFT            12
1124 #define UV2H_GR0_TLB_INT0_CONFIG_P_SHFT                 13
1125 #define UV2H_GR0_TLB_INT0_CONFIG_T_SHFT                 15
1126 #define UV2H_GR0_TLB_INT0_CONFIG_M_SHFT                 16
1127 #define UV2H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT           32
1128 #define UV2H_GR0_TLB_INT0_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1129 #define UV2H_GR0_TLB_INT0_CONFIG_DM_MASK                0x0000000000000700UL
1130 #define UV2H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1131 #define UV2H_GR0_TLB_INT0_CONFIG_STATUS_MASK            0x0000000000001000UL
1132 #define UV2H_GR0_TLB_INT0_CONFIG_P_MASK                 0x0000000000002000UL
1133 #define UV2H_GR0_TLB_INT0_CONFIG_T_MASK                 0x0000000000008000UL
1134 #define UV2H_GR0_TLB_INT0_CONFIG_M_MASK                 0x0000000000010000UL
1135 #define UV2H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1136
1137 #define UV3H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT            0
1138 #define UV3H_GR0_TLB_INT0_CONFIG_DM_SHFT                8
1139 #define UV3H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT          11
1140 #define UV3H_GR0_TLB_INT0_CONFIG_STATUS_SHFT            12
1141 #define UV3H_GR0_TLB_INT0_CONFIG_P_SHFT                 13
1142 #define UV3H_GR0_TLB_INT0_CONFIG_T_SHFT                 15
1143 #define UV3H_GR0_TLB_INT0_CONFIG_M_SHFT                 16
1144 #define UV3H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT           32
1145 #define UV3H_GR0_TLB_INT0_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1146 #define UV3H_GR0_TLB_INT0_CONFIG_DM_MASK                0x0000000000000700UL
1147 #define UV3H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1148 #define UV3H_GR0_TLB_INT0_CONFIG_STATUS_MASK            0x0000000000001000UL
1149 #define UV3H_GR0_TLB_INT0_CONFIG_P_MASK                 0x0000000000002000UL
1150 #define UV3H_GR0_TLB_INT0_CONFIG_T_MASK                 0x0000000000008000UL
1151 #define UV3H_GR0_TLB_INT0_CONFIG_M_MASK                 0x0000000000010000UL
1152 #define UV3H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1153
1154 union uvh_gr0_tlb_int0_config_u {
1155         unsigned long   v;
1156         struct uvh_gr0_tlb_int0_config_s {
1157                 unsigned long   vector_:8;                      /* RW */
1158                 unsigned long   dm:3;                           /* RW */
1159                 unsigned long   destmode:1;                     /* RW */
1160                 unsigned long   status:1;                       /* RO */
1161                 unsigned long   p:1;                            /* RO */
1162                 unsigned long   rsvd_14:1;
1163                 unsigned long   t:1;                            /* RO */
1164                 unsigned long   m:1;                            /* RW */
1165                 unsigned long   rsvd_17_31:15;
1166                 unsigned long   apic_id:32;                     /* RW */
1167         } s;
1168         struct uv1h_gr0_tlb_int0_config_s {
1169                 unsigned long   vector_:8;                      /* RW */
1170                 unsigned long   dm:3;                           /* RW */
1171                 unsigned long   destmode:1;                     /* RW */
1172                 unsigned long   status:1;                       /* RO */
1173                 unsigned long   p:1;                            /* RO */
1174                 unsigned long   rsvd_14:1;
1175                 unsigned long   t:1;                            /* RO */
1176                 unsigned long   m:1;                            /* RW */
1177                 unsigned long   rsvd_17_31:15;
1178                 unsigned long   apic_id:32;                     /* RW */
1179         } s1;
1180         struct uvxh_gr0_tlb_int0_config_s {
1181                 unsigned long   vector_:8;                      /* RW */
1182                 unsigned long   dm:3;                           /* RW */
1183                 unsigned long   destmode:1;                     /* RW */
1184                 unsigned long   status:1;                       /* RO */
1185                 unsigned long   p:1;                            /* RO */
1186                 unsigned long   rsvd_14:1;
1187                 unsigned long   t:1;                            /* RO */
1188                 unsigned long   m:1;                            /* RW */
1189                 unsigned long   rsvd_17_31:15;
1190                 unsigned long   apic_id:32;                     /* RW */
1191         } sx;
1192         struct uv2h_gr0_tlb_int0_config_s {
1193                 unsigned long   vector_:8;                      /* RW */
1194                 unsigned long   dm:3;                           /* RW */
1195                 unsigned long   destmode:1;                     /* RW */
1196                 unsigned long   status:1;                       /* RO */
1197                 unsigned long   p:1;                            /* RO */
1198                 unsigned long   rsvd_14:1;
1199                 unsigned long   t:1;                            /* RO */
1200                 unsigned long   m:1;                            /* RW */
1201                 unsigned long   rsvd_17_31:15;
1202                 unsigned long   apic_id:32;                     /* RW */
1203         } s2;
1204         struct uv3h_gr0_tlb_int0_config_s {
1205                 unsigned long   vector_:8;                      /* RW */
1206                 unsigned long   dm:3;                           /* RW */
1207                 unsigned long   destmode:1;                     /* RW */
1208                 unsigned long   status:1;                       /* RO */
1209                 unsigned long   p:1;                            /* RO */
1210                 unsigned long   rsvd_14:1;
1211                 unsigned long   t:1;                            /* RO */
1212                 unsigned long   m:1;                            /* RW */
1213                 unsigned long   rsvd_17_31:15;
1214                 unsigned long   apic_id:32;                     /* RW */
1215         } s3;
1216 };
1217
1218 /* ========================================================================= */
1219 /*                         UVH_GR0_TLB_INT1_CONFIG                           */
1220 /* ========================================================================= */
1221 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
1222 #define UV1H_GR0_TLB_INT1_CONFIG 0x61b40UL
1223 #define UV2H_GR0_TLB_INT1_CONFIG 0x61b40UL
1224 #define UV3H_GR0_TLB_INT1_CONFIG 0x61b40UL
1225
1226 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT             0
1227 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT                 8
1228 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT           11
1229 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT             12
1230 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT                  13
1231 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT                  15
1232 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT                  16
1233 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT            32
1234 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK             0x00000000000000ffUL
1235 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK                 0x0000000000000700UL
1236 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK           0x0000000000000800UL
1237 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK             0x0000000000001000UL
1238 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK                  0x0000000000002000UL
1239 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK                  0x0000000000008000UL
1240 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
1241 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
1242
1243 #define UV1H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT            0
1244 #define UV1H_GR0_TLB_INT1_CONFIG_DM_SHFT                8
1245 #define UV1H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT          11
1246 #define UV1H_GR0_TLB_INT1_CONFIG_STATUS_SHFT            12
1247 #define UV1H_GR0_TLB_INT1_CONFIG_P_SHFT                 13
1248 #define UV1H_GR0_TLB_INT1_CONFIG_T_SHFT                 15
1249 #define UV1H_GR0_TLB_INT1_CONFIG_M_SHFT                 16
1250 #define UV1H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT           32
1251 #define UV1H_GR0_TLB_INT1_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1252 #define UV1H_GR0_TLB_INT1_CONFIG_DM_MASK                0x0000000000000700UL
1253 #define UV1H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1254 #define UV1H_GR0_TLB_INT1_CONFIG_STATUS_MASK            0x0000000000001000UL
1255 #define UV1H_GR0_TLB_INT1_CONFIG_P_MASK                 0x0000000000002000UL
1256 #define UV1H_GR0_TLB_INT1_CONFIG_T_MASK                 0x0000000000008000UL
1257 #define UV1H_GR0_TLB_INT1_CONFIG_M_MASK                 0x0000000000010000UL
1258 #define UV1H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1259
1260 #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT            0
1261 #define UVXH_GR0_TLB_INT1_CONFIG_DM_SHFT                8
1262 #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT          11
1263 #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_SHFT            12
1264 #define UVXH_GR0_TLB_INT1_CONFIG_P_SHFT                 13
1265 #define UVXH_GR0_TLB_INT1_CONFIG_T_SHFT                 15
1266 #define UVXH_GR0_TLB_INT1_CONFIG_M_SHFT                 16
1267 #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT           32
1268 #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1269 #define UVXH_GR0_TLB_INT1_CONFIG_DM_MASK                0x0000000000000700UL
1270 #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1271 #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_MASK            0x0000000000001000UL
1272 #define UVXH_GR0_TLB_INT1_CONFIG_P_MASK                 0x0000000000002000UL
1273 #define UVXH_GR0_TLB_INT1_CONFIG_T_MASK                 0x0000000000008000UL
1274 #define UVXH_GR0_TLB_INT1_CONFIG_M_MASK                 0x0000000000010000UL
1275 #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1276
1277 #define UV2H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT            0
1278 #define UV2H_GR0_TLB_INT1_CONFIG_DM_SHFT                8
1279 #define UV2H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT          11
1280 #define UV2H_GR0_TLB_INT1_CONFIG_STATUS_SHFT            12
1281 #define UV2H_GR0_TLB_INT1_CONFIG_P_SHFT                 13
1282 #define UV2H_GR0_TLB_INT1_CONFIG_T_SHFT                 15
1283 #define UV2H_GR0_TLB_INT1_CONFIG_M_SHFT                 16
1284 #define UV2H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT           32
1285 #define UV2H_GR0_TLB_INT1_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1286 #define UV2H_GR0_TLB_INT1_CONFIG_DM_MASK                0x0000000000000700UL
1287 #define UV2H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1288 #define UV2H_GR0_TLB_INT1_CONFIG_STATUS_MASK            0x0000000000001000UL
1289 #define UV2H_GR0_TLB_INT1_CONFIG_P_MASK                 0x0000000000002000UL
1290 #define UV2H_GR0_TLB_INT1_CONFIG_T_MASK                 0x0000000000008000UL
1291 #define UV2H_GR0_TLB_INT1_CONFIG_M_MASK                 0x0000000000010000UL
1292 #define UV2H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1293
1294 #define UV3H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT            0
1295 #define UV3H_GR0_TLB_INT1_CONFIG_DM_SHFT                8
1296 #define UV3H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT          11
1297 #define UV3H_GR0_TLB_INT1_CONFIG_STATUS_SHFT            12
1298 #define UV3H_GR0_TLB_INT1_CONFIG_P_SHFT                 13
1299 #define UV3H_GR0_TLB_INT1_CONFIG_T_SHFT                 15
1300 #define UV3H_GR0_TLB_INT1_CONFIG_M_SHFT                 16
1301 #define UV3H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT           32
1302 #define UV3H_GR0_TLB_INT1_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1303 #define UV3H_GR0_TLB_INT1_CONFIG_DM_MASK                0x0000000000000700UL
1304 #define UV3H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1305 #define UV3H_GR0_TLB_INT1_CONFIG_STATUS_MASK            0x0000000000001000UL
1306 #define UV3H_GR0_TLB_INT1_CONFIG_P_MASK                 0x0000000000002000UL
1307 #define UV3H_GR0_TLB_INT1_CONFIG_T_MASK                 0x0000000000008000UL
1308 #define UV3H_GR0_TLB_INT1_CONFIG_M_MASK                 0x0000000000010000UL
1309 #define UV3H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1310
1311 union uvh_gr0_tlb_int1_config_u {
1312         unsigned long   v;
1313         struct uvh_gr0_tlb_int1_config_s {
1314                 unsigned long   vector_:8;                      /* RW */
1315                 unsigned long   dm:3;                           /* RW */
1316                 unsigned long   destmode:1;                     /* RW */
1317                 unsigned long   status:1;                       /* RO */
1318                 unsigned long   p:1;                            /* RO */
1319                 unsigned long   rsvd_14:1;
1320                 unsigned long   t:1;                            /* RO */
1321                 unsigned long   m:1;                            /* RW */
1322                 unsigned long   rsvd_17_31:15;
1323                 unsigned long   apic_id:32;                     /* RW */
1324         } s;
1325         struct uv1h_gr0_tlb_int1_config_s {
1326                 unsigned long   vector_:8;                      /* RW */
1327                 unsigned long   dm:3;                           /* RW */
1328                 unsigned long   destmode:1;                     /* RW */
1329                 unsigned long   status:1;                       /* RO */
1330                 unsigned long   p:1;                            /* RO */
1331                 unsigned long   rsvd_14:1;
1332                 unsigned long   t:1;                            /* RO */
1333                 unsigned long   m:1;                            /* RW */
1334                 unsigned long   rsvd_17_31:15;
1335                 unsigned long   apic_id:32;                     /* RW */
1336         } s1;
1337         struct uvxh_gr0_tlb_int1_config_s {
1338                 unsigned long   vector_:8;                      /* RW */
1339                 unsigned long   dm:3;                           /* RW */
1340                 unsigned long   destmode:1;                     /* RW */
1341                 unsigned long   status:1;                       /* RO */
1342                 unsigned long   p:1;                            /* RO */
1343                 unsigned long   rsvd_14:1;
1344                 unsigned long   t:1;                            /* RO */
1345                 unsigned long   m:1;                            /* RW */
1346                 unsigned long   rsvd_17_31:15;
1347                 unsigned long   apic_id:32;                     /* RW */
1348         } sx;
1349         struct uv2h_gr0_tlb_int1_config_s {
1350                 unsigned long   vector_:8;                      /* RW */
1351                 unsigned long   dm:3;                           /* RW */
1352                 unsigned long   destmode:1;                     /* RW */
1353                 unsigned long   status:1;                       /* RO */
1354                 unsigned long   p:1;                            /* RO */
1355                 unsigned long   rsvd_14:1;
1356                 unsigned long   t:1;                            /* RO */
1357                 unsigned long   m:1;                            /* RW */
1358                 unsigned long   rsvd_17_31:15;
1359                 unsigned long   apic_id:32;                     /* RW */
1360         } s2;
1361         struct uv3h_gr0_tlb_int1_config_s {
1362                 unsigned long   vector_:8;                      /* RW */
1363                 unsigned long   dm:3;                           /* RW */
1364                 unsigned long   destmode:1;                     /* RW */
1365                 unsigned long   status:1;                       /* RO */
1366                 unsigned long   p:1;                            /* RO */
1367                 unsigned long   rsvd_14:1;
1368                 unsigned long   t:1;                            /* RO */
1369                 unsigned long   m:1;                            /* RW */
1370                 unsigned long   rsvd_17_31:15;
1371                 unsigned long   apic_id:32;                     /* RW */
1372         } s3;
1373 };
1374
1375 /* ========================================================================= */
1376 /*                         UVH_GR0_TLB_MMR_CONTROL                           */
1377 /* ========================================================================= */
1378 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
1379 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
1380 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL
1381 #define UVH_GR0_TLB_MMR_CONTROL                                         \
1382                 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL :              \
1383                 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL :              \
1384                                 UV3H_GR0_TLB_MMR_CONTROL))
1385
1386 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT              0
1387 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT            12
1388 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
1389 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
1390 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
1391 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT           31
1392 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK              0x0000000000000fffUL
1393 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK            0x0000000000003000UL
1394 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
1395 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
1396 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
1397 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK           0x0000000080000000UL
1398
1399 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
1400 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1401 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1402 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1403 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1404 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1405 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
1406 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
1407 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
1408 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT   56
1409 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT   60
1410 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1411 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1412 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1413 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1414 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1415 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1416 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
1417 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
1418 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
1419 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK   0x0100000000000000UL
1420 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
1421
1422 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
1423 #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1424 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1425 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1426 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1427 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1428 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1429 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1430 #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1431 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1432 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1433 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1434 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1435 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1436
1437 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
1438 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1439 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1440 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1441 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1442 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1443 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1444 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
1445 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
1446 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1447 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1448 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1449 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1450 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1451 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1452 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1453 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
1454 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
1455
1456 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
1457 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1458 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1459 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1460 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
1461 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1462 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1463 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1464 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1465 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1466 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1467 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1468 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
1469 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1470 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1471 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1472
1473 union uvh_gr0_tlb_mmr_control_u {
1474         unsigned long   v;
1475         struct uvh_gr0_tlb_mmr_control_s {
1476                 unsigned long   index:12;                       /* RW */
1477                 unsigned long   mem_sel:2;                      /* RW */
1478                 unsigned long   rsvd_14_15:2;
1479                 unsigned long   auto_valid_en:1;                /* RW */
1480                 unsigned long   rsvd_17_19:3;
1481                 unsigned long   mmr_hash_index_en:1;            /* RW */
1482                 unsigned long   rsvd_21_29:9;
1483                 unsigned long   mmr_write:1;                    /* WP */
1484                 unsigned long   mmr_read:1;                     /* WP */
1485                 unsigned long   rsvd_32_48:17;
1486                 unsigned long   rsvd_49_51:3;
1487                 unsigned long   rsvd_52_63:12;
1488         } s;
1489         struct uv1h_gr0_tlb_mmr_control_s {
1490                 unsigned long   index:12;                       /* RW */
1491                 unsigned long   mem_sel:2;                      /* RW */
1492                 unsigned long   rsvd_14_15:2;
1493                 unsigned long   auto_valid_en:1;                /* RW */
1494                 unsigned long   rsvd_17_19:3;
1495                 unsigned long   mmr_hash_index_en:1;            /* RW */
1496                 unsigned long   rsvd_21_29:9;
1497                 unsigned long   mmr_write:1;                    /* WP */
1498                 unsigned long   mmr_read:1;                     /* WP */
1499                 unsigned long   rsvd_32_47:16;
1500                 unsigned long   mmr_inj_con:1;                  /* RW */
1501                 unsigned long   rsvd_49_51:3;
1502                 unsigned long   mmr_inj_tlbram:1;               /* RW */
1503                 unsigned long   rsvd_53:1;
1504                 unsigned long   mmr_inj_tlbpgsize:1;            /* RW */
1505                 unsigned long   rsvd_55:1;
1506                 unsigned long   mmr_inj_tlbrreg:1;              /* RW */
1507                 unsigned long   rsvd_57_59:3;
1508                 unsigned long   mmr_inj_tlblruv:1;              /* RW */
1509                 unsigned long   rsvd_61_63:3;
1510         } s1;
1511         struct uvxh_gr0_tlb_mmr_control_s {
1512                 unsigned long   index:12;                       /* RW */
1513                 unsigned long   mem_sel:2;                      /* RW */
1514                 unsigned long   rsvd_14_15:2;
1515                 unsigned long   auto_valid_en:1;                /* RW */
1516                 unsigned long   rsvd_17_19:3;
1517                 unsigned long   mmr_hash_index_en:1;            /* RW */
1518                 unsigned long   rsvd_21_29:9;
1519                 unsigned long   mmr_write:1;                    /* WP */
1520                 unsigned long   mmr_read:1;                     /* WP */
1521                 unsigned long   mmr_op_done:1;                  /* RW */
1522                 unsigned long   rsvd_33_47:15;
1523                 unsigned long   rsvd_48:1;
1524                 unsigned long   rsvd_49_51:3;
1525                 unsigned long   rsvd_52:1;
1526                 unsigned long   rsvd_53_63:11;
1527         } sx;
1528         struct uv2h_gr0_tlb_mmr_control_s {
1529                 unsigned long   index:12;                       /* RW */
1530                 unsigned long   mem_sel:2;                      /* RW */
1531                 unsigned long   rsvd_14_15:2;
1532                 unsigned long   auto_valid_en:1;                /* RW */
1533                 unsigned long   rsvd_17_19:3;
1534                 unsigned long   mmr_hash_index_en:1;            /* RW */
1535                 unsigned long   rsvd_21_29:9;
1536                 unsigned long   mmr_write:1;                    /* WP */
1537                 unsigned long   mmr_read:1;                     /* WP */
1538                 unsigned long   mmr_op_done:1;                  /* RW */
1539                 unsigned long   rsvd_33_47:15;
1540                 unsigned long   mmr_inj_con:1;                  /* RW */
1541                 unsigned long   rsvd_49_51:3;
1542                 unsigned long   mmr_inj_tlbram:1;               /* RW */
1543                 unsigned long   rsvd_53_63:11;
1544         } s2;
1545         struct uv3h_gr0_tlb_mmr_control_s {
1546                 unsigned long   index:12;                       /* RW */
1547                 unsigned long   mem_sel:2;                      /* RW */
1548                 unsigned long   rsvd_14_15:2;
1549                 unsigned long   auto_valid_en:1;                /* RW */
1550                 unsigned long   rsvd_17_19:3;
1551                 unsigned long   mmr_hash_index_en:1;            /* RW */
1552                 unsigned long   ecc_sel:1;                      /* RW */
1553                 unsigned long   rsvd_22_29:8;
1554                 unsigned long   mmr_write:1;                    /* WP */
1555                 unsigned long   mmr_read:1;                     /* WP */
1556                 unsigned long   mmr_op_done:1;                  /* RW */
1557                 unsigned long   rsvd_33_47:15;
1558                 unsigned long   undef_48:1;                     /* Undefined */
1559                 unsigned long   rsvd_49_51:3;
1560                 unsigned long   undef_52:1;                     /* Undefined */
1561                 unsigned long   rsvd_53_63:11;
1562         } s3;
1563 };
1564
1565 /* ========================================================================= */
1566 /*                       UVH_GR0_TLB_MMR_READ_DATA_HI                        */
1567 /* ========================================================================= */
1568 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
1569 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
1570 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
1571 #define UVH_GR0_TLB_MMR_READ_DATA_HI                                    \
1572                 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI :         \
1573                 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI :         \
1574                                 UV3H_GR0_TLB_MMR_READ_DATA_HI))
1575
1576 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
1577 #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT           41
1578 #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT         43
1579 #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT        44
1580 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK           0x000001ffffffffffUL
1581 #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK           0x0000060000000000UL
1582 #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK         0x0000080000000000UL
1583 #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK        0x0000100000000000UL
1584
1585 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1586 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1587 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1588 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1589 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1590 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1591 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1592 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1593
1594 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1595 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1596 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1597 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1598 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1599 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1600 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1601 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1602
1603 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1604 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1605 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1606 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1607 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1608 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1609 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1610 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1611
1612 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1613 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1614 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1615 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1616 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       45
1617 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
1618 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1619 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1620 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1621 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1622 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0000200000000000UL
1623 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
1624
1625 union uvh_gr0_tlb_mmr_read_data_hi_u {
1626         unsigned long   v;
1627         struct uvh_gr0_tlb_mmr_read_data_hi_s {
1628                 unsigned long   pfn:41;                         /* RO */
1629                 unsigned long   gaa:2;                          /* RO */
1630                 unsigned long   dirty:1;                        /* RO */
1631                 unsigned long   larger:1;                       /* RO */
1632                 unsigned long   rsvd_45_63:19;
1633         } s;
1634         struct uv1h_gr0_tlb_mmr_read_data_hi_s {
1635                 unsigned long   pfn:41;                         /* RO */
1636                 unsigned long   gaa:2;                          /* RO */
1637                 unsigned long   dirty:1;                        /* RO */
1638                 unsigned long   larger:1;                       /* RO */
1639                 unsigned long   rsvd_45_63:19;
1640         } s1;
1641         struct uvxh_gr0_tlb_mmr_read_data_hi_s {
1642                 unsigned long   pfn:41;                         /* RO */
1643                 unsigned long   gaa:2;                          /* RO */
1644                 unsigned long   dirty:1;                        /* RO */
1645                 unsigned long   larger:1;                       /* RO */
1646                 unsigned long   rsvd_45_63:19;
1647         } sx;
1648         struct uv2h_gr0_tlb_mmr_read_data_hi_s {
1649                 unsigned long   pfn:41;                         /* RO */
1650                 unsigned long   gaa:2;                          /* RO */
1651                 unsigned long   dirty:1;                        /* RO */
1652                 unsigned long   larger:1;                       /* RO */
1653                 unsigned long   rsvd_45_63:19;
1654         } s2;
1655         struct uv3h_gr0_tlb_mmr_read_data_hi_s {
1656                 unsigned long   pfn:41;                         /* RO */
1657                 unsigned long   gaa:2;                          /* RO */
1658                 unsigned long   dirty:1;                        /* RO */
1659                 unsigned long   larger:1;                       /* RO */
1660                 unsigned long   aa_ext:1;                       /* RO */
1661                 unsigned long   undef_46_54:9;                  /* Undefined */
1662                 unsigned long   way_ecc:9;                      /* RO */
1663         } s3;
1664 };
1665
1666 /* ========================================================================= */
1667 /*                       UVH_GR0_TLB_MMR_READ_DATA_LO                        */
1668 /* ========================================================================= */
1669 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
1670 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
1671 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
1672 #define UVH_GR0_TLB_MMR_READ_DATA_LO                                    \
1673                 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO :         \
1674                 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO :         \
1675                                 UV3H_GR0_TLB_MMR_READ_DATA_LO))
1676
1677 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
1678 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
1679 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT         63
1680 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK           0x0000007fffffffffUL
1681 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK          0x7fffff8000000000UL
1682 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK         0x8000000000000000UL
1683
1684 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1685 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1686 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1687 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1688 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1689 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1690
1691 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1692 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1693 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1694 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1695 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1696 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1697
1698 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1699 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1700 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1701 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1702 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1703 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1704
1705 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1706 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1707 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1708 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1709 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1710 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1711
1712 union uvh_gr0_tlb_mmr_read_data_lo_u {
1713         unsigned long   v;
1714         struct uvh_gr0_tlb_mmr_read_data_lo_s {
1715                 unsigned long   vpn:39;                         /* RO */
1716                 unsigned long   asid:24;                        /* RO */
1717                 unsigned long   valid:1;                        /* RO */
1718         } s;
1719         struct uv1h_gr0_tlb_mmr_read_data_lo_s {
1720                 unsigned long   vpn:39;                         /* RO */
1721                 unsigned long   asid:24;                        /* RO */
1722                 unsigned long   valid:1;                        /* RO */
1723         } s1;
1724         struct uvxh_gr0_tlb_mmr_read_data_lo_s {
1725                 unsigned long   vpn:39;                         /* RO */
1726                 unsigned long   asid:24;                        /* RO */
1727                 unsigned long   valid:1;                        /* RO */
1728         } sx;
1729         struct uv2h_gr0_tlb_mmr_read_data_lo_s {
1730                 unsigned long   vpn:39;                         /* RO */
1731                 unsigned long   asid:24;                        /* RO */
1732                 unsigned long   valid:1;                        /* RO */
1733         } s2;
1734         struct uv3h_gr0_tlb_mmr_read_data_lo_s {
1735                 unsigned long   vpn:39;                         /* RO */
1736                 unsigned long   asid:24;                        /* RO */
1737                 unsigned long   valid:1;                        /* RO */
1738         } s3;
1739 };
1740
1741 /* ========================================================================= */
1742 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
1743 /* ========================================================================= */
1744 #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
1745 #define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL
1746 #define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL
1747 #define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL
1748
1749 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT             0
1750 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT                 8
1751 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT           11
1752 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT             12
1753 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT                  13
1754 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT                  15
1755 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT                  16
1756 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT            32
1757 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK             0x00000000000000ffUL
1758 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK                 0x0000000000000700UL
1759 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK           0x0000000000000800UL
1760 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK             0x0000000000001000UL
1761 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK                  0x0000000000002000UL
1762 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK                  0x0000000000008000UL
1763 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
1764 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
1765
1766 #define UV1H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT            0
1767 #define UV1H_GR1_TLB_INT0_CONFIG_DM_SHFT                8
1768 #define UV1H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT          11
1769 #define UV1H_GR1_TLB_INT0_CONFIG_STATUS_SHFT            12
1770 #define UV1H_GR1_TLB_INT0_CONFIG_P_SHFT                 13
1771 #define UV1H_GR1_TLB_INT0_CONFIG_T_SHFT                 15
1772 #define UV1H_GR1_TLB_INT0_CONFIG_M_SHFT                 16
1773 #define UV1H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT           32
1774 #define UV1H_GR1_TLB_INT0_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1775 #define UV1H_GR1_TLB_INT0_CONFIG_DM_MASK                0x0000000000000700UL
1776 #define UV1H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1777 #define UV1H_GR1_TLB_INT0_CONFIG_STATUS_MASK            0x0000000000001000UL
1778 #define UV1H_GR1_TLB_INT0_CONFIG_P_MASK                 0x0000000000002000UL
1779 #define UV1H_GR1_TLB_INT0_CONFIG_T_MASK                 0x0000000000008000UL
1780 #define UV1H_GR1_TLB_INT0_CONFIG_M_MASK                 0x0000000000010000UL
1781 #define UV1H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1782
1783 #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT            0
1784 #define UVXH_GR1_TLB_INT0_CONFIG_DM_SHFT                8
1785 #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT          11
1786 #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_SHFT            12
1787 #define UVXH_GR1_TLB_INT0_CONFIG_P_SHFT                 13
1788 #define UVXH_GR1_TLB_INT0_CONFIG_T_SHFT                 15
1789 #define UVXH_GR1_TLB_INT0_CONFIG_M_SHFT                 16
1790 #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT           32
1791 #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1792 #define UVXH_GR1_TLB_INT0_CONFIG_DM_MASK                0x0000000000000700UL
1793 #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1794 #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_MASK            0x0000000000001000UL
1795 #define UVXH_GR1_TLB_INT0_CONFIG_P_MASK                 0x0000000000002000UL
1796 #define UVXH_GR1_TLB_INT0_CONFIG_T_MASK                 0x0000000000008000UL
1797 #define UVXH_GR1_TLB_INT0_CONFIG_M_MASK                 0x0000000000010000UL
1798 #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1799
1800 #define UV2H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT            0
1801 #define UV2H_GR1_TLB_INT0_CONFIG_DM_SHFT                8
1802 #define UV2H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT          11
1803 #define UV2H_GR1_TLB_INT0_CONFIG_STATUS_SHFT            12
1804 #define UV2H_GR1_TLB_INT0_CONFIG_P_SHFT                 13
1805 #define UV2H_GR1_TLB_INT0_CONFIG_T_SHFT                 15
1806 #define UV2H_GR1_TLB_INT0_CONFIG_M_SHFT                 16
1807 #define UV2H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT           32
1808 #define UV2H_GR1_TLB_INT0_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1809 #define UV2H_GR1_TLB_INT0_CONFIG_DM_MASK                0x0000000000000700UL
1810 #define UV2H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1811 #define UV2H_GR1_TLB_INT0_CONFIG_STATUS_MASK            0x0000000000001000UL
1812 #define UV2H_GR1_TLB_INT0_CONFIG_P_MASK                 0x0000000000002000UL
1813 #define UV2H_GR1_TLB_INT0_CONFIG_T_MASK                 0x0000000000008000UL
1814 #define UV2H_GR1_TLB_INT0_CONFIG_M_MASK                 0x0000000000010000UL
1815 #define UV2H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1816
1817 #define UV3H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT            0
1818 #define UV3H_GR1_TLB_INT0_CONFIG_DM_SHFT                8
1819 #define UV3H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT          11
1820 #define UV3H_GR1_TLB_INT0_CONFIG_STATUS_SHFT            12
1821 #define UV3H_GR1_TLB_INT0_CONFIG_P_SHFT                 13
1822 #define UV3H_GR1_TLB_INT0_CONFIG_T_SHFT                 15
1823 #define UV3H_GR1_TLB_INT0_CONFIG_M_SHFT                 16
1824 #define UV3H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT           32
1825 #define UV3H_GR1_TLB_INT0_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1826 #define UV3H_GR1_TLB_INT0_CONFIG_DM_MASK                0x0000000000000700UL
1827 #define UV3H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1828 #define UV3H_GR1_TLB_INT0_CONFIG_STATUS_MASK            0x0000000000001000UL
1829 #define UV3H_GR1_TLB_INT0_CONFIG_P_MASK                 0x0000000000002000UL
1830 #define UV3H_GR1_TLB_INT0_CONFIG_T_MASK                 0x0000000000008000UL
1831 #define UV3H_GR1_TLB_INT0_CONFIG_M_MASK                 0x0000000000010000UL
1832 #define UV3H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1833
1834 union uvh_gr1_tlb_int0_config_u {
1835         unsigned long   v;
1836         struct uvh_gr1_tlb_int0_config_s {
1837                 unsigned long   vector_:8;                      /* RW */
1838                 unsigned long   dm:3;                           /* RW */
1839                 unsigned long   destmode:1;                     /* RW */
1840                 unsigned long   status:1;                       /* RO */
1841                 unsigned long   p:1;                            /* RO */
1842                 unsigned long   rsvd_14:1;
1843                 unsigned long   t:1;                            /* RO */
1844                 unsigned long   m:1;                            /* RW */
1845                 unsigned long   rsvd_17_31:15;
1846                 unsigned long   apic_id:32;                     /* RW */
1847         } s;
1848         struct uv1h_gr1_tlb_int0_config_s {
1849                 unsigned long   vector_:8;                      /* RW */
1850                 unsigned long   dm:3;                           /* RW */
1851                 unsigned long   destmode:1;                     /* RW */
1852                 unsigned long   status:1;                       /* RO */
1853                 unsigned long   p:1;                            /* RO */
1854                 unsigned long   rsvd_14:1;
1855                 unsigned long   t:1;                            /* RO */
1856                 unsigned long   m:1;                            /* RW */
1857                 unsigned long   rsvd_17_31:15;
1858                 unsigned long   apic_id:32;                     /* RW */
1859         } s1;
1860         struct uvxh_gr1_tlb_int0_config_s {
1861                 unsigned long   vector_:8;                      /* RW */
1862                 unsigned long   dm:3;                           /* RW */
1863                 unsigned long   destmode:1;                     /* RW */
1864                 unsigned long   status:1;                       /* RO */
1865                 unsigned long   p:1;                            /* RO */
1866                 unsigned long   rsvd_14:1;
1867                 unsigned long   t:1;                            /* RO */
1868                 unsigned long   m:1;                            /* RW */
1869                 unsigned long   rsvd_17_31:15;
1870                 unsigned long   apic_id:32;                     /* RW */
1871         } sx;
1872         struct uv2h_gr1_tlb_int0_config_s {
1873                 unsigned long   vector_:8;                      /* RW */
1874                 unsigned long   dm:3;                           /* RW */
1875                 unsigned long   destmode:1;                     /* RW */
1876                 unsigned long   status:1;                       /* RO */
1877                 unsigned long   p:1;                            /* RO */
1878                 unsigned long   rsvd_14:1;
1879                 unsigned long   t:1;                            /* RO */
1880                 unsigned long   m:1;                            /* RW */
1881                 unsigned long   rsvd_17_31:15;
1882                 unsigned long   apic_id:32;                     /* RW */
1883         } s2;
1884         struct uv3h_gr1_tlb_int0_config_s {
1885                 unsigned long   vector_:8;                      /* RW */
1886                 unsigned long   dm:3;                           /* RW */
1887                 unsigned long   destmode:1;                     /* RW */
1888                 unsigned long   status:1;                       /* RO */
1889                 unsigned long   p:1;                            /* RO */
1890                 unsigned long   rsvd_14:1;
1891                 unsigned long   t:1;                            /* RO */
1892                 unsigned long   m:1;                            /* RW */
1893                 unsigned long   rsvd_17_31:15;
1894                 unsigned long   apic_id:32;                     /* RW */
1895         } s3;
1896 };
1897
1898 /* ========================================================================= */
1899 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
1900 /* ========================================================================= */
1901 #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
1902 #define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL
1903 #define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL
1904 #define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL
1905
1906 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT             0
1907 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT                 8
1908 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT           11
1909 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT             12
1910 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT                  13
1911 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT                  15
1912 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT                  16
1913 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT            32
1914 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK             0x00000000000000ffUL
1915 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK                 0x0000000000000700UL
1916 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK           0x0000000000000800UL
1917 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK             0x0000000000001000UL
1918 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK                  0x0000000000002000UL
1919 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK                  0x0000000000008000UL
1920 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
1921 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
1922
1923 #define UV1H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT            0
1924 #define UV1H_GR1_TLB_INT1_CONFIG_DM_SHFT                8
1925 #define UV1H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT          11
1926 #define UV1H_GR1_TLB_INT1_CONFIG_STATUS_SHFT            12
1927 #define UV1H_GR1_TLB_INT1_CONFIG_P_SHFT                 13
1928 #define UV1H_GR1_TLB_INT1_CONFIG_T_SHFT                 15
1929 #define UV1H_GR1_TLB_INT1_CONFIG_M_SHFT                 16
1930 #define UV1H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT           32
1931 #define UV1H_GR1_TLB_INT1_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1932 #define UV1H_GR1_TLB_INT1_CONFIG_DM_MASK                0x0000000000000700UL
1933 #define UV1H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1934 #define UV1H_GR1_TLB_INT1_CONFIG_STATUS_MASK            0x0000000000001000UL
1935 #define UV1H_GR1_TLB_INT1_CONFIG_P_MASK                 0x0000000000002000UL
1936 #define UV1H_GR1_TLB_INT1_CONFIG_T_MASK                 0x0000000000008000UL
1937 #define UV1H_GR1_TLB_INT1_CONFIG_M_MASK                 0x0000000000010000UL
1938 #define UV1H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1939
1940 #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT            0
1941 #define UVXH_GR1_TLB_INT1_CONFIG_DM_SHFT                8
1942 #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT          11
1943 #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_SHFT            12
1944 #define UVXH_GR1_TLB_INT1_CONFIG_P_SHFT                 13
1945 #define UVXH_GR1_TLB_INT1_CONFIG_T_SHFT                 15
1946 #define UVXH_GR1_TLB_INT1_CONFIG_M_SHFT                 16
1947 #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT           32
1948 #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1949 #define UVXH_GR1_TLB_INT1_CONFIG_DM_MASK                0x0000000000000700UL
1950 #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1951 #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_MASK            0x0000000000001000UL
1952 #define UVXH_GR1_TLB_INT1_CONFIG_P_MASK                 0x0000000000002000UL
1953 #define UVXH_GR1_TLB_INT1_CONFIG_T_MASK                 0x0000000000008000UL
1954 #define UVXH_GR1_TLB_INT1_CONFIG_M_MASK                 0x0000000000010000UL
1955 #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1956
1957 #define UV2H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT            0
1958 #define UV2H_GR1_TLB_INT1_CONFIG_DM_SHFT                8
1959 #define UV2H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT          11
1960 #define UV2H_GR1_TLB_INT1_CONFIG_STATUS_SHFT            12
1961 #define UV2H_GR1_TLB_INT1_CONFIG_P_SHFT                 13
1962 #define UV2H_GR1_TLB_INT1_CONFIG_T_SHFT                 15
1963 #define UV2H_GR1_TLB_INT1_CONFIG_M_SHFT                 16
1964 #define UV2H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT           32
1965 #define UV2H_GR1_TLB_INT1_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1966 #define UV2H_GR1_TLB_INT1_CONFIG_DM_MASK                0x0000000000000700UL
1967 #define UV2H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1968 #define UV2H_GR1_TLB_INT1_CONFIG_STATUS_MASK            0x0000000000001000UL
1969 #define UV2H_GR1_TLB_INT1_CONFIG_P_MASK                 0x0000000000002000UL
1970 #define UV2H_GR1_TLB_INT1_CONFIG_T_MASK                 0x0000000000008000UL
1971 #define UV2H_GR1_TLB_INT1_CONFIG_M_MASK                 0x0000000000010000UL
1972 #define UV2H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1973
1974 #define UV3H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT            0
1975 #define UV3H_GR1_TLB_INT1_CONFIG_DM_SHFT                8
1976 #define UV3H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT          11
1977 #define UV3H_GR1_TLB_INT1_CONFIG_STATUS_SHFT            12
1978 #define UV3H_GR1_TLB_INT1_CONFIG_P_SHFT                 13
1979 #define UV3H_GR1_TLB_INT1_CONFIG_T_SHFT                 15
1980 #define UV3H_GR1_TLB_INT1_CONFIG_M_SHFT                 16
1981 #define UV3H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT           32
1982 #define UV3H_GR1_TLB_INT1_CONFIG_VECTOR_MASK            0x00000000000000ffUL
1983 #define UV3H_GR1_TLB_INT1_CONFIG_DM_MASK                0x0000000000000700UL
1984 #define UV3H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK          0x0000000000000800UL
1985 #define UV3H_GR1_TLB_INT1_CONFIG_STATUS_MASK            0x0000000000001000UL
1986 #define UV3H_GR1_TLB_INT1_CONFIG_P_MASK                 0x0000000000002000UL
1987 #define UV3H_GR1_TLB_INT1_CONFIG_T_MASK                 0x0000000000008000UL
1988 #define UV3H_GR1_TLB_INT1_CONFIG_M_MASK                 0x0000000000010000UL
1989 #define UV3H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK           0xffffffff00000000UL
1990
1991 union uvh_gr1_tlb_int1_config_u {
1992         unsigned long   v;
1993         struct uvh_gr1_tlb_int1_config_s {
1994                 unsigned long   vector_:8;                      /* RW */
1995                 unsigned long   dm:3;                           /* RW */
1996                 unsigned long   destmode:1;                     /* RW */
1997                 unsigned long   status:1;                       /* RO */
1998                 unsigned long   p:1;                            /* RO */
1999                 unsigned long   rsvd_14:1;
2000                 unsigned long   t:1;                            /* RO */
2001                 unsigned long   m:1;                            /* RW */
2002                 unsigned long   rsvd_17_31:15;
2003                 unsigned long   apic_id:32;                     /* RW */
2004         } s;
2005         struct uv1h_gr1_tlb_int1_config_s {
2006                 unsigned long   vector_:8;                      /* RW */
2007                 unsigned long   dm:3;                           /* RW */
2008                 unsigned long   destmode:1;                     /* RW */
2009                 unsigned long   status:1;                       /* RO */
2010                 unsigned long   p:1;                            /* RO */
2011                 unsigned long   rsvd_14:1;
2012                 unsigned long   t:1;                            /* RO */
2013                 unsigned long   m:1;                            /* RW */
2014                 unsigned long   rsvd_17_31:15;
2015                 unsigned long   apic_id:32;                     /* RW */
2016         } s1;
2017         struct uvxh_gr1_tlb_int1_config_s {
2018                 unsigned long   vector_:8;                      /* RW */
2019                 unsigned long   dm:3;                           /* RW */
2020                 unsigned long   destmode:1;                     /* RW */
2021                 unsigned long   status:1;                       /* RO */
2022                 unsigned long   p:1;                            /* RO */
2023                 unsigned long   rsvd_14:1;
2024                 unsigned long   t:1;                            /* RO */
2025                 unsigned long   m:1;                            /* RW */
2026                 unsigned long   rsvd_17_31:15;
2027                 unsigned long   apic_id:32;                     /* RW */
2028         } sx;
2029         struct uv2h_gr1_tlb_int1_config_s {
2030                 unsigned long   vector_:8;                      /* RW */
2031                 unsigned long   dm:3;                           /* RW */
2032                 unsigned long   destmode:1;                     /* RW */
2033                 unsigned long   status:1;                       /* RO */
2034                 unsigned long   p:1;                            /* RO */
2035                 unsigned long   rsvd_14:1;
2036                 unsigned long   t:1;                            /* RO */
2037                 unsigned long   m:1;                            /* RW */
2038                 unsigned long   rsvd_17_31:15;
2039                 unsigned long   apic_id:32;                     /* RW */
2040         } s2;
2041         struct uv3h_gr1_tlb_int1_config_s {
2042                 unsigned long   vector_:8;                      /* RW */
2043                 unsigned long   dm:3;                           /* RW */
2044                 unsigned long   destmode:1;                     /* RW */
2045                 unsigned long   status:1;                       /* RO */
2046                 unsigned long   p:1;                            /* RO */
2047                 unsigned long   rsvd_14:1;
2048                 unsigned long   t:1;                            /* RO */
2049                 unsigned long   m:1;                            /* RW */
2050                 unsigned long   rsvd_17_31:15;
2051                 unsigned long   apic_id:32;                     /* RW */
2052         } s3;
2053 };
2054
2055 /* ========================================================================= */
2056 /*                         UVH_GR1_TLB_MMR_CONTROL                           */
2057 /* ========================================================================= */
2058 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
2059 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
2060 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL
2061 #define UVH_GR1_TLB_MMR_CONTROL                                         \
2062                 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL :              \
2063                 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL :              \
2064                                 UV3H_GR1_TLB_MMR_CONTROL))
2065
2066 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT              0
2067 #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT            12
2068 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
2069 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
2070 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
2071 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT           31
2072 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK              0x0000000000000fffUL
2073 #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK            0x0000000000003000UL
2074 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
2075 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
2076 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
2077 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK           0x0000000080000000UL
2078
2079 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
2080 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
2081 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
2082 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
2083 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
2084 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
2085 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
2086 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
2087 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
2088 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT   56
2089 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT   60
2090 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
2091 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
2092 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
2093 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
2094 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
2095 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
2096 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
2097 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
2098 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
2099 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK   0x0100000000000000UL
2100 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
2101
2102 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
2103 #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
2104 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
2105 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
2106 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
2107 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
2108 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
2109 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
2110 #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
2111 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
2112 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
2113 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
2114 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
2115 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
2116
2117 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
2118 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
2119 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
2120 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
2121 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
2122 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
2123 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
2124 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
2125 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
2126 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
2127 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
2128 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
2129 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
2130 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
2131 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
2132 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
2133 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
2134 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
2135
2136 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
2137 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
2138 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
2139 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
2140 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
2141 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
2142 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
2143 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
2144 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
2145 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
2146 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
2147 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
2148 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
2149 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
2150 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
2151 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
2152
2153 union uvh_gr1_tlb_mmr_control_u {
2154         unsigned long   v;
2155         struct uvh_gr1_tlb_mmr_control_s {
2156                 unsigned long   index:12;                       /* RW */
2157                 unsigned long   mem_sel:2;                      /* RW */
2158                 unsigned long   rsvd_14_15:2;
2159                 unsigned long   auto_valid_en:1;                /* RW */
2160                 unsigned long   rsvd_17_19:3;
2161                 unsigned long   mmr_hash_index_en:1;            /* RW */
2162                 unsigned long   rsvd_21_29:9;
2163                 unsigned long   mmr_write:1;                    /* WP */
2164                 unsigned long   mmr_read:1;                     /* WP */
2165                 unsigned long   rsvd_32_48:17;
2166                 unsigned long   rsvd_49_51:3;
2167                 unsigned long   rsvd_52_63:12;
2168         } s;
2169         struct uv1h_gr1_tlb_mmr_control_s {
2170                 unsigned long   index:12;                       /* RW */
2171                 unsigned long   mem_sel:2;                      /* RW */
2172                 unsigned long   rsvd_14_15:2;
2173                 unsigned long   auto_valid_en:1;                /* RW */
2174                 unsigned long   rsvd_17_19:3;
2175                 unsigned long   mmr_hash_index_en:1;            /* RW */
2176                 unsigned long   rsvd_21_29:9;
2177                 unsigned long   mmr_write:1;                    /* WP */
2178                 unsigned long   mmr_read:1;                     /* WP */
2179                 unsigned long   rsvd_32_47:16;
2180                 unsigned long   mmr_inj_con:1;                  /* RW */
2181                 unsigned long   rsvd_49_51:3;
2182                 unsigned long   mmr_inj_tlbram:1;               /* RW */
2183                 unsigned long   rsvd_53:1;
2184                 unsigned long   mmr_inj_tlbpgsize:1;            /* RW */
2185                 unsigned long   rsvd_55:1;
2186                 unsigned long   mmr_inj_tlbrreg:1;              /* RW */
2187                 unsigned long   rsvd_57_59:3;
2188                 unsigned long   mmr_inj_tlblruv:1;              /* RW */
2189                 unsigned long   rsvd_61_63:3;
2190         } s1;
2191         struct uvxh_gr1_tlb_mmr_control_s {
2192                 unsigned long   index:12;                       /* RW */
2193                 unsigned long   mem_sel:2;                      /* RW */
2194                 unsigned long   rsvd_14_15:2;
2195                 unsigned long   auto_valid_en:1;                /* RW */
2196                 unsigned long   rsvd_17_19:3;
2197                 unsigned long   mmr_hash_index_en:1;            /* RW */
2198                 unsigned long   rsvd_21_29:9;
2199                 unsigned long   mmr_write:1;                    /* WP */
2200                 unsigned long   mmr_read:1;                     /* WP */
2201                 unsigned long   mmr_op_done:1;                  /* RW */
2202                 unsigned long   rsvd_33_47:15;
2203                 unsigned long   rsvd_48:1;
2204                 unsigned long   rsvd_49_51:3;
2205                 unsigned long   rsvd_52:1;
2206                 unsigned long   rsvd_53_63:11;
2207         } sx;
2208         struct uv2h_gr1_tlb_mmr_control_s {
2209                 unsigned long   index:12;                       /* RW */
2210                 unsigned long   mem_sel:2;                      /* RW */
2211                 unsigned long   rsvd_14_15:2;
2212                 unsigned long   auto_valid_en:1;                /* RW */
2213                 unsigned long   rsvd_17_19:3;
2214                 unsigned long   mmr_hash_index_en:1;            /* RW */
2215                 unsigned long   rsvd_21_29:9;
2216                 unsigned long   mmr_write:1;                    /* WP */
2217                 unsigned long   mmr_read:1;                     /* WP */
2218                 unsigned long   mmr_op_done:1;                  /* RW */
2219                 unsigned long   rsvd_33_47:15;
2220                 unsigned long   mmr_inj_con:1;                  /* RW */
2221                 unsigned long   rsvd_49_51:3;
2222                 unsigned long   mmr_inj_tlbram:1;               /* RW */
2223                 unsigned long   rsvd_53_63:11;
2224         } s2;
2225         struct uv3h_gr1_tlb_mmr_control_s {
2226                 unsigned long   index:12;                       /* RW */
2227                 unsigned long   mem_sel:2;                      /* RW */
2228                 unsigned long   rsvd_14_15:2;
2229                 unsigned long   auto_valid_en:1;                /* RW */
2230                 unsigned long   rsvd_17_19:3;
2231                 unsigned long   mmr_hash_index_en:1;            /* RW */
2232                 unsigned long   ecc_sel:1;                      /* RW */
2233                 unsigned long   rsvd_22_29:8;
2234                 unsigned long   mmr_write:1;                    /* WP */
2235                 unsigned long   mmr_read:1;                     /* WP */
2236                 unsigned long   mmr_op_done:1;                  /* RW */
2237                 unsigned long   rsvd_33_47:15;
2238                 unsigned long   undef_48:1;                     /* Undefined */
2239                 unsigned long   rsvd_49_51:3;
2240                 unsigned long   undef_52:1;                     /* Undefined */
2241                 unsigned long   rsvd_53_63:11;
2242         } s3;
2243 };
2244
2245 /* ========================================================================= */
2246 /*                       UVH_GR1_TLB_MMR_READ_DATA_HI                        */
2247 /* ========================================================================= */
2248 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
2249 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
2250 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
2251 #define UVH_GR1_TLB_MMR_READ_DATA_HI                                    \
2252                 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI :         \
2253                 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI :         \
2254                                 UV3H_GR1_TLB_MMR_READ_DATA_HI))
2255
2256 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
2257 #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT           41
2258 #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT         43
2259 #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT        44
2260 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK           0x000001ffffffffffUL
2261 #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK           0x0000060000000000UL
2262 #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK         0x0000080000000000UL
2263 #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK        0x0000100000000000UL
2264
2265 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
2266 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
2267 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
2268 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
2269 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
2270 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
2271 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
2272 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
2273
2274 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
2275 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
2276 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
2277 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
2278 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
2279 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
2280 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
2281 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
2282
2283 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
2284 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
2285 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
2286 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
2287 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
2288 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
2289 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
2290 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
2291
2292 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
2293 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
2294 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
2295 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
2296 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       45
2297 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
2298 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
2299 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
2300 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
2301 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
2302 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0000200000000000UL
2303 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
2304
2305 union uvh_gr1_tlb_mmr_read_data_hi_u {
2306         unsigned long   v;
2307         struct uvh_gr1_tlb_mmr_read_data_hi_s {
2308                 unsigned long   pfn:41;                         /* RO */
2309                 unsigned long   gaa:2;                          /* RO */
2310                 unsigned long   dirty:1;                        /* RO */
2311                 unsigned long   larger:1;                       /* RO */
2312                 unsigned long   rsvd_45_63:19;
2313         } s;
2314         struct uv1h_gr1_tlb_mmr_read_data_hi_s {
2315                 unsigned long   pfn:41;                         /* RO */
2316                 unsigned long   gaa:2;                          /* RO */
2317                 unsigned long   dirty:1;                        /* RO */
2318                 unsigned long   larger:1;                       /* RO */
2319                 unsigned long   rsvd_45_63:19;
2320         } s1;
2321         struct uvxh_gr1_tlb_mmr_read_data_hi_s {
2322                 unsigned long   pfn:41;                         /* RO */
2323                 unsigned long   gaa:2;                          /* RO */
2324                 unsigned long   dirty:1;                        /* RO */
2325                 unsigned long   larger:1;                       /* RO */
2326                 unsigned long   rsvd_45_63:19;
2327         } sx;
2328         struct uv2h_gr1_tlb_mmr_read_data_hi_s {
2329                 unsigned long   pfn:41;                         /* RO */
2330                 unsigned long   gaa:2;                          /* RO */
2331                 unsigned long   dirty:1;                        /* RO */
2332                 unsigned long   larger:1;                       /* RO */
2333                 unsigned long   rsvd_45_63:19;
2334         } s2;
2335         struct uv3h_gr1_tlb_mmr_read_data_hi_s {
2336                 unsigned long   pfn:41;                         /* RO */
2337                 unsigned long   gaa:2;                          /* RO */
2338                 unsigned long   dirty:1;                        /* RO */
2339                 unsigned long   larger:1;                       /* RO */
2340                 unsigned long   aa_ext:1;                       /* RO */
2341                 unsigned long   undef_46_54:9;                  /* Undefined */
2342                 unsigned long   way_ecc:9;                      /* RO */
2343         } s3;
2344 };
2345
2346 /* ========================================================================= */
2347 /*                       UVH_GR1_TLB_MMR_READ_DATA_LO                        */
2348 /* ========================================================================= */
2349 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
2350 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
2351 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
2352 #define UVH_GR1_TLB_MMR_READ_DATA_LO                                    \
2353                 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO :         \
2354                 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO :         \
2355                                 UV3H_GR1_TLB_MMR_READ_DATA_LO))
2356
2357 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
2358 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
2359 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT         63
2360 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK           0x0000007fffffffffUL
2361 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK          0x7fffff8000000000UL
2362 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK         0x8000000000000000UL
2363
2364 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
2365 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
2366 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
2367 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
2368 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
2369 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
2370
2371 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
2372 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
2373 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
2374 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
2375 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
2376 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
2377
2378 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
2379 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
2380 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
2381 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
2382 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
2383 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
2384
2385 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
2386 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
2387 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
2388 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
2389 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
2390 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
2391
2392 union uvh_gr1_tlb_mmr_read_data_lo_u {
2393         unsigned long   v;
2394         struct uvh_gr1_tlb_mmr_read_data_lo_s {
2395                 unsigned long   vpn:39;                         /* RO */
2396                 unsigned long   asid:24;                        /* RO */
2397                 unsigned long   valid:1;                        /* RO */
2398         } s;
2399         struct uv1h_gr1_tlb_mmr_read_data_lo_s {
2400                 unsigned long   vpn:39;                         /* RO */
2401                 unsigned long   asid:24;                        /* RO */
2402                 unsigned long   valid:1;                        /* RO */
2403         } s1;
2404         struct uvxh_gr1_tlb_mmr_read_data_lo_s {
2405                 unsigned long   vpn:39;                         /* RO */
2406                 unsigned long   asid:24;                        /* RO */
2407                 unsigned long   valid:1;                        /* RO */
2408         } sx;
2409         struct uv2h_gr1_tlb_mmr_read_data_lo_s {
2410                 unsigned long   vpn:39;                         /* RO */
2411                 unsigned long   asid:24;                        /* RO */
2412                 unsigned long   valid:1;                        /* RO */
2413         } s2;
2414         struct uv3h_gr1_tlb_mmr_read_data_lo_s {
2415                 unsigned long   vpn:39;                         /* RO */
2416                 unsigned long   asid:24;                        /* RO */
2417                 unsigned long   valid:1;                        /* RO */
2418         } s3;
2419 };
2420
2421 /* ========================================================================= */
2422 /*                               UVH_INT_CMPB                                */
2423 /* ========================================================================= */
2424 #define UVH_INT_CMPB 0x22080UL
2425 #define UV1H_INT_CMPB 0x22080UL
2426 #define UV2H_INT_CMPB 0x22080UL
2427 #define UV3H_INT_CMPB 0x22080UL
2428
2429 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT                0
2430 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK                0x00ffffffffffffffUL
2431
2432 #define UV1H_INT_CMPB_REAL_TIME_CMPB_SHFT               0
2433 #define UV1H_INT_CMPB_REAL_TIME_CMPB_MASK               0x00ffffffffffffffUL
2434
2435 #define UVXH_INT_CMPB_REAL_TIME_CMPB_SHFT               0
2436 #define UVXH_INT_CMPB_REAL_TIME_CMPB_MASK               0x00ffffffffffffffUL
2437
2438 #define UV2H_INT_CMPB_REAL_TIME_CMPB_SHFT               0
2439 #define UV2H_INT_CMPB_REAL_TIME_CMPB_MASK               0x00ffffffffffffffUL
2440
2441 #define UV3H_INT_CMPB_REAL_TIME_CMPB_SHFT               0
2442 #define UV3H_INT_CMPB_REAL_TIME_CMPB_MASK               0x00ffffffffffffffUL
2443
2444 union uvh_int_cmpb_u {
2445         unsigned long   v;
2446         struct uvh_int_cmpb_s {
2447                 unsigned long   real_time_cmpb:56;              /* RW */
2448                 unsigned long   rsvd_56_63:8;
2449         } s;
2450         struct uv1h_int_cmpb_s {
2451                 unsigned long   real_time_cmpb:56;              /* RW */
2452                 unsigned long   rsvd_56_63:8;
2453         } s1;
2454         struct uvxh_int_cmpb_s {
2455                 unsigned long   real_time_cmpb:56;              /* RW */
2456                 unsigned long   rsvd_56_63:8;
2457         } sx;
2458         struct uv2h_int_cmpb_s {
2459                 unsigned long   real_time_cmpb:56;              /* RW */
2460                 unsigned long   rsvd_56_63:8;
2461         } s2;
2462         struct uv3h_int_cmpb_s {
2463                 unsigned long   real_time_cmpb:56;              /* RW */
2464                 unsigned long   rsvd_56_63:8;
2465         } s3;
2466 };
2467
2468 /* ========================================================================= */
2469 /*                               UVH_INT_CMPC                                */
2470 /* ========================================================================= */
2471 #define UVH_INT_CMPC 0x22100UL
2472 #define UV1H_INT_CMPC 0x22100UL
2473 #define UV2H_INT_CMPC 0x22100UL
2474 #define UV3H_INT_CMPC 0x22100UL
2475
2476 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT               0
2477 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK               0x00ffffffffffffffUL
2478
2479 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT              0
2480 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK              0x00ffffffffffffffUL
2481
2482 #define UV2H_INT_CMPC_REAL_TIME_CMP_2_SHFT              0
2483 #define UV2H_INT_CMPC_REAL_TIME_CMP_2_MASK              0x00ffffffffffffffUL
2484
2485 #define UV3H_INT_CMPC_REAL_TIME_CMP_2_SHFT              0
2486 #define UV3H_INT_CMPC_REAL_TIME_CMP_2_MASK              0x00ffffffffffffffUL
2487
2488 union uvh_int_cmpc_u {
2489         unsigned long   v;
2490         struct uvh_int_cmpc_s {
2491                 unsigned long   real_time_cmpc:56;              /* RW */
2492                 unsigned long   rsvd_56_63:8;
2493         } s;
2494         struct uv1h_int_cmpc_s {
2495                 unsigned long   real_time_cmpc:56;              /* RW */
2496                 unsigned long   rsvd_56_63:8;
2497         } s1;
2498         struct uvxh_int_cmpc_s {
2499                 unsigned long   real_time_cmpc:56;              /* RW */
2500                 unsigned long   rsvd_56_63:8;
2501         } sx;
2502         struct uv2h_int_cmpc_s {
2503                 unsigned long   real_time_cmpc:56;              /* RW */
2504                 unsigned long   rsvd_56_63:8;
2505         } s2;
2506         struct uv3h_int_cmpc_s {
2507                 unsigned long   real_time_cmpc:56;              /* RW */
2508                 unsigned long   rsvd_56_63:8;
2509         } s3;
2510 };
2511
2512 /* ========================================================================= */
2513 /*                               UVH_INT_CMPD                                */
2514 /* ========================================================================= */
2515 #define UVH_INT_CMPD 0x22180UL
2516 #define UV1H_INT_CMPD 0x22180UL
2517 #define UV2H_INT_CMPD 0x22180UL
2518 #define UV3H_INT_CMPD 0x22180UL
2519
2520 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT               0
2521 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK               0x00ffffffffffffffUL
2522
2523 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT              0
2524 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK              0x00ffffffffffffffUL
2525
2526 #define UV2H_INT_CMPD_REAL_TIME_CMP_3_SHFT              0
2527 #define UV2H_INT_CMPD_REAL_TIME_CMP_3_MASK              0x00ffffffffffffffUL
2528
2529 #define UV3H_INT_CMPD_REAL_TIME_CMP_3_SHFT              0
2530 #define UV3H_INT_CMPD_REAL_TIME_CMP_3_MASK              0x00ffffffffffffffUL
2531
2532 union uvh_int_cmpd_u {
2533         unsigned long   v;
2534         struct uvh_int_cmpd_s {
2535                 unsigned long   real_time_cmpd:56;              /* RW */
2536                 unsigned long   rsvd_56_63:8;
2537         } s;
2538         struct uv1h_int_cmpd_s {
2539                 unsigned long   real_time_cmpd:56;              /* RW */
2540                 unsigned long   rsvd_56_63:8;
2541         } s1;
2542         struct uvxh_int_cmpd_s {
2543                 unsigned long   real_time_cmpd:56;              /* RW */
2544                 unsigned long   rsvd_56_63:8;
2545         } sx;
2546         struct uv2h_int_cmpd_s {
2547                 unsigned long   real_time_cmpd:56;              /* RW */
2548                 unsigned long   rsvd_56_63:8;
2549         } s2;
2550         struct uv3h_int_cmpd_s {
2551                 unsigned long   real_time_cmpd:56;              /* RW */
2552                 unsigned long   rsvd_56_63:8;
2553         } s3;
2554 };
2555
2556 /* ========================================================================= */
2557 /*                               UVH_IPI_INT                                 */
2558 /* ========================================================================= */
2559 #define UVH_IPI_INT 0x60500UL
2560 #define UV1H_IPI_INT 0x60500UL
2561 #define UV2H_IPI_INT 0x60500UL
2562 #define UV3H_IPI_INT 0x60500UL
2563 #define UVH_IPI_INT_32 0x348
2564 #define UV1H_IPI_INT_32 0x60500UL
2565 #define UV2H_IPI_INT_32 0x60500UL
2566 #define UV3H_IPI_INT_32 0x60500UL
2567
2568 #define UVH_IPI_INT_VECTOR_SHFT                         0
2569 #define UVH_IPI_INT_DELIVERY_MODE_SHFT                  8
2570 #define UVH_IPI_INT_DESTMODE_SHFT                       11
2571 #define UVH_IPI_INT_APIC_ID_SHFT                        16
2572 #define UVH_IPI_INT_SEND_SHFT                           63
2573 #define UVH_IPI_INT_VECTOR_MASK                         0x00000000000000ffUL
2574 #define UVH_IPI_INT_DELIVERY_MODE_MASK                  0x0000000000000700UL
2575 #define UVH_IPI_INT_DESTMODE_MASK                       0x0000000000000800UL
2576 #define UVH_IPI_INT_APIC_ID_MASK                        0x0000ffffffff0000UL
2577 #define UVH_IPI_INT_SEND_MASK                           0x8000000000000000UL
2578
2579 #define UV1H_IPI_INT_VECTOR_SHFT                        0
2580 #define UV1H_IPI_INT_DELIVERY_MODE_SHFT                 8
2581 #define UV1H_IPI_INT_DESTMODE_SHFT                      11
2582 #define UV1H_IPI_INT_APIC_ID_SHFT                       16
2583 #define UV1H_IPI_INT_SEND_SHFT                          63
2584 #define UV1H_IPI_INT_VECTOR_MASK                        0x00000000000000ffUL
2585 #define UV1H_IPI_INT_DELIVERY_MODE_MASK                 0x0000000000000700UL
2586 #define UV1H_IPI_INT_DESTMODE_MASK                      0x0000000000000800UL
2587 #define UV1H_IPI_INT_APIC_ID_MASK                       0x0000ffffffff0000UL
2588 #define UV1H_IPI_INT_SEND_MASK                          0x8000000000000000UL
2589
2590 #define UVXH_IPI_INT_VECTOR_SHFT                        0
2591 #define UVXH_IPI_INT_DELIVERY_MODE_SHFT                 8
2592 #define UVXH_IPI_INT_DESTMODE_SHFT                      11
2593 #define UVXH_IPI_INT_APIC_ID_SHFT                       16
2594 #define UVXH_IPI_INT_SEND_SHFT                          63
2595 #define UVXH_IPI_INT_VECTOR_MASK                        0x00000000000000ffUL
2596 #define UVXH_IPI_INT_DELIVERY_MODE_MASK                 0x0000000000000700UL
2597 #define UVXH_IPI_INT_DESTMODE_MASK                      0x0000000000000800UL
2598 #define UVXH_IPI_INT_APIC_ID_MASK                       0x0000ffffffff0000UL
2599 #define UVXH_IPI_INT_SEND_MASK                          0x8000000000000000UL
2600
2601 #define UV2H_IPI_INT_VECTOR_SHFT                        0
2602 #define UV2H_IPI_INT_DELIVERY_MODE_SHFT                 8
2603 #define UV2H_IPI_INT_DESTMODE_SHFT                      11
2604 #define UV2H_IPI_INT_APIC_ID_SHFT                       16
2605 #define UV2H_IPI_INT_SEND_SHFT                          63
2606 #define UV2H_IPI_INT_VECTOR_MASK                        0x00000000000000ffUL
2607 #define UV2H_IPI_INT_DELIVERY_MODE_MASK                 0x0000000000000700UL
2608 #define UV2H_IPI_INT_DESTMODE_MASK                      0x0000000000000800UL
2609 #define UV2H_IPI_INT_APIC_ID_MASK                       0x0000ffffffff0000UL
2610 #define UV2H_IPI_INT_SEND_MASK                          0x8000000000000000UL
2611
2612 #define UV3H_IPI_INT_VECTOR_SHFT                        0
2613 #define UV3H_IPI_INT_DELIVERY_MODE_SHFT                 8
2614 #define UV3H_IPI_INT_DESTMODE_SHFT                      11
2615 #define UV3H_IPI_INT_APIC_ID_SHFT                       16
2616 #define UV3H_IPI_INT_SEND_SHFT                          63
2617 #define UV3H_IPI_INT_VECTOR_MASK                        0x00000000000000ffUL
2618 #define UV3H_IPI_INT_DELIVERY_MODE_MASK                 0x0000000000000700UL
2619 #define UV3H_IPI_INT_DESTMODE_MASK                      0x0000000000000800UL
2620 #define UV3H_IPI_INT_APIC_ID_MASK                       0x0000ffffffff0000UL
2621 #define UV3H_IPI_INT_SEND_MASK                          0x8000000000000000UL
2622
2623 union uvh_ipi_int_u {
2624         unsigned long   v;
2625         struct uvh_ipi_int_s {
2626                 unsigned long   vector_:8;                      /* RW */
2627                 unsigned long   delivery_mode:3;                /* RW */
2628                 unsigned long   destmode:1;                     /* RW */
2629                 unsigned long   rsvd_12_15:4;
2630                 unsigned long   apic_id:32;                     /* RW */
2631                 unsigned long   rsvd_48_62:15;
2632                 unsigned long   send:1;                         /* WP */
2633         } s;
2634         struct uv1h_ipi_int_s {
2635                 unsigned long   vector_:8;                      /* RW */
2636                 unsigned long   delivery_mode:3;                /* RW */
2637                 unsigned long   destmode:1;                     /* RW */
2638                 unsigned long   rsvd_12_15:4;
2639                 unsigned long   apic_id:32;                     /* RW */
2640                 unsigned long   rsvd_48_62:15;
2641                 unsigned long   send:1;                         /* WP */
2642         } s1;
2643         struct uvxh_ipi_int_s {
2644                 unsigned long   vector_:8;                      /* RW */
2645                 unsigned long   delivery_mode:3;                /* RW */
2646                 unsigned long   destmode:1;                     /* RW */
2647                 unsigned long   rsvd_12_15:4;
2648                 unsigned long   apic_id:32;                     /* RW */
2649                 unsigned long   rsvd_48_62:15;
2650                 unsigned long   send:1;                         /* WP */
2651         } sx;
2652         struct uv2h_ipi_int_s {
2653                 unsigned long   vector_:8;                      /* RW */
2654                 unsigned long   delivery_mode:3;                /* RW */
2655                 unsigned long   destmode:1;                     /* RW */
2656                 unsigned long   rsvd_12_15:4;
2657                 unsigned long   apic_id:32;                     /* RW */
2658                 unsigned long   rsvd_48_62:15;
2659                 unsigned long   send:1;                         /* WP */
2660         } s2;
2661         struct uv3h_ipi_int_s {
2662                 unsigned long   vector_:8;                      /* RW */
2663                 unsigned long   delivery_mode:3;                /* RW */
2664                 unsigned long   destmode:1;                     /* RW */
2665                 unsigned long   rsvd_12_15:4;
2666                 unsigned long   apic_id:32;                     /* RW */
2667                 unsigned long   rsvd_48_62:15;
2668                 unsigned long   send:1;                         /* WP */
2669         } s3;
2670 };
2671
2672 /* ========================================================================= */
2673 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
2674 /* ========================================================================= */
2675 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
2676 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
2677 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
2678 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
2679 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
2680 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL
2681 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL
2682 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL
2683
2684 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2685 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2686 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2687 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2688
2689 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2690 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2691 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2692 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2693
2694 #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2695 #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2696 #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2697 #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2698
2699 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2700 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2701 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2702 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2703
2704 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2705 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2706 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2707 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2708
2709 union uvh_lb_bau_intd_payload_queue_first_u {
2710         unsigned long   v;
2711         struct uvh_lb_bau_intd_payload_queue_first_s {
2712                 unsigned long   rsvd_0_3:4;
2713                 unsigned long   address:39;                     /* RW */
2714                 unsigned long   rsvd_43_48:6;
2715                 unsigned long   node_id:14;                     /* RW */
2716                 unsigned long   rsvd_63:1;
2717         } s;
2718         struct uv1h_lb_bau_intd_payload_queue_first_s {
2719                 unsigned long   rsvd_0_3:4;
2720                 unsigned long   address:39;                     /* RW */
2721                 unsigned long   rsvd_43_48:6;
2722                 unsigned long   node_id:14;                     /* RW */
2723                 unsigned long   rsvd_63:1;
2724         } s1;
2725         struct uvxh_lb_bau_intd_payload_queue_first_s {
2726                 unsigned long   rsvd_0_3:4;
2727                 unsigned long   address:39;                     /* RW */
2728                 unsigned long   rsvd_43_48:6;
2729                 unsigned long   node_id:14;                     /* RW */
2730                 unsigned long   rsvd_63:1;
2731         } sx;
2732         struct uv2h_lb_bau_intd_payload_queue_first_s {
2733                 unsigned long   rsvd_0_3:4;
2734                 unsigned long   address:39;                     /* RW */
2735                 unsigned long   rsvd_43_48:6;
2736                 unsigned long   node_id:14;                     /* RW */
2737                 unsigned long   rsvd_63:1;
2738         } s2;
2739         struct uv3h_lb_bau_intd_payload_queue_first_s {
2740                 unsigned long   rsvd_0_3:4;
2741                 unsigned long   address:39;                     /* RW */
2742                 unsigned long   rsvd_43_48:6;
2743                 unsigned long   node_id:14;                     /* RW */
2744                 unsigned long   rsvd_63:1;
2745         } s3;
2746 };
2747
2748 /* ========================================================================= */
2749 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
2750 /* ========================================================================= */
2751 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
2752 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
2753 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
2754 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
2755 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
2756 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL
2757 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL
2758 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL
2759
2760 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2761 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2762
2763 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2764 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2765
2766 #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2767 #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2768
2769 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2770 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2771
2772 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2773 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2774
2775 union uvh_lb_bau_intd_payload_queue_last_u {
2776         unsigned long   v;
2777         struct uvh_lb_bau_intd_payload_queue_last_s {
2778                 unsigned long   rsvd_0_3:4;
2779                 unsigned long   address:39;                     /* RW */
2780                 unsigned long   rsvd_43_63:21;
2781         } s;
2782         struct uv1h_lb_bau_intd_payload_queue_last_s {
2783                 unsigned long   rsvd_0_3:4;
2784                 unsigned long   address:39;                     /* RW */
2785                 unsigned long   rsvd_43_63:21;
2786         } s1;
2787         struct uvxh_lb_bau_intd_payload_queue_last_s {
2788                 unsigned long   rsvd_0_3:4;
2789                 unsigned long   address:39;                     /* RW */
2790                 unsigned long   rsvd_43_63:21;
2791         } sx;
2792         struct uv2h_lb_bau_intd_payload_queue_last_s {
2793                 unsigned long   rsvd_0_3:4;
2794                 unsigned long   address:39;                     /* RW */
2795                 unsigned long   rsvd_43_63:21;
2796         } s2;
2797         struct uv3h_lb_bau_intd_payload_queue_last_s {
2798                 unsigned long   rsvd_0_3:4;
2799                 unsigned long   address:39;                     /* RW */
2800                 unsigned long   rsvd_43_63:21;
2801         } s3;
2802 };
2803
2804 /* ========================================================================= */
2805 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
2806 /* ========================================================================= */
2807 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
2808 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
2809 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
2810 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
2811 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
2812 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL
2813 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL
2814 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL
2815
2816 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2817 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2818
2819 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2820 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2821
2822 #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2823 #define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2824
2825 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2826 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2827
2828 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2829 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2830
2831 union uvh_lb_bau_intd_payload_queue_tail_u {
2832         unsigned long   v;
2833         struct uvh_lb_bau_intd_payload_queue_tail_s {
2834                 unsigned long   rsvd_0_3:4;
2835                 unsigned long   address:39;                     /* RW */
2836                 unsigned long   rsvd_43_63:21;
2837         } s;
2838         struct uv1h_lb_bau_intd_payload_queue_tail_s {
2839                 unsigned long   rsvd_0_3:4;
2840                 unsigned long   address:39;                     /* RW */
2841                 unsigned long   rsvd_43_63:21;
2842         } s1;
2843         struct uvxh_lb_bau_intd_payload_queue_tail_s {
2844                 unsigned long   rsvd_0_3:4;
2845                 unsigned long   address:39;                     /* RW */
2846                 unsigned long   rsvd_43_63:21;
2847         } sx;
2848         struct uv2h_lb_bau_intd_payload_queue_tail_s {
2849                 unsigned long   rsvd_0_3:4;
2850                 unsigned long   address:39;                     /* RW */
2851                 unsigned long   rsvd_43_63:21;
2852         } s2;
2853         struct uv3h_lb_bau_intd_payload_queue_tail_s {
2854                 unsigned long   rsvd_0_3:4;
2855                 unsigned long   address:39;                     /* RW */
2856                 unsigned long   rsvd_43_63:21;
2857         } s3;
2858 };
2859
2860 /* ========================================================================= */
2861 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
2862 /* ========================================================================= */
2863 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2864 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2865 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2866 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2867 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
2868 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL
2869 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL
2870 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL
2871
2872 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2873 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2874 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2875 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2876 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2877 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2878 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2879 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2880 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2881 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2882 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2883 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2884 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2885 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2886 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2887 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2888 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2889 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2890 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2891 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2892 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2893 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2894 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2895 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2896 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2897 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2898 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2899 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2900 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2901 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2902 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2903 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2904
2905 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2906 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2907 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2908 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2909 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2910 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2911 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2912 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2913 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2914 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2915 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2916 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2917 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2918 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2919 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2920 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2921 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2922 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2923 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2924 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2925 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2926 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2927 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2928 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2929 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2930 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2931 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2932 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2933 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2934 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2935 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2936 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2937
2938 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2939 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2940 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2941 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2942 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2943 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2944 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2945 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2946 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2947 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2948 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2949 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2950 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2951 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2952 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2953 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2954 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2955 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2956 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2957 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2958 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2959 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2960 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2961 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2962 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2963 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2964 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2965 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2966 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2967 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2968 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2969 #define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2970
2971 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2972 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2973 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2974 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2975 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2976 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2977 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2978 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2979 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2980 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2981 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2982 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2983 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2984 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2985 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2986 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2987 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2988 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2989 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2990 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2991 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2992 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2993 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2994 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2995 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2996 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2997 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2998 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2999 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
3000 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
3001 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
3002 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
3003
3004 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
3005 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
3006 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
3007 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
3008 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
3009 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
3010 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
3011 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
3012 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
3013 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
3014 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
3015 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
3016 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
3017 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
3018 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
3019 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
3020 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
3021 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
3022 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
3023 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
3024 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
3025 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
3026 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
3027 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
3028 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
3029 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
3030 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
3031 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
3032 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
3033 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
3034 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
3035 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
3036
3037 union uvh_lb_bau_intd_software_acknowledge_u {
3038         unsigned long   v;
3039         struct uvh_lb_bau_intd_software_acknowledge_s {
3040                 unsigned long   pending_0:1;                    /* RW, W1C */
3041                 unsigned long   pending_1:1;                    /* RW, W1C */
3042                 unsigned long   pending_2:1;                    /* RW, W1C */
3043                 unsigned long   pending_3:1;                    /* RW, W1C */
3044                 unsigned long   pending_4:1;                    /* RW, W1C */
3045                 unsigned long   pending_5:1;                    /* RW, W1C */
3046                 unsigned long   pending_6:1;                    /* RW, W1C */
3047                 unsigned long   pending_7:1;                    /* RW, W1C */
3048                 unsigned long   timeout_0:1;                    /* RW, W1C */
3049                 unsigned long   timeout_1:1;                    /* RW, W1C */
3050                 unsigned long   timeout_2:1;                    /* RW, W1C */
3051                 unsigned long   timeout_3:1;                    /* RW, W1C */
3052                 unsigned long   timeout_4:1;                    /* RW, W1C */
3053                 unsigned long   timeout_5:1;                    /* RW, W1C */
3054                 unsigned long   timeout_6:1;                    /* RW, W1C */
3055                 unsigned long   timeout_7:1;                    /* RW, W1C */
3056                 unsigned long   rsvd_16_63:48;
3057         } s;
3058         struct uv1h_lb_bau_intd_software_acknowledge_s {
3059                 unsigned long   pending_0:1;                    /* RW, W1C */
3060                 unsigned long   pending_1:1;                    /* RW, W1C */
3061                 unsigned long   pending_2:1;                    /* RW, W1C */
3062                 unsigned long   pending_3:1;                    /* RW, W1C */
3063                 unsigned long   pending_4:1;                    /* RW, W1C */
3064                 unsigned long   pending_5:1;                    /* RW, W1C */
3065                 unsigned long   pending_6:1;                    /* RW, W1C */
3066                 unsigned long   pending_7:1;                    /* RW, W1C */
3067                 unsigned long   timeout_0:1;                    /* RW, W1C */
3068                 unsigned long   timeout_1:1;                    /* RW, W1C */
3069                 unsigned long   timeout_2:1;                    /* RW, W1C */
3070                 unsigned long   timeout_3:1;                    /* RW, W1C */
3071                 unsigned long   timeout_4:1;                    /* RW, W1C */
3072                 unsigned long   timeout_5:1;                    /* RW, W1C */
3073                 unsigned long   timeout_6:1;                    /* RW, W1C */
3074                 unsigned long   timeout_7:1;                    /* RW, W1C */
3075                 unsigned long   rsvd_16_63:48;
3076         } s1;
3077         struct uvxh_lb_bau_intd_software_acknowledge_s {
3078                 unsigned long   pending_0:1;                    /* RW */
3079                 unsigned long   pending_1:1;                    /* RW */
3080                 unsigned long   pending_2:1;                    /* RW */
3081                 unsigned long   pending_3:1;                    /* RW */
3082                 unsigned long   pending_4:1;                    /* RW */
3083                 unsigned long   pending_5:1;                    /* RW */
3084                 unsigned long   pending_6:1;                    /* RW */
3085                 unsigned long   pending_7:1;                    /* RW */
3086                 unsigned long   timeout_0:1;                    /* RW */
3087                 unsigned long   timeout_1:1;                    /* RW */
3088                 unsigned long   timeout_2:1;                    /* RW */
3089                 unsigned long   timeout_3:1;                    /* RW */
3090                 unsigned long   timeout_4:1;                    /* RW */
3091                 unsigned long   timeout_5:1;                    /* RW */
3092                 unsigned long   timeout_6:1;                    /* RW */
3093                 unsigned long   timeout_7:1;                    /* RW */
3094                 unsigned long   rsvd_16_63:48;
3095         } sx;
3096         struct uv2h_lb_bau_intd_software_acknowledge_s {
3097                 unsigned long   pending_0:1;                    /* RW */
3098                 unsigned long   pending_1:1;                    /* RW */
3099                 unsigned long   pending_2:1;                    /* RW */