x86/apic: Add separate apic_id_valid() functions for selected apic drivers
[~shefty/rdma-dev.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV APIC functions (note: not an Intel compatible APIC)
7  *
8  * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
9  */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28
29 #include <asm/uv/uv_mmrs.h>
30 #include <asm/uv/uv_hub.h>
31 #include <asm/current.h>
32 #include <asm/pgtable.h>
33 #include <asm/uv/bios.h>
34 #include <asm/uv/uv.h>
35 #include <asm/apic.h>
36 #include <asm/ipi.h>
37 #include <asm/smp.h>
38 #include <asm/x86_init.h>
39 #include <asm/emergency-restart.h>
40 #include <asm/nmi.h>
41
42 /* BMC sets a bit this MMR non-zero before sending an NMI */
43 #define UVH_NMI_MMR                             UVH_SCRATCH5
44 #define UVH_NMI_MMR_CLEAR                       (UVH_NMI_MMR + 8)
45 #define UV_NMI_PENDING_MASK                     (1UL << 63)
46 DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
47
48 DEFINE_PER_CPU(int, x2apic_extra_bits);
49
50 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
51
52 static enum uv_system_type uv_system_type;
53 static u64 gru_start_paddr, gru_end_paddr;
54 static union uvh_apicid uvh_apicid;
55 int uv_min_hub_revision_id;
56 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
57 unsigned int uv_apicid_hibits;
58 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
59 static DEFINE_SPINLOCK(uv_nmi_lock);
60
61 static struct apic apic_x2apic_uv_x;
62
63 static unsigned long __init uv_early_read_mmr(unsigned long addr)
64 {
65         unsigned long val, *mmr;
66
67         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
68         val = *mmr;
69         early_iounmap(mmr, sizeof(*mmr));
70         return val;
71 }
72
73 static inline bool is_GRU_range(u64 start, u64 end)
74 {
75         return start >= gru_start_paddr && end <= gru_end_paddr;
76 }
77
78 static bool uv_is_untracked_pat_range(u64 start, u64 end)
79 {
80         return is_ISA_range(start, end) || is_GRU_range(start, end);
81 }
82
83 static int __init early_get_pnodeid(void)
84 {
85         union uvh_node_id_u node_id;
86         union uvh_rh_gam_config_mmr_u  m_n_config;
87         int pnode;
88
89         /* Currently, all blades have same revision number */
90         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
91         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
92         uv_min_hub_revision_id = node_id.s.revision;
93
94         if (node_id.s.part_number == UV2_HUB_PART_NUMBER)
95                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
96         if (node_id.s.part_number == UV2_HUB_PART_NUMBER_X)
97                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
98
99         uv_hub_info->hub_revision = uv_min_hub_revision_id;
100         pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
101         return pnode;
102 }
103
104 static void __init early_get_apic_pnode_shift(void)
105 {
106         uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
107         if (!uvh_apicid.v)
108                 /*
109                  * Old bios, use default value
110                  */
111                 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
112 }
113
114 /*
115  * Add an extra bit as dictated by bios to the destination apicid of
116  * interrupts potentially passing through the UV HUB.  This prevents
117  * a deadlock between interrupts and IO port operations.
118  */
119 static void __init uv_set_apicid_hibit(void)
120 {
121         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
122
123         if (is_uv1_hub()) {
124                 apicid_mask.v =
125                         uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
126                 uv_apicid_hibits =
127                         apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
128         }
129 }
130
131 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
132 {
133         int pnodeid, is_uv1, is_uv2;
134
135         is_uv1 = !strcmp(oem_id, "SGI");
136         is_uv2 = !strcmp(oem_id, "SGI2");
137         if (is_uv1 || is_uv2) {
138                 uv_hub_info->hub_revision =
139                         is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE;
140                 pnodeid = early_get_pnodeid();
141                 early_get_apic_pnode_shift();
142                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
143                 x86_platform.nmi_init = uv_nmi_init;
144                 if (!strcmp(oem_table_id, "UVL"))
145                         uv_system_type = UV_LEGACY_APIC;
146                 else if (!strcmp(oem_table_id, "UVX"))
147                         uv_system_type = UV_X2APIC;
148                 else if (!strcmp(oem_table_id, "UVH")) {
149                         __this_cpu_write(x2apic_extra_bits,
150                                 pnodeid << uvh_apicid.s.pnode_shift);
151                         uv_system_type = UV_NON_UNIQUE_APIC;
152                         uv_set_apicid_hibit();
153                         return 1;
154                 }
155         }
156         return 0;
157 }
158
159 enum uv_system_type get_uv_system_type(void)
160 {
161         return uv_system_type;
162 }
163
164 int is_uv_system(void)
165 {
166         return uv_system_type != UV_NONE;
167 }
168 EXPORT_SYMBOL_GPL(is_uv_system);
169
170 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
171 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
172
173 struct uv_blade_info *uv_blade_info;
174 EXPORT_SYMBOL_GPL(uv_blade_info);
175
176 short *uv_node_to_blade;
177 EXPORT_SYMBOL_GPL(uv_node_to_blade);
178
179 short *uv_cpu_to_blade;
180 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
181
182 short uv_possible_blades;
183 EXPORT_SYMBOL_GPL(uv_possible_blades);
184
185 unsigned long sn_rtc_cycles_per_second;
186 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
187
188 static const struct cpumask *uv_target_cpus(void)
189 {
190         return cpu_online_mask;
191 }
192
193 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
194 {
195         cpumask_clear(retmask);
196         cpumask_set_cpu(cpu, retmask);
197 }
198
199 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
200 {
201 #ifdef CONFIG_SMP
202         unsigned long val;
203         int pnode;
204
205         pnode = uv_apicid_to_pnode(phys_apicid);
206         phys_apicid |= uv_apicid_hibits;
207         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
208             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
209             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
210             APIC_DM_INIT;
211         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
212
213         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
214             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
215             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
216             APIC_DM_STARTUP;
217         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
218
219         atomic_set(&init_deasserted, 1);
220 #endif
221         return 0;
222 }
223
224 static void uv_send_IPI_one(int cpu, int vector)
225 {
226         unsigned long apicid;
227         int pnode;
228
229         apicid = per_cpu(x86_cpu_to_apicid, cpu);
230         pnode = uv_apicid_to_pnode(apicid);
231         uv_hub_send_ipi(pnode, apicid, vector);
232 }
233
234 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
235 {
236         unsigned int cpu;
237
238         for_each_cpu(cpu, mask)
239                 uv_send_IPI_one(cpu, vector);
240 }
241
242 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
243 {
244         unsigned int this_cpu = smp_processor_id();
245         unsigned int cpu;
246
247         for_each_cpu(cpu, mask) {
248                 if (cpu != this_cpu)
249                         uv_send_IPI_one(cpu, vector);
250         }
251 }
252
253 static void uv_send_IPI_allbutself(int vector)
254 {
255         unsigned int this_cpu = smp_processor_id();
256         unsigned int cpu;
257
258         for_each_online_cpu(cpu) {
259                 if (cpu != this_cpu)
260                         uv_send_IPI_one(cpu, vector);
261         }
262 }
263
264 static void uv_send_IPI_all(int vector)
265 {
266         uv_send_IPI_mask(cpu_online_mask, vector);
267 }
268
269 static int uv_apic_id_valid(int apicid)
270 {
271         return 1;
272 }
273
274 static int uv_apic_id_registered(void)
275 {
276         return 1;
277 }
278
279 static void uv_init_apic_ldr(void)
280 {
281 }
282
283 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
284 {
285         /*
286          * We're using fixed IRQ delivery, can only return one phys APIC ID.
287          * May as well be the first.
288          */
289         int cpu = cpumask_first(cpumask);
290
291         if ((unsigned)cpu < nr_cpu_ids)
292                 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
293         else
294                 return BAD_APICID;
295 }
296
297 static unsigned int
298 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
299                           const struct cpumask *andmask)
300 {
301         int cpu;
302
303         /*
304          * We're using fixed IRQ delivery, can only return one phys APIC ID.
305          * May as well be the first.
306          */
307         for_each_cpu_and(cpu, cpumask, andmask) {
308                 if (cpumask_test_cpu(cpu, cpu_online_mask))
309                         break;
310         }
311         return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
312 }
313
314 static unsigned int x2apic_get_apic_id(unsigned long x)
315 {
316         unsigned int id;
317
318         WARN_ON(preemptible() && num_online_cpus() > 1);
319         id = x | __this_cpu_read(x2apic_extra_bits);
320
321         return id;
322 }
323
324 static unsigned long set_apic_id(unsigned int id)
325 {
326         unsigned long x;
327
328         /* maskout x2apic_extra_bits ? */
329         x = id;
330         return x;
331 }
332
333 static unsigned int uv_read_apic_id(void)
334 {
335
336         return x2apic_get_apic_id(apic_read(APIC_ID));
337 }
338
339 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
340 {
341         return uv_read_apic_id() >> index_msb;
342 }
343
344 static void uv_send_IPI_self(int vector)
345 {
346         apic_write(APIC_SELF_IPI, vector);
347 }
348
349 static int uv_probe(void)
350 {
351         return apic == &apic_x2apic_uv_x;
352 }
353
354 static struct apic __refdata apic_x2apic_uv_x = {
355
356         .name                           = "UV large system",
357         .probe                          = uv_probe,
358         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
359         .apic_id_valid                  = uv_apic_id_valid,
360         .apic_id_registered             = uv_apic_id_registered,
361
362         .irq_delivery_mode              = dest_Fixed,
363         .irq_dest_mode                  = 0, /* physical */
364
365         .target_cpus                    = uv_target_cpus,
366         .disable_esr                    = 0,
367         .dest_logical                   = APIC_DEST_LOGICAL,
368         .check_apicid_used              = NULL,
369         .check_apicid_present           = NULL,
370
371         .vector_allocation_domain       = uv_vector_allocation_domain,
372         .init_apic_ldr                  = uv_init_apic_ldr,
373
374         .ioapic_phys_id_map             = NULL,
375         .setup_apic_routing             = NULL,
376         .multi_timer_check              = NULL,
377         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
378         .apicid_to_cpu_present          = NULL,
379         .setup_portio_remap             = NULL,
380         .check_phys_apicid_present      = default_check_phys_apicid_present,
381         .enable_apic_mode               = NULL,
382         .phys_pkg_id                    = uv_phys_pkg_id,
383         .mps_oem_check                  = NULL,
384
385         .get_apic_id                    = x2apic_get_apic_id,
386         .set_apic_id                    = set_apic_id,
387         .apic_id_mask                   = 0xFFFFFFFFu,
388
389         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
390         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
391
392         .send_IPI_mask                  = uv_send_IPI_mask,
393         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
394         .send_IPI_allbutself            = uv_send_IPI_allbutself,
395         .send_IPI_all                   = uv_send_IPI_all,
396         .send_IPI_self                  = uv_send_IPI_self,
397
398         .wakeup_secondary_cpu           = uv_wakeup_secondary,
399         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
400         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
401         .wait_for_init_deassert         = NULL,
402         .smp_callin_clear_local_apic    = NULL,
403         .inquire_remote_apic            = NULL,
404
405         .read                           = native_apic_msr_read,
406         .write                          = native_apic_msr_write,
407         .icr_read                       = native_x2apic_icr_read,
408         .icr_write                      = native_x2apic_icr_write,
409         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
410         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
411 };
412
413 static __cpuinit void set_x2apic_extra_bits(int pnode)
414 {
415         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
416 }
417
418 /*
419  * Called on boot cpu.
420  */
421 static __init int boot_pnode_to_blade(int pnode)
422 {
423         int blade;
424
425         for (blade = 0; blade < uv_num_possible_blades(); blade++)
426                 if (pnode == uv_blade_info[blade].pnode)
427                         return blade;
428         BUG();
429 }
430
431 struct redir_addr {
432         unsigned long redirect;
433         unsigned long alias;
434 };
435
436 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
437
438 static __initdata struct redir_addr redir_addrs[] = {
439         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
440         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
441         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
442 };
443
444 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
445 {
446         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
447         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
448         int i;
449
450         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
451                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
452                 if (alias.s.enable && alias.s.base == 0) {
453                         *size = (1UL << alias.s.m_alias);
454                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
455                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
456                         return;
457                 }
458         }
459         *base = *size = 0;
460 }
461
462 enum map_type {map_wb, map_uc};
463
464 static __init void map_high(char *id, unsigned long base, int pshift,
465                         int bshift, int max_pnode, enum map_type map_type)
466 {
467         unsigned long bytes, paddr;
468
469         paddr = base << pshift;
470         bytes = (1UL << bshift) * (max_pnode + 1);
471         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
472                                                 paddr + bytes);
473         if (map_type == map_uc)
474                 init_extra_mapping_uc(paddr, bytes);
475         else
476                 init_extra_mapping_wb(paddr, bytes);
477
478 }
479 static __init void map_gru_high(int max_pnode)
480 {
481         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
482         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
483
484         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
485         if (gru.s.enable) {
486                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
487                 gru_start_paddr = ((u64)gru.s.base << shift);
488                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
489
490         }
491 }
492
493 static __init void map_mmr_high(int max_pnode)
494 {
495         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
496         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
497
498         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
499         if (mmr.s.enable)
500                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
501 }
502
503 static __init void map_mmioh_high(int max_pnode)
504 {
505         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
506         int shift;
507
508         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
509         if (is_uv1_hub() && mmioh.s1.enable) {
510                 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
511                 map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io,
512                         max_pnode, map_uc);
513         }
514         if (is_uv2_hub() && mmioh.s2.enable) {
515                 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
516                 map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io,
517                         max_pnode, map_uc);
518         }
519 }
520
521 static __init void map_low_mmrs(void)
522 {
523         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
524         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
525 }
526
527 static __init void uv_rtc_init(void)
528 {
529         long status;
530         u64 ticks_per_sec;
531
532         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
533                                         &ticks_per_sec);
534         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
535                 printk(KERN_WARNING
536                         "unable to determine platform RTC clock frequency, "
537                         "guessing.\n");
538                 /* BIOS gives wrong value for clock freq. so guess */
539                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
540         } else
541                 sn_rtc_cycles_per_second = ticks_per_sec;
542 }
543
544 /*
545  * percpu heartbeat timer
546  */
547 static void uv_heartbeat(unsigned long ignored)
548 {
549         struct timer_list *timer = &uv_hub_info->scir.timer;
550         unsigned char bits = uv_hub_info->scir.state;
551
552         /* flip heartbeat bit */
553         bits ^= SCIR_CPU_HEARTBEAT;
554
555         /* is this cpu idle? */
556         if (idle_cpu(raw_smp_processor_id()))
557                 bits &= ~SCIR_CPU_ACTIVITY;
558         else
559                 bits |= SCIR_CPU_ACTIVITY;
560
561         /* update system controller interface reg */
562         uv_set_scir_bits(bits);
563
564         /* enable next timer period */
565         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
566 }
567
568 static void __cpuinit uv_heartbeat_enable(int cpu)
569 {
570         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
571                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
572
573                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
574                 setup_timer(timer, uv_heartbeat, cpu);
575                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
576                 add_timer_on(timer, cpu);
577                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
578
579                 /* also ensure that boot cpu is enabled */
580                 cpu = 0;
581         }
582 }
583
584 #ifdef CONFIG_HOTPLUG_CPU
585 static void __cpuinit uv_heartbeat_disable(int cpu)
586 {
587         if (uv_cpu_hub_info(cpu)->scir.enabled) {
588                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
589                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
590         }
591         uv_set_cpu_scir_bits(cpu, 0xff);
592 }
593
594 /*
595  * cpu hotplug notifier
596  */
597 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
598                                        unsigned long action, void *hcpu)
599 {
600         long cpu = (long)hcpu;
601
602         switch (action) {
603         case CPU_ONLINE:
604                 uv_heartbeat_enable(cpu);
605                 break;
606         case CPU_DOWN_PREPARE:
607                 uv_heartbeat_disable(cpu);
608                 break;
609         default:
610                 break;
611         }
612         return NOTIFY_OK;
613 }
614
615 static __init void uv_scir_register_cpu_notifier(void)
616 {
617         hotcpu_notifier(uv_scir_cpu_notify, 0);
618 }
619
620 #else /* !CONFIG_HOTPLUG_CPU */
621
622 static __init void uv_scir_register_cpu_notifier(void)
623 {
624 }
625
626 static __init int uv_init_heartbeat(void)
627 {
628         int cpu;
629
630         if (is_uv_system())
631                 for_each_online_cpu(cpu)
632                         uv_heartbeat_enable(cpu);
633         return 0;
634 }
635
636 late_initcall(uv_init_heartbeat);
637
638 #endif /* !CONFIG_HOTPLUG_CPU */
639
640 /* Direct Legacy VGA I/O traffic to designated IOH */
641 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
642                       unsigned int command_bits, u32 flags)
643 {
644         int domain, bus, rc;
645
646         PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
647                         pdev->devfn, decode, command_bits, flags);
648
649         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
650                 return 0;
651
652         if ((command_bits & PCI_COMMAND_IO) == 0)
653                 return 0;
654
655         domain = pci_domain_nr(pdev->bus);
656         bus = pdev->bus->number;
657
658         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
659         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
660
661         return rc;
662 }
663
664 /*
665  * Called on each cpu to initialize the per_cpu UV data area.
666  * FIXME: hotplug not supported yet
667  */
668 void __cpuinit uv_cpu_init(void)
669 {
670         /* CPU 0 initilization will be done via uv_system_init. */
671         if (!uv_blade_info)
672                 return;
673
674         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
675
676         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
677                 set_x2apic_extra_bits(uv_hub_info->pnode);
678 }
679
680 /*
681  * When NMI is received, print a stack trace.
682  */
683 int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
684 {
685         unsigned long real_uv_nmi;
686         int bid;
687
688         /*
689          * Each blade has an MMR that indicates when an NMI has been sent
690          * to cpus on the blade. If an NMI is detected, atomically
691          * clear the MMR and update a per-blade NMI count used to
692          * cause each cpu on the blade to notice a new NMI.
693          */
694         bid = uv_numa_blade_id();
695         real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
696
697         if (unlikely(real_uv_nmi)) {
698                 spin_lock(&uv_blade_info[bid].nmi_lock);
699                 real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
700                 if (real_uv_nmi) {
701                         uv_blade_info[bid].nmi_count++;
702                         uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);
703                 }
704                 spin_unlock(&uv_blade_info[bid].nmi_lock);
705         }
706
707         if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))
708                 return NMI_DONE;
709
710         __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
711
712         /*
713          * Use a lock so only one cpu prints at a time.
714          * This prevents intermixed output.
715          */
716         spin_lock(&uv_nmi_lock);
717         pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
718         dump_stack();
719         spin_unlock(&uv_nmi_lock);
720
721         return NMI_HANDLED;
722 }
723
724 void uv_register_nmi_notifier(void)
725 {
726         if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))
727                 printk(KERN_WARNING "UV NMI handler failed to register\n");
728 }
729
730 void uv_nmi_init(void)
731 {
732         unsigned int value;
733
734         /*
735          * Unmask NMI on all cpus
736          */
737         value = apic_read(APIC_LVT1) | APIC_DM_NMI;
738         value &= ~APIC_LVT_MASKED;
739         apic_write(APIC_LVT1, value);
740 }
741
742 void __init uv_system_init(void)
743 {
744         union uvh_rh_gam_config_mmr_u  m_n_config;
745         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
746         union uvh_node_id_u node_id;
747         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
748         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
749         int gnode_extra, max_pnode = 0;
750         unsigned long mmr_base, present, paddr;
751         unsigned short pnode_mask, pnode_io_mask;
752
753         printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2");
754         map_low_mmrs();
755
756         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
757         m_val = m_n_config.s.m_skt;
758         n_val = m_n_config.s.n_skt;
759         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
760         n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io;
761         mmr_base =
762             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
763             ~UV_MMR_ENABLE;
764         pnode_mask = (1 << n_val) - 1;
765         pnode_io_mask = (1 << n_io) - 1;
766
767         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
768         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
769         gnode_upper = ((unsigned long)gnode_extra  << m_val);
770         printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
771                         n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
772
773         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
774
775         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
776                 uv_possible_blades +=
777                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
778
779         /* uv_num_possible_blades() is really the hub count */
780         printk(KERN_INFO "UV: Found %d blades, %d hubs\n",
781                         is_uv1_hub() ? uv_num_possible_blades() :
782                         (uv_num_possible_blades() + 1) / 2,
783                         uv_num_possible_blades());
784
785         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
786         uv_blade_info = kzalloc(bytes, GFP_KERNEL);
787         BUG_ON(!uv_blade_info);
788
789         for (blade = 0; blade < uv_num_possible_blades(); blade++)
790                 uv_blade_info[blade].memory_nid = -1;
791
792         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
793
794         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
795         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
796         BUG_ON(!uv_node_to_blade);
797         memset(uv_node_to_blade, 255, bytes);
798
799         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
800         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
801         BUG_ON(!uv_cpu_to_blade);
802         memset(uv_cpu_to_blade, 255, bytes);
803
804         blade = 0;
805         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
806                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
807                 for (j = 0; j < 64; j++) {
808                         if (!test_bit(j, &present))
809                                 continue;
810                         pnode = (i * 64 + j) & pnode_mask;
811                         uv_blade_info[blade].pnode = pnode;
812                         uv_blade_info[blade].nr_possible_cpus = 0;
813                         uv_blade_info[blade].nr_online_cpus = 0;
814                         spin_lock_init(&uv_blade_info[blade].nmi_lock);
815                         max_pnode = max(pnode, max_pnode);
816                         blade++;
817                 }
818         }
819
820         uv_bios_init();
821         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
822                             &sn_region_size, &system_serial_number);
823         uv_rtc_init();
824
825         for_each_present_cpu(cpu) {
826                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
827
828                 nid = cpu_to_node(cpu);
829                 /*
830                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
831                  */
832                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
833                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
834                 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
835
836                 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
837                 uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ?
838                                 (m_val == 40 ? 40 : 39) : m_val;
839
840                 pnode = uv_apicid_to_pnode(apicid);
841                 blade = boot_pnode_to_blade(pnode);
842                 lcpu = uv_blade_info[blade].nr_possible_cpus;
843                 uv_blade_info[blade].nr_possible_cpus++;
844
845                 /* Any node on the blade, else will contain -1. */
846                 uv_blade_info[blade].memory_nid = nid;
847
848                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
849                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
850                 uv_cpu_hub_info(cpu)->m_val = m_val;
851                 uv_cpu_hub_info(cpu)->n_val = n_val;
852                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
853                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
854                 uv_cpu_hub_info(cpu)->pnode = pnode;
855                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
856                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
857                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
858                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
859                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
860                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
861                 uv_node_to_blade[nid] = blade;
862                 uv_cpu_to_blade[cpu] = blade;
863         }
864
865         /* Add blade/pnode info for nodes without cpus */
866         for_each_online_node(nid) {
867                 if (uv_node_to_blade[nid] >= 0)
868                         continue;
869                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
870                 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
871                 blade = boot_pnode_to_blade(pnode);
872                 uv_node_to_blade[nid] = blade;
873         }
874
875         map_gru_high(max_pnode);
876         map_mmr_high(max_pnode);
877         map_mmioh_high(max_pnode & pnode_io_mask);
878
879         uv_cpu_init();
880         uv_scir_register_cpu_notifier();
881         uv_register_nmi_notifier();
882         proc_mkdir("sgi_uv", NULL);
883
884         /* register Legacy VGA I/O redirection handler */
885         pci_register_set_vga_state(uv_set_vga_state);
886
887         /*
888          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
889          * EFI is not enabled in the kdump kernel.
890          */
891         if (is_kdump_kernel())
892                 reboot_type = BOOT_ACPI;
893 }
894
895 apic_driver(apic_x2apic_uv_x);