fc47714258524ddce82163eaf11aef32189a6f84
[~shefty/rdma-dev.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV APIC functions (note: not an Intel compatible APIC)
7  *
8  * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
9  */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28
29 #include <asm/uv/uv_mmrs.h>
30 #include <asm/uv/uv_hub.h>
31 #include <asm/current.h>
32 #include <asm/pgtable.h>
33 #include <asm/uv/bios.h>
34 #include <asm/uv/uv.h>
35 #include <asm/apic.h>
36 #include <asm/ipi.h>
37 #include <asm/smp.h>
38 #include <asm/x86_init.h>
39 #include <asm/emergency-restart.h>
40 #include <asm/nmi.h>
41
42 /* BMC sets a bit this MMR non-zero before sending an NMI */
43 #define UVH_NMI_MMR                             UVH_SCRATCH5
44 #define UVH_NMI_MMR_CLEAR                       (UVH_NMI_MMR + 8)
45 #define UV_NMI_PENDING_MASK                     (1UL << 63)
46 DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
47
48 DEFINE_PER_CPU(int, x2apic_extra_bits);
49
50 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
51
52 static enum uv_system_type uv_system_type;
53 static u64 gru_start_paddr, gru_end_paddr;
54 static union uvh_apicid uvh_apicid;
55 int uv_min_hub_revision_id;
56 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
57 unsigned int uv_apicid_hibits;
58 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
59 static DEFINE_SPINLOCK(uv_nmi_lock);
60
61 static struct apic apic_x2apic_uv_x;
62
63 static unsigned long __init uv_early_read_mmr(unsigned long addr)
64 {
65         unsigned long val, *mmr;
66
67         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
68         val = *mmr;
69         early_iounmap(mmr, sizeof(*mmr));
70         return val;
71 }
72
73 static inline bool is_GRU_range(u64 start, u64 end)
74 {
75         return start >= gru_start_paddr && end <= gru_end_paddr;
76 }
77
78 static bool uv_is_untracked_pat_range(u64 start, u64 end)
79 {
80         return is_ISA_range(start, end) || is_GRU_range(start, end);
81 }
82
83 static int __init early_get_pnodeid(void)
84 {
85         union uvh_node_id_u node_id;
86         union uvh_rh_gam_config_mmr_u  m_n_config;
87         int pnode;
88
89         /* Currently, all blades have same revision number */
90         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
91         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
92         uv_min_hub_revision_id = node_id.s.revision;
93
94         if (node_id.s.part_number == UV2_HUB_PART_NUMBER)
95                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
96         if (node_id.s.part_number == UV2_HUB_PART_NUMBER_X)
97                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
98
99         uv_hub_info->hub_revision = uv_min_hub_revision_id;
100         pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
101         return pnode;
102 }
103
104 static void __init early_get_apic_pnode_shift(void)
105 {
106         uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
107         if (!uvh_apicid.v)
108                 /*
109                  * Old bios, use default value
110                  */
111                 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
112 }
113
114 /*
115  * Add an extra bit as dictated by bios to the destination apicid of
116  * interrupts potentially passing through the UV HUB.  This prevents
117  * a deadlock between interrupts and IO port operations.
118  */
119 static void __init uv_set_apicid_hibit(void)
120 {
121         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
122
123         if (is_uv1_hub()) {
124                 apicid_mask.v =
125                         uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
126                 uv_apicid_hibits =
127                         apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
128         }
129 }
130
131 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
132 {
133         int pnodeid, is_uv1, is_uv2;
134
135         is_uv1 = !strcmp(oem_id, "SGI");
136         is_uv2 = !strcmp(oem_id, "SGI2");
137         if (is_uv1 || is_uv2) {
138                 uv_hub_info->hub_revision =
139                         is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE;
140                 pnodeid = early_get_pnodeid();
141                 early_get_apic_pnode_shift();
142                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
143                 x86_platform.nmi_init = uv_nmi_init;
144                 if (!strcmp(oem_table_id, "UVL"))
145                         uv_system_type = UV_LEGACY_APIC;
146                 else if (!strcmp(oem_table_id, "UVX"))
147                         uv_system_type = UV_X2APIC;
148                 else if (!strcmp(oem_table_id, "UVH")) {
149                         __this_cpu_write(x2apic_extra_bits,
150                                 pnodeid << uvh_apicid.s.pnode_shift);
151                         uv_system_type = UV_NON_UNIQUE_APIC;
152                         uv_set_apicid_hibit();
153                         return 1;
154                 }
155         }
156         return 0;
157 }
158
159 enum uv_system_type get_uv_system_type(void)
160 {
161         return uv_system_type;
162 }
163
164 int is_uv_system(void)
165 {
166         return uv_system_type != UV_NONE;
167 }
168 EXPORT_SYMBOL_GPL(is_uv_system);
169
170 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
171 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
172
173 struct uv_blade_info *uv_blade_info;
174 EXPORT_SYMBOL_GPL(uv_blade_info);
175
176 short *uv_node_to_blade;
177 EXPORT_SYMBOL_GPL(uv_node_to_blade);
178
179 short *uv_cpu_to_blade;
180 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
181
182 short uv_possible_blades;
183 EXPORT_SYMBOL_GPL(uv_possible_blades);
184
185 unsigned long sn_rtc_cycles_per_second;
186 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
187
188 static const struct cpumask *uv_target_cpus(void)
189 {
190         return cpu_online_mask;
191 }
192
193 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
194 {
195         cpumask_clear(retmask);
196         cpumask_set_cpu(cpu, retmask);
197 }
198
199 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
200 {
201 #ifdef CONFIG_SMP
202         unsigned long val;
203         int pnode;
204
205         pnode = uv_apicid_to_pnode(phys_apicid);
206         phys_apicid |= uv_apicid_hibits;
207         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
208             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
209             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
210             APIC_DM_INIT;
211         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
212
213         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
214             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
215             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
216             APIC_DM_STARTUP;
217         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
218
219         atomic_set(&init_deasserted, 1);
220 #endif
221         return 0;
222 }
223
224 static void uv_send_IPI_one(int cpu, int vector)
225 {
226         unsigned long apicid;
227         int pnode;
228
229         apicid = per_cpu(x86_cpu_to_apicid, cpu);
230         pnode = uv_apicid_to_pnode(apicid);
231         uv_hub_send_ipi(pnode, apicid, vector);
232 }
233
234 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
235 {
236         unsigned int cpu;
237
238         for_each_cpu(cpu, mask)
239                 uv_send_IPI_one(cpu, vector);
240 }
241
242 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
243 {
244         unsigned int this_cpu = smp_processor_id();
245         unsigned int cpu;
246
247         for_each_cpu(cpu, mask) {
248                 if (cpu != this_cpu)
249                         uv_send_IPI_one(cpu, vector);
250         }
251 }
252
253 static void uv_send_IPI_allbutself(int vector)
254 {
255         unsigned int this_cpu = smp_processor_id();
256         unsigned int cpu;
257
258         for_each_online_cpu(cpu) {
259                 if (cpu != this_cpu)
260                         uv_send_IPI_one(cpu, vector);
261         }
262 }
263
264 static void uv_send_IPI_all(int vector)
265 {
266         uv_send_IPI_mask(cpu_online_mask, vector);
267 }
268
269 static int uv_apic_id_registered(void)
270 {
271         return 1;
272 }
273
274 static void uv_init_apic_ldr(void)
275 {
276 }
277
278 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
279 {
280         /*
281          * We're using fixed IRQ delivery, can only return one phys APIC ID.
282          * May as well be the first.
283          */
284         int cpu = cpumask_first(cpumask);
285
286         if ((unsigned)cpu < nr_cpu_ids)
287                 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
288         else
289                 return BAD_APICID;
290 }
291
292 static unsigned int
293 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
294                           const struct cpumask *andmask)
295 {
296         int cpu;
297
298         /*
299          * We're using fixed IRQ delivery, can only return one phys APIC ID.
300          * May as well be the first.
301          */
302         for_each_cpu_and(cpu, cpumask, andmask) {
303                 if (cpumask_test_cpu(cpu, cpu_online_mask))
304                         break;
305         }
306         return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
307 }
308
309 static unsigned int x2apic_get_apic_id(unsigned long x)
310 {
311         unsigned int id;
312
313         WARN_ON(preemptible() && num_online_cpus() > 1);
314         id = x | __this_cpu_read(x2apic_extra_bits);
315
316         return id;
317 }
318
319 static unsigned long set_apic_id(unsigned int id)
320 {
321         unsigned long x;
322
323         /* maskout x2apic_extra_bits ? */
324         x = id;
325         return x;
326 }
327
328 static unsigned int uv_read_apic_id(void)
329 {
330
331         return x2apic_get_apic_id(apic_read(APIC_ID));
332 }
333
334 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
335 {
336         return uv_read_apic_id() >> index_msb;
337 }
338
339 static void uv_send_IPI_self(int vector)
340 {
341         apic_write(APIC_SELF_IPI, vector);
342 }
343
344 static int uv_probe(void)
345 {
346         return apic == &apic_x2apic_uv_x;
347 }
348
349 static struct apic __refdata apic_x2apic_uv_x = {
350
351         .name                           = "UV large system",
352         .probe                          = uv_probe,
353         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
354         .apic_id_valid                  = default_apic_id_valid,
355         .apic_id_registered             = uv_apic_id_registered,
356
357         .irq_delivery_mode              = dest_Fixed,
358         .irq_dest_mode                  = 0, /* physical */
359
360         .target_cpus                    = uv_target_cpus,
361         .disable_esr                    = 0,
362         .dest_logical                   = APIC_DEST_LOGICAL,
363         .check_apicid_used              = NULL,
364         .check_apicid_present           = NULL,
365
366         .vector_allocation_domain       = uv_vector_allocation_domain,
367         .init_apic_ldr                  = uv_init_apic_ldr,
368
369         .ioapic_phys_id_map             = NULL,
370         .setup_apic_routing             = NULL,
371         .multi_timer_check              = NULL,
372         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
373         .apicid_to_cpu_present          = NULL,
374         .setup_portio_remap             = NULL,
375         .check_phys_apicid_present      = default_check_phys_apicid_present,
376         .enable_apic_mode               = NULL,
377         .phys_pkg_id                    = uv_phys_pkg_id,
378         .mps_oem_check                  = NULL,
379
380         .get_apic_id                    = x2apic_get_apic_id,
381         .set_apic_id                    = set_apic_id,
382         .apic_id_mask                   = 0xFFFFFFFFu,
383
384         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
385         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
386
387         .send_IPI_mask                  = uv_send_IPI_mask,
388         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
389         .send_IPI_allbutself            = uv_send_IPI_allbutself,
390         .send_IPI_all                   = uv_send_IPI_all,
391         .send_IPI_self                  = uv_send_IPI_self,
392
393         .wakeup_secondary_cpu           = uv_wakeup_secondary,
394         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
395         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
396         .wait_for_init_deassert         = NULL,
397         .smp_callin_clear_local_apic    = NULL,
398         .inquire_remote_apic            = NULL,
399
400         .read                           = native_apic_msr_read,
401         .write                          = native_apic_msr_write,
402         .icr_read                       = native_x2apic_icr_read,
403         .icr_write                      = native_x2apic_icr_write,
404         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
405         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
406 };
407
408 static __cpuinit void set_x2apic_extra_bits(int pnode)
409 {
410         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
411 }
412
413 /*
414  * Called on boot cpu.
415  */
416 static __init int boot_pnode_to_blade(int pnode)
417 {
418         int blade;
419
420         for (blade = 0; blade < uv_num_possible_blades(); blade++)
421                 if (pnode == uv_blade_info[blade].pnode)
422                         return blade;
423         BUG();
424 }
425
426 struct redir_addr {
427         unsigned long redirect;
428         unsigned long alias;
429 };
430
431 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
432
433 static __initdata struct redir_addr redir_addrs[] = {
434         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
435         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
436         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
437 };
438
439 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
440 {
441         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
442         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
443         int i;
444
445         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
446                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
447                 if (alias.s.enable && alias.s.base == 0) {
448                         *size = (1UL << alias.s.m_alias);
449                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
450                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
451                         return;
452                 }
453         }
454         *base = *size = 0;
455 }
456
457 enum map_type {map_wb, map_uc};
458
459 static __init void map_high(char *id, unsigned long base, int pshift,
460                         int bshift, int max_pnode, enum map_type map_type)
461 {
462         unsigned long bytes, paddr;
463
464         paddr = base << pshift;
465         bytes = (1UL << bshift) * (max_pnode + 1);
466         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
467                                                 paddr + bytes);
468         if (map_type == map_uc)
469                 init_extra_mapping_uc(paddr, bytes);
470         else
471                 init_extra_mapping_wb(paddr, bytes);
472
473 }
474 static __init void map_gru_high(int max_pnode)
475 {
476         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
477         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
478
479         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
480         if (gru.s.enable) {
481                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
482                 gru_start_paddr = ((u64)gru.s.base << shift);
483                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
484
485         }
486 }
487
488 static __init void map_mmr_high(int max_pnode)
489 {
490         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
491         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
492
493         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
494         if (mmr.s.enable)
495                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
496 }
497
498 static __init void map_mmioh_high(int max_pnode)
499 {
500         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
501         int shift;
502
503         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
504         if (is_uv1_hub() && mmioh.s1.enable) {
505                 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
506                 map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io,
507                         max_pnode, map_uc);
508         }
509         if (is_uv2_hub() && mmioh.s2.enable) {
510                 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
511                 map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io,
512                         max_pnode, map_uc);
513         }
514 }
515
516 static __init void map_low_mmrs(void)
517 {
518         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
519         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
520 }
521
522 static __init void uv_rtc_init(void)
523 {
524         long status;
525         u64 ticks_per_sec;
526
527         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
528                                         &ticks_per_sec);
529         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
530                 printk(KERN_WARNING
531                         "unable to determine platform RTC clock frequency, "
532                         "guessing.\n");
533                 /* BIOS gives wrong value for clock freq. so guess */
534                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
535         } else
536                 sn_rtc_cycles_per_second = ticks_per_sec;
537 }
538
539 /*
540  * percpu heartbeat timer
541  */
542 static void uv_heartbeat(unsigned long ignored)
543 {
544         struct timer_list *timer = &uv_hub_info->scir.timer;
545         unsigned char bits = uv_hub_info->scir.state;
546
547         /* flip heartbeat bit */
548         bits ^= SCIR_CPU_HEARTBEAT;
549
550         /* is this cpu idle? */
551         if (idle_cpu(raw_smp_processor_id()))
552                 bits &= ~SCIR_CPU_ACTIVITY;
553         else
554                 bits |= SCIR_CPU_ACTIVITY;
555
556         /* update system controller interface reg */
557         uv_set_scir_bits(bits);
558
559         /* enable next timer period */
560         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
561 }
562
563 static void __cpuinit uv_heartbeat_enable(int cpu)
564 {
565         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
566                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
567
568                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
569                 setup_timer(timer, uv_heartbeat, cpu);
570                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
571                 add_timer_on(timer, cpu);
572                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
573
574                 /* also ensure that boot cpu is enabled */
575                 cpu = 0;
576         }
577 }
578
579 #ifdef CONFIG_HOTPLUG_CPU
580 static void __cpuinit uv_heartbeat_disable(int cpu)
581 {
582         if (uv_cpu_hub_info(cpu)->scir.enabled) {
583                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
584                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
585         }
586         uv_set_cpu_scir_bits(cpu, 0xff);
587 }
588
589 /*
590  * cpu hotplug notifier
591  */
592 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
593                                        unsigned long action, void *hcpu)
594 {
595         long cpu = (long)hcpu;
596
597         switch (action) {
598         case CPU_ONLINE:
599                 uv_heartbeat_enable(cpu);
600                 break;
601         case CPU_DOWN_PREPARE:
602                 uv_heartbeat_disable(cpu);
603                 break;
604         default:
605                 break;
606         }
607         return NOTIFY_OK;
608 }
609
610 static __init void uv_scir_register_cpu_notifier(void)
611 {
612         hotcpu_notifier(uv_scir_cpu_notify, 0);
613 }
614
615 #else /* !CONFIG_HOTPLUG_CPU */
616
617 static __init void uv_scir_register_cpu_notifier(void)
618 {
619 }
620
621 static __init int uv_init_heartbeat(void)
622 {
623         int cpu;
624
625         if (is_uv_system())
626                 for_each_online_cpu(cpu)
627                         uv_heartbeat_enable(cpu);
628         return 0;
629 }
630
631 late_initcall(uv_init_heartbeat);
632
633 #endif /* !CONFIG_HOTPLUG_CPU */
634
635 /* Direct Legacy VGA I/O traffic to designated IOH */
636 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
637                       unsigned int command_bits, u32 flags)
638 {
639         int domain, bus, rc;
640
641         PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
642                         pdev->devfn, decode, command_bits, flags);
643
644         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
645                 return 0;
646
647         if ((command_bits & PCI_COMMAND_IO) == 0)
648                 return 0;
649
650         domain = pci_domain_nr(pdev->bus);
651         bus = pdev->bus->number;
652
653         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
654         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
655
656         return rc;
657 }
658
659 /*
660  * Called on each cpu to initialize the per_cpu UV data area.
661  * FIXME: hotplug not supported yet
662  */
663 void __cpuinit uv_cpu_init(void)
664 {
665         /* CPU 0 initilization will be done via uv_system_init. */
666         if (!uv_blade_info)
667                 return;
668
669         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
670
671         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
672                 set_x2apic_extra_bits(uv_hub_info->pnode);
673 }
674
675 /*
676  * When NMI is received, print a stack trace.
677  */
678 int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
679 {
680         unsigned long real_uv_nmi;
681         int bid;
682
683         /*
684          * Each blade has an MMR that indicates when an NMI has been sent
685          * to cpus on the blade. If an NMI is detected, atomically
686          * clear the MMR and update a per-blade NMI count used to
687          * cause each cpu on the blade to notice a new NMI.
688          */
689         bid = uv_numa_blade_id();
690         real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
691
692         if (unlikely(real_uv_nmi)) {
693                 spin_lock(&uv_blade_info[bid].nmi_lock);
694                 real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
695                 if (real_uv_nmi) {
696                         uv_blade_info[bid].nmi_count++;
697                         uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);
698                 }
699                 spin_unlock(&uv_blade_info[bid].nmi_lock);
700         }
701
702         if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))
703                 return NMI_DONE;
704
705         __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
706
707         /*
708          * Use a lock so only one cpu prints at a time.
709          * This prevents intermixed output.
710          */
711         spin_lock(&uv_nmi_lock);
712         pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
713         dump_stack();
714         spin_unlock(&uv_nmi_lock);
715
716         return NMI_HANDLED;
717 }
718
719 void uv_register_nmi_notifier(void)
720 {
721         if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))
722                 printk(KERN_WARNING "UV NMI handler failed to register\n");
723 }
724
725 void uv_nmi_init(void)
726 {
727         unsigned int value;
728
729         /*
730          * Unmask NMI on all cpus
731          */
732         value = apic_read(APIC_LVT1) | APIC_DM_NMI;
733         value &= ~APIC_LVT_MASKED;
734         apic_write(APIC_LVT1, value);
735 }
736
737 void __init uv_system_init(void)
738 {
739         union uvh_rh_gam_config_mmr_u  m_n_config;
740         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
741         union uvh_node_id_u node_id;
742         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
743         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
744         int gnode_extra, max_pnode = 0;
745         unsigned long mmr_base, present, paddr;
746         unsigned short pnode_mask, pnode_io_mask;
747
748         printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2");
749         map_low_mmrs();
750
751         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
752         m_val = m_n_config.s.m_skt;
753         n_val = m_n_config.s.n_skt;
754         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
755         n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io;
756         mmr_base =
757             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
758             ~UV_MMR_ENABLE;
759         pnode_mask = (1 << n_val) - 1;
760         pnode_io_mask = (1 << n_io) - 1;
761
762         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
763         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
764         gnode_upper = ((unsigned long)gnode_extra  << m_val);
765         printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
766                         n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
767
768         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
769
770         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
771                 uv_possible_blades +=
772                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
773
774         /* uv_num_possible_blades() is really the hub count */
775         printk(KERN_INFO "UV: Found %d blades, %d hubs\n",
776                         is_uv1_hub() ? uv_num_possible_blades() :
777                         (uv_num_possible_blades() + 1) / 2,
778                         uv_num_possible_blades());
779
780         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
781         uv_blade_info = kzalloc(bytes, GFP_KERNEL);
782         BUG_ON(!uv_blade_info);
783
784         for (blade = 0; blade < uv_num_possible_blades(); blade++)
785                 uv_blade_info[blade].memory_nid = -1;
786
787         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
788
789         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
790         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
791         BUG_ON(!uv_node_to_blade);
792         memset(uv_node_to_blade, 255, bytes);
793
794         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
795         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
796         BUG_ON(!uv_cpu_to_blade);
797         memset(uv_cpu_to_blade, 255, bytes);
798
799         blade = 0;
800         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
801                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
802                 for (j = 0; j < 64; j++) {
803                         if (!test_bit(j, &present))
804                                 continue;
805                         pnode = (i * 64 + j) & pnode_mask;
806                         uv_blade_info[blade].pnode = pnode;
807                         uv_blade_info[blade].nr_possible_cpus = 0;
808                         uv_blade_info[blade].nr_online_cpus = 0;
809                         spin_lock_init(&uv_blade_info[blade].nmi_lock);
810                         max_pnode = max(pnode, max_pnode);
811                         blade++;
812                 }
813         }
814
815         uv_bios_init();
816         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
817                             &sn_region_size, &system_serial_number);
818         uv_rtc_init();
819
820         for_each_present_cpu(cpu) {
821                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
822
823                 nid = cpu_to_node(cpu);
824                 /*
825                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
826                  */
827                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
828                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
829                 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
830
831                 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
832                 uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ?
833                                 (m_val == 40 ? 40 : 39) : m_val;
834
835                 pnode = uv_apicid_to_pnode(apicid);
836                 blade = boot_pnode_to_blade(pnode);
837                 lcpu = uv_blade_info[blade].nr_possible_cpus;
838                 uv_blade_info[blade].nr_possible_cpus++;
839
840                 /* Any node on the blade, else will contain -1. */
841                 uv_blade_info[blade].memory_nid = nid;
842
843                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
844                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
845                 uv_cpu_hub_info(cpu)->m_val = m_val;
846                 uv_cpu_hub_info(cpu)->n_val = n_val;
847                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
848                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
849                 uv_cpu_hub_info(cpu)->pnode = pnode;
850                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
851                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
852                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
853                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
854                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
855                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
856                 uv_node_to_blade[nid] = blade;
857                 uv_cpu_to_blade[cpu] = blade;
858         }
859
860         /* Add blade/pnode info for nodes without cpus */
861         for_each_online_node(nid) {
862                 if (uv_node_to_blade[nid] >= 0)
863                         continue;
864                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
865                 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
866                 blade = boot_pnode_to_blade(pnode);
867                 uv_node_to_blade[nid] = blade;
868         }
869
870         map_gru_high(max_pnode);
871         map_mmr_high(max_pnode);
872         map_mmioh_high(max_pnode & pnode_io_mask);
873
874         uv_cpu_init();
875         uv_scir_register_cpu_notifier();
876         uv_register_nmi_notifier();
877         proc_mkdir("sgi_uv", NULL);
878
879         /* register Legacy VGA I/O redirection handler */
880         pci_register_set_vga_state(uv_set_vga_state);
881
882         /*
883          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
884          * EFI is not enabled in the kdump kernel.
885          */
886         if (is_kdump_kernel())
887                 reboot_type = BOOT_ACPI;
888 }
889
890 apic_driver(apic_x2apic_uv_x);