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x86/mce: Fix return value of mce_chrdev_read() when erst is disabled
[~shefty/rdma-dev.git] / arch / x86 / kernel / cpu / mcheck / mce_amd.c
1 /*
2  *  (c) 2005, 2006 Advanced Micro Devices, Inc.
3  *  Your use of this code is subject to the terms and conditions of the
4  *  GNU general public license version 2. See "COPYING" or
5  *  http://www.gnu.org/licenses/gpl.html
6  *
7  *  Written by Jacob Shin - AMD, Inc.
8  *
9  *  Support : jacob.shin@amd.com
10  *
11  *  April 2006
12  *     - added support for AMD Family 0x10 processors
13  *
14  *  All MC4_MISCi registers are shared between multi-cores
15  */
16 #include <linux/interrupt.h>
17 #include <linux/notifier.h>
18 #include <linux/kobject.h>
19 #include <linux/percpu.h>
20 #include <linux/errno.h>
21 #include <linux/sched.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/init.h>
25 #include <linux/cpu.h>
26 #include <linux/smp.h>
27
28 #include <asm/apic.h>
29 #include <asm/idle.h>
30 #include <asm/mce.h>
31 #include <asm/msr.h>
32
33 #define NR_BANKS          6
34 #define NR_BLOCKS         9
35 #define THRESHOLD_MAX     0xFFF
36 #define INT_TYPE_APIC     0x00020000
37 #define MASK_VALID_HI     0x80000000
38 #define MASK_CNTP_HI      0x40000000
39 #define MASK_LOCKED_HI    0x20000000
40 #define MASK_LVTOFF_HI    0x00F00000
41 #define MASK_COUNT_EN_HI  0x00080000
42 #define MASK_INT_TYPE_HI  0x00060000
43 #define MASK_OVERFLOW_HI  0x00010000
44 #define MASK_ERR_COUNT_HI 0x00000FFF
45 #define MASK_BLKPTR_LO    0xFF000000
46 #define MCG_XBLK_ADDR     0xC0000400
47
48 struct threshold_block {
49         unsigned int            block;
50         unsigned int            bank;
51         unsigned int            cpu;
52         u32                     address;
53         u16                     interrupt_enable;
54         u16                     threshold_limit;
55         struct kobject          kobj;
56         struct list_head        miscj;
57 };
58
59 struct threshold_bank {
60         struct kobject          *kobj;
61         struct threshold_block  *blocks;
62         cpumask_var_t           cpus;
63 };
64 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
65
66 static unsigned char shared_bank[NR_BANKS] = {
67         0, 0, 0, 0, 1
68 };
69
70 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
71
72 static void amd_threshold_interrupt(void);
73
74 /*
75  * CPU Initialization
76  */
77
78 struct thresh_restart {
79         struct threshold_block  *b;
80         int                     reset;
81         int                     set_lvt_off;
82         int                     lvt_off;
83         u16                     old_limit;
84 };
85
86 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
87 {
88         int msr = (hi & MASK_LVTOFF_HI) >> 20;
89
90         if (apic < 0) {
91                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
92                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
93                        b->bank, b->block, b->address, hi, lo);
94                 return 0;
95         }
96
97         if (apic != msr) {
98                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
99                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
100                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
101                 return 0;
102         }
103
104         return 1;
105 };
106
107 /* must be called with correct cpu affinity */
108 /* Called via smp_call_function_single() */
109 static void threshold_restart_bank(void *_tr)
110 {
111         struct thresh_restart *tr = _tr;
112         u32 hi, lo;
113
114         rdmsr(tr->b->address, lo, hi);
115
116         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
117                 tr->reset = 1;  /* limit cannot be lower than err count */
118
119         if (tr->reset) {                /* reset err count and overflow bit */
120                 hi =
121                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
122                     (THRESHOLD_MAX - tr->b->threshold_limit);
123         } else if (tr->old_limit) {     /* change limit w/o reset */
124                 int new_count = (hi & THRESHOLD_MAX) +
125                     (tr->old_limit - tr->b->threshold_limit);
126
127                 hi = (hi & ~MASK_ERR_COUNT_HI) |
128                     (new_count & THRESHOLD_MAX);
129         }
130
131         if (tr->set_lvt_off) {
132                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
133                         /* set new lvt offset */
134                         hi &= ~MASK_LVTOFF_HI;
135                         hi |= tr->lvt_off << 20;
136                 }
137         }
138
139         tr->b->interrupt_enable ?
140             (hi = (hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
141             (hi &= ~MASK_INT_TYPE_HI);
142
143         hi |= MASK_COUNT_EN_HI;
144         wrmsr(tr->b->address, lo, hi);
145 }
146
147 static void mce_threshold_block_init(struct threshold_block *b, int offset)
148 {
149         struct thresh_restart tr = {
150                 .b                      = b,
151                 .set_lvt_off            = 1,
152                 .lvt_off                = offset,
153         };
154
155         b->threshold_limit              = THRESHOLD_MAX;
156         threshold_restart_bank(&tr);
157 };
158
159 static int setup_APIC_mce(int reserved, int new)
160 {
161         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
162                                               APIC_EILVT_MSG_FIX, 0))
163                 return new;
164
165         return reserved;
166 }
167
168 /* cpu init entry point, called from mce.c with preempt off */
169 void mce_amd_feature_init(struct cpuinfo_x86 *c)
170 {
171         struct threshold_block b;
172         unsigned int cpu = smp_processor_id();
173         u32 low = 0, high = 0, address = 0;
174         unsigned int bank, block;
175         int offset = -1;
176
177         for (bank = 0; bank < NR_BANKS; ++bank) {
178                 for (block = 0; block < NR_BLOCKS; ++block) {
179                         if (block == 0)
180                                 address = MSR_IA32_MC0_MISC + bank * 4;
181                         else if (block == 1) {
182                                 address = (low & MASK_BLKPTR_LO) >> 21;
183                                 if (!address)
184                                         break;
185
186                                 address += MCG_XBLK_ADDR;
187                         } else
188                                 ++address;
189
190                         if (rdmsr_safe(address, &low, &high))
191                                 break;
192
193                         if (!(high & MASK_VALID_HI))
194                                 continue;
195
196                         if (!(high & MASK_CNTP_HI)  ||
197                              (high & MASK_LOCKED_HI))
198                                 continue;
199
200                         if (!block)
201                                 per_cpu(bank_map, cpu) |= (1 << bank);
202                         if (shared_bank[bank] && c->cpu_core_id)
203                                 break;
204
205                         offset = setup_APIC_mce(offset,
206                                                 (high & MASK_LVTOFF_HI) >> 20);
207
208                         memset(&b, 0, sizeof(b));
209                         b.cpu           = cpu;
210                         b.bank          = bank;
211                         b.block         = block;
212                         b.address       = address;
213
214                         mce_threshold_block_init(&b, offset);
215                         mce_threshold_vector = amd_threshold_interrupt;
216                 }
217         }
218 }
219
220 /*
221  * APIC Interrupt Handler
222  */
223
224 /*
225  * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
226  * the interrupt goes off when error_count reaches threshold_limit.
227  * the handler will simply log mcelog w/ software defined bank number.
228  */
229 static void amd_threshold_interrupt(void)
230 {
231         u32 low = 0, high = 0, address = 0;
232         unsigned int bank, block;
233         struct mce m;
234
235         mce_setup(&m);
236
237         /* assume first bank caused it */
238         for (bank = 0; bank < NR_BANKS; ++bank) {
239                 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
240                         continue;
241                 for (block = 0; block < NR_BLOCKS; ++block) {
242                         if (block == 0) {
243                                 address = MSR_IA32_MC0_MISC + bank * 4;
244                         } else if (block == 1) {
245                                 address = (low & MASK_BLKPTR_LO) >> 21;
246                                 if (!address)
247                                         break;
248                                 address += MCG_XBLK_ADDR;
249                         } else {
250                                 ++address;
251                         }
252
253                         if (rdmsr_safe(address, &low, &high))
254                                 break;
255
256                         if (!(high & MASK_VALID_HI)) {
257                                 if (block)
258                                         continue;
259                                 else
260                                         break;
261                         }
262
263                         if (!(high & MASK_CNTP_HI)  ||
264                              (high & MASK_LOCKED_HI))
265                                 continue;
266
267                         /*
268                          * Log the machine check that caused the threshold
269                          * event.
270                          */
271                         machine_check_poll(MCP_TIMESTAMP,
272                                         &__get_cpu_var(mce_poll_banks));
273
274                         if (high & MASK_OVERFLOW_HI) {
275                                 rdmsrl(address, m.misc);
276                                 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
277                                        m.status);
278                                 m.bank = K8_MCE_THRESHOLD_BASE
279                                        + bank * NR_BLOCKS
280                                        + block;
281                                 mce_log(&m);
282                                 return;
283                         }
284                 }
285         }
286 }
287
288 /*
289  * Sysfs Interface
290  */
291
292 struct threshold_attr {
293         struct attribute attr;
294         ssize_t (*show) (struct threshold_block *, char *);
295         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
296 };
297
298 #define SHOW_FIELDS(name)                                               \
299 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
300 {                                                                       \
301         return sprintf(buf, "%lx\n", (unsigned long) b->name);          \
302 }
303 SHOW_FIELDS(interrupt_enable)
304 SHOW_FIELDS(threshold_limit)
305
306 static ssize_t
307 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
308 {
309         struct thresh_restart tr;
310         unsigned long new;
311
312         if (strict_strtoul(buf, 0, &new) < 0)
313                 return -EINVAL;
314
315         b->interrupt_enable = !!new;
316
317         memset(&tr, 0, sizeof(tr));
318         tr.b            = b;
319
320         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
321
322         return size;
323 }
324
325 static ssize_t
326 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
327 {
328         struct thresh_restart tr;
329         unsigned long new;
330
331         if (strict_strtoul(buf, 0, &new) < 0)
332                 return -EINVAL;
333
334         if (new > THRESHOLD_MAX)
335                 new = THRESHOLD_MAX;
336         if (new < 1)
337                 new = 1;
338
339         memset(&tr, 0, sizeof(tr));
340         tr.old_limit = b->threshold_limit;
341         b->threshold_limit = new;
342         tr.b = b;
343
344         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
345
346         return size;
347 }
348
349 struct threshold_block_cross_cpu {
350         struct threshold_block  *tb;
351         long                    retval;
352 };
353
354 static void local_error_count_handler(void *_tbcc)
355 {
356         struct threshold_block_cross_cpu *tbcc = _tbcc;
357         struct threshold_block *b = tbcc->tb;
358         u32 low, high;
359
360         rdmsr(b->address, low, high);
361         tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
362 }
363
364 static ssize_t show_error_count(struct threshold_block *b, char *buf)
365 {
366         struct threshold_block_cross_cpu tbcc = { .tb = b, };
367
368         smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
369         return sprintf(buf, "%lx\n", tbcc.retval);
370 }
371
372 static ssize_t store_error_count(struct threshold_block *b,
373                                  const char *buf, size_t count)
374 {
375         struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
376
377         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
378         return 1;
379 }
380
381 #define RW_ATTR(val)                                                    \
382 static struct threshold_attr val = {                                    \
383         .attr   = {.name = __stringify(val), .mode = 0644 },            \
384         .show   = show_## val,                                          \
385         .store  = store_## val,                                         \
386 };
387
388 RW_ATTR(interrupt_enable);
389 RW_ATTR(threshold_limit);
390 RW_ATTR(error_count);
391
392 static struct attribute *default_attrs[] = {
393         &interrupt_enable.attr,
394         &threshold_limit.attr,
395         &error_count.attr,
396         NULL
397 };
398
399 #define to_block(k)     container_of(k, struct threshold_block, kobj)
400 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
401
402 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
403 {
404         struct threshold_block *b = to_block(kobj);
405         struct threshold_attr *a = to_attr(attr);
406         ssize_t ret;
407
408         ret = a->show ? a->show(b, buf) : -EIO;
409
410         return ret;
411 }
412
413 static ssize_t store(struct kobject *kobj, struct attribute *attr,
414                      const char *buf, size_t count)
415 {
416         struct threshold_block *b = to_block(kobj);
417         struct threshold_attr *a = to_attr(attr);
418         ssize_t ret;
419
420         ret = a->store ? a->store(b, buf, count) : -EIO;
421
422         return ret;
423 }
424
425 static const struct sysfs_ops threshold_ops = {
426         .show                   = show,
427         .store                  = store,
428 };
429
430 static struct kobj_type threshold_ktype = {
431         .sysfs_ops              = &threshold_ops,
432         .default_attrs          = default_attrs,
433 };
434
435 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
436                                                unsigned int bank,
437                                                unsigned int block,
438                                                u32 address)
439 {
440         struct threshold_block *b = NULL;
441         u32 low, high;
442         int err;
443
444         if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
445                 return 0;
446
447         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
448                 return 0;
449
450         if (!(high & MASK_VALID_HI)) {
451                 if (block)
452                         goto recurse;
453                 else
454                         return 0;
455         }
456
457         if (!(high & MASK_CNTP_HI)  ||
458              (high & MASK_LOCKED_HI))
459                 goto recurse;
460
461         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
462         if (!b)
463                 return -ENOMEM;
464
465         b->block                = block;
466         b->bank                 = bank;
467         b->cpu                  = cpu;
468         b->address              = address;
469         b->interrupt_enable     = 0;
470         b->threshold_limit      = THRESHOLD_MAX;
471
472         INIT_LIST_HEAD(&b->miscj);
473
474         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
475                 list_add(&b->miscj,
476                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
477         } else {
478                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
479         }
480
481         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
482                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
483                                    "misc%i", block);
484         if (err)
485                 goto out_free;
486 recurse:
487         if (!block) {
488                 address = (low & MASK_BLKPTR_LO) >> 21;
489                 if (!address)
490                         return 0;
491                 address += MCG_XBLK_ADDR;
492         } else {
493                 ++address;
494         }
495
496         err = allocate_threshold_blocks(cpu, bank, ++block, address);
497         if (err)
498                 goto out_free;
499
500         if (b)
501                 kobject_uevent(&b->kobj, KOBJ_ADD);
502
503         return err;
504
505 out_free:
506         if (b) {
507                 kobject_put(&b->kobj);
508                 list_del(&b->miscj);
509                 kfree(b);
510         }
511         return err;
512 }
513
514 static __cpuinit long
515 local_allocate_threshold_blocks(int cpu, unsigned int bank)
516 {
517         return allocate_threshold_blocks(cpu, bank, 0,
518                                          MSR_IA32_MC0_MISC + bank * 4);
519 }
520
521 /* symlinks sibling shared banks to first core.  first core owns dir/files. */
522 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
523 {
524         int i, err = 0;
525         struct threshold_bank *b = NULL;
526         struct device *dev = per_cpu(mce_device, cpu);
527         char name[32];
528
529         sprintf(name, "threshold_bank%i", bank);
530
531         if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) {   /* symlink */
532                 i = cpumask_first(cpu_llc_shared_mask(cpu));
533
534                 /* first core not up yet */
535                 if (cpu_data(i).cpu_core_id)
536                         goto out;
537
538                 /* already linked */
539                 if (per_cpu(threshold_banks, cpu)[bank])
540                         goto out;
541
542                 b = per_cpu(threshold_banks, i)[bank];
543
544                 if (!b)
545                         goto out;
546
547                 err = sysfs_create_link(&dev->kobj, b->kobj, name);
548                 if (err)
549                         goto out;
550
551                 cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));
552                 per_cpu(threshold_banks, cpu)[bank] = b;
553
554                 goto out;
555         }
556
557         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
558         if (!b) {
559                 err = -ENOMEM;
560                 goto out;
561         }
562         if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
563                 kfree(b);
564                 err = -ENOMEM;
565                 goto out;
566         }
567
568         b->kobj = kobject_create_and_add(name, &dev->kobj);
569         if (!b->kobj)
570                 goto out_free;
571
572 #ifndef CONFIG_SMP
573         cpumask_setall(b->cpus);
574 #else
575         cpumask_set_cpu(cpu, b->cpus);
576 #endif
577
578         per_cpu(threshold_banks, cpu)[bank] = b;
579
580         err = local_allocate_threshold_blocks(cpu, bank);
581         if (err)
582                 goto out_free;
583
584         for_each_cpu(i, b->cpus) {
585                 if (i == cpu)
586                         continue;
587
588                 dev = per_cpu(mce_device, i);
589                 if (dev)
590                         err = sysfs_create_link(&dev->kobj,b->kobj, name);
591                 if (err)
592                         goto out;
593
594                 per_cpu(threshold_banks, i)[bank] = b;
595         }
596
597         goto out;
598
599 out_free:
600         per_cpu(threshold_banks, cpu)[bank] = NULL;
601         free_cpumask_var(b->cpus);
602         kfree(b);
603 out:
604         return err;
605 }
606
607 /* create dir/files for all valid threshold banks */
608 static __cpuinit int threshold_create_device(unsigned int cpu)
609 {
610         unsigned int bank;
611         int err = 0;
612
613         for (bank = 0; bank < NR_BANKS; ++bank) {
614                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
615                         continue;
616                 err = threshold_create_bank(cpu, bank);
617                 if (err)
618                         return err;
619         }
620
621         return err;
622 }
623
624 /*
625  * let's be hotplug friendly.
626  * in case of multiple core processors, the first core always takes ownership
627  *   of shared sysfs dir/files, and rest of the cores will be symlinked to it.
628  */
629
630 static void deallocate_threshold_block(unsigned int cpu,
631                                                  unsigned int bank)
632 {
633         struct threshold_block *pos = NULL;
634         struct threshold_block *tmp = NULL;
635         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
636
637         if (!head)
638                 return;
639
640         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
641                 kobject_put(&pos->kobj);
642                 list_del(&pos->miscj);
643                 kfree(pos);
644         }
645
646         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
647         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
648 }
649
650 static void threshold_remove_bank(unsigned int cpu, int bank)
651 {
652         struct threshold_bank *b;
653         struct device *dev;
654         char name[32];
655         int i = 0;
656
657         b = per_cpu(threshold_banks, cpu)[bank];
658         if (!b)
659                 return;
660         if (!b->blocks)
661                 goto free_out;
662
663         sprintf(name, "threshold_bank%i", bank);
664
665 #ifdef CONFIG_SMP
666         /* sibling symlink */
667         if (shared_bank[bank] && b->blocks->cpu != cpu) {
668                 dev = per_cpu(mce_device, cpu);
669                 sysfs_remove_link(&dev->kobj, name);
670                 per_cpu(threshold_banks, cpu)[bank] = NULL;
671
672                 return;
673         }
674 #endif
675
676         /* remove all sibling symlinks before unregistering */
677         for_each_cpu(i, b->cpus) {
678                 if (i == cpu)
679                         continue;
680
681                 dev = per_cpu(mce_device, i);
682                 if (dev)
683                         sysfs_remove_link(&dev->kobj, name);
684                 per_cpu(threshold_banks, i)[bank] = NULL;
685         }
686
687         deallocate_threshold_block(cpu, bank);
688
689 free_out:
690         kobject_del(b->kobj);
691         kobject_put(b->kobj);
692         free_cpumask_var(b->cpus);
693         kfree(b);
694         per_cpu(threshold_banks, cpu)[bank] = NULL;
695 }
696
697 static void threshold_remove_device(unsigned int cpu)
698 {
699         unsigned int bank;
700
701         for (bank = 0; bank < NR_BANKS; ++bank) {
702                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
703                         continue;
704                 threshold_remove_bank(cpu, bank);
705         }
706 }
707
708 /* get notified when a cpu comes on/off */
709 static void __cpuinit
710 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
711 {
712         switch (action) {
713         case CPU_ONLINE:
714         case CPU_ONLINE_FROZEN:
715                 threshold_create_device(cpu);
716                 break;
717         case CPU_DEAD:
718         case CPU_DEAD_FROZEN:
719                 threshold_remove_device(cpu);
720                 break;
721         default:
722                 break;
723         }
724 }
725
726 static __init int threshold_init_device(void)
727 {
728         unsigned lcpu = 0;
729
730         /* to hit CPUs online before the notifier is up */
731         for_each_online_cpu(lcpu) {
732                 int err = threshold_create_device(lcpu);
733
734                 if (err)
735                         return err;
736         }
737         threshold_cpu_callback = amd_64_threshold_cpu_callback;
738
739         return 0;
740 }
741 device_initcall(threshold_init_device);