arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/ftrace_event.h>
  31 #include <linux/slab.h>
  32 #include <linux/tboot.h>
  33 #include "kvm_cache_regs.h"
  34 #include "x86.h"
  35
  36 #include <asm/io.h>
  37 #include <asm/desc.h>
  38 #include <asm/vmx.h>
  39 #include <asm/virtext.h>
  40 #include <asm/mce.h>
  41 #include <asm/i387.h>
  42 #include <asm/xcr.h>
  43 #include <asm/perf_event.h>
  44
  45 #include "trace.h"
  46
  47 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  48 #define __ex_clear(x, reg) \
  49         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  50
  51 MODULE_AUTHOR("Qumranet");
  52 MODULE_LICENSE("GPL");
  53
  54 static bool __read_mostly enable_vpid = 1;
  55 module_param_named(vpid, enable_vpid, bool, 0444);
  56
  57 static bool __read_mostly flexpriority_enabled = 1;
  58 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  59
  60 static bool __read_mostly enable_ept = 1;
  61 module_param_named(ept, enable_ept, bool, S_IRUGO);
  62
  63 static bool __read_mostly enable_unrestricted_guest = 1;
  64 module_param_named(unrestricted_guest,
  65                         enable_unrestricted_guest, bool, S_IRUGO);
  66
  67 static bool __read_mostly emulate_invalid_guest_state = 0;
  68 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  69
  70 static bool __read_mostly vmm_exclusive = 1;
  71 module_param(vmm_exclusive, bool, S_IRUGO);
  72
  73 static bool __read_mostly fasteoi = 1;
  74 module_param(fasteoi, bool, S_IRUGO);
  75
  76 /*
  77  * If nested=1, nested virtualization is supported, i.e., guests may use
  78  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  79  * use VMX instructions.
  80  */
  81 static bool __read_mostly nested = 0;
  82 module_param(nested, bool, S_IRUGO);
  83
  84 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  85         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  86 #define KVM_GUEST_CR0_MASK                                              \
  87         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  88 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  89         (X86_CR0_WP | X86_CR0_NE)
  90 #define KVM_VM_CR0_ALWAYS_ON                                            \
  91         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  92 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  93         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  94          | X86_CR4_OSXMMEXCPT)
  95
  96 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  97 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  98
  99 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 100
 101 /*
 102  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 103  * ple_gap:    upper bound on the amount of time between two successive
 104  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 105  *             According to test, this time is usually smaller than 128 cycles.
 106  * ple_window: upper bound on the amount of time a guest is allowed to execute
 107  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 108  *             less than 2^12 cycles
 109  * Time is measured based on a counter that runs at the same rate as the TSC,
 110  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 111  */
 112 #define KVM_VMX_DEFAULT_PLE_GAP    128
 113 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 114 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 115 module_param(ple_gap, int, S_IRUGO);
 116
 117 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 118 module_param(ple_window, int, S_IRUGO);
 119
 120 #define NR_AUTOLOAD_MSRS 8
 121 #define VMCS02_POOL_SIZE 1
 122
 123 struct vmcs {
 124         u32 revision_id;
 125         u32 abort;
 126         char data[0];
 127 };
 128
 129 /*
 130  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 131  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 132  * loaded on this CPU (so we can clear them if the CPU goes down).
 133  */
 134 struct loaded_vmcs {
 135         struct vmcs *vmcs;
 136         int cpu;
 137         int launched;
 138         struct list_head loaded_vmcss_on_cpu_link;
 139 };
 140
 141 struct shared_msr_entry {
 142         unsigned index;
 143         u64 data;
 144         u64 mask;
 145 };
 146
 147 /*
 148  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 149  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 150  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 151  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 152  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 153  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 154  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 155  * underlying hardware which will be used to run L2.
 156  * This structure is packed to ensure that its layout is identical across
 157  * machines (necessary for live migration).
 158  * If there are changes in this struct, VMCS12_REVISION must be changed.
 159  */
 160 typedef u64 natural_width;
 161 struct __packed vmcs12 {
 162         /* According to the Intel spec, a VMCS region must start with the
 163          * following two fields. Then follow implementation-specific data.
 164          */
 165         u32 revision_id;
 166         u32 abort;
 167
 168         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 169         u32 padding[7]; /* room for future expansion */
 170
 171         u64 io_bitmap_a;
 172         u64 io_bitmap_b;
 173         u64 msr_bitmap;
 174         u64 vm_exit_msr_store_addr;
 175         u64 vm_exit_msr_load_addr;
 176         u64 vm_entry_msr_load_addr;
 177         u64 tsc_offset;
 178         u64 virtual_apic_page_addr;
 179         u64 apic_access_addr;
 180         u64 ept_pointer;
 181         u64 guest_physical_address;
 182         u64 vmcs_link_pointer;
 183         u64 guest_ia32_debugctl;
 184         u64 guest_ia32_pat;
 185         u64 guest_ia32_efer;
 186         u64 guest_ia32_perf_global_ctrl;
 187         u64 guest_pdptr0;
 188         u64 guest_pdptr1;
 189         u64 guest_pdptr2;
 190         u64 guest_pdptr3;
 191         u64 host_ia32_pat;
 192         u64 host_ia32_efer;
 193         u64 host_ia32_perf_global_ctrl;
 194         u64 padding64[8]; /* room for future expansion */
 195         /*
 196          * To allow migration of L1 (complete with its L2 guests) between
 197          * machines of different natural widths (32 or 64 bit), we cannot have
 198          * unsigned long fields with no explict size. We use u64 (aliased
 199          * natural_width) instead. Luckily, x86 is little-endian.
 200          */
 201         natural_width cr0_guest_host_mask;
 202         natural_width cr4_guest_host_mask;
 203         natural_width cr0_read_shadow;
 204         natural_width cr4_read_shadow;
 205         natural_width cr3_target_value0;
 206         natural_width cr3_target_value1;
 207         natural_width cr3_target_value2;
 208         natural_width cr3_target_value3;
 209         natural_width exit_qualification;
 210         natural_width guest_linear_address;
 211         natural_width guest_cr0;
 212         natural_width guest_cr3;
 213         natural_width guest_cr4;
 214         natural_width guest_es_base;
 215         natural_width guest_cs_base;
 216         natural_width guest_ss_base;
 217         natural_width guest_ds_base;
 218         natural_width guest_fs_base;
 219         natural_width guest_gs_base;
 220         natural_width guest_ldtr_base;
 221         natural_width guest_tr_base;
 222         natural_width guest_gdtr_base;
 223         natural_width guest_idtr_base;
 224         natural_width guest_dr7;
 225         natural_width guest_rsp;
 226         natural_width guest_rip;
 227         natural_width guest_rflags;
 228         natural_width guest_pending_dbg_exceptions;
 229         natural_width guest_sysenter_esp;
 230         natural_width guest_sysenter_eip;
 231         natural_width host_cr0;
 232         natural_width host_cr3;
 233         natural_width host_cr4;
 234         natural_width host_fs_base;
 235         natural_width host_gs_base;
 236         natural_width host_tr_base;
 237         natural_width host_gdtr_base;
 238         natural_width host_idtr_base;
 239         natural_width host_ia32_sysenter_esp;
 240         natural_width host_ia32_sysenter_eip;
 241         natural_width host_rsp;
 242         natural_width host_rip;
 243         natural_width paddingl[8]; /* room for future expansion */
 244         u32 pin_based_vm_exec_control;
 245         u32 cpu_based_vm_exec_control;
 246         u32 exception_bitmap;
 247         u32 page_fault_error_code_mask;
 248         u32 page_fault_error_code_match;
 249         u32 cr3_target_count;
 250         u32 vm_exit_controls;
 251         u32 vm_exit_msr_store_count;
 252         u32 vm_exit_msr_load_count;
 253         u32 vm_entry_controls;
 254         u32 vm_entry_msr_load_count;
 255         u32 vm_entry_intr_info_field;
 256         u32 vm_entry_exception_error_code;
 257         u32 vm_entry_instruction_len;
 258         u32 tpr_threshold;
 259         u32 secondary_vm_exec_control;
 260         u32 vm_instruction_error;
 261         u32 vm_exit_reason;
 262         u32 vm_exit_intr_info;
 263         u32 vm_exit_intr_error_code;
 264         u32 idt_vectoring_info_field;
 265         u32 idt_vectoring_error_code;
 266         u32 vm_exit_instruction_len;
 267         u32 vmx_instruction_info;
 268         u32 guest_es_limit;
 269         u32 guest_cs_limit;
 270         u32 guest_ss_limit;
 271         u32 guest_ds_limit;
 272         u32 guest_fs_limit;
 273         u32 guest_gs_limit;
 274         u32 guest_ldtr_limit;
 275         u32 guest_tr_limit;
 276         u32 guest_gdtr_limit;
 277         u32 guest_idtr_limit;
 278         u32 guest_es_ar_bytes;
 279         u32 guest_cs_ar_bytes;
 280         u32 guest_ss_ar_bytes;
 281         u32 guest_ds_ar_bytes;
 282         u32 guest_fs_ar_bytes;
 283         u32 guest_gs_ar_bytes;
 284         u32 guest_ldtr_ar_bytes;
 285         u32 guest_tr_ar_bytes;
 286         u32 guest_interruptibility_info;
 287         u32 guest_activity_state;
 288         u32 guest_sysenter_cs;
 289         u32 host_ia32_sysenter_cs;
 290         u32 padding32[8]; /* room for future expansion */
 291         u16 virtual_processor_id;
 292         u16 guest_es_selector;
 293         u16 guest_cs_selector;
 294         u16 guest_ss_selector;
 295         u16 guest_ds_selector;
 296         u16 guest_fs_selector;
 297         u16 guest_gs_selector;
 298         u16 guest_ldtr_selector;
 299         u16 guest_tr_selector;
 300         u16 host_es_selector;
 301         u16 host_cs_selector;
 302         u16 host_ss_selector;
 303         u16 host_ds_selector;
 304         u16 host_fs_selector;
 305         u16 host_gs_selector;
 306         u16 host_tr_selector;
 307 };
 308
 309 /*
 310  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 311  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 312  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 313  */
 314 #define VMCS12_REVISION 0x11e57ed0
 315
 316 /*
 317  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 318  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 319  * current implementation, 4K are reserved to avoid future complications.
 320  */
 321 #define VMCS12_SIZE 0x1000
 322
 323 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 324 struct vmcs02_list {
 325         struct list_head list;
 326         gpa_t vmptr;
 327         struct loaded_vmcs vmcs02;
 328 };
 329
 330 /*
 331  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 332  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 333  */
 334 struct nested_vmx {
 335         /* Has the level1 guest done vmxon? */
 336         bool vmxon;
 337
 338         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 339         gpa_t current_vmptr;
 340         /* The host-usable pointer to the above */
 341         struct page *current_vmcs12_page;
 342         struct vmcs12 *current_vmcs12;
 343
 344         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 345         struct list_head vmcs02_pool;
 346         int vmcs02_num;
 347         u64 vmcs01_tsc_offset;
 348         /* L2 must run next, and mustn't decide to exit to L1. */
 349         bool nested_run_pending;
 350         /*
 351          * Guest pages referred to in vmcs02 with host-physical pointers, so
 352          * we must keep them pinned while L2 runs.
 353          */
 354         struct page *apic_access_page;
 355 };
 356
 357 struct vcpu_vmx {
 358         struct kvm_vcpu       vcpu;
 359         unsigned long         host_rsp;
 360         u8                    fail;
 361         u8                    cpl;
 362         bool                  nmi_known_unmasked;
 363         u32                   exit_intr_info;
 364         u32                   idt_vectoring_info;
 365         ulong                 rflags;
 366         struct shared_msr_entry *guest_msrs;
 367         int                   nmsrs;
 368         int                   save_nmsrs;
 369 #ifdef CONFIG_X86_64
 370         u64                   msr_host_kernel_gs_base;
 371         u64                   msr_guest_kernel_gs_base;
 372 #endif
 373         /*
 374          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 375          * non-nested (L1) guest, it always points to vmcs01. For a nested
 376          * guest (L2), it points to a different VMCS.
 377          */
 378         struct loaded_vmcs    vmcs01;
 379         struct loaded_vmcs   *loaded_vmcs;
 380         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 381         struct msr_autoload {
 382                 unsigned nr;
 383                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 384                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 385         } msr_autoload;
 386         struct {
 387                 int           loaded;
 388                 u16           fs_sel, gs_sel, ldt_sel;
 389                 int           gs_ldt_reload_needed;
 390                 int           fs_reload_needed;
 391         } host_state;
 392         struct {
 393                 int vm86_active;
 394                 ulong save_rflags;
 395                 struct kvm_save_segment {
 396                         u16 selector;
 397                         unsigned long base;
 398                         u32 limit;
 399                         u32 ar;
 400                 } tr, es, ds, fs, gs;
 401         } rmode;
 402         struct {
 403                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 404                 struct kvm_save_segment seg[8];
 405         } segment_cache;
 406         int vpid;
 407         bool emulation_required;
 408
 409         /* Support for vnmi-less CPUs */
 410         int soft_vnmi_blocked;
 411         ktime_t entry_time;
 412         s64 vnmi_blocked_time;
 413         u32 exit_reason;
 414
 415         bool rdtscp_enabled;
 416
 417         /* Support for a guest hypervisor (nested VMX) */
 418         struct nested_vmx nested;
 419 };
 420
 421 enum segment_cache_field {
 422         SEG_FIELD_SEL = 0,
 423         SEG_FIELD_BASE = 1,
 424         SEG_FIELD_LIMIT = 2,
 425         SEG_FIELD_AR = 3,
 426
 427         SEG_FIELD_NR = 4
 428 };
 429
 430 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 431 {
 432         return container_of(vcpu, struct vcpu_vmx, vcpu);
 433 }
 434
 435 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 436 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 437 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 438                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 439
 440 static unsigned short vmcs_field_to_offset_table[] = {
 441         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 442         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 443         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 444         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 445         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 446         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 447         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 448         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 449         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 450         FIELD(HOST_ES_SELECTOR, host_es_selector),
 451         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 452         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 453         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 454         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 455         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 456         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 457         FIELD64(IO_BITMAP_A, io_bitmap_a),
 458         FIELD64(IO_BITMAP_B, io_bitmap_b),
 459         FIELD64(MSR_BITMAP, msr_bitmap),
 460         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 461         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 462         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 463         FIELD64(TSC_OFFSET, tsc_offset),
 464         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 465         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 466         FIELD64(EPT_POINTER, ept_pointer),
 467         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 468         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 469         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 470         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 471         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 472         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 473         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 474         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 475         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 476         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 477         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 478         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 479         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 480         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 481         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 482         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 483         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 484         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 485         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 486         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 487         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 488         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 489         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 490         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 491         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 492         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 493         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 494         FIELD(TPR_THRESHOLD, tpr_threshold),
 495         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 496         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 497         FIELD(VM_EXIT_REASON, vm_exit_reason),
 498         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 499         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 500         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 501         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 502         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 503         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 504         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 505         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 506         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 507         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 508         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 509         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 510         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 511         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 512         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 513         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 514         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 515         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 516         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 517         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 518         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 519         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 520         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 521         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 522         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 523         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 524         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 525         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 526         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 527         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 528         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 529         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 530         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 531         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 532         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 533         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 534         FIELD(EXIT_QUALIFICATION, exit_qualification),
 535         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 536         FIELD(GUEST_CR0, guest_cr0),
 537         FIELD(GUEST_CR3, guest_cr3),
 538         FIELD(GUEST_CR4, guest_cr4),
 539         FIELD(GUEST_ES_BASE, guest_es_base),
 540         FIELD(GUEST_CS_BASE, guest_cs_base),
 541         FIELD(GUEST_SS_BASE, guest_ss_base),
 542         FIELD(GUEST_DS_BASE, guest_ds_base),
 543         FIELD(GUEST_FS_BASE, guest_fs_base),
 544         FIELD(GUEST_GS_BASE, guest_gs_base),
 545         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 546         FIELD(GUEST_TR_BASE, guest_tr_base),
 547         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 548         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 549         FIELD(GUEST_DR7, guest_dr7),
 550         FIELD(GUEST_RSP, guest_rsp),
 551         FIELD(GUEST_RIP, guest_rip),
 552         FIELD(GUEST_RFLAGS, guest_rflags),
 553         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 554         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 555         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 556         FIELD(HOST_CR0, host_cr0),
 557         FIELD(HOST_CR3, host_cr3),
 558         FIELD(HOST_CR4, host_cr4),
 559         FIELD(HOST_FS_BASE, host_fs_base),
 560         FIELD(HOST_GS_BASE, host_gs_base),
 561         FIELD(HOST_TR_BASE, host_tr_base),
 562         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 563         FIELD(HOST_IDTR_BASE, host_idtr_base),
 564         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 565         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 566         FIELD(HOST_RSP, host_rsp),
 567         FIELD(HOST_RIP, host_rip),
 568 };
 569 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 570
 571 static inline short vmcs_field_to_offset(unsigned long field)
 572 {
 573         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 574                 return -1;
 575         return vmcs_field_to_offset_table[field];
 576 }
 577
 578 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 579 {
 580         return to_vmx(vcpu)->nested.current_vmcs12;
 581 }
 582
 583 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 584 {
 585         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 586         if (is_error_page(page)) {
 587                 kvm_release_page_clean(page);
 588                 return NULL;
 589         }
 590         return page;
 591 }
 592
 593 static void nested_release_page(struct page *page)
 594 {
 595         kvm_release_page_dirty(page);
 596 }
 597
 598 static void nested_release_page_clean(struct page *page)
 599 {
 600         kvm_release_page_clean(page);
 601 }
 602
 603 static u64 construct_eptp(unsigned long root_hpa);
 604 static void kvm_cpu_vmxon(u64 addr);
 605 static void kvm_cpu_vmxoff(void);
 606 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 607 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 608
 609 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 610 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 611 /*
 612  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 613  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 614  */
 615 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 616 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 617
 618 static unsigned long *vmx_io_bitmap_a;
 619 static unsigned long *vmx_io_bitmap_b;
 620 static unsigned long *vmx_msr_bitmap_legacy;
 621 static unsigned long *vmx_msr_bitmap_longmode;
 622
 623 static bool cpu_has_load_ia32_efer;
 624 static bool cpu_has_load_perf_global_ctrl;
 625
 626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 627 static DEFINE_SPINLOCK(vmx_vpid_lock);
 628
 629 static struct vmcs_config {
 630         int size;
 631         int order;
 632         u32 revision_id;
 633         u32 pin_based_exec_ctrl;
 634         u32 cpu_based_exec_ctrl;
 635         u32 cpu_based_2nd_exec_ctrl;
 636         u32 vmexit_ctrl;
 637         u32 vmentry_ctrl;
 638 } vmcs_config;
 639
 640 static struct vmx_capability {
 641         u32 ept;
 642         u32 vpid;
 643 } vmx_capability;
 644
 645 #define VMX_SEGMENT_FIELD(seg)                                  \
 646         [VCPU_SREG_##seg] = {                                   \
 647                 .selector = GUEST_##seg##_SELECTOR,             \
 648                 .base = GUEST_##seg##_BASE,                     \
 649                 .limit = GUEST_##seg##_LIMIT,                   \
 650                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 651         }
 652
 653 static struct kvm_vmx_segment_field {
 654         unsigned selector;
 655         unsigned base;
 656         unsigned limit;
 657         unsigned ar_bytes;
 658 } kvm_vmx_segment_fields[] = {
 659         VMX_SEGMENT_FIELD(CS),
 660         VMX_SEGMENT_FIELD(DS),
 661         VMX_SEGMENT_FIELD(ES),
 662         VMX_SEGMENT_FIELD(FS),
 663         VMX_SEGMENT_FIELD(GS),
 664         VMX_SEGMENT_FIELD(SS),
 665         VMX_SEGMENT_FIELD(TR),
 666         VMX_SEGMENT_FIELD(LDTR),
 667 };
 668
 669 static u64 host_efer;
 670
 671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 672
 673 /*
 674  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 675  * away by decrementing the array size.
 676  */
 677 static const u32 vmx_msr_index[] = {
 678 #ifdef CONFIG_X86_64
 679         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 680 #endif
 681         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 682 };
 683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 684
 685 static inline bool is_page_fault(u32 intr_info)
 686 {
 687         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 688                              INTR_INFO_VALID_MASK)) ==
 689                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 690 }
 691
 692 static inline bool is_no_device(u32 intr_info)
 693 {
 694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 695                              INTR_INFO_VALID_MASK)) ==
 696                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 697 }
 698
 699 static inline bool is_invalid_opcode(u32 intr_info)
 700 {
 701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 702                              INTR_INFO_VALID_MASK)) ==
 703                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 704 }
 705
 706 static inline bool is_external_interrupt(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 709                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 710 }
 711
 712 static inline bool is_machine_check(u32 intr_info)
 713 {
 714         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 715                              INTR_INFO_VALID_MASK)) ==
 716                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 717 }
 718
 719 static inline bool cpu_has_vmx_msr_bitmap(void)
 720 {
 721         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 722 }
 723
 724 static inline bool cpu_has_vmx_tpr_shadow(void)
 725 {
 726         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 727 }
 728
 729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 730 {
 731         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 732 }
 733
 734 static inline bool cpu_has_secondary_exec_ctrls(void)
 735 {
 736         return vmcs_config.cpu_based_exec_ctrl &
 737                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 738 }
 739
 740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 741 {
 742         return vmcs_config.cpu_based_2nd_exec_ctrl &
 743                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 744 }
 745
 746 static inline bool cpu_has_vmx_flexpriority(void)
 747 {
 748         return cpu_has_vmx_tpr_shadow() &&
 749                 cpu_has_vmx_virtualize_apic_accesses();
 750 }
 751
 752 static inline bool cpu_has_vmx_ept_execute_only(void)
 753 {
 754         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 755 }
 756
 757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 758 {
 759         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 760 }
 761
 762 static inline bool cpu_has_vmx_eptp_writeback(void)
 763 {
 764         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 765 }
 766
 767 static inline bool cpu_has_vmx_ept_2m_page(void)
 768 {
 769         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 770 }
 771
 772 static inline bool cpu_has_vmx_ept_1g_page(void)
 773 {
 774         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 775 }
 776
 777 static inline bool cpu_has_vmx_ept_4levels(void)
 778 {
 779         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 780 }
 781
 782 static inline bool cpu_has_vmx_invept_individual_addr(void)
 783 {
 784         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 785 }
 786
 787 static inline bool cpu_has_vmx_invept_context(void)
 788 {
 789         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 790 }
 791
 792 static inline bool cpu_has_vmx_invept_global(void)
 793 {
 794         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 795 }
 796
 797 static inline bool cpu_has_vmx_invvpid_single(void)
 798 {
 799         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 800 }
 801
 802 static inline bool cpu_has_vmx_invvpid_global(void)
 803 {
 804         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 805 }
 806
 807 static inline bool cpu_has_vmx_ept(void)
 808 {
 809         return vmcs_config.cpu_based_2nd_exec_ctrl &
 810                 SECONDARY_EXEC_ENABLE_EPT;
 811 }
 812
 813 static inline bool cpu_has_vmx_unrestricted_guest(void)
 814 {
 815         return vmcs_config.cpu_based_2nd_exec_ctrl &
 816                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 817 }
 818
 819 static inline bool cpu_has_vmx_ple(void)
 820 {
 821         return vmcs_config.cpu_based_2nd_exec_ctrl &
 822                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 823 }
 824
 825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 826 {
 827         return flexpriority_enabled && irqchip_in_kernel(kvm);
 828 }
 829
 830 static inline bool cpu_has_vmx_vpid(void)
 831 {
 832         return vmcs_config.cpu_based_2nd_exec_ctrl &
 833                 SECONDARY_EXEC_ENABLE_VPID;
 834 }
 835
 836 static inline bool cpu_has_vmx_rdtscp(void)
 837 {
 838         return vmcs_config.cpu_based_2nd_exec_ctrl &
 839                 SECONDARY_EXEC_RDTSCP;
 840 }
 841
 842 static inline bool cpu_has_virtual_nmis(void)
 843 {
 844         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 845 }
 846
 847 static inline bool cpu_has_vmx_wbinvd_exit(void)
 848 {
 849         return vmcs_config.cpu_based_2nd_exec_ctrl &
 850                 SECONDARY_EXEC_WBINVD_EXITING;
 851 }
 852
 853 static inline bool report_flexpriority(void)
 854 {
 855         return flexpriority_enabled;
 856 }
 857
 858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 859 {
 860         return vmcs12->cpu_based_vm_exec_control & bit;
 861 }
 862
 863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 864 {
 865         return (vmcs12->cpu_based_vm_exec_control &
 866                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 867                 (vmcs12->secondary_vm_exec_control & bit);
 868 }
 869
 870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 871         struct kvm_vcpu *vcpu)
 872 {
 873         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 874 }
 875
 876 static inline bool is_exception(u32 intr_info)
 877 {
 878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 879                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 880 }
 881
 882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 884                         struct vmcs12 *vmcs12,
 885                         u32 reason, unsigned long qualification);
 886
 887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 888 {
 889         int i;
 890
 891         for (i = 0; i < vmx->nmsrs; ++i)
 892                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 893                         return i;
 894         return -1;
 895 }
 896
 897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 898 {
 899     struct {
 900         u64 vpid : 16;
 901         u64 rsvd : 48;
 902         u64 gva;
 903     } operand = { vpid, 0, gva };
 904
 905     asm volatile (__ex(ASM_VMX_INVVPID)
 906                   /* CF==1 or ZF==1 --> rc = -1 */
 907                   "; ja 1f ; ud2 ; 1:"
 908                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 909 }
 910
 911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 912 {
 913         struct {
 914                 u64 eptp, gpa;
 915         } operand = {eptp, gpa};
 916
 917         asm volatile (__ex(ASM_VMX_INVEPT)
 918                         /* CF==1 or ZF==1 --> rc = -1 */
 919                         "; ja 1f ; ud2 ; 1:\n"
 920                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 921 }
 922
 923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 924 {
 925         int i;
 926
 927         i = __find_msr_index(vmx, msr);
 928         if (i >= 0)
 929                 return &vmx->guest_msrs[i];
 930         return NULL;
 931 }
 932
 933 static void vmcs_clear(struct vmcs *vmcs)
 934 {
 935         u64 phys_addr = __pa(vmcs);
 936         u8 error;
 937
 938         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 939                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 940                       : "cc", "memory");
 941         if (error)
 942                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 943                        vmcs, phys_addr);
 944 }
 945
 946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 947 {
 948         vmcs_clear(loaded_vmcs->vmcs);
 949         loaded_vmcs->cpu = -1;
 950         loaded_vmcs->launched = 0;
 951 }
 952
 953 static void vmcs_load(struct vmcs *vmcs)
 954 {
 955         u64 phys_addr = __pa(vmcs);
 956         u8 error;
 957
 958         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 959                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 960                         : "cc", "memory");
 961         if (error)
 962                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 963                        vmcs, phys_addr);
 964 }
 965
 966 static void __loaded_vmcs_clear(void *arg)
 967 {
 968         struct loaded_vmcs *loaded_vmcs = arg;
 969         int cpu = raw_smp_processor_id();
 970
 971         if (loaded_vmcs->cpu != cpu)
 972                 return; /* vcpu migration can race with cpu offline */
 973         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 974                 per_cpu(current_vmcs, cpu) = NULL;
 975         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 976         loaded_vmcs_init(loaded_vmcs);
 977 }
 978
 979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 980 {
 981         if (loaded_vmcs->cpu != -1)
 982                 smp_call_function_single(
 983                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 984 }
 985
 986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 987 {
 988         if (vmx->vpid == 0)
 989                 return;
 990
 991         if (cpu_has_vmx_invvpid_single())
 992                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 993 }
 994
 995 static inline void vpid_sync_vcpu_global(void)
 996 {
 997         if (cpu_has_vmx_invvpid_global())
 998                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 999 }
1000
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002 {
1003         if (cpu_has_vmx_invvpid_single())
1004                 vpid_sync_vcpu_single(vmx);
1005         else
1006                 vpid_sync_vcpu_global();
1007 }
1008
1009 static inline void ept_sync_global(void)
1010 {
1011         if (cpu_has_vmx_invept_global())
1012                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013 }
1014
1015 static inline void ept_sync_context(u64 eptp)
1016 {
1017         if (enable_ept) {
1018                 if (cpu_has_vmx_invept_context())
1019                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020                 else
1021                         ept_sync_global();
1022         }
1023 }
1024
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026 {
1027         if (enable_ept) {
1028                 if (cpu_has_vmx_invept_individual_addr())
1029                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030                                         eptp, gpa);
1031                 else
1032                         ept_sync_context(eptp);
1033         }
1034 }
1035
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1037 {
1038         unsigned long value;
1039
1040         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041                       : "=a"(value) : "d"(field) : "cc");
1042         return value;
1043 }
1044
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1046 {
1047         return vmcs_readl(field);
1048 }
1049
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1051 {
1052         return vmcs_readl(field);
1053 }
1054
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1056 {
1057 #ifdef CONFIG_X86_64
1058         return vmcs_readl(field);
1059 #else
1060         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061 #endif
1062 }
1063
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065 {
1066         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068         dump_stack();
1069 }
1070
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1072 {
1073         u8 error;
1074
1075         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1077         if (unlikely(error))
1078                 vmwrite_error(field, value);
1079 }
1080
1081 static void vmcs_write16(unsigned long field, u16 value)
1082 {
1083         vmcs_writel(field, value);
1084 }
1085
1086 static void vmcs_write32(unsigned long field, u32 value)
1087 {
1088         vmcs_writel(field, value);
1089 }
1090
1091 static void vmcs_write64(unsigned long field, u64 value)
1092 {
1093         vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1095         asm volatile ("");
1096         vmcs_writel(field+1, value >> 32);
1097 #endif
1098 }
1099
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1101 {
1102         vmcs_writel(field, vmcs_readl(field) & ~mask);
1103 }
1104
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1106 {
1107         vmcs_writel(field, vmcs_readl(field) | mask);
1108 }
1109
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111 {
1112         vmx->segment_cache.bitmask = 0;
1113 }
1114
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116                                        unsigned field)
1117 {
1118         bool ret;
1119         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123                 vmx->segment_cache.bitmask = 0;
1124         }
1125         ret = vmx->segment_cache.bitmask & mask;
1126         vmx->segment_cache.bitmask |= mask;
1127         return ret;
1128 }
1129
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131 {
1132         u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136         return *p;
1137 }
1138
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140 {
1141         ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145         return *p;
1146 }
1147
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149 {
1150         u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154         return *p;
1155 }
1156
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163         return *p;
1164 }
1165
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167 {
1168         u32 eb;
1169
1170         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172         if ((vcpu->guest_debug &
1173              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175                 eb |= 1u << BP_VECTOR;
1176         if (to_vmx(vcpu)->rmode.vm86_active)
1177                 eb = ~0;
1178         if (enable_ept)
1179                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180         if (vcpu->fpu_active)
1181                 eb &= ~(1u << NM_VECTOR);
1182
1183         /* When we are running a nested L2 guest and L1 specified for it a
1184          * certain exception bitmap, we must trap the same exceptions and pass
1185          * them to L1. When running L2, we will only handle the exceptions
1186          * specified above if L1 did not want them.
1187          */
1188         if (is_guest_mode(vcpu))
1189                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1190
1191         vmcs_write32(EXCEPTION_BITMAP, eb);
1192 }
1193
1194 static void clear_atomic_switch_msr_special(unsigned long entry,
1195                 unsigned long exit)
1196 {
1197         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1198         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1199 }
1200
1201 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1202 {
1203         unsigned i;
1204         struct msr_autoload *m = &vmx->msr_autoload;
1205
1206         switch (msr) {
1207         case MSR_EFER:
1208                 if (cpu_has_load_ia32_efer) {
1209                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1210                                         VM_EXIT_LOAD_IA32_EFER);
1211                         return;
1212                 }
1213                 break;
1214         case MSR_CORE_PERF_GLOBAL_CTRL:
1215                 if (cpu_has_load_perf_global_ctrl) {
1216                         clear_atomic_switch_msr_special(
1217                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1218                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1219                         return;
1220                 }
1221                 break;
1222         }
1223
1224         for (i = 0; i < m->nr; ++i)
1225                 if (m->guest[i].index == msr)
1226                         break;
1227
1228         if (i == m->nr)
1229                 return;
1230         --m->nr;
1231         m->guest[i] = m->guest[m->nr];
1232         m->host[i] = m->host[m->nr];
1233         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1234         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1235 }
1236
1237 static void add_atomic_switch_msr_special(unsigned long entry,
1238                 unsigned long exit, unsigned long guest_val_vmcs,
1239                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1240 {
1241         vmcs_write64(guest_val_vmcs, guest_val);
1242         vmcs_write64(host_val_vmcs, host_val);
1243         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1244         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1245 }
1246
1247 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1248                                   u64 guest_val, u64 host_val)
1249 {
1250         unsigned i;
1251         struct msr_autoload *m = &vmx->msr_autoload;
1252
1253         switch (msr) {
1254         case MSR_EFER:
1255                 if (cpu_has_load_ia32_efer) {
1256                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1257                                         VM_EXIT_LOAD_IA32_EFER,
1258                                         GUEST_IA32_EFER,
1259                                         HOST_IA32_EFER,
1260                                         guest_val, host_val);
1261                         return;
1262                 }
1263                 break;
1264         case MSR_CORE_PERF_GLOBAL_CTRL:
1265                 if (cpu_has_load_perf_global_ctrl) {
1266                         add_atomic_switch_msr_special(
1267                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1268                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1269                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1270                                         HOST_IA32_PERF_GLOBAL_CTRL,
1271                                         guest_val, host_val);
1272                         return;
1273                 }
1274                 break;
1275         }
1276
1277         for (i = 0; i < m->nr; ++i)
1278                 if (m->guest[i].index == msr)
1279                         break;
1280
1281         if (i == NR_AUTOLOAD_MSRS) {
1282                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1283                                 "Can't add msr %x\n", msr);
1284                 return;
1285         } else if (i == m->nr) {
1286                 ++m->nr;
1287                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1288                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1289         }
1290
1291         m->guest[i].index = msr;
1292         m->guest[i].value = guest_val;
1293         m->host[i].index = msr;
1294         m->host[i].value = host_val;
1295 }
1296
1297 static void reload_tss(void)
1298 {
1299         /*
1300          * VT restores TR but not its size.  Useless.
1301          */
1302         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1303         struct desc_struct *descs;
1304
1305         descs = (void *)gdt->address;
1306         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1307         load_TR_desc();
1308 }
1309
1310 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1311 {
1312         u64 guest_efer;
1313         u64 ignore_bits;
1314
1315         guest_efer = vmx->vcpu.arch.efer;
1316
1317         /*
1318          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1319          * outside long mode
1320          */
1321         ignore_bits = EFER_NX | EFER_SCE;
1322 #ifdef CONFIG_X86_64
1323         ignore_bits |= EFER_LMA | EFER_LME;
1324         /* SCE is meaningful only in long mode on Intel */
1325         if (guest_efer & EFER_LMA)
1326                 ignore_bits &= ~(u64)EFER_SCE;
1327 #endif
1328         guest_efer &= ~ignore_bits;
1329         guest_efer |= host_efer & ignore_bits;
1330         vmx->guest_msrs[efer_offset].data = guest_efer;
1331         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1332
1333         clear_atomic_switch_msr(vmx, MSR_EFER);
1334         /* On ept, can't emulate nx, and must switch nx atomically */
1335         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1336                 guest_efer = vmx->vcpu.arch.efer;
1337                 if (!(guest_efer & EFER_LMA))
1338                         guest_efer &= ~EFER_LME;
1339                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1340                 return false;
1341         }
1342
1343         return true;
1344 }
1345
1346 static unsigned long segment_base(u16 selector)
1347 {
1348         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1349         struct desc_struct *d;
1350         unsigned long table_base;
1351         unsigned long v;
1352
1353         if (!(selector & ~3))
1354                 return 0;
1355
1356         table_base = gdt->address;
1357
1358         if (selector & 4) {           /* from ldt */
1359                 u16 ldt_selector = kvm_read_ldt();
1360
1361                 if (!(ldt_selector & ~3))
1362                         return 0;
1363
1364                 table_base = segment_base(ldt_selector);
1365         }
1366         d = (struct desc_struct *)(table_base + (selector & ~7));
1367         v = get_desc_base(d);
1368 #ifdef CONFIG_X86_64
1369        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1370                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1371 #endif
1372         return v;
1373 }
1374
1375 static inline unsigned long kvm_read_tr_base(void)
1376 {
1377         u16 tr;
1378         asm("str %0" : "=g"(tr));
1379         return segment_base(tr);
1380 }
1381
1382 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1383 {
1384         struct vcpu_vmx *vmx = to_vmx(vcpu);
1385         int i;
1386
1387         if (vmx->host_state.loaded)
1388                 return;
1389
1390         vmx->host_state.loaded = 1;
1391         /*
1392          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1393          * allow segment selectors with cpl > 0 or ti == 1.
1394          */
1395         vmx->host_state.ldt_sel = kvm_read_ldt();
1396         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1397         savesegment(fs, vmx->host_state.fs_sel);
1398         if (!(vmx->host_state.fs_sel & 7)) {
1399                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1400                 vmx->host_state.fs_reload_needed = 0;
1401         } else {
1402                 vmcs_write16(HOST_FS_SELECTOR, 0);
1403                 vmx->host_state.fs_reload_needed = 1;
1404         }
1405         savesegment(gs, vmx->host_state.gs_sel);
1406         if (!(vmx->host_state.gs_sel & 7))
1407                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1408         else {
1409                 vmcs_write16(HOST_GS_SELECTOR, 0);
1410                 vmx->host_state.gs_ldt_reload_needed = 1;
1411         }
1412
1413 #ifdef CONFIG_X86_64
1414         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1415         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1416 #else
1417         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1418         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1419 #endif
1420
1421 #ifdef CONFIG_X86_64
1422         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1423         if (is_long_mode(&vmx->vcpu))
1424                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1425 #endif
1426         for (i = 0; i < vmx->save_nmsrs; ++i)
1427                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1428                                    vmx->guest_msrs[i].data,
1429                                    vmx->guest_msrs[i].mask);
1430 }
1431
1432 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1433 {
1434         if (!vmx->host_state.loaded)
1435                 return;
1436
1437         ++vmx->vcpu.stat.host_state_reload;
1438         vmx->host_state.loaded = 0;
1439 #ifdef CONFIG_X86_64
1440         if (is_long_mode(&vmx->vcpu))
1441                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1442 #endif
1443         if (vmx->host_state.gs_ldt_reload_needed) {
1444                 kvm_load_ldt(vmx->host_state.ldt_sel);
1445 #ifdef CONFIG_X86_64
1446                 load_gs_index(vmx->host_state.gs_sel);
1447 #else
1448                 loadsegment(gs, vmx->host_state.gs_sel);
1449 #endif
1450         }
1451         if (vmx->host_state.fs_reload_needed)
1452                 loadsegment(fs, vmx->host_state.fs_sel);
1453         reload_tss();
1454 #ifdef CONFIG_X86_64
1455         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1456 #endif
1457         if (__thread_has_fpu(current))
1458                 clts();
1459         load_gdt(&__get_cpu_var(host_gdt));
1460 }
1461
1462 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1463 {
1464         preempt_disable();
1465         __vmx_load_host_state(vmx);
1466         preempt_enable();
1467 }
1468
1469 /*
1470  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1471  * vcpu mutex is already taken.
1472  */
1473 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1474 {
1475         struct vcpu_vmx *vmx = to_vmx(vcpu);
1476         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1477
1478         if (!vmm_exclusive)
1479                 kvm_cpu_vmxon(phys_addr);
1480         else if (vmx->loaded_vmcs->cpu != cpu)
1481                 loaded_vmcs_clear(vmx->loaded_vmcs);
1482
1483         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1484                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1485                 vmcs_load(vmx->loaded_vmcs->vmcs);
1486         }
1487
1488         if (vmx->loaded_vmcs->cpu != cpu) {
1489                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1490                 unsigned long sysenter_esp;
1491
1492                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1493                 local_irq_disable();
1494                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1495                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1496                 local_irq_enable();
1497
1498                 /*
1499                  * Linux uses per-cpu TSS and GDT, so set these when switching
1500                  * processors.
1501                  */
1502                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1503                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1504
1505                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1506                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1507                 vmx->loaded_vmcs->cpu = cpu;
1508         }
1509 }
1510
1511 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1512 {
1513         __vmx_load_host_state(to_vmx(vcpu));
1514         if (!vmm_exclusive) {
1515                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1516                 vcpu->cpu = -1;
1517                 kvm_cpu_vmxoff();
1518         }
1519 }
1520
1521 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1522 {
1523         ulong cr0;
1524
1525         if (vcpu->fpu_active)
1526                 return;
1527         vcpu->fpu_active = 1;
1528         cr0 = vmcs_readl(GUEST_CR0);
1529         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1530         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1531         vmcs_writel(GUEST_CR0, cr0);
1532         update_exception_bitmap(vcpu);
1533         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1534         if (is_guest_mode(vcpu))
1535                 vcpu->arch.cr0_guest_owned_bits &=
1536                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1537         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1538 }
1539
1540 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1541
1542 /*
1543  * Return the cr0 value that a nested guest would read. This is a combination
1544  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1545  * its hypervisor (cr0_read_shadow).
1546  */
1547 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1548 {
1549         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1550                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1551 }
1552 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1553 {
1554         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1555                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1556 }
1557
1558 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1559 {
1560         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1561          * set this *before* calling this function.
1562          */
1563         vmx_decache_cr0_guest_bits(vcpu);
1564         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1565         update_exception_bitmap(vcpu);
1566         vcpu->arch.cr0_guest_owned_bits = 0;
1567         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1568         if (is_guest_mode(vcpu)) {
1569                 /*
1570                  * L1's specified read shadow might not contain the TS bit,
1571                  * so now that we turned on shadowing of this bit, we need to
1572                  * set this bit of the shadow. Like in nested_vmx_run we need
1573                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1574                  * up-to-date here because we just decached cr0.TS (and we'll
1575                  * only update vmcs12->guest_cr0 on nested exit).
1576                  */
1577                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1578                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1579                         (vcpu->arch.cr0 & X86_CR0_TS);
1580                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1581         } else
1582                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1583 }
1584
1585 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1586 {
1587         unsigned long rflags, save_rflags;
1588
1589         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1590                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1591                 rflags = vmcs_readl(GUEST_RFLAGS);
1592                 if (to_vmx(vcpu)->rmode.vm86_active) {
1593                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1594                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1595                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1596                 }
1597                 to_vmx(vcpu)->rflags = rflags;
1598         }
1599         return to_vmx(vcpu)->rflags;
1600 }
1601
1602 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1603 {
1604         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1605         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1606         to_vmx(vcpu)->rflags = rflags;
1607         if (to_vmx(vcpu)->rmode.vm86_active) {
1608                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1609                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1610         }
1611         vmcs_writel(GUEST_RFLAGS, rflags);
1612 }
1613
1614 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1615 {
1616         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1617         int ret = 0;
1618
1619         if (interruptibility & GUEST_INTR_STATE_STI)
1620                 ret |= KVM_X86_SHADOW_INT_STI;
1621         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1622                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1623
1624         return ret & mask;
1625 }
1626
1627 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1628 {
1629         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1630         u32 interruptibility = interruptibility_old;
1631
1632         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1633
1634         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1635                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1636         else if (mask & KVM_X86_SHADOW_INT_STI)
1637                 interruptibility |= GUEST_INTR_STATE_STI;
1638
1639         if ((interruptibility != interruptibility_old))
1640                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1641 }
1642
1643 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1644 {
1645         unsigned long rip;
1646
1647         rip = kvm_rip_read(vcpu);
1648         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1649         kvm_rip_write(vcpu, rip);
1650
1651         /* skipping an emulated instruction also counts */
1652         vmx_set_interrupt_shadow(vcpu, 0);
1653 }
1654
1655 /*
1656  * KVM wants to inject page-faults which it got to the guest. This function
1657  * checks whether in a nested guest, we need to inject them to L1 or L2.
1658  * This function assumes it is called with the exit reason in vmcs02 being
1659  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1660  * is running).
1661  */
1662 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1663 {
1664         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1665
1666         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1667         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1668                 return 0;
1669
1670         nested_vmx_vmexit(vcpu);
1671         return 1;
1672 }
1673
1674 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1675                                 bool has_error_code, u32 error_code,
1676                                 bool reinject)
1677 {
1678         struct vcpu_vmx *vmx = to_vmx(vcpu);
1679         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1680
1681         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1682                 nested_pf_handled(vcpu))
1683                 return;
1684
1685         if (has_error_code) {
1686                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1687                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1688         }
1689
1690         if (vmx->rmode.vm86_active) {
1691                 int inc_eip = 0;
1692                 if (kvm_exception_is_soft(nr))
1693                         inc_eip = vcpu->arch.event_exit_inst_len;
1694                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1695                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1696                 return;
1697         }
1698
1699         if (kvm_exception_is_soft(nr)) {
1700                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1701                              vmx->vcpu.arch.event_exit_inst_len);
1702                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1703         } else
1704                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1705
1706         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1707 }
1708
1709 static bool vmx_rdtscp_supported(void)
1710 {
1711         return cpu_has_vmx_rdtscp();
1712 }
1713
1714 /*
1715  * Swap MSR entry in host/guest MSR entry array.
1716  */
1717 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1718 {
1719         struct shared_msr_entry tmp;
1720
1721         tmp = vmx->guest_msrs[to];
1722         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1723         vmx->guest_msrs[from] = tmp;
1724 }
1725
1726 /*
1727  * Set up the vmcs to automatically save and restore system
1728  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1729  * mode, as fiddling with msrs is very expensive.
1730  */
1731 static void setup_msrs(struct vcpu_vmx *vmx)
1732 {
1733         int save_nmsrs, index;
1734         unsigned long *msr_bitmap;
1735
1736         save_nmsrs = 0;
1737 #ifdef CONFIG_X86_64
1738         if (is_long_mode(&vmx->vcpu)) {
1739                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1740                 if (index >= 0)
1741                         move_msr_up(vmx, index, save_nmsrs++);
1742                 index = __find_msr_index(vmx, MSR_LSTAR);
1743                 if (index >= 0)
1744                         move_msr_up(vmx, index, save_nmsrs++);
1745                 index = __find_msr_index(vmx, MSR_CSTAR);
1746                 if (index >= 0)
1747                         move_msr_up(vmx, index, save_nmsrs++);
1748                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1749                 if (index >= 0 && vmx->rdtscp_enabled)
1750                         move_msr_up(vmx, index, save_nmsrs++);
1751                 /*
1752                  * MSR_STAR is only needed on long mode guests, and only
1753                  * if efer.sce is enabled.
1754                  */
1755                 index = __find_msr_index(vmx, MSR_STAR);
1756                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1757                         move_msr_up(vmx, index, save_nmsrs++);
1758         }
1759 #endif
1760         index = __find_msr_index(vmx, MSR_EFER);
1761         if (index >= 0 && update_transition_efer(vmx, index))
1762                 move_msr_up(vmx, index, save_nmsrs++);
1763
1764         vmx->save_nmsrs = save_nmsrs;
1765
1766         if (cpu_has_vmx_msr_bitmap()) {
1767                 if (is_long_mode(&vmx->vcpu))
1768                         msr_bitmap = vmx_msr_bitmap_longmode;
1769                 else
1770                         msr_bitmap = vmx_msr_bitmap_legacy;
1771
1772                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1773         }
1774 }
1775
1776 /*
1777  * reads and returns guest's timestamp counter "register"
1778  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1779  */
1780 static u64 guest_read_tsc(void)
1781 {
1782         u64 host_tsc, tsc_offset;
1783
1784         rdtscll(host_tsc);
1785         tsc_offset = vmcs_read64(TSC_OFFSET);
1786         return host_tsc + tsc_offset;
1787 }
1788
1789 /*
1790  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1791  * counter, even if a nested guest (L2) is currently running.
1792  */
1793 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1794 {
1795         u64 host_tsc, tsc_offset;
1796
1797         rdtscll(host_tsc);
1798         tsc_offset = is_guest_mode(vcpu) ?
1799                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1800                 vmcs_read64(TSC_OFFSET);
1801         return host_tsc + tsc_offset;
1802 }
1803
1804 /*
1805  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1806  * software catchup for faster rates on slower CPUs.
1807  */
1808 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1809 {
1810         if (!scale)
1811                 return;
1812
1813         if (user_tsc_khz > tsc_khz) {
1814                 vcpu->arch.tsc_catchup = 1;
1815                 vcpu->arch.tsc_always_catchup = 1;
1816         } else
1817                 WARN(1, "user requested TSC rate below hardware speed\n");
1818 }
1819
1820 /*
1821  * writes 'offset' into guest's timestamp counter offset register
1822  */
1823 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1824 {
1825         if (is_guest_mode(vcpu)) {
1826                 /*
1827                  * We're here if L1 chose not to trap WRMSR to TSC. According
1828                  * to the spec, this should set L1's TSC; The offset that L1
1829                  * set for L2 remains unchanged, and still needs to be added
1830                  * to the newly set TSC to get L2's TSC.
1831                  */
1832                 struct vmcs12 *vmcs12;
1833                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1834                 /* recalculate vmcs02.TSC_OFFSET: */
1835                 vmcs12 = get_vmcs12(vcpu);
1836                 vmcs_write64(TSC_OFFSET, offset +
1837                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1838                          vmcs12->tsc_offset : 0));
1839         } else {
1840                 vmcs_write64(TSC_OFFSET, offset);
1841         }
1842 }
1843
1844 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1845 {
1846         u64 offset = vmcs_read64(TSC_OFFSET);
1847         vmcs_write64(TSC_OFFSET, offset + adjustment);
1848         if (is_guest_mode(vcpu)) {
1849                 /* Even when running L2, the adjustment needs to apply to L1 */
1850                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1851         }
1852 }
1853
1854 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1855 {
1856         return target_tsc - native_read_tsc();
1857 }
1858
1859 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1860 {
1861         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1862         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1863 }
1864
1865 /*
1866  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1867  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1868  * all guests if the "nested" module option is off, and can also be disabled
1869  * for a single guest by disabling its VMX cpuid bit.
1870  */
1871 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1872 {
1873         return nested && guest_cpuid_has_vmx(vcpu);
1874 }
1875
1876 /*
1877  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1878  * returned for the various VMX controls MSRs when nested VMX is enabled.
1879  * The same values should also be used to verify that vmcs12 control fields are
1880  * valid during nested entry from L1 to L2.
1881  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1882  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1883  * bit in the high half is on if the corresponding bit in the control field
1884  * may be on. See also vmx_control_verify().
1885  * TODO: allow these variables to be modified (downgraded) by module options
1886  * or other means.
1887  */
1888 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1889 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1890 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1891 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1892 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1893 static __init void nested_vmx_setup_ctls_msrs(void)
1894 {
1895         /*
1896          * Note that as a general rule, the high half of the MSRs (bits in
1897          * the control fields which may be 1) should be initialized by the
1898          * intersection of the underlying hardware's MSR (i.e., features which
1899          * can be supported) and the list of features we want to expose -
1900          * because they are known to be properly supported in our code.
1901          * Also, usually, the low half of the MSRs (bits which must be 1) can
1902          * be set to 0, meaning that L1 may turn off any of these bits. The
1903          * reason is that if one of these bits is necessary, it will appear
1904          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1905          * fields of vmcs01 and vmcs02, will turn these bits off - and
1906          * nested_vmx_exit_handled() will not pass related exits to L1.
1907          * These rules have exceptions below.
1908          */
1909
1910         /* pin-based controls */
1911         /*
1912          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1913          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1914          */
1915         nested_vmx_pinbased_ctls_low = 0x16 ;
1916         nested_vmx_pinbased_ctls_high = 0x16 |
1917                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1918                 PIN_BASED_VIRTUAL_NMIS;
1919
1920         /* exit controls */
1921         nested_vmx_exit_ctls_low = 0;
1922         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1923 #ifdef CONFIG_X86_64
1924         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1925 #else
1926         nested_vmx_exit_ctls_high = 0;
1927 #endif
1928
1929         /* entry controls */
1930         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1931                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1932         nested_vmx_entry_ctls_low = 0;
1933         nested_vmx_entry_ctls_high &=
1934                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1935
1936         /* cpu-based controls */
1937         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1938                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1939         nested_vmx_procbased_ctls_low = 0;
1940         nested_vmx_procbased_ctls_high &=
1941                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1942                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1943                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1944                 CPU_BASED_CR3_STORE_EXITING |
1945 #ifdef CONFIG_X86_64
1946                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1947 #endif
1948                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1949                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1950                 CPU_BASED_RDPMC_EXITING |
1951                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1952         /*
1953          * We can allow some features even when not supported by the
1954          * hardware. For example, L1 can specify an MSR bitmap - and we
1955          * can use it to avoid exits to L1 - even when L0 runs L2
1956          * without MSR bitmaps.
1957          */
1958         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1959
1960         /* secondary cpu-based controls */
1961         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1962                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1963         nested_vmx_secondary_ctls_low = 0;
1964         nested_vmx_secondary_ctls_high &=
1965                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1966 }
1967
1968 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1969 {
1970         /*
1971          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1972          */
1973         return ((control & high) | low) == control;
1974 }
1975
1976 static inline u64 vmx_control_msr(u32 low, u32 high)
1977 {
1978         return low | ((u64)high << 32);
1979 }
1980
1981 /*
1982  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1983  * also let it use VMX-specific MSRs.
1984  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1985  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1986  * like all other MSRs).
1987  */
1988 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1989 {
1990         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1991                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1992                 /*
1993                  * According to the spec, processors which do not support VMX
1994                  * should throw a #GP(0) when VMX capability MSRs are read.
1995                  */
1996                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1997                 return 1;
1998         }
1999
2000         switch (msr_index) {
2001         case MSR_IA32_FEATURE_CONTROL:
2002                 *pdata = 0;
2003                 break;
2004         case MSR_IA32_VMX_BASIC:
2005                 /*
2006                  * This MSR reports some information about VMX support. We
2007                  * should return information about the VMX we emulate for the
2008                  * guest, and the VMCS structure we give it - not about the
2009                  * VMX support of the underlying hardware.
2010                  */
2011                 *pdata = VMCS12_REVISION |
2012                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2013                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2014                 break;
2015         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2016         case MSR_IA32_VMX_PINBASED_CTLS:
2017                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2018                                         nested_vmx_pinbased_ctls_high);
2019                 break;
2020         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2021         case MSR_IA32_VMX_PROCBASED_CTLS:
2022                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2023                                         nested_vmx_procbased_ctls_high);
2024                 break;
2025         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2026         case MSR_IA32_VMX_EXIT_CTLS:
2027                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2028                                         nested_vmx_exit_ctls_high);
2029                 break;
2030         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2031         case MSR_IA32_VMX_ENTRY_CTLS:
2032                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2033                                         nested_vmx_entry_ctls_high);
2034                 break;
2035         case MSR_IA32_VMX_MISC:
2036                 *pdata = 0;
2037                 break;
2038         /*
2039          * These MSRs specify bits which the guest must keep fixed (on or off)
2040          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2041          * We picked the standard core2 setting.
2042          */
2043 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2044 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2045         case MSR_IA32_VMX_CR0_FIXED0:
2046                 *pdata = VMXON_CR0_ALWAYSON;
2047                 break;
2048         case MSR_IA32_VMX_CR0_FIXED1:
2049                 *pdata = -1ULL;
2050                 break;
2051         case MSR_IA32_VMX_CR4_FIXED0:
2052                 *pdata = VMXON_CR4_ALWAYSON;
2053                 break;
2054         case MSR_IA32_VMX_CR4_FIXED1:
2055                 *pdata = -1ULL;
2056                 break;
2057         case MSR_IA32_VMX_VMCS_ENUM:
2058                 *pdata = 0x1f;
2059                 break;
2060         case MSR_IA32_VMX_PROCBASED_CTLS2:
2061                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2062                                         nested_vmx_secondary_ctls_high);
2063                 break;
2064         case MSR_IA32_VMX_EPT_VPID_CAP:
2065                 /* Currently, no nested ept or nested vpid */
2066                 *pdata = 0;
2067                 break;
2068         default:
2069                 return 0;
2070         }
2071
2072         return 1;
2073 }
2074
2075 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2076 {
2077         if (!nested_vmx_allowed(vcpu))
2078                 return 0;
2079
2080         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2081                 /* TODO: the right thing. */
2082                 return 1;
2083         /*
2084          * No need to treat VMX capability MSRs specially: If we don't handle
2085          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2086          */
2087         return 0;
2088 }
2089
2090 /*
2091  * Reads an msr value (of 'msr_index') into 'pdata'.
2092  * Returns 0 on success, non-0 otherwise.
2093  * Assumes vcpu_load() was already called.
2094  */
2095 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2096 {
2097         u64 data;
2098         struct shared_msr_entry *msr;
2099
2100         if (!pdata) {
2101                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2102                 return -EINVAL;
2103         }
2104
2105         switch (msr_index) {
2106 #ifdef CONFIG_X86_64
2107         case MSR_FS_BASE:
2108                 data = vmcs_readl(GUEST_FS_BASE);
2109                 break;
2110         case MSR_GS_BASE:
2111                 data = vmcs_readl(GUEST_GS_BASE);
2112                 break;
2113         case MSR_KERNEL_GS_BASE:
2114                 vmx_load_host_state(to_vmx(vcpu));
2115                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2116                 break;
2117 #endif
2118         case MSR_EFER:
2119                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2120         case MSR_IA32_TSC:
2121                 data = guest_read_tsc();
2122                 break;
2123         case MSR_IA32_SYSENTER_CS:
2124                 data = vmcs_read32(GUEST_SYSENTER_CS);
2125                 break;
2126         case MSR_IA32_SYSENTER_EIP:
2127                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2128                 break;
2129         case MSR_IA32_SYSENTER_ESP:
2130                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2131                 break;
2132         case MSR_TSC_AUX:
2133                 if (!to_vmx(vcpu)->rdtscp_enabled)
2134                         return 1;
2135                 /* Otherwise falls through */
2136         default:
2137                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2138                         return 0;
2139                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2140                 if (msr) {
2141                         data = msr->data;
2142                         break;
2143                 }
2144                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2145         }
2146
2147         *pdata = data;
2148         return 0;
2149 }
2150
2151 /*
2152  * Writes msr value into into the appropriate "register".
2153  * Returns 0 on success, non-0 otherwise.
2154  * Assumes vcpu_load() was already called.
2155  */
2156 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2157 {
2158         struct vcpu_vmx *vmx = to_vmx(vcpu);
2159         struct shared_msr_entry *msr;
2160         int ret = 0;
2161
2162         switch (msr_index) {
2163         case MSR_EFER:
2164                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2165                 break;
2166 #ifdef CONFIG_X86_64
2167         case MSR_FS_BASE:
2168                 vmx_segment_cache_clear(vmx);
2169                 vmcs_writel(GUEST_FS_BASE, data);
2170                 break;
2171         case MSR_GS_BASE:
2172                 vmx_segment_cache_clear(vmx);
2173                 vmcs_writel(GUEST_GS_BASE, data);
2174                 break;
2175         case MSR_KERNEL_GS_BASE:
2176                 vmx_load_host_state(vmx);
2177                 vmx->msr_guest_kernel_gs_base = data;
2178                 break;
2179 #endif
2180         case MSR_IA32_SYSENTER_CS:
2181                 vmcs_write32(GUEST_SYSENTER_CS, data);
2182                 break;
2183         case MSR_IA32_SYSENTER_EIP:
2184                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2185                 break;
2186         case MSR_IA32_SYSENTER_ESP:
2187                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2188                 break;
2189         case MSR_IA32_TSC:
2190                 kvm_write_tsc(vcpu, data);
2191                 break;
2192         case MSR_IA32_CR_PAT:
2193                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2194                         vmcs_write64(GUEST_IA32_PAT, data);
2195                         vcpu->arch.pat = data;
2196                         break;
2197                 }
2198                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2199                 break;
2200         case MSR_TSC_AUX:
2201                 if (!vmx->rdtscp_enabled)
2202                         return 1;
2203                 /* Check reserved bit, higher 32 bits should be zero */
2204                 if ((data >> 32) != 0)
2205                         return 1;
2206                 /* Otherwise falls through */
2207         default:
2208                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2209                         break;
2210                 msr = find_msr_entry(vmx, msr_index);
2211                 if (msr) {
2212                         msr->data = data;
2213                         if (msr - vmx->guest_msrs < vmx->save_nmsrs)
2214                                 kvm_set_shared_msr(msr->index, msr->data,
2215                                                    msr->mask);
2216                         break;
2217                 }
2218                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2219         }
2220
2221         return ret;
2222 }
2223
2224 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2225 {
2226         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2227         switch (reg) {
2228         case VCPU_REGS_RSP:
2229                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2230                 break;
2231         case VCPU_REGS_RIP:
2232                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2233                 break;
2234         case VCPU_EXREG_PDPTR:
2235                 if (enable_ept)
2236                         ept_save_pdptrs(vcpu);
2237                 break;
2238         default:
2239                 break;
2240         }
2241 }
2242
2243 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2244 {
2245         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2246                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2247         else
2248                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2249
2250         update_exception_bitmap(vcpu);
2251 }
2252
2253 static __init int cpu_has_kvm_support(void)
2254 {
2255         return cpu_has_vmx();
2256 }
2257
2258 static __init int vmx_disabled_by_bios(void)
2259 {
2260         u64 msr;
2261
2262         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2263         if (msr & FEATURE_CONTROL_LOCKED) {
2264                 /* launched w/ TXT and VMX disabled */
2265                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2266                         && tboot_enabled())
2267                         return 1;
2268                 /* launched w/o TXT and VMX only enabled w/ TXT */
2269                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2270                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2271                         && !tboot_enabled()) {
2272                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2273                                 "activate TXT before enabling KVM\n");
2274                         return 1;
2275                 }
2276                 /* launched w/o TXT and VMX disabled */
2277                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2278                         && !tboot_enabled())
2279                         return 1;
2280         }
2281
2282         return 0;
2283 }
2284
2285 static void kvm_cpu_vmxon(u64 addr)
2286 {
2287         asm volatile (ASM_VMX_VMXON_RAX
2288                         : : "a"(&addr), "m"(addr)
2289                         : "memory", "cc");
2290 }
2291
2292 static int hardware_enable(void *garbage)
2293 {
2294         int cpu = raw_smp_processor_id();
2295         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2296         u64 old, test_bits;
2297
2298         if (read_cr4() & X86_CR4_VMXE)
2299                 return -EBUSY;
2300
2301         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2302         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2303
2304         test_bits = FEATURE_CONTROL_LOCKED;
2305         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2306         if (tboot_enabled())
2307                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2308
2309         if ((old & test_bits) != test_bits) {
2310                 /* enable and lock */
2311                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2312         }
2313         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2314
2315         if (vmm_exclusive) {
2316                 kvm_cpu_vmxon(phys_addr);
2317                 ept_sync_global();
2318         }
2319
2320         store_gdt(&__get_cpu_var(host_gdt));
2321
2322         return 0;
2323 }
2324
2325 static void vmclear_local_loaded_vmcss(void)
2326 {
2327         int cpu = raw_smp_processor_id();
2328         struct loaded_vmcs *v, *n;
2329
2330         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2331                                  loaded_vmcss_on_cpu_link)
2332                 __loaded_vmcs_clear(v);
2333 }
2334
2335
2336 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2337  * tricks.
2338  */
2339 static void kvm_cpu_vmxoff(void)
2340 {
2341         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2342 }
2343
2344 static void hardware_disable(void *garbage)
2345 {
2346         if (vmm_exclusive) {
2347                 vmclear_local_loaded_vmcss();
2348                 kvm_cpu_vmxoff();
2349         }
2350         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2351 }
2352
2353 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2354                                       u32 msr, u32 *result)
2355 {
2356         u32 vmx_msr_low, vmx_msr_high;
2357         u32 ctl = ctl_min | ctl_opt;
2358
2359         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2360
2361         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2362         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2363
2364         /* Ensure minimum (required) set of control bits are supported. */
2365         if (ctl_min & ~ctl)
2366                 return -EIO;
2367
2368         *result = ctl;
2369         return 0;
2370 }
2371
2372 static __init bool allow_1_setting(u32 msr, u32 ctl)
2373 {
2374         u32 vmx_msr_low, vmx_msr_high;
2375
2376         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2377         return vmx_msr_high & ctl;
2378 }
2379
2380 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2381 {
2382         u32 vmx_msr_low, vmx_msr_high;
2383         u32 min, opt, min2, opt2;
2384         u32 _pin_based_exec_control = 0;
2385         u32 _cpu_based_exec_control = 0;
2386         u32 _cpu_based_2nd_exec_control = 0;
2387         u32 _vmexit_control = 0;
2388         u32 _vmentry_control = 0;
2389
2390         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2391         opt = PIN_BASED_VIRTUAL_NMIS;
2392         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2393                                 &_pin_based_exec_control) < 0)
2394                 return -EIO;
2395
2396         min = CPU_BASED_HLT_EXITING |
2397 #ifdef CONFIG_X86_64
2398               CPU_BASED_CR8_LOAD_EXITING |
2399               CPU_BASED_CR8_STORE_EXITING |
2400 #endif
2401               CPU_BASED_CR3_LOAD_EXITING |
2402               CPU_BASED_CR3_STORE_EXITING |
2403               CPU_BASED_USE_IO_BITMAPS |
2404               CPU_BASED_MOV_DR_EXITING |
2405               CPU_BASED_USE_TSC_OFFSETING |
2406               CPU_BASED_MWAIT_EXITING |
2407               CPU_BASED_MONITOR_EXITING |
2408               CPU_BASED_INVLPG_EXITING |
2409               CPU_BASED_RDPMC_EXITING;
2410
2411         opt = CPU_BASED_TPR_SHADOW |
2412               CPU_BASED_USE_MSR_BITMAPS |
2413               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2414         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2415                                 &_cpu_based_exec_control) < 0)
2416                 return -EIO;
2417 #ifdef CONFIG_X86_64
2418         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2419                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2420                                            ~CPU_BASED_CR8_STORE_EXITING;
2421 #endif
2422         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2423                 min2 = 0;
2424                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2425                         SECONDARY_EXEC_WBINVD_EXITING |
2426                         SECONDARY_EXEC_ENABLE_VPID |
2427                         SECONDARY_EXEC_ENABLE_EPT |
2428                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2429                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2430                         SECONDARY_EXEC_RDTSCP;
2431                 if (adjust_vmx_controls(min2, opt2,
2432                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2433                                         &_cpu_based_2nd_exec_control) < 0)
2434                         return -EIO;
2435         }
2436 #ifndef CONFIG_X86_64
2437         if (!(_cpu_based_2nd_exec_control &
2438                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2439                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2440 #endif
2441         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2442                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2443                    enabled */
2444                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2445                                              CPU_BASED_CR3_STORE_EXITING |
2446                                              CPU_BASED_INVLPG_EXITING);
2447                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2448                       vmx_capability.ept, vmx_capability.vpid);
2449         }
2450
2451         min = 0;
2452 #ifdef CONFIG_X86_64
2453         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2454 #endif
2455         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2456         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2457                                 &_vmexit_control) < 0)
2458                 return -EIO;
2459
2460         min = 0;
2461         opt = VM_ENTRY_LOAD_IA32_PAT;
2462         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2463                                 &_vmentry_control) < 0)
2464                 return -EIO;
2465
2466         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2467
2468         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2469         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2470                 return -EIO;
2471
2472 #ifdef CONFIG_X86_64
2473         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2474         if (vmx_msr_high & (1u<<16))
2475                 return -EIO;
2476 #endif
2477
2478         /* Require Write-Back (WB) memory type for VMCS accesses. */
2479         if (((vmx_msr_high >> 18) & 15) != 6)
2480                 return -EIO;
2481
2482         vmcs_conf->size = vmx_msr_high & 0x1fff;
2483         vmcs_conf->order = get_order(vmcs_config.size);
2484         vmcs_conf->revision_id = vmx_msr_low;
2485
2486         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2487         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2488         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2489         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2490         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2491
2492         cpu_has_load_ia32_efer =
2493                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2494                                 VM_ENTRY_LOAD_IA32_EFER)
2495                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2496                                    VM_EXIT_LOAD_IA32_EFER);
2497
2498         cpu_has_load_perf_global_ctrl =
2499                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2500                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2501                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2502                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2503
2504         /*
2505          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2506          * but due to arrata below it can't be used. Workaround is to use
2507          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2508          *
2509          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2510          *
2511          * AAK155             (model 26)
2512          * AAP115             (model 30)
2513          * AAT100             (model 37)
2514          * BC86,AAY89,BD102   (model 44)
2515          * BA97               (model 46)
2516          *
2517          */
2518         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2519                 switch (boot_cpu_data.x86_model) {
2520                 case 26:
2521                 case 30:
2522                 case 37:
2523                 case 44:
2524                 case 46:
2525                         cpu_has_load_perf_global_ctrl = false;
2526                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2527                                         "does not work properly. Using workaround\n");
2528                         break;
2529                 default:
2530                         break;
2531                 }
2532         }
2533
2534         return 0;
2535 }
2536
2537 static struct vmcs *alloc_vmcs_cpu(int cpu)
2538 {
2539         int node = cpu_to_node(cpu);
2540         struct page *pages;
2541         struct vmcs *vmcs;
2542
2543         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2544         if (!pages)
2545                 return NULL;
2546         vmcs = page_address(pages);
2547         memset(vmcs, 0, vmcs_config.size);
2548         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2549         return vmcs;
2550 }
2551
2552 static struct vmcs *alloc_vmcs(void)
2553 {
2554         return alloc_vmcs_cpu(raw_smp_processor_id());
2555 }
2556
2557 static void free_vmcs(struct vmcs *vmcs)
2558 {
2559         free_pages((unsigned long)vmcs, vmcs_config.order);
2560 }
2561
2562 /*
2563  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2564  */
2565 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2566 {
2567         if (!loaded_vmcs->vmcs)
2568                 return;
2569         loaded_vmcs_clear(loaded_vmcs);
2570         free_vmcs(loaded_vmcs->vmcs);
2571         loaded_vmcs->vmcs = NULL;
2572 }
2573
2574 static void free_kvm_area(void)
2575 {
2576         int cpu;
2577
2578         for_each_possible_cpu(cpu) {
2579                 free_vmcs(per_cpu(vmxarea, cpu));
2580                 per_cpu(vmxarea, cpu) = NULL;
2581         }
2582 }
2583
2584 static __init int alloc_kvm_area(void)
2585 {
2586         int cpu;
2587
2588         for_each_possible_cpu(cpu) {
2589                 struct vmcs *vmcs;
2590
2591                 vmcs = alloc_vmcs_cpu(cpu);
2592                 if (!vmcs) {
2593                         free_kvm_area();
2594                         return -ENOMEM;
2595                 }
2596
2597                 per_cpu(vmxarea, cpu) = vmcs;
2598         }
2599         return 0;
2600 }
2601
2602 static __init int hardware_setup(void)
2603 {
2604         if (setup_vmcs_config(&vmcs_config) < 0)
2605                 return -EIO;
2606
2607         if (boot_cpu_has(X86_FEATURE_NX))
2608                 kvm_enable_efer_bits(EFER_NX);
2609
2610         if (!cpu_has_vmx_vpid())
2611                 enable_vpid = 0;
2612
2613         if (!cpu_has_vmx_ept() ||
2614             !cpu_has_vmx_ept_4levels()) {
2615                 enable_ept = 0;
2616                 enable_unrestricted_guest = 0;
2617         }
2618
2619         if (!cpu_has_vmx_unrestricted_guest())
2620                 enable_unrestricted_guest = 0;
2621
2622         if (!cpu_has_vmx_flexpriority())
2623                 flexpriority_enabled = 0;
2624
2625         if (!cpu_has_vmx_tpr_shadow())
2626                 kvm_x86_ops->update_cr8_intercept = NULL;
2627
2628         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2629                 kvm_disable_largepages();
2630
2631         if (!cpu_has_vmx_ple())
2632                 ple_gap = 0;
2633
2634         if (nested)
2635                 nested_vmx_setup_ctls_msrs();
2636
2637         return alloc_kvm_area();
2638 }
2639
2640 static __exit void hardware_unsetup(void)
2641 {
2642         free_kvm_area();
2643 }
2644
2645 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2646 {
2647         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2648
2649         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2650                 vmcs_write16(sf->selector, save->selector);
2651                 vmcs_writel(sf->base, save->base);
2652                 vmcs_write32(sf->limit, save->limit);
2653                 vmcs_write32(sf->ar_bytes, save->ar);
2654         } else {
2655                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2656                         << AR_DPL_SHIFT;
2657                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2658         }
2659 }
2660
2661 static void enter_pmode(struct kvm_vcpu *vcpu)
2662 {
2663         unsigned long flags;
2664         struct vcpu_vmx *vmx = to_vmx(vcpu);
2665
2666         vmx->emulation_required = 1;
2667         vmx->rmode.vm86_active = 0;
2668
2669         vmx_segment_cache_clear(vmx);
2670
2671         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2672         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2673         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2674         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2675
2676         flags = vmcs_readl(GUEST_RFLAGS);
2677         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2678         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2679         vmcs_writel(GUEST_RFLAGS, flags);
2680
2681         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2682                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2683
2684         update_exception_bitmap(vcpu);
2685
2686         if (emulate_invalid_guest_state)
2687                 return;
2688
2689         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2690         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2691         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2692         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2693
2694         vmx_segment_cache_clear(vmx);
2695
2696         vmcs_write16(GUEST_SS_SELECTOR, 0);
2697         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2698
2699         vmcs_write16(GUEST_CS_SELECTOR,
2700                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2701         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2702 }
2703
2704 static gva_t rmode_tss_base(struct kvm *kvm)
2705 {
2706         if (!kvm->arch.tss_addr) {
2707                 struct kvm_memslots *slots;
2708                 struct kvm_memory_slot *slot;
2709                 gfn_t base_gfn;
2710
2711                 slots = kvm_memslots(kvm);
2712                 slot = id_to_memslot(slots, 0);
2713                 base_gfn = slot->base_gfn + slot->npages - 3;
2714
2715                 return base_gfn << PAGE_SHIFT;
2716         }
2717         return kvm->arch.tss_addr;
2718 }
2719
2720 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2721 {
2722         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2723
2724         save->selector = vmcs_read16(sf->selector);
2725         save->base = vmcs_readl(sf->base);
2726         save->limit = vmcs_read32(sf->limit);
2727         save->ar = vmcs_read32(sf->ar_bytes);
2728         vmcs_write16(sf->selector, save->base >> 4);
2729         vmcs_write32(sf->base, save->base & 0xffff0);
2730         vmcs_write32(sf->limit, 0xffff);
2731         vmcs_write32(sf->ar_bytes, 0xf3);
2732         if (save->base & 0xf)
2733                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2734                             " aligned when entering protected mode (seg=%d)",
2735                             seg);
2736 }
2737
2738 static void enter_rmode(struct kvm_vcpu *vcpu)
2739 {
2740         unsigned long flags;
2741         struct vcpu_vmx *vmx = to_vmx(vcpu);
2742
2743         if (enable_unrestricted_guest)
2744                 return;
2745
2746         vmx->emulation_required = 1;
2747         vmx->rmode.vm86_active = 1;
2748
2749         /*
2750          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2751          * vcpu. Call it here with phys address pointing 16M below 4G.
2752          */
2753         if (!vcpu->kvm->arch.tss_addr) {
2754                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2755                              "called before entering vcpu\n");
2756                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2757                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2758                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2759         }
2760
2761         vmx_segment_cache_clear(vmx);
2762
2763         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2764         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2765         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2766
2767         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2768         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2769
2770         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2771         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2772
2773         flags = vmcs_readl(GUEST_RFLAGS);
2774         vmx->rmode.save_rflags = flags;
2775
2776         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2777
2778         vmcs_writel(GUEST_RFLAGS, flags);
2779         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2780         update_exception_bitmap(vcpu);
2781
2782         if (emulate_invalid_guest_state)
2783                 goto continue_rmode;
2784
2785         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2786         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2787         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2788
2789         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2790         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2791         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2792                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2793         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2794
2795         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2796         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2797         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2798         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2799
2800 continue_rmode:
2801         kvm_mmu_reset_context(vcpu);
2802 }
2803
2804 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2805 {
2806         struct vcpu_vmx *vmx = to_vmx(vcpu);
2807         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2808
2809         if (!msr)
2810                 return;
2811
2812         /*
2813          * Force kernel_gs_base reloading before EFER changes, as control
2814          * of this msr depends on is_long_mode().
2815          */
2816         vmx_load_host_state(to_vmx(vcpu));
2817         vcpu->arch.efer = efer;
2818         if (efer & EFER_LMA) {
2819                 vmcs_write32(VM_ENTRY_CONTROLS,
2820                              vmcs_read32(VM_ENTRY_CONTROLS) |
2821                              VM_ENTRY_IA32E_MODE);
2822                 msr->data = efer;
2823         } else {
2824                 vmcs_write32(VM_ENTRY_CONTROLS,
2825                              vmcs_read32(VM_ENTRY_CONTROLS) &
2826                              ~VM_ENTRY_IA32E_MODE);
2827
2828                 msr->data = efer & ~EFER_LME;
2829         }
2830         setup_msrs(vmx);
2831 }
2832
2833 #ifdef CONFIG_X86_64
2834
2835 static void enter_lmode(struct kvm_vcpu *vcpu)
2836 {
2837         u32 guest_tr_ar;
2838
2839         vmx_segment_cache_clear(to_vmx(vcpu));
2840
2841         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2842         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2843                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2844                                      __func__);
2845                 vmcs_write32(GUEST_TR_AR_BYTES,
2846                              (guest_tr_ar & ~AR_TYPE_MASK)
2847                              | AR_TYPE_BUSY_64_TSS);
2848         }
2849         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2850 }
2851
2852 static void exit_lmode(struct kvm_vcpu *vcpu)
2853 {
2854         vmcs_write32(VM_ENTRY_CONTROLS,
2855                      vmcs_read32(VM_ENTRY_CONTROLS)
2856                      & ~VM_ENTRY_IA32E_MODE);
2857         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2858 }
2859
2860 #endif
2861
2862 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2863 {
2864         vpid_sync_context(to_vmx(vcpu));
2865         if (enable_ept) {
2866                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2867                         return;
2868                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2869         }
2870 }
2871
2872 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2873 {
2874         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2875
2876         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2877         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2878 }
2879
2880 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2881 {
2882         if (enable_ept && is_paging(vcpu))
2883                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2884         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2885 }
2886
2887 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2888 {
2889         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2890
2891         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2892         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2893 }
2894
2895 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2896 {
2897         if (!test_bit(VCPU_EXREG_PDPTR,
2898                       (unsigned long *)&vcpu->arch.regs_dirty))
2899                 return;
2900
2901         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2902                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2903                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2904                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2905                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2906         }
2907 }
2908
2909 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2910 {
2911         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2912                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2913                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2914                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2915                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2916         }
2917
2918         __set_bit(VCPU_EXREG_PDPTR,
2919                   (unsigned long *)&vcpu->arch.regs_avail);
2920         __set_bit(VCPU_EXREG_PDPTR,
2921                   (unsigned long *)&vcpu->arch.regs_dirty);
2922 }
2923
2924 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2925
2926 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2927                                         unsigned long cr0,
2928                                         struct kvm_vcpu *vcpu)
2929 {
2930         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2931                 vmx_decache_cr3(vcpu);
2932         if (!(cr0 & X86_CR0_PG)) {
2933                 /* From paging/starting to nonpaging */
2934                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2935                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2936                              (CPU_BASED_CR3_LOAD_EXITING |
2937                               CPU_BASED_CR3_STORE_EXITING));
2938                 vcpu->arch.cr0 = cr0;
2939                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2940         } else if (!is_paging(vcpu)) {
2941                 /* From nonpaging to paging */
2942                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2943                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2944                              ~(CPU_BASED_CR3_LOAD_EXITING |
2945                                CPU_BASED_CR3_STORE_EXITING));
2946                 vcpu->arch.cr0 = cr0;
2947                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2948         }
2949
2950         if (!(cr0 & X86_CR0_WP))
2951                 *hw_cr0 &= ~X86_CR0_WP;
2952 }
2953
2954 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2955 {
2956         struct vcpu_vmx *vmx = to_vmx(vcpu);
2957         unsigned long hw_cr0;
2958
2959         if (enable_unrestricted_guest)
2960                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2961                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2962         else
2963                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2964
2965         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2966                 enter_pmode(vcpu);
2967
2968         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2969                 enter_rmode(vcpu);
2970
2971 #ifdef CONFIG_X86_64
2972         if (vcpu->arch.efer & EFER_LME) {
2973                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2974                         enter_lmode(vcpu);
2975                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2976                         exit_lmode(vcpu);
2977         }
2978 #endif
2979
2980         if (enable_ept)
2981                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2982
2983         if (!vcpu->fpu_active)
2984                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2985
2986         vmcs_writel(CR0_READ_SHADOW, cr0);
2987         vmcs_writel(GUEST_CR0, hw_cr0);
2988         vcpu->arch.cr0 = cr0;
2989         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2990 }
2991
2992 static u64 construct_eptp(unsigned long root_hpa)
2993 {
2994         u64 eptp;
2995
2996         /* TODO write the value reading from MSR */
2997         eptp = VMX_EPT_DEFAULT_MT |
2998                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2999         eptp |= (root_hpa & PAGE_MASK);
3000
3001         return eptp;
3002 }
3003
3004 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3005 {
3006         unsigned long guest_cr3;
3007         u64 eptp;
3008
3009         guest_cr3 = cr3;
3010         if (enable_ept) {
3011                 eptp = construct_eptp(cr3);
3012                 vmcs_write64(EPT_POINTER, eptp);
3013                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3014                         vcpu->kvm->arch.ept_identity_map_addr;
3015                 ept_load_pdptrs(vcpu);
3016         }
3017
3018         vmx_flush_tlb(vcpu);
3019         vmcs_writel(GUEST_CR3, guest_cr3);
3020 }
3021
3022 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3023 {
3024         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3025                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3026
3027         if (cr4 & X86_CR4_VMXE) {
3028                 /*
3029                  * To use VMXON (and later other VMX instructions), a guest
3030                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3031                  * So basically the check on whether to allow nested VMX
3032                  * is here.
3033                  */
3034                 if (!nested_vmx_allowed(vcpu))
3035                         return 1;
3036         } else if (to_vmx(vcpu)->nested.vmxon)
3037                 return 1;
3038
3039         vcpu->arch.cr4 = cr4;
3040         if (enable_ept) {
3041                 if (!is_paging(vcpu)) {
3042                         hw_cr4 &= ~X86_CR4_PAE;
3043                         hw_cr4 |= X86_CR4_PSE;
3044                 } else if (!(cr4 & X86_CR4_PAE)) {
3045                         hw_cr4 &= ~X86_CR4_PAE;
3046                 }
3047         }
3048
3049         vmcs_writel(CR4_READ_SHADOW, cr4);
3050         vmcs_writel(GUEST_CR4, hw_cr4);
3051         return 0;
3052 }
3053
3054 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3055                             struct kvm_segment *var, int seg)
3056 {
3057         struct vcpu_vmx *vmx = to_vmx(vcpu);
3058         struct kvm_save_segment *save;
3059         u32 ar;
3060
3061         if (vmx->rmode.vm86_active
3062             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3063                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3064                 || seg == VCPU_SREG_GS)
3065             && !emulate_invalid_guest_state) {
3066                 switch (seg) {
3067                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3068                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3069                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3070                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3071                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3072                 default: BUG();
3073                 }
3074                 var->selector = save->selector;
3075                 var->base = save->base;
3076                 var->limit = save->limit;
3077                 ar = save->ar;
3078                 if (seg == VCPU_SREG_TR
3079                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3080                         goto use_saved_rmode_seg;
3081         }
3082         var->base = vmx_read_guest_seg_base(vmx, seg);
3083         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3084         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3085         ar = vmx_read_guest_seg_ar(vmx, seg);
3086 use_saved_rmode_seg:
3087         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3088                 ar = 0;
3089         var->type = ar & 15;
3090         var->s = (ar >> 4) & 1;
3091         var->dpl = (ar >> 5) & 3;
3092         var->present = (ar >> 7) & 1;
3093         var->avl = (ar >> 12) & 1;
3094         var->l = (ar >> 13) & 1;
3095         var->db = (ar >> 14) & 1;
3096         var->g = (ar >> 15) & 1;
3097         var->unusable = (ar >> 16) & 1;
3098 }
3099
3100 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3101 {
3102         struct kvm_segment s;
3103
3104         if (to_vmx(vcpu)->rmode.vm86_active) {
3105                 vmx_get_segment(vcpu, &s, seg);
3106                 return s.base;
3107         }
3108         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3109 }
3110
3111 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3112 {
3113         if (!is_protmode(vcpu))
3114                 return 0;
3115
3116         if (!is_long_mode(vcpu)
3117             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3118                 return 3;
3119
3120         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3121 }
3122
3123 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3124 {
3125         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3126                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3127                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3128         }
3129         return to_vmx(vcpu)->cpl;
3130 }
3131
3132
3133 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3134 {
3135         u32 ar;
3136
3137         if (var->unusable)
3138                 ar = 1 << 16;
3139         else {
3140                 ar = var->type & 15;
3141                 ar |= (var->s & 1) << 4;
3142                 ar |= (var->dpl & 3) << 5;
3143                 ar |= (var->present & 1) << 7;
3144                 ar |= (var->avl & 1) << 12;
3145                 ar |= (var->l & 1) << 13;
3146                 ar |= (var->db & 1) << 14;
3147                 ar |= (var->g & 1) << 15;
3148         }
3149         if (ar == 0) /* a 0 value means unusable */
3150                 ar = AR_UNUSABLE_MASK;
3151
3152         return ar;
3153 }
3154
3155 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3156                             struct kvm_segment *var, int seg)
3157 {
3158         struct vcpu_vmx *vmx = to_vmx(vcpu);
3159         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3160         u32 ar;
3161
3162         vmx_segment_cache_clear(vmx);
3163
3164         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3165                 vmcs_write16(sf->selector, var->selector);
3166                 vmx->rmode.tr.selector = var->selector;
3167                 vmx->rmode.tr.base = var->base;
3168                 vmx->rmode.tr.limit = var->limit;
3169                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3170                 return;
3171         }
3172         vmcs_writel(sf->base, var->base);
3173         vmcs_write32(sf->limit, var->limit);
3174         vmcs_write16(sf->selector, var->selector);
3175         if (vmx->rmode.vm86_active && var->s) {
3176                 /*
3177                  * Hack real-mode segments into vm86 compatibility.
3178                  */
3179                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3180                         vmcs_writel(sf->base, 0xf0000);
3181                 ar = 0xf3;
3182         } else
3183                 ar = vmx_segment_access_rights(var);
3184
3185         /*
3186          *   Fix the "Accessed" bit in AR field of segment registers for older
3187          * qemu binaries.
3188          *   IA32 arch specifies that at the time of processor reset the
3189          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3190          * is setting it to 0 in the usedland code. This causes invalid guest
3191          * state vmexit when "unrestricted guest" mode is turned on.
3192          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3193          * tree. Newer qemu binaries with that qemu fix would not need this
3194          * kvm hack.
3195          */
3196         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3197                 ar |= 0x1; /* Accessed */
3198
3199         vmcs_write32(sf->ar_bytes, ar);
3200         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3201 }
3202
3203 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3204 {
3205         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3206
3207         *db = (ar >> 14) & 1;
3208         *l = (ar >> 13) & 1;
3209 }
3210
3211 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3212 {
3213         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3214         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3215 }
3216
3217 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3218 {
3219         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3220         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3221 }
3222
3223 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3224 {
3225         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3226         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3227 }
3228
3229 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3230 {
3231         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3232         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3233 }
3234
3235 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3236 {
3237         struct kvm_segment var;
3238         u32 ar;
3239
3240         vmx_get_segment(vcpu, &var, seg);
3241         ar = vmx_segment_access_rights(&var);
3242
3243         if (var.base != (var.selector << 4))
3244                 return false;
3245         if (var.limit != 0xffff)
3246                 return false;
3247         if (ar != 0xf3)
3248                 return false;
3249
3250         return true;
3251 }
3252
3253 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3254 {
3255         struct kvm_segment cs;
3256         unsigned int cs_rpl;
3257
3258         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3259         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3260
3261         if (cs.unusable)
3262                 return false;
3263         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3264                 return false;
3265         if (!cs.s)
3266                 return false;
3267         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3268                 if (cs.dpl > cs_rpl)
3269                         return false;
3270         } else {
3271                 if (cs.dpl != cs_rpl)
3272                         return false;
3273         }
3274         if (!cs.present)
3275                 return false;
3276
3277         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3278         return true;
3279 }
3280
3281 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3282 {
3283         struct kvm_segment ss;
3284         unsigned int ss_rpl;
3285
3286         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3287         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3288
3289         if (ss.unusable)
3290                 return true;
3291         if (ss.type != 3 && ss.type != 7)
3292                 return false;
3293         if (!ss.s)
3294                 return false;
3295         if (ss.dpl != ss_rpl) /* DPL != RPL */
3296                 return false;
3297         if (!ss.present)
3298                 return false;
3299
3300         return true;
3301 }
3302
3303 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3304 {
3305         struct kvm_segment var;
3306         unsigned int rpl;
3307
3308         vmx_get_segment(vcpu, &var, seg);
3309         rpl = var.selector & SELECTOR_RPL_MASK;
3310
3311         if (var.unusable)
3312                 return true;
3313         if (!var.s)
3314                 return false;
3315         if (!var.present)
3316                 return false;
3317         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3318                 if (var.dpl < rpl) /* DPL < RPL */
3319                         return false;
3320         }
3321
3322         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3323          * rights flags
3324          */
3325         return true;
3326 }
3327
3328 static bool tr_valid(struct kvm_vcpu *vcpu)
3329 {
3330         struct kvm_segment tr;
3331
3332         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3333
3334         if (tr.unusable)
3335                 return false;
3336         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3337                 return false;
3338         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3339                 return false;
3340         if (!tr.present)
3341                 return false;
3342
3343         return true;
3344 }
3345
3346 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3347 {
3348         struct kvm_segment ldtr;
3349
3350         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3351
3352         if (ldtr.unusable)
3353                 return true;
3354         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3355                 return false;
3356         if (ldtr.type != 2)
3357                 return false;
3358         if (!ldtr.present)
3359                 return false;
3360
3361         return true;
3362 }
3363
3364 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3365 {
3366         struct kvm_segment cs, ss;
3367
3368         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3369         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3370
3371         return ((cs.selector & SELECTOR_RPL_MASK) ==
3372                  (ss.selector & SELECTOR_RPL_MASK));
3373 }
3374
3375 /*
3376  * Check if guest state is valid. Returns true if valid, false if
3377  * not.
3378  * We assume that registers are always usable
3379  */
3380 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3381 {
3382         /* real mode guest state checks */
3383         if (!is_protmode(vcpu)) {
3384                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3385                         return false;
3386                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3387                         return false;
3388                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3389                         return false;
3390                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3391                         return false;
3392                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3393                         return false;
3394                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3395                         return false;
3396         } else {
3397         /* protected mode guest state checks */
3398                 if (!cs_ss_rpl_check(vcpu))
3399                         return false;
3400                 if (!code_segment_valid(vcpu))
3401                         return false;
3402                 if (!stack_segment_valid(vcpu))
3403                         return false;
3404                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3405                         return false;
3406                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3407                         return false;
3408                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3409                         return false;
3410                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3411                         return false;
3412                 if (!tr_valid(vcpu))
3413                         return false;
3414                 if (!ldtr_valid(vcpu))
3415                         return false;
3416         }
3417         /* TODO:
3418          * - Add checks on RIP
3419          * - Add checks on RFLAGS
3420          */
3421
3422         return true;
3423 }
3424
3425 static int init_rmode_tss(struct kvm *kvm)
3426 {
3427         gfn_t fn;
3428         u16 data = 0;
3429         int r, idx, ret = 0;
3430
3431         idx = srcu_read_lock(&kvm->srcu);
3432         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3433         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3434         if (r < 0)
3435                 goto out;
3436         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3437         r = kvm_write_guest_page(kvm, fn++, &data,
3438                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3439         if (r < 0)
3440                 goto out;
3441         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3442         if (r < 0)
3443                 goto out;
3444         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3445         if (r < 0)
3446                 goto out;
3447         data = ~0;
3448         r = kvm_write_guest_page(kvm, fn, &data,
3449                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3450                                  sizeof(u8));
3451         if (r < 0)
3452                 goto out;
3453
3454         ret = 1;
3455 out:
3456         srcu_read_unlock(&kvm->srcu, idx);
3457         return ret;
3458 }
3459
3460 static int init_rmode_identity_map(struct kvm *kvm)
3461 {
3462         int i, idx, r, ret;
3463         pfn_t identity_map_pfn;
3464         u32 tmp;
3465
3466         if (!enable_ept)
3467                 return 1;
3468         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3469                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3470                         "haven't been allocated!\n");
3471                 return 0;
3472         }
3473         if (likely(kvm->arch.ept_identity_pagetable_done))
3474                 return 1;
3475         ret = 0;
3476         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3477         idx = srcu_read_lock(&kvm->srcu);
3478         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3479         if (r < 0)
3480                 goto out;
3481         /* Set up identity-mapping pagetable for EPT in real mode */
3482         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3483                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3484                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3485                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3486                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3487                 if (r < 0)
3488                         goto out;
3489         }
3490         kvm->arch.ept_identity_pagetable_done = true;
3491         ret = 1;
3492 out:
3493         srcu_read_unlock(&kvm->srcu, idx);
3494         return ret;
3495 }
3496
3497 static void seg_setup(int seg)
3498 {
3499         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3500         unsigned int ar;
3501
3502         vmcs_write16(sf->selector, 0);
3503         vmcs_writel(sf->base, 0);
3504         vmcs_write32(sf->limit, 0xffff);
3505         if (enable_unrestricted_guest) {
3506                 ar = 0x93;
3507                 if (seg == VCPU_SREG_CS)
3508                         ar |= 0x08; /* code segment */
3509         } else
3510                 ar = 0xf3;