arch/x86/kvm/x86.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * derived from drivers/kvm/kvm_main.c
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright (C) 2008 Qumranet, Inc.
   8  * Copyright IBM Corporation, 2008
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Amit Shah    <amit.shah@qumranet.com>
  15  *   Ben-Ami Yassour <benami@il.ibm.com>
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  *
  20  */
  21
  22 #include <linux/kvm_host.h>
  23 #include "irq.h"
  24 #include "mmu.h"
  25 #include "i8254.h"
  26 #include "tss.h"
  27 #include "kvm_cache_regs.h"
  28 #include "x86.h"
  29 #include "cpuid.h"
  30
  31 #include <linux/clocksource.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/kvm.h>
  34 #include <linux/fs.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/module.h>
  37 #include <linux/mman.h>
  38 #include <linux/highmem.h>
  39 #include <linux/iommu.h>
  40 #include <linux/intel-iommu.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/user-return-notifier.h>
  43 #include <linux/srcu.h>
  44 #include <linux/slab.h>
  45 #include <linux/perf_event.h>
  46 #include <linux/uaccess.h>
  47 #include <linux/hash.h>
  48 #include <linux/pci.h>
  49 #include <trace/events/kvm.h>
  50
  51 #define CREATE_TRACE_POINTS
  52 #include "trace.h"
  53
  54 #include <asm/debugreg.h>
  55 #include <asm/msr.h>
  56 #include <asm/desc.h>
  57 #include <asm/mtrr.h>
  58 #include <asm/mce.h>
  59 #include <asm/i387.h>
  60 #include <asm/fpu-internal.h> /* Ugh! */
  61 #include <asm/xcr.h>
  62 #include <asm/pvclock.h>
  63 #include <asm/div64.h>
  64
  65 #define MAX_IO_MSRS 256
  66 #define KVM_MAX_MCE_BANKS 32
  67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
  68
  69 #define emul_to_vcpu(ctxt) \
  70         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
  71
  72 /* EFER defaults:
  73  * - enable syscall per default because its emulated by KVM
  74  * - enable LME and LMA per default on 64 bit KVM
  75  */
  76 #ifdef CONFIG_X86_64
  77 static
  78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  79 #else
  80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  81 #endif
  82
  83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
  84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
  85
  86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
  87 static void process_nmi(struct kvm_vcpu *vcpu);
  88
  89 struct kvm_x86_ops *kvm_x86_ops;
  90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
  91
  92 static bool ignore_msrs = 0;
  93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
  94
  95 bool kvm_has_tsc_control;
  96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
  97 u32  kvm_max_guest_tsc_khz;
  98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
  99
 100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 101 static u32 tsc_tolerance_ppm = 250;
 102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 103
 104 #define KVM_NR_SHARED_MSRS 16
 105
 106 struct kvm_shared_msrs_global {
 107         int nr;
 108         u32 msrs[KVM_NR_SHARED_MSRS];
 109 };
 110
 111 struct kvm_shared_msrs {
 112         struct user_return_notifier urn;
 113         bool registered;
 114         struct kvm_shared_msr_values {
 115                 u64 host;
 116                 u64 curr;
 117         } values[KVM_NR_SHARED_MSRS];
 118 };
 119
 120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
 122
 123 struct kvm_stats_debugfs_item debugfs_entries[] = {
 124         { "pf_fixed", VCPU_STAT(pf_fixed) },
 125         { "pf_guest", VCPU_STAT(pf_guest) },
 126         { "tlb_flush", VCPU_STAT(tlb_flush) },
 127         { "invlpg", VCPU_STAT(invlpg) },
 128         { "exits", VCPU_STAT(exits) },
 129         { "io_exits", VCPU_STAT(io_exits) },
 130         { "mmio_exits", VCPU_STAT(mmio_exits) },
 131         { "signal_exits", VCPU_STAT(signal_exits) },
 132         { "irq_window", VCPU_STAT(irq_window_exits) },
 133         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 134         { "halt_exits", VCPU_STAT(halt_exits) },
 135         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 136         { "hypercalls", VCPU_STAT(hypercalls) },
 137         { "request_irq", VCPU_STAT(request_irq_exits) },
 138         { "irq_exits", VCPU_STAT(irq_exits) },
 139         { "host_state_reload", VCPU_STAT(host_state_reload) },
 140         { "efer_reload", VCPU_STAT(efer_reload) },
 141         { "fpu_reload", VCPU_STAT(fpu_reload) },
 142         { "insn_emulation", VCPU_STAT(insn_emulation) },
 143         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 144         { "irq_injections", VCPU_STAT(irq_injections) },
 145         { "nmi_injections", VCPU_STAT(nmi_injections) },
 146         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 147         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 148         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 149         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 150         { "mmu_flooded", VM_STAT(mmu_flooded) },
 151         { "mmu_recycled", VM_STAT(mmu_recycled) },
 152         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 153         { "mmu_unsync", VM_STAT(mmu_unsync) },
 154         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 155         { "largepages", VM_STAT(lpages) },
 156         { NULL }
 157 };
 158
 159 u64 __read_mostly host_xcr0;
 160
 161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 162
 163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 164 {
 165         int i;
 166         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 167                 vcpu->arch.apf.gfns[i] = ~0;
 168 }
 169
 170 static void kvm_on_user_return(struct user_return_notifier *urn)
 171 {
 172         unsigned slot;
 173         struct kvm_shared_msrs *locals
 174                 = container_of(urn, struct kvm_shared_msrs, urn);
 175         struct kvm_shared_msr_values *values;
 176
 177         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 178                 values = &locals->values[slot];
 179                 if (values->host != values->curr) {
 180                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 181                         values->curr = values->host;
 182                 }
 183         }
 184         locals->registered = false;
 185         user_return_notifier_unregister(urn);
 186 }
 187
 188 static void shared_msr_update(unsigned slot, u32 msr)
 189 {
 190         struct kvm_shared_msrs *smsr;
 191         u64 value;
 192
 193         smsr = &__get_cpu_var(shared_msrs);
 194         /* only read, and nobody should modify it at this time,
 195          * so don't need lock */
 196         if (slot >= shared_msrs_global.nr) {
 197                 printk(KERN_ERR "kvm: invalid MSR slot!");
 198                 return;
 199         }
 200         rdmsrl_safe(msr, &value);
 201         smsr->values[slot].host = value;
 202         smsr->values[slot].curr = value;
 203 }
 204
 205 void kvm_define_shared_msr(unsigned slot, u32 msr)
 206 {
 207         if (slot >= shared_msrs_global.nr)
 208                 shared_msrs_global.nr = slot + 1;
 209         shared_msrs_global.msrs[slot] = msr;
 210         /* we need ensured the shared_msr_global have been updated */
 211         smp_wmb();
 212 }
 213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 214
 215 static void kvm_shared_msr_cpu_online(void)
 216 {
 217         unsigned i;
 218
 219         for (i = 0; i < shared_msrs_global.nr; ++i)
 220                 shared_msr_update(i, shared_msrs_global.msrs[i]);
 221 }
 222
 223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 224 {
 225         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
 226
 227         if (((value ^ smsr->values[slot].curr) & mask) == 0)
 228                 return;
 229         smsr->values[slot].curr = value;
 230         wrmsrl(shared_msrs_global.msrs[slot], value);
 231         if (!smsr->registered) {
 232                 smsr->urn.on_user_return = kvm_on_user_return;
 233                 user_return_notifier_register(&smsr->urn);
 234                 smsr->registered = true;
 235         }
 236 }
 237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 238
 239 static void drop_user_return_notifiers(void *ignore)
 240 {
 241         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
 242
 243         if (smsr->registered)
 244                 kvm_on_user_return(&smsr->urn);
 245 }
 246
 247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 248 {
 249         if (irqchip_in_kernel(vcpu->kvm))
 250                 return vcpu->arch.apic_base;
 251         else
 252                 return vcpu->arch.apic_base;
 253 }
 254 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 255
 256 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
 257 {
 258         /* TODO: reserve bits check */
 259         if (irqchip_in_kernel(vcpu->kvm))
 260                 kvm_lapic_set_base(vcpu, data);
 261         else
 262                 vcpu->arch.apic_base = data;
 263 }
 264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 265
 266 #define EXCPT_BENIGN            0
 267 #define EXCPT_CONTRIBUTORY      1
 268 #define EXCPT_PF                2
 269
 270 static int exception_class(int vector)
 271 {
 272         switch (vector) {
 273         case PF_VECTOR:
 274                 return EXCPT_PF;
 275         case DE_VECTOR:
 276         case TS_VECTOR:
 277         case NP_VECTOR:
 278         case SS_VECTOR:
 279         case GP_VECTOR:
 280                 return EXCPT_CONTRIBUTORY;
 281         default:
 282                 break;
 283         }
 284         return EXCPT_BENIGN;
 285 }
 286
 287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 288                 unsigned nr, bool has_error, u32 error_code,
 289                 bool reinject)
 290 {
 291         u32 prev_nr;
 292         int class1, class2;
 293
 294         kvm_make_request(KVM_REQ_EVENT, vcpu);
 295
 296         if (!vcpu->arch.exception.pending) {
 297         queue:
 298                 vcpu->arch.exception.pending = true;
 299                 vcpu->arch.exception.has_error_code = has_error;
 300                 vcpu->arch.exception.nr = nr;
 301                 vcpu->arch.exception.error_code = error_code;
 302                 vcpu->arch.exception.reinject = reinject;
 303                 return;
 304         }
 305
 306         /* to check exception */
 307         prev_nr = vcpu->arch.exception.nr;
 308         if (prev_nr == DF_VECTOR) {
 309                 /* triple fault -> shutdown */
 310                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 311                 return;
 312         }
 313         class1 = exception_class(prev_nr);
 314         class2 = exception_class(nr);
 315         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 316                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 317                 /* generate double fault per SDM Table 5-5 */
 318                 vcpu->arch.exception.pending = true;
 319                 vcpu->arch.exception.has_error_code = true;
 320                 vcpu->arch.exception.nr = DF_VECTOR;
 321                 vcpu->arch.exception.error_code = 0;
 322         } else
 323                 /* replace previous exception with a new one in a hope
 324                    that instruction re-execution will regenerate lost
 325                    exception */
 326                 goto queue;
 327 }
 328
 329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 330 {
 331         kvm_multiple_exception(vcpu, nr, false, 0, false);
 332 }
 333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 334
 335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 336 {
 337         kvm_multiple_exception(vcpu, nr, false, 0, true);
 338 }
 339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 340
 341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 342 {
 343         if (err)
 344                 kvm_inject_gp(vcpu, 0);
 345         else
 346                 kvm_x86_ops->skip_emulated_instruction(vcpu);
 347 }
 348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 349
 350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 351 {
 352         ++vcpu->stat.pf_guest;
 353         vcpu->arch.cr2 = fault->address;
 354         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 355 }
 356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 357
 358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 359 {
 360         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 361                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 362         else
 363                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
 364 }
 365
 366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 367 {
 368         atomic_inc(&vcpu->arch.nmi_queued);
 369         kvm_make_request(KVM_REQ_NMI, vcpu);
 370 }
 371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 372
 373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 374 {
 375         kvm_multiple_exception(vcpu, nr, true, error_code, false);
 376 }
 377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 378
 379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 380 {
 381         kvm_multiple_exception(vcpu, nr, true, error_code, true);
 382 }
 383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 384
 385 /*
 386  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 387  * a #GP and return false.
 388  */
 389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 390 {
 391         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
 392                 return true;
 393         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 394         return false;
 395 }
 396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 397
 398 /*
 399  * This function will be used to read from the physical memory of the currently
 400  * running guest. The difference to kvm_read_guest_page is that this function
 401  * can read from guest physical or from the guest's guest physical memory.
 402  */
 403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 404                             gfn_t ngfn, void *data, int offset, int len,
 405                             u32 access)
 406 {
 407         gfn_t real_gfn;
 408         gpa_t ngpa;
 409
 410         ngpa     = gfn_to_gpa(ngfn);
 411         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
 412         if (real_gfn == UNMAPPED_GVA)
 413                 return -EFAULT;
 414
 415         real_gfn = gpa_to_gfn(real_gfn);
 416
 417         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
 418 }
 419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 420
 421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 422                                void *data, int offset, int len, u32 access)
 423 {
 424         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 425                                        data, offset, len, access);
 426 }
 427
 428 /*
 429  * Load the pae pdptrs.  Return true is they are all valid.
 430  */
 431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 432 {
 433         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 434         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 435         int i;
 436         int ret;
 437         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 438
 439         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 440                                       offset * sizeof(u64), sizeof(pdpte),
 441                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 442         if (ret < 0) {
 443                 ret = 0;
 444                 goto out;
 445         }
 446         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 447                 if (is_present_gpte(pdpte[i]) &&
 448                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
 449                         ret = 0;
 450                         goto out;
 451                 }
 452         }
 453         ret = 1;
 454
 455         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 456         __set_bit(VCPU_EXREG_PDPTR,
 457                   (unsigned long *)&vcpu->arch.regs_avail);
 458         __set_bit(VCPU_EXREG_PDPTR,
 459                   (unsigned long *)&vcpu->arch.regs_dirty);
 460 out:
 461
 462         return ret;
 463 }
 464 EXPORT_SYMBOL_GPL(load_pdptrs);
 465
 466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
 467 {
 468         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 469         bool changed = true;
 470         int offset;
 471         gfn_t gfn;
 472         int r;
 473
 474         if (is_long_mode(vcpu) || !is_pae(vcpu))
 475                 return false;
 476
 477         if (!test_bit(VCPU_EXREG_PDPTR,
 478                       (unsigned long *)&vcpu->arch.regs_avail))
 479                 return true;
 480
 481         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
 482         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
 483         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 484                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 485         if (r < 0)
 486                 goto out;
 487         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 488 out:
 489
 490         return changed;
 491 }
 492
 493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 494 {
 495         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 496         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
 497                                     X86_CR0_CD | X86_CR0_NW;
 498
 499         cr0 |= X86_CR0_ET;
 500
 501 #ifdef CONFIG_X86_64
 502         if (cr0 & 0xffffffff00000000UL)
 503                 return 1;
 504 #endif
 505
 506         cr0 &= ~CR0_RESERVED_BITS;
 507
 508         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 509                 return 1;
 510
 511         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 512                 return 1;
 513
 514         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 515 #ifdef CONFIG_X86_64
 516                 if ((vcpu->arch.efer & EFER_LME)) {
 517                         int cs_db, cs_l;
 518
 519                         if (!is_pae(vcpu))
 520                                 return 1;
 521                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 522                         if (cs_l)
 523                                 return 1;
 524                 } else
 525 #endif
 526                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 527                                                  kvm_read_cr3(vcpu)))
 528                         return 1;
 529         }
 530
 531         kvm_x86_ops->set_cr0(vcpu, cr0);
 532
 533         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 534                 kvm_clear_async_pf_completion_queue(vcpu);
 535                 kvm_async_pf_hash_reset(vcpu);
 536         }
 537
 538         if ((cr0 ^ old_cr0) & update_bits)
 539                 kvm_mmu_reset_context(vcpu);
 540         return 0;
 541 }
 542 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 543
 544 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 545 {
 546         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 547 }
 548 EXPORT_SYMBOL_GPL(kvm_lmsw);
 549
 550 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 551 {
 552         u64 xcr0;
 553
 554         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 555         if (index != XCR_XFEATURE_ENABLED_MASK)
 556                 return 1;
 557         xcr0 = xcr;
 558         if (kvm_x86_ops->get_cpl(vcpu) != 0)
 559                 return 1;
 560         if (!(xcr0 & XSTATE_FP))
 561                 return 1;
 562         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
 563                 return 1;
 564         if (xcr0 & ~host_xcr0)
 565                 return 1;
 566         vcpu->arch.xcr0 = xcr0;
 567         vcpu->guest_xcr0_loaded = 0;
 568         return 0;
 569 }
 570
 571 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 572 {
 573         if (__kvm_set_xcr(vcpu, index, xcr)) {
 574                 kvm_inject_gp(vcpu, 0);
 575                 return 1;
 576         }
 577         return 0;
 578 }
 579 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 580
 581 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 582 {
 583         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 584         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
 585                                    X86_CR4_PAE | X86_CR4_SMEP;
 586         if (cr4 & CR4_RESERVED_BITS)
 587                 return 1;
 588
 589         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
 590                 return 1;
 591
 592         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
 593                 return 1;
 594
 595         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
 596                 return 1;
 597
 598         if (is_long_mode(vcpu)) {
 599                 if (!(cr4 & X86_CR4_PAE))
 600                         return 1;
 601         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 602                    && ((cr4 ^ old_cr4) & pdptr_bits)
 603                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 604                                    kvm_read_cr3(vcpu)))
 605                 return 1;
 606
 607         if (kvm_x86_ops->set_cr4(vcpu, cr4))
 608                 return 1;
 609
 610         if ((cr4 ^ old_cr4) & pdptr_bits)
 611                 kvm_mmu_reset_context(vcpu);
 612
 613         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
 614                 kvm_update_cpuid(vcpu);
 615
 616         return 0;
 617 }
 618 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 619
 620 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 621 {
 622         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
 623                 kvm_mmu_sync_roots(vcpu);
 624                 kvm_mmu_flush_tlb(vcpu);
 625                 return 0;
 626         }
 627
 628         if (is_long_mode(vcpu)) {
 629                 if (cr3 & CR3_L_MODE_RESERVED_BITS)
 630                         return 1;
 631         } else {
 632                 if (is_pae(vcpu)) {
 633                         if (cr3 & CR3_PAE_RESERVED_BITS)
 634                                 return 1;
 635                         if (is_paging(vcpu) &&
 636                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
 637                                 return 1;
 638                 }
 639                 /*
 640                  * We don't check reserved bits in nonpae mode, because
 641                  * this isn't enforced, and VMware depends on this.
 642                  */
 643         }
 644
 645         /*
 646          * Does the new cr3 value map to physical memory? (Note, we
 647          * catch an invalid cr3 even in real-mode, because it would
 648          * cause trouble later on when we turn on paging anyway.)
 649          *
 650          * A real CPU would silently accept an invalid cr3 and would
 651          * attempt to use it - with largely undefined (and often hard
 652          * to debug) behavior on the guest side.
 653          */
 654         if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
 655                 return 1;
 656         vcpu->arch.cr3 = cr3;
 657         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
 658         vcpu->arch.mmu.new_cr3(vcpu);
 659         return 0;
 660 }
 661 EXPORT_SYMBOL_GPL(kvm_set_cr3);
 662
 663 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 664 {
 665         if (cr8 & CR8_RESERVED_BITS)
 666                 return 1;
 667         if (irqchip_in_kernel(vcpu->kvm))
 668                 kvm_lapic_set_tpr(vcpu, cr8);
 669         else
 670                 vcpu->arch.cr8 = cr8;
 671         return 0;
 672 }
 673 EXPORT_SYMBOL_GPL(kvm_set_cr8);
 674
 675 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
 676 {
 677         if (irqchip_in_kernel(vcpu->kvm))
 678                 return kvm_lapic_get_cr8(vcpu);
 679         else
 680                 return vcpu->arch.cr8;
 681 }
 682 EXPORT_SYMBOL_GPL(kvm_get_cr8);
 683
 684 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 685 {
 686         switch (dr) {
 687         case 0 ... 3:
 688                 vcpu->arch.db[dr] = val;
 689                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
 690                         vcpu->arch.eff_db[dr] = val;
 691                 break;
 692         case 4:
 693                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 694                         return 1; /* #UD */
 695                 /* fall through */
 696         case 6:
 697                 if (val & 0xffffffff00000000ULL)
 698                         return -1; /* #GP */
 699                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
 700                 break;
 701         case 5:
 702                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 703                         return 1; /* #UD */
 704                 /* fall through */
 705         default: /* 7 */
 706                 if (val & 0xffffffff00000000ULL)
 707                         return -1; /* #GP */
 708                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
 709                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
 710                         kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
 711                         vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
 712                 }
 713                 break;
 714         }
 715
 716         return 0;
 717 }
 718
 719 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 720 {
 721         int res;
 722
 723         res = __kvm_set_dr(vcpu, dr, val);
 724         if (res > 0)
 725                 kvm_queue_exception(vcpu, UD_VECTOR);
 726         else if (res < 0)
 727                 kvm_inject_gp(vcpu, 0);
 728
 729         return res;
 730 }
 731 EXPORT_SYMBOL_GPL(kvm_set_dr);
 732
 733 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 734 {
 735         switch (dr) {
 736         case 0 ... 3:
 737                 *val = vcpu->arch.db[dr];
 738                 break;
 739         case 4:
 740                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 741                         return 1;
 742                 /* fall through */
 743         case 6:
 744                 *val = vcpu->arch.dr6;
 745                 break;
 746         case 5:
 747                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 748                         return 1;
 749                 /* fall through */
 750         default: /* 7 */
 751                 *val = vcpu->arch.dr7;
 752                 break;
 753         }
 754
 755         return 0;
 756 }
 757
 758 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 759 {
 760         if (_kvm_get_dr(vcpu, dr, val)) {
 761                 kvm_queue_exception(vcpu, UD_VECTOR);
 762                 return 1;
 763         }
 764         return 0;
 765 }
 766 EXPORT_SYMBOL_GPL(kvm_get_dr);
 767
 768 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
 769 {
 770         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
 771         u64 data;
 772         int err;
 773
 774         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
 775         if (err)
 776                 return err;
 777         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
 778         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
 779         return err;
 780 }
 781 EXPORT_SYMBOL_GPL(kvm_rdpmc);
 782
 783 /*
 784  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
 785  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
 786  *
 787  * This list is modified at module load time to reflect the
 788  * capabilities of the host cpu. This capabilities test skips MSRs that are
 789  * kvm-specific. Those are put in the beginning of the list.
 790  */
 791
 792 #define KVM_SAVE_MSRS_BEGIN     9
 793 static u32 msrs_to_save[] = {
 794         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
 795         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
 796         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
 797         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
 798         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 799         MSR_STAR,
 800 #ifdef CONFIG_X86_64
 801         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
 802 #endif
 803         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
 804 };
 805
 806 static unsigned num_msrs_to_save;
 807
 808 static u32 emulated_msrs[] = {
 809         MSR_IA32_TSCDEADLINE,
 810         MSR_IA32_MISC_ENABLE,
 811         MSR_IA32_MCG_STATUS,
 812         MSR_IA32_MCG_CTL,
 813 };
 814
 815 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
 816 {
 817         u64 old_efer = vcpu->arch.efer;
 818
 819         if (efer & efer_reserved_bits)
 820                 return 1;
 821
 822         if (is_paging(vcpu)
 823             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
 824                 return 1;
 825
 826         if (efer & EFER_FFXSR) {
 827                 struct kvm_cpuid_entry2 *feat;
 828
 829                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 830                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
 831                         return 1;
 832         }
 833
 834         if (efer & EFER_SVME) {
 835                 struct kvm_cpuid_entry2 *feat;
 836
 837                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 838                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
 839                         return 1;
 840         }
 841
 842         efer &= ~EFER_LMA;
 843         efer |= vcpu->arch.efer & EFER_LMA;
 844
 845         kvm_x86_ops->set_efer(vcpu, efer);
 846
 847         vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
 848
 849         /* Update reserved bits */
 850         if ((efer ^ old_efer) & EFER_NX)
 851                 kvm_mmu_reset_context(vcpu);
 852
 853         return 0;
 854 }
 855
 856 void kvm_enable_efer_bits(u64 mask)
 857 {
 858        efer_reserved_bits &= ~mask;
 859 }
 860 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
 861
 862
 863 /*
 864  * Writes msr value into into the appropriate "register".
 865  * Returns 0 on success, non-0 otherwise.
 866  * Assumes vcpu_load() was already called.
 867  */
 868 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 869 {
 870         return kvm_x86_ops->set_msr(vcpu, msr_index, data);
 871 }
 872
 873 /*
 874  * Adapt set_msr() to msr_io()'s calling convention
 875  */
 876 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
 877 {
 878         return kvm_set_msr(vcpu, index, *data);
 879 }
 880
 881 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
 882 {
 883         int version;
 884         int r;
 885         struct pvclock_wall_clock wc;
 886         struct timespec boot;
 887
 888         if (!wall_clock)
 889                 return;
 890
 891         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
 892         if (r)
 893                 return;
 894
 895         if (version & 1)
 896                 ++version;  /* first time write, random junk */
 897
 898         ++version;
 899
 900         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
 901
 902         /*
 903          * The guest calculates current wall clock time by adding
 904          * system time (updated by kvm_guest_time_update below) to the
 905          * wall clock specified here.  guest system time equals host
 906          * system time for us, thus we must fill in host boot time here.
 907          */
 908         getboottime(&boot);
 909
 910         wc.sec = boot.tv_sec;
 911         wc.nsec = boot.tv_nsec;
 912         wc.version = version;
 913
 914         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
 915
 916         version++;
 917         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
 918 }
 919
 920 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
 921 {
 922         uint32_t quotient, remainder;
 923
 924         /* Don't try to replace with do_div(), this one calculates
 925          * "(dividend << 32) / divisor" */
 926         __asm__ ( "divl %4"
 927                   : "=a" (quotient), "=d" (remainder)
 928                   : "0" (0), "1" (dividend), "r" (divisor) );
 929         return quotient;
 930 }
 931
 932 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
 933                                s8 *pshift, u32 *pmultiplier)
 934 {
 935         uint64_t scaled64;
 936         int32_t  shift = 0;
 937         uint64_t tps64;
 938         uint32_t tps32;
 939
 940         tps64 = base_khz * 1000LL;
 941         scaled64 = scaled_khz * 1000LL;
 942         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
 943                 tps64 >>= 1;
 944                 shift--;
 945         }
 946
 947         tps32 = (uint32_t)tps64;
 948         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
 949                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
 950                         scaled64 >>= 1;
 951                 else
 952                         tps32 <<= 1;
 953                 shift++;
 954         }
 955
 956         *pshift = shift;
 957         *pmultiplier = div_frac(scaled64, tps32);
 958
 959         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
 960                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
 961 }
 962
 963 static inline u64 get_kernel_ns(void)
 964 {
 965         struct timespec ts;
 966
 967         WARN_ON(preemptible());
 968         ktime_get_ts(&ts);
 969         monotonic_to_bootbased(&ts);
 970         return timespec_to_ns(&ts);
 971 }
 972
 973 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
 974 unsigned long max_tsc_khz;
 975
 976 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
 977 {
 978         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
 979                                    vcpu->arch.virtual_tsc_shift);
 980 }
 981
 982 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
 983 {
 984         u64 v = (u64)khz * (1000000 + ppm);
 985         do_div(v, 1000000);
 986         return v;
 987 }
 988
 989 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
 990 {
 991         u32 thresh_lo, thresh_hi;
 992         int use_scaling = 0;
 993
 994         /* Compute a scale to convert nanoseconds in TSC cycles */
 995         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
 996                            &vcpu->arch.virtual_tsc_shift,
 997                            &vcpu->arch.virtual_tsc_mult);
 998         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
 999
1000         /*
1001          * Compute the variation in TSC rate which is acceptable
1002          * within the range of tolerance and decide if the
1003          * rate being applied is within that bounds of the hardware
1004          * rate.  If so, no scaling or compensation need be done.
1005          */
1006         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1007         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1008         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1009                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1010                 use_scaling = 1;
1011         }
1012         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1013 }
1014
1015 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1016 {
1017         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1018                                       vcpu->arch.virtual_tsc_mult,
1019                                       vcpu->arch.virtual_tsc_shift);
1020         tsc += vcpu->arch.this_tsc_write;
1021         return tsc;
1022 }
1023
1024 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1025 {
1026         struct kvm *kvm = vcpu->kvm;
1027         u64 offset, ns, elapsed;
1028         unsigned long flags;
1029         s64 usdiff;
1030
1031         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1032         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1033         ns = get_kernel_ns();
1034         elapsed = ns - kvm->arch.last_tsc_nsec;
1035
1036         /* n.b - signed multiplication and division required */
1037         usdiff = data - kvm->arch.last_tsc_write;
1038 #ifdef CONFIG_X86_64
1039         usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1040 #else
1041         /* do_div() only does unsigned */
1042         asm("idivl %2; xor %%edx, %%edx"
1043             : "=A"(usdiff)
1044             : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1045 #endif
1046         do_div(elapsed, 1000);
1047         usdiff -= elapsed;
1048         if (usdiff < 0)
1049                 usdiff = -usdiff;
1050
1051         /*
1052          * Special case: TSC write with a small delta (1 second) of virtual
1053          * cycle time against real time is interpreted as an attempt to
1054          * synchronize the CPU.
1055          *
1056          * For a reliable TSC, we can match TSC offsets, and for an unstable
1057          * TSC, we add elapsed time in this computation.  We could let the
1058          * compensation code attempt to catch up if we fall behind, but
1059          * it's better to try to match offsets from the beginning.
1060          */
1061         if (usdiff < USEC_PER_SEC &&
1062             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1063                 if (!check_tsc_unstable()) {
1064                         offset = kvm->arch.cur_tsc_offset;
1065                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1066                 } else {
1067                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1068                         data += delta;
1069                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1070                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1071                 }
1072         } else {
1073                 /*
1074                  * We split periods of matched TSC writes into generations.
1075                  * For each generation, we track the original measured
1076                  * nanosecond time, offset, and write, so if TSCs are in
1077                  * sync, we can match exact offset, and if not, we can match
1078                  * exact software computaion in compute_guest_tsc()
1079                  *
1080                  * These values are tracked in kvm->arch.cur_xxx variables.
1081                  */
1082                 kvm->arch.cur_tsc_generation++;
1083                 kvm->arch.cur_tsc_nsec = ns;
1084                 kvm->arch.cur_tsc_write = data;
1085                 kvm->arch.cur_tsc_offset = offset;
1086                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1087                          kvm->arch.cur_tsc_generation, data);
1088         }
1089
1090         /*
1091          * We also track th most recent recorded KHZ, write and time to
1092          * allow the matching interval to be extended at each write.
1093          */
1094         kvm->arch.last_tsc_nsec = ns;
1095         kvm->arch.last_tsc_write = data;
1096         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1097
1098         /* Reset of TSC must disable overshoot protection below */
1099         vcpu->arch.hv_clock.tsc_timestamp = 0;
1100         vcpu->arch.last_guest_tsc = data;
1101
1102         /* Keep track of which generation this VCPU has synchronized to */
1103         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1104         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1105         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1106
1107         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1108         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1109 }
1110
1111 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1112
1113 static int kvm_guest_time_update(struct kvm_vcpu *v)
1114 {
1115         unsigned long flags;
1116         struct kvm_vcpu_arch *vcpu = &v->arch;
1117         void *shared_kaddr;
1118         unsigned long this_tsc_khz;
1119         s64 kernel_ns, max_kernel_ns;
1120         u64 tsc_timestamp;
1121
1122         /* Keep irq disabled to prevent changes to the clock */
1123         local_irq_save(flags);
1124         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1125         kernel_ns = get_kernel_ns();
1126         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1127         if (unlikely(this_tsc_khz == 0)) {
1128                 local_irq_restore(flags);
1129                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1130                 return 1;
1131         }
1132
1133         /*
1134          * We may have to catch up the TSC to match elapsed wall clock
1135          * time for two reasons, even if kvmclock is used.
1136          *   1) CPU could have been running below the maximum TSC rate
1137          *   2) Broken TSC compensation resets the base at each VCPU
1138          *      entry to avoid unknown leaps of TSC even when running
1139          *      again on the same CPU.  This may cause apparent elapsed
1140          *      time to disappear, and the guest to stand still or run
1141          *      very slowly.
1142          */
1143         if (vcpu->tsc_catchup) {
1144                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1145                 if (tsc > tsc_timestamp) {
1146                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1147                         tsc_timestamp = tsc;
1148                 }
1149         }
1150
1151         local_irq_restore(flags);
1152
1153         if (!vcpu->time_page)
1154                 return 0;
1155
1156         /*
1157          * Time as measured by the TSC may go backwards when resetting the base
1158          * tsc_timestamp.  The reason for this is that the TSC resolution is
1159          * higher than the resolution of the other clock scales.  Thus, many
1160          * possible measurments of the TSC correspond to one measurement of any
1161          * other clock, and so a spread of values is possible.  This is not a
1162          * problem for the computation of the nanosecond clock; with TSC rates
1163          * around 1GHZ, there can only be a few cycles which correspond to one
1164          * nanosecond value, and any path through this code will inevitably
1165          * take longer than that.  However, with the kernel_ns value itself,
1166          * the precision may be much lower, down to HZ granularity.  If the
1167          * first sampling of TSC against kernel_ns ends in the low part of the
1168          * range, and the second in the high end of the range, we can get:
1169          *
1170          * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1171          *
1172          * As the sampling errors potentially range in the thousands of cycles,
1173          * it is possible such a time value has already been observed by the
1174          * guest.  To protect against this, we must compute the system time as
1175          * observed by the guest and ensure the new system time is greater.
1176          */
1177         max_kernel_ns = 0;
1178         if (vcpu->hv_clock.tsc_timestamp) {
1179                 max_kernel_ns = vcpu->last_guest_tsc -
1180                                 vcpu->hv_clock.tsc_timestamp;
1181                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1182                                     vcpu->hv_clock.tsc_to_system_mul,
1183                                     vcpu->hv_clock.tsc_shift);
1184                 max_kernel_ns += vcpu->last_kernel_ns;
1185         }
1186
1187         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1188                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1189                                    &vcpu->hv_clock.tsc_shift,
1190                                    &vcpu->hv_clock.tsc_to_system_mul);
1191                 vcpu->hw_tsc_khz = this_tsc_khz;
1192         }
1193
1194         if (max_kernel_ns > kernel_ns)
1195                 kernel_ns = max_kernel_ns;
1196
1197         /* With all the info we got, fill in the values */
1198         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1199         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1200         vcpu->last_kernel_ns = kernel_ns;
1201         vcpu->last_guest_tsc = tsc_timestamp;
1202         vcpu->hv_clock.flags = 0;
1203
1204         /*
1205          * The interface expects us to write an even number signaling that the
1206          * update is finished. Since the guest won't see the intermediate
1207          * state, we just increase by 2 at the end.
1208          */
1209         vcpu->hv_clock.version += 2;
1210
1211         shared_kaddr = kmap_atomic(vcpu->time_page);
1212
1213         memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1214                sizeof(vcpu->hv_clock));
1215
1216         kunmap_atomic(shared_kaddr);
1217
1218         mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1219         return 0;
1220 }
1221
1222 static bool msr_mtrr_valid(unsigned msr)
1223 {
1224         switch (msr) {
1225         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1226         case MSR_MTRRfix64K_00000:
1227         case MSR_MTRRfix16K_80000:
1228         case MSR_MTRRfix16K_A0000:
1229         case MSR_MTRRfix4K_C0000:
1230         case MSR_MTRRfix4K_C8000:
1231         case MSR_MTRRfix4K_D0000:
1232         case MSR_MTRRfix4K_D8000:
1233         case MSR_MTRRfix4K_E0000:
1234         case MSR_MTRRfix4K_E8000:
1235         case MSR_MTRRfix4K_F0000:
1236         case MSR_MTRRfix4K_F8000:
1237         case MSR_MTRRdefType:
1238         case MSR_IA32_CR_PAT:
1239                 return true;
1240         case 0x2f8:
1241                 return true;
1242         }
1243         return false;
1244 }
1245
1246 static bool valid_pat_type(unsigned t)
1247 {
1248         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1249 }
1250
1251 static bool valid_mtrr_type(unsigned t)
1252 {
1253         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1254 }
1255
1256 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1257 {
1258         int i;
1259
1260         if (!msr_mtrr_valid(msr))
1261                 return false;
1262
1263         if (msr == MSR_IA32_CR_PAT) {
1264                 for (i = 0; i < 8; i++)
1265                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1266                                 return false;
1267                 return true;
1268         } else if (msr == MSR_MTRRdefType) {
1269                 if (data & ~0xcff)
1270                         return false;
1271                 return valid_mtrr_type(data & 0xff);
1272         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1273                 for (i = 0; i < 8 ; i++)
1274                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1275                                 return false;
1276                 return true;
1277         }
1278
1279         /* variable MTRRs */
1280         return valid_mtrr_type(data & 0xff);
1281 }
1282
1283 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1284 {
1285         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1286
1287         if (!mtrr_valid(vcpu, msr, data))
1288                 return 1;
1289
1290         if (msr == MSR_MTRRdefType) {
1291                 vcpu->arch.mtrr_state.def_type = data;
1292                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1293         } else if (msr == MSR_MTRRfix64K_00000)
1294                 p[0] = data;
1295         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1296                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1297         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1298                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1299         else if (msr == MSR_IA32_CR_PAT)
1300                 vcpu->arch.pat = data;
1301         else {  /* Variable MTRRs */
1302                 int idx, is_mtrr_mask;
1303                 u64 *pt;
1304
1305                 idx = (msr - 0x200) / 2;
1306                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1307                 if (!is_mtrr_mask)
1308                         pt =
1309                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1310                 else
1311                         pt =
1312                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1313                 *pt = data;
1314         }
1315
1316         kvm_mmu_reset_context(vcpu);
1317         return 0;
1318 }
1319
1320 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1321 {
1322         u64 mcg_cap = vcpu->arch.mcg_cap;
1323         unsigned bank_num = mcg_cap & 0xff;
1324
1325         switch (msr) {
1326         case MSR_IA32_MCG_STATUS:
1327                 vcpu->arch.mcg_status = data;
1328                 break;
1329         case MSR_IA32_MCG_CTL:
1330                 if (!(mcg_cap & MCG_CTL_P))
1331                         return 1;
1332                 if (data != 0 && data != ~(u64)0)
1333                         return -1;
1334                 vcpu->arch.mcg_ctl = data;
1335                 break;
1336         default:
1337                 if (msr >= MSR_IA32_MC0_CTL &&
1338                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1339                         u32 offset = msr - MSR_IA32_MC0_CTL;
1340                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1341                          * some Linux kernels though clear bit 10 in bank 4 to
1342                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1343                          * this to avoid an uncatched #GP in the guest
1344                          */
1345                         if ((offset & 0x3) == 0 &&
1346                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1347                                 return -1;
1348                         vcpu->arch.mce_banks[offset] = data;
1349                         break;
1350                 }
1351                 return 1;
1352         }
1353         return 0;
1354 }
1355
1356 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1357 {
1358         struct kvm *kvm = vcpu->kvm;
1359         int lm = is_long_mode(vcpu);
1360         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1361                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1362         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1363                 : kvm->arch.xen_hvm_config.blob_size_32;
1364         u32 page_num = data & ~PAGE_MASK;
1365         u64 page_addr = data & PAGE_MASK;
1366         u8 *page;
1367         int r;
1368
1369         r = -E2BIG;
1370         if (page_num >= blob_size)
1371                 goto out;
1372         r = -ENOMEM;
1373         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1374         if (IS_ERR(page)) {
1375                 r = PTR_ERR(page);
1376                 goto out;
1377         }
1378         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1379                 goto out_free;
1380         r = 0;
1381 out_free:
1382         kfree(page);
1383 out:
1384         return r;
1385 }
1386
1387 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1388 {
1389         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1390 }
1391
1392 static bool kvm_hv_msr_partition_wide(u32 msr)
1393 {
1394         bool r = false;
1395         switch (msr) {
1396         case HV_X64_MSR_GUEST_OS_ID:
1397         case HV_X64_MSR_HYPERCALL:
1398                 r = true;
1399                 break;
1400         }
1401
1402         return r;
1403 }
1404
1405 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1406 {
1407         struct kvm *kvm = vcpu->kvm;
1408
1409         switch (msr) {
1410         case HV_X64_MSR_GUEST_OS_ID:
1411                 kvm->arch.hv_guest_os_id = data;
1412                 /* setting guest os id to zero disables hypercall page */
1413                 if (!kvm->arch.hv_guest_os_id)
1414                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1415                 break;
1416         case HV_X64_MSR_HYPERCALL: {
1417                 u64 gfn;
1418                 unsigned long addr;
1419                 u8 instructions[4];
1420
1421                 /* if guest os id is not set hypercall should remain disabled */
1422                 if (!kvm->arch.hv_guest_os_id)
1423                         break;
1424                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1425                         kvm->arch.hv_hypercall = data;
1426                         break;
1427                 }
1428                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1429                 addr = gfn_to_hva(kvm, gfn);
1430                 if (kvm_is_error_hva(addr))
1431                         return 1;
1432                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1433                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1434                 if (__copy_to_user((void __user *)addr, instructions, 4))
1435                         return 1;
1436                 kvm->arch.hv_hypercall = data;
1437                 break;
1438         }
1439         default:
1440                 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1441                           "data 0x%llx\n", msr, data);
1442                 return 1;
1443         }
1444         return 0;
1445 }
1446
1447 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1448 {
1449         switch (msr) {
1450         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1451                 unsigned long addr;
1452
1453                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1454                         vcpu->arch.hv_vapic = data;
1455                         break;
1456                 }
1457                 addr = gfn_to_hva(vcpu->kvm, data >>
1458                                   HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1459                 if (kvm_is_error_hva(addr))
1460                         return 1;
1461                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1462                         return 1;
1463                 vcpu->arch.hv_vapic = data;
1464                 break;
1465         }
1466         case HV_X64_MSR_EOI:
1467                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1468         case HV_X64_MSR_ICR:
1469                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1470         case HV_X64_MSR_TPR:
1471                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1472         default:
1473                 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1474                           "data 0x%llx\n", msr, data);
1475                 return 1;
1476         }
1477
1478         return 0;
1479 }
1480
1481 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1482 {
1483         gpa_t gpa = data & ~0x3f;
1484
1485         /* Bits 2:5 are resrved, Should be zero */
1486         if (data & 0x3c)
1487                 return 1;
1488
1489         vcpu->arch.apf.msr_val = data;
1490
1491         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1492                 kvm_clear_async_pf_completion_queue(vcpu);
1493                 kvm_async_pf_hash_reset(vcpu);
1494                 return 0;
1495         }
1496
1497         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1498                 return 1;
1499
1500         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1501         kvm_async_pf_wakeup_all(vcpu);
1502         return 0;
1503 }
1504
1505 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1506 {
1507         if (vcpu->arch.time_page) {
1508                 kvm_release_page_dirty(vcpu->arch.time_page);
1509                 vcpu->arch.time_page = NULL;
1510         }
1511 }
1512
1513 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1514 {
1515         u64 delta;
1516
1517         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1518                 return;
1519
1520         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1521         vcpu->arch.st.last_steal = current->sched_info.run_delay;
1522         vcpu->arch.st.accum_steal = delta;
1523 }
1524
1525 static void record_steal_time(struct kvm_vcpu *vcpu)
1526 {
1527         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1528                 return;
1529
1530         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1531                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1532                 return;
1533
1534         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1535         vcpu->arch.st.steal.version += 2;
1536         vcpu->arch.st.accum_steal = 0;
1537
1538         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1539                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1540 }
1541
1542 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1543 {
1544         bool pr = false;
1545
1546         switch (msr) {
1547         case MSR_EFER:
1548                 return set_efer(vcpu, data);
1549         case MSR_K7_HWCR:
1550                 data &= ~(u64)0x40;     /* ignore flush filter disable */
1551                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
1552                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
1553                 if (data != 0) {
1554                         pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1555                                 data);
1556                         return 1;
1557                 }
1558                 break;
1559         case MSR_FAM10H_MMIO_CONF_BASE:
1560                 if (data != 0) {
1561                         pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1562                                 "0x%llx\n", data);
1563                         return 1;
1564                 }
1565                 break;
1566         case MSR_AMD64_NB_CFG:
1567                 break;
1568         case MSR_IA32_DEBUGCTLMSR:
1569                 if (!data) {
1570                         /* We support the non-activated case already */
1571                         break;
1572                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1573                         /* Values other than LBR and BTF are vendor-specific,
1574                            thus reserved and should throw a #GP */
1575                         return 1;
1576                 }
1577                 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1578                         __func__, data);
1579                 break;
1580         case MSR_IA32_UCODE_REV:
1581         case MSR_IA32_UCODE_WRITE:
1582         case MSR_VM_HSAVE_PA:
1583         case MSR_AMD64_PATCH_LOADER:
1584                 break;
1585         case 0x200 ... 0x2ff:
1586                 return set_msr_mtrr(vcpu, msr, data);
1587         case MSR_IA32_APICBASE:
1588                 kvm_set_apic_base(vcpu, data);
1589                 break;
1590         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1591                 return kvm_x2apic_msr_write(vcpu, msr, data);
1592         case MSR_IA32_TSCDEADLINE:
1593                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1594                 break;
1595         case MSR_IA32_MISC_ENABLE:
1596                 vcpu->arch.ia32_misc_enable_msr = data;
1597                 break;
1598         case MSR_KVM_WALL_CLOCK_NEW:
1599         case MSR_KVM_WALL_CLOCK:
1600                 vcpu->kvm->arch.wall_clock = data;
1601                 kvm_write_wall_clock(vcpu->kvm, data);
1602                 break;
1603         case MSR_KVM_SYSTEM_TIME_NEW:
1604         case MSR_KVM_SYSTEM_TIME: {
1605                 kvmclock_reset(vcpu);
1606
1607                 vcpu->arch.time = data;
1608                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1609
1610                 /* we verify if the enable bit is set... */
1611                 if (!(data & 1))
1612                         break;
1613
1614                 /* ...but clean it before doing the actual write */
1615                 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1616
1617                 vcpu->arch.time_page =
1618                                 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1619
1620                 if (is_error_page(vcpu->arch.time_page)) {
1621                         kvm_release_page_clean(vcpu->arch.time_page);
1622                         vcpu->arch.time_page = NULL;
1623                 }
1624                 break;
1625         }
1626         case MSR_KVM_ASYNC_PF_EN:
1627                 if (kvm_pv_enable_async_pf(vcpu, data))
1628                         return 1;
1629                 break;
1630         case MSR_KVM_STEAL_TIME:
1631
1632                 if (unlikely(!sched_info_on()))
1633                         return 1;
1634
1635                 if (data & KVM_STEAL_RESERVED_MASK)
1636                         return 1;
1637
1638                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1639                                                         data & KVM_STEAL_VALID_BITS))
1640                         return 1;
1641
1642                 vcpu->arch.st.msr_val = data;
1643
1644                 if (!(data & KVM_MSR_ENABLED))
1645                         break;
1646
1647                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1648
1649                 preempt_disable();
1650                 accumulate_steal_time(vcpu);
1651                 preempt_enable();
1652
1653                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1654
1655                 break;
1656
1657         case MSR_IA32_MCG_CTL:
1658         case MSR_IA32_MCG_STATUS:
1659         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1660                 return set_msr_mce(vcpu, msr, data);
1661
1662         /* Performance counters are not protected by a CPUID bit,
1663          * so we should check all of them in the generic path for the sake of
1664          * cross vendor migration.
1665          * Writing a zero into the event select MSRs disables them,
1666          * which we perfectly emulate ;-). Any other value should be at least
1667          * reported, some guests depend on them.
1668          */
1669         case MSR_K7_EVNTSEL0:
1670         case MSR_K7_EVNTSEL1:
1671         case MSR_K7_EVNTSEL2:
1672         case MSR_K7_EVNTSEL3:
1673                 if (data != 0)
1674                         pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1675                                 "0x%x data 0x%llx\n", msr, data);
1676                 break;
1677         /* at least RHEL 4 unconditionally writes to the perfctr registers,
1678          * so we ignore writes to make it happy.
1679          */
1680         case MSR_K7_PERFCTR0:
1681         case MSR_K7_PERFCTR1:
1682         case MSR_K7_PERFCTR2:
1683         case MSR_K7_PERFCTR3:
1684                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1685                         "0x%x data 0x%llx\n", msr, data);
1686                 break;
1687         case MSR_P6_PERFCTR0:
1688         case MSR_P6_PERFCTR1:
1689                 pr = true;
1690         case MSR_P6_EVNTSEL0:
1691         case MSR_P6_EVNTSEL1:
1692                 if (kvm_pmu_msr(vcpu, msr))
1693                         return kvm_pmu_set_msr(vcpu, msr, data);
1694
1695                 if (pr || data != 0)
1696                         pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1697                                 "0x%x data 0x%llx\n", msr, data);
1698                 break;
1699         case MSR_K7_CLK_CTL:
1700                 /*
1701                  * Ignore all writes to this no longer documented MSR.
1702                  * Writes are only relevant for old K7 processors,
1703                  * all pre-dating SVM, but a recommended workaround from
1704                  * AMD for these chips. It is possible to speicify the
1705                  * affected processor models on the command line, hence
1706                  * the need to ignore the workaround.
1707                  */
1708                 break;
1709         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1710                 if (kvm_hv_msr_partition_wide(msr)) {
1711                         int r;
1712                         mutex_lock(&vcpu->kvm->lock);
1713                         r = set_msr_hyperv_pw(vcpu, msr, data);
1714                         mutex_unlock(&vcpu->kvm->lock);
1715                         return r;
1716                 } else
1717                         return set_msr_hyperv(vcpu, msr, data);
1718                 break;
1719         case MSR_IA32_BBL_CR_CTL3:
1720                 /* Drop writes to this legacy MSR -- see rdmsr
1721                  * counterpart for further detail.
1722                  */
1723                 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1724                 break;
1725         case MSR_AMD64_OSVW_ID_LENGTH:
1726                 if (!guest_cpuid_has_osvw(vcpu))
1727                         return 1;
1728                 vcpu->arch.osvw.length = data;
1729                 break;
1730         case MSR_AMD64_OSVW_STATUS:
1731                 if (!guest_cpuid_has_osvw(vcpu))
1732                         return 1;
1733                 vcpu->arch.osvw.status = data;
1734                 break;
1735         default:
1736                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1737                         return xen_hvm_config(vcpu, data);
1738                 if (kvm_pmu_msr(vcpu, msr))
1739                         return kvm_pmu_set_msr(vcpu, msr, data);
1740                 if (!ignore_msrs) {
1741                         pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1742                                 msr, data);
1743                         return 1;
1744                 } else {
1745                         pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1746                                 msr, data);
1747                         break;
1748                 }
1749         }
1750         return 0;
1751 }
1752 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1753
1754
1755 /*
1756  * Reads an msr value (of 'msr_index') into 'pdata'.
1757  * Returns 0 on success, non-0 otherwise.
1758  * Assumes vcpu_load() was already called.
1759  */
1760 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1761 {
1762         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1763 }
1764
1765 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1766 {
1767         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1768
1769         if (!msr_mtrr_valid(msr))
1770                 return 1;
1771
1772         if (msr == MSR_MTRRdefType)
1773                 *pdata = vcpu->arch.mtrr_state.def_type +
1774                          (vcpu->arch.mtrr_state.enabled << 10);
1775         else if (msr == MSR_MTRRfix64K_00000)
1776                 *pdata = p[0];
1777         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1778                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1779         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1780                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1781         else if (msr == MSR_IA32_CR_PAT)
1782                 *pdata = vcpu->arch.pat;
1783         else {  /* Variable MTRRs */
1784                 int idx, is_mtrr_mask;
1785                 u64 *pt;
1786
1787                 idx = (msr - 0x200) / 2;
1788                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1789                 if (!is_mtrr_mask)
1790                         pt =
1791                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1792                 else
1793                         pt =
1794                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1795                 *pdata = *pt;
1796         }
1797
1798         return 0;
1799 }
1800
1801 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1802 {
1803         u64 data;
1804         u64 mcg_cap = vcpu->arch.mcg_cap;
1805         unsigned bank_num = mcg_cap & 0xff;
1806
1807         switch (msr) {
1808         case MSR_IA32_P5_MC_ADDR:
1809         case MSR_IA32_P5_MC_TYPE:
1810                 data = 0;
1811                 break;
1812         case MSR_IA32_MCG_CAP:
1813                 data = vcpu->arch.mcg_cap;
1814                 break;
1815         case MSR_IA32_MCG_CTL:
1816                 if (!(mcg_cap & MCG_CTL_P))
1817                         return 1;
1818                 data = vcpu->arch.mcg_ctl;
1819                 break;
1820         case MSR_IA32_MCG_STATUS:
1821                 data = vcpu->arch.mcg_status;
1822                 break;
1823         default:
1824                 if (msr >= MSR_IA32_MC0_CTL &&
1825                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1826                         u32 offset = msr - MSR_IA32_MC0_CTL;
1827                         data = vcpu->arch.mce_banks[offset];
1828                         break;
1829                 }
1830                 return 1;
1831         }
1832         *pdata = data;
1833         return 0;
1834 }
1835
1836 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1837 {
1838         u64 data = 0;
1839         struct kvm *kvm = vcpu->kvm;
1840
1841         switch (msr) {
1842         case HV_X64_MSR_GUEST_OS_ID:
1843                 data = kvm->arch.hv_guest_os_id;
1844                 break;
1845         case HV_X64_MSR_HYPERCALL:
1846                 data = kvm->arch.hv_hypercall;
1847                 break;
1848         default:
1849                 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1850                 return 1;
1851         }
1852
1853         *pdata = data;
1854         return 0;
1855 }
1856
1857 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1858 {
1859         u64 data = 0;
1860
1861         switch (msr) {
1862         case HV_X64_MSR_VP_INDEX: {
1863                 int r;
1864                 struct kvm_vcpu *v;
1865                 kvm_for_each_vcpu(r, v, vcpu->kvm)
1866                         if (v == vcpu)
1867                                 data = r;
1868                 break;
1869         }
1870         case HV_X64_MSR_EOI:
1871                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1872         case HV_X64_MSR_ICR:
1873                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1874         case HV_X64_MSR_TPR:
1875                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1876         case HV_X64_MSR_APIC_ASSIST_PAGE:
1877                 data = vcpu->arch.hv_vapic;
1878                 break;
1879         default:
1880                 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1881                 return 1;
1882         }
1883         *pdata = data;
1884         return 0;
1885 }
1886
1887 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1888 {
1889         u64 data;
1890
1891         switch (msr) {
1892         case MSR_IA32_PLATFORM_ID:
1893         case MSR_IA32_EBL_CR_POWERON:
1894         case MSR_IA32_DEBUGCTLMSR:
1895         case MSR_IA32_LASTBRANCHFROMIP:
1896         case MSR_IA32_LASTBRANCHTOIP:
1897         case MSR_IA32_LASTINTFROMIP:
1898         case MSR_IA32_LASTINTTOIP:
1899         case MSR_K8_SYSCFG:
1900         case MSR_K7_HWCR:
1901         case MSR_VM_HSAVE_PA:
1902         case MSR_K7_EVNTSEL0:
1903         case MSR_K7_PERFCTR0:
1904         case MSR_K8_INT_PENDING_MSG:
1905         case MSR_AMD64_NB_CFG:
1906         case MSR_FAM10H_MMIO_CONF_BASE:
1907                 data = 0;
1908                 break;
1909         case MSR_P6_PERFCTR0:
1910         case MSR_P6_PERFCTR1:
1911         case MSR_P6_EVNTSEL0:
1912         case MSR_P6_EVNTSEL1:
1913                 if (kvm_pmu_msr(vcpu, msr))
1914                         return kvm_pmu_get_msr(vcpu, msr, pdata);
1915                 data = 0;
1916                 break;
1917         case MSR_IA32_UCODE_REV:
1918                 data = 0x100000000ULL;
1919                 break;
1920         case MSR_MTRRcap:
1921                 data = 0x500 | KVM_NR_VAR_MTRR;
1922                 break;
1923         case 0x200 ... 0x2ff:
1924                 return get_msr_mtrr(vcpu, msr, pdata);
1925         case 0xcd: /* fsb frequency */
1926                 data = 3;
1927                 break;
1928                 /*
1929                  * MSR_EBC_FREQUENCY_ID
1930                  * Conservative value valid for even the basic CPU models.
1931                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1932                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1933                  * and 266MHz for model 3, or 4. Set Core Clock
1934                  * Frequency to System Bus Frequency Ratio to 1 (bits
1935                  * 31:24) even though these are only valid for CPU
1936                  * models > 2, however guests may end up dividing or
1937                  * multiplying by zero otherwise.
1938                  */
1939         case MSR_EBC_FREQUENCY_ID:
1940                 data = 1 << 24;
1941                 break;
1942         case MSR_IA32_APICBASE:
1943                 data = kvm_get_apic_base(vcpu);
1944                 break;
1945         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1946                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1947                 break;
1948         case MSR_IA32_TSCDEADLINE:
1949                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1950                 break;
1951         case MSR_IA32_MISC_ENABLE:
1952                 data = vcpu->arch.ia32_misc_enable_msr;
1953                 break;
1954         case MSR_IA32_PERF_STATUS:
1955                 /* TSC increment by tick */
1956                 data = 1000ULL;
1957                 /* CPU multiplier */
1958                 data |= (((uint64_t)4ULL) << 40);
1959                 break;
1960         case MSR_EFER:
1961                 data = vcpu->arch.efer;
1962                 break;
1963         case MSR_KVM_WALL_CLOCK:
1964         case MSR_KVM_WALL_CLOCK_NEW:
1965                 data = vcpu->kvm->arch.wall_clock;
1966                 break;
1967         case MSR_KVM_SYSTEM_TIME:
1968         case MSR_KVM_SYSTEM_TIME_NEW:
1969                 data = vcpu->arch.time;
1970                 break;
1971         case MSR_KVM_ASYNC_PF_EN:
1972                 data = vcpu->arch.apf.msr_val;
1973                 break;
1974         case MSR_KVM_STEAL_TIME:
1975                 data = vcpu->arch.st.msr_val;
1976                 break;
1977         case MSR_IA32_P5_MC_ADDR:
1978         case MSR_IA32_P5_MC_TYPE:
1979         case MSR_IA32_MCG_CAP:
1980         case MSR_IA32_MCG_CTL:
1981         case MSR_IA32_MCG_STATUS:
1982         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1983                 return get_msr_mce(vcpu, msr, pdata);
1984         case MSR_K7_CLK_CTL:
1985                 /*
1986                  * Provide expected ramp-up count for K7. All other
1987                  * are set to zero, indicating minimum divisors for
1988                  * every field.
1989                  *
1990                  * This prevents guest kernels on AMD host with CPU
1991                  * type 6, model 8 and higher from exploding due to
1992                  * the rdmsr failing.
1993                  */
1994                 data = 0x20000000;
1995                 break;
1996         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1997                 if (kvm_hv_msr_partition_wide(msr)) {
1998                         int r;
1999                         mutex_lock(&vcpu->kvm->lock);
2000                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2001                         mutex_unlock(&vcpu->kvm->lock);
2002                         return r;
2003                 } else
2004                         return get_msr_hyperv(vcpu, msr, pdata);
2005                 break;
2006         case MSR_IA32_BBL_CR_CTL3:
2007                 /* This legacy MSR exists but isn't fully documented in current
2008                  * silicon.  It is however accessed by winxp in very narrow
2009                  * scenarios where it sets bit #19, itself documented as
2010                  * a "reserved" bit.  Best effort attempt to source coherent
2011                  * read data here should the balance of the register be
2012                  * interpreted by the guest:
2013                  *
2014                  * L2 cache control register 3: 64GB range, 256KB size,
2015                  * enabled, latency 0x1, configured
2016                  */
2017                 data = 0xbe702111;
2018                 break;
2019         case MSR_AMD64_OSVW_ID_LENGTH:
2020                 if (!guest_cpuid_has_osvw(vcpu))
2021                         return 1;
2022                 data = vcpu->arch.osvw.length;
2023                 break;
2024         case MSR_AMD64_OSVW_STATUS:
2025                 if (!guest_cpuid_has_osvw(vcpu))
2026                         return 1;
2027                 data = vcpu->arch.osvw.status;
2028                 break;
2029         default:
2030                 if (kvm_pmu_msr(vcpu, msr))
2031                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2032                 if (!ignore_msrs) {
2033                         pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2034                         return 1;
2035                 } else {
2036                         pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2037                         data = 0;
2038                 }
2039                 break;
2040         }
2041         *pdata = data;
2042         return 0;
2043 }
2044 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2045
2046 /*
2047  * Read or write a bunch of msrs. All parameters are kernel addresses.
2048  *
2049  * @return number of msrs set successfully.
2050  */
2051 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2052                     struct kvm_msr_entry *entries,
2053                     int (*do_msr)(struct kvm_vcpu *vcpu,
2054                                   unsigned index, u64 *data))
2055 {
2056         int i, idx;
2057
2058         idx = srcu_read_lock(&vcpu->kvm->srcu);
2059         for (i = 0; i < msrs->nmsrs; ++i)
2060                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2061                         break;
2062         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2063
2064         return i;
2065 }
2066
2067 /*
2068  * Read or write a bunch of msrs. Parameters are user addresses.
2069  *
2070  * @return number of msrs set successfully.
2071  */
2072 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2073                   int (*do_msr)(struct kvm_vcpu *vcpu,
2074                                 unsigned index, u64 *data),
2075                   int writeback)
2076 {
2077         struct kvm_msrs msrs;
2078         struct kvm_msr_entry *entries;
2079         int r, n;
2080         unsigned size;
2081
2082         r = -EFAULT;
2083         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2084                 goto out;
2085
2086         r = -E2BIG;
2087         if (msrs.nmsrs >= MAX_IO_MSRS)
2088                 goto out;
2089
2090         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2091         entries = memdup_user(user_msrs->entries, size);
2092         if (IS_ERR(entries)) {
2093                 r = PTR_ERR(entries);
2094                 goto out;
2095         }
2096
2097         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2098         if (r < 0)
2099                 goto out_free;
2100
2101         r = -EFAULT;
2102         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2103                 goto out_free;
2104
2105         r = n;
2106
2107 out_free:
2108         kfree(entries);
2109 out:
2110         return r;
2111 }
2112
2113 int kvm_dev_ioctl_check_extension(long ext)
2114 {
2115         int r;
2116
2117         switch (ext) {
2118         case KVM_CAP_IRQCHIP:
2119         case KVM_CAP_HLT:
2120         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2121         case KVM_CAP_SET_TSS_ADDR:
2122         case KVM_CAP_EXT_CPUID:
2123         case KVM_CAP_CLOCKSOURCE:
2124         case KVM_CAP_PIT:
2125         case KVM_CAP_NOP_IO_DELAY:
2126         case KVM_CAP_MP_STATE:
2127         case KVM_CAP_SYNC_MMU:
2128         case KVM_CAP_USER_NMI:
2129         case KVM_CAP_REINJECT_CONTROL:
2130         case KVM_CAP_IRQ_INJECT_STATUS:
2131         case KVM_CAP_ASSIGN_DEV_IRQ:
2132         case KVM_CAP_IRQFD:
2133         case KVM_CAP_IOEVENTFD:
2134         case KVM_CAP_PIT2:
2135         case KVM_CAP_PIT_STATE2:
2136         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2137         case KVM_CAP_XEN_HVM:
2138         case KVM_CAP_ADJUST_CLOCK:
2139         case KVM_CAP_VCPU_EVENTS:
2140         case KVM_CAP_HYPERV:
2141         case KVM_CAP_HYPERV_VAPIC:
2142         case KVM_CAP_HYPERV_SPIN:
2143         case KVM_CAP_PCI_SEGMENT:
2144         case KVM_CAP_DEBUGREGS:
2145         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2146         case KVM_CAP_XSAVE:
2147         case KVM_CAP_ASYNC_PF:
2148         case KVM_CAP_GET_TSC_KHZ:
2149         case KVM_CAP_PCI_2_3:
2150                 r = 1;
2151                 break;
2152         case KVM_CAP_COALESCED_MMIO:
2153                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2154                 break;
2155         case KVM_CAP_VAPIC:
2156                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2157                 break;
2158         case KVM_CAP_NR_VCPUS:
2159                 r = KVM_SOFT_MAX_VCPUS;
2160                 break;
2161         case KVM_CAP_MAX_VCPUS:
2162                 r = KVM_MAX_VCPUS;
2163                 break;
2164         case KVM_CAP_NR_MEMSLOTS:
2165                 r = KVM_MEMORY_SLOTS;
2166                 break;
2167         case KVM_CAP_PV_MMU:    /* obsolete */
2168                 r = 0;
2169                 break;
2170         case KVM_CAP_IOMMU:
2171                 r = iommu_present(&pci_bus_type);
2172                 break;
2173         case KVM_CAP_MCE:
2174                 r = KVM_MAX_MCE_BANKS;
2175                 break;
2176         case KVM_CAP_XCRS:
2177                 r = cpu_has_xsave;
2178                 break;
2179         case KVM_CAP_TSC_CONTROL:
2180                 r = kvm_has_tsc_control;
2181                 break;
2182         case KVM_CAP_TSC_DEADLINE_TIMER:
2183                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2184                 break;
2185         default:
2186                 r = 0;
2187                 break;
2188         }
2189         return r;
2190
2191 }
2192
2193 long kvm_arch_dev_ioctl(struct file *filp,
2194                         unsigned int ioctl, unsigned long arg)
2195 {
2196         void __user *argp = (void __user *)arg;
2197         long r;
2198
2199         switch (ioctl) {
2200         case KVM_GET_MSR_INDEX_LIST: {
2201                 struct kvm_msr_list __user *user_msr_list = argp;
2202                 struct kvm_msr_list msr_list;
2203                 unsigned n;
2204
2205                 r = -EFAULT;
2206                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2207                         goto out;
2208                 n = msr_list.nmsrs;
2209                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2210                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2211                         goto out;
2212                 r = -E2BIG;
2213                 if (n < msr_list.nmsrs)
2214                         goto out;
2215                 r = -EFAULT;
2216                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2217                                  num_msrs_to_save * sizeof(u32)))
2218                         goto out;
2219                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2220                                  &emulated_msrs,
2221                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2222                         goto out;
2223                 r = 0;
2224                 break;
2225         }
2226         case KVM_GET_SUPPORTED_CPUID: {
2227                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2228                 struct kvm_cpuid2 cpuid;
2229
2230                 r = -EFAULT;
2231                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2232                         goto out;
2233                 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2234                                                       cpuid_arg->entries);
2235                 if (r)
2236                         goto out;
2237
2238                 r = -EFAULT;
2239                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2240                         goto out;
2241                 r = 0;
2242                 break;
2243         }
2244         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2245                 u64 mce_cap;
2246
2247                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2248                 r = -EFAULT;
2249                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2250                         goto out;
2251                 r = 0;
2252                 break;
2253         }
2254         default:
2255                 r = -EINVAL;
2256         }
2257 out:
2258         return r;
2259 }
2260
2261 static void wbinvd_ipi(void *garbage)
2262 {
2263         wbinvd();
2264 }
2265
2266 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2267 {
2268         return vcpu->kvm->arch.iommu_domain &&
2269                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2270 }
2271
2272 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2273 {
2274         /* Address WBINVD may be executed by guest */
2275         if (need_emulate_wbinvd(vcpu)) {
2276                 if (kvm_x86_ops->has_wbinvd_exit())
2277                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2278                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2279                         smp_call_function_single(vcpu->cpu,
2280                                         wbinvd_ipi, NULL, 1);
2281         }
2282
2283         kvm_x86_ops->vcpu_load(vcpu, cpu);
2284
2285         /* Apply any externally detected TSC adjustments (due to suspend) */
2286         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2287                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2288                 vcpu->arch.tsc_offset_adjustment = 0;
2289                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2290         }
2291
2292         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2293                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2294                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2295                 if (tsc_delta < 0)
2296                         mark_tsc_unstable("KVM discovered backwards TSC");
2297                 if (check_tsc_unstable()) {
2298                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2299                                                 vcpu->arch.last_guest_tsc);
2300                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2301                         vcpu->arch.tsc_catchup = 1;
2302                 }
2303                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2304                 if (vcpu->cpu != cpu)
2305                         kvm_migrate_timers(vcpu);
2306                 vcpu->cpu = cpu;
2307         }
2308
2309         accumulate_steal_time(vcpu);
2310         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2311 }
2312
2313 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2314 {
2315         kvm_x86_ops->vcpu_put(vcpu);
2316         kvm_put_guest_fpu(vcpu);
2317         vcpu->arch.last_host_tsc = native_read_tsc();
2318 }
2319
2320 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2321                                     struct kvm_lapic_state *s)
2322 {
2323         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2324
2325         return 0;
2326 }
2327
2328 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2329                                     struct kvm_lapic_state *s)
2330 {
2331         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2332         kvm_apic_post_state_restore(vcpu);
2333         update_cr8_intercept(vcpu);
2334
2335         return 0;
2336 }
2337
2338 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2339                                     struct kvm_interrupt *irq)
2340 {
2341         if (irq->irq < 0 || irq->irq >= 256)
2342                 return -EINVAL;
2343         if (irqchip_in_kernel(vcpu->kvm))
2344                 return -ENXIO;
2345
2346         kvm_queue_interrupt(vcpu, irq->irq, false);
2347         kvm_make_request(KVM_REQ_EVENT, vcpu);
2348
2349         return 0;
2350 }
2351
2352 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2353 {
2354         kvm_inject_nmi(vcpu);
2355
2356         return 0;
2357 }
2358
2359 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2360                                            struct kvm_tpr_access_ctl *tac)
2361 {
2362         if (tac->flags)
2363                 return -EINVAL;
2364         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2365         return 0;
2366 }
2367
2368 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2369                                         u64 mcg_cap)
2370 {
2371         int r;
2372         unsigned bank_num = mcg_cap & 0xff, bank;
2373
2374         r = -EINVAL;
2375         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2376                 goto out;
2377         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2378                 goto out;
2379         r = 0;
2380         vcpu->arch.mcg_cap = mcg_cap;
2381         /* Init IA32_MCG_CTL to all 1s */
2382         if (mcg_cap & MCG_CTL_P)
2383                 vcpu->arch.mcg_ctl = ~(u64)0;
2384         /* Init IA32_MCi_CTL to all 1s */
2385         for (bank = 0; bank < bank_num; bank++)
2386                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2387 out:
2388         return r;
2389 }
2390
2391 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2392                                       struct kvm_x86_mce *mce)
2393 {
2394         u64 mcg_cap = vcpu->arch.mcg_cap;
2395         unsigned bank_num = mcg_cap & 0xff;
2396         u64 *banks = vcpu->arch.mce_banks;
2397
2398         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2399                 return -EINVAL;
2400         /*
2401          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2402          * reporting is disabled
2403          */
2404         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2405             vcpu->arch.mcg_ctl != ~(u64)0)
2406                 return 0;
2407         banks += 4 * mce->bank;
2408         /*
2409          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2410          * reporting is disabled for the bank
2411          */
2412         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2413                 return 0;
2414         if (mce->status & MCI_STATUS_UC) {
2415                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2416                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2417                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2418                         return 0;
2419                 }
2420                 if (banks[1] & MCI_STATUS_VAL)
2421                         mce->status |= MCI_STATUS_OVER;
2422                 banks[2] = mce->addr;
2423                 banks[3] = mce->misc;
2424                 vcpu->arch.mcg_status = mce->mcg_status;
2425                 banks[1] = mce->status;
2426                 kvm_queue_exception(vcpu, MC_VECTOR);
2427         } else if (!(banks[1] & MCI_STATUS_VAL)
2428                    || !(banks[1] & MCI_STATUS_UC)) {
2429                 if (banks[1] & MCI_STATUS_VAL)
2430                         mce->status |= MCI_STATUS_OVER;
2431                 banks[2] = mce->addr;
2432                 banks[3] = mce->misc;
2433                 banks[1] = mce->status;
2434         } else
2435                 banks[1] |= MCI_STATUS_OVER;
2436         return 0;
2437 }
2438
2439 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2440                                                struct kvm_vcpu_events *events)
2441 {
2442         process_nmi(vcpu);
2443         events->exception.injected =
2444                 vcpu->arch.exception.pending &&
2445                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2446         events->exception.nr = vcpu->arch.exception.nr;
2447         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2448         events->exception.pad = 0;
2449         events->exception.error_code = vcpu->arch.exception.error_code;
2450
2451         events->interrupt.injected =
2452                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2453         events->interrupt.nr = vcpu->arch.interrupt.nr;
2454         events->interrupt.soft = 0;
2455         events->interrupt.shadow =
2456                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2457                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2458
2459         events->nmi.injected = vcpu->arch.nmi_injected;
2460         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2461         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2462         events->nmi.pad = 0;
2463
2464         events->sipi_vector = vcpu->arch.sipi_vector;
2465
2466         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2467                          | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2468                          | KVM_VCPUEVENT_VALID_SHADOW);
2469         memset(&events->reserved, 0, sizeof(events->reserved));
2470 }
2471
2472 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2473                                               struct kvm_vcpu_events *events)
2474 {
2475         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2476                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2477                               | KVM_VCPUEVENT_VALID_SHADOW))
2478                 return -EINVAL;
2479
2480         process_nmi(vcpu);
2481         vcpu->arch.exception.pending = events->exception.injected;
2482         vcpu->arch.exception.nr = events->exception.nr;
2483         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2484         vcpu->arch.exception.error_code = events->exception.error_code;
2485
2486         vcpu->arch.interrupt.pending = events->interrupt.injected;
2487         vcpu->arch.interrupt.nr = events->interrupt.nr;
2488         vcpu->arch.interrupt.soft = events->interrupt.soft;
2489         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2490                 kvm_x86_ops->set_interrupt_shadow(vcpu,
2491                                                   events->interrupt.shadow);
2492
2493         vcpu->arch.nmi_injected = events->nmi.injected;
2494         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2495                 vcpu->arch.nmi_pending = events->nmi.pending;
2496         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2497
2498         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2499                 vcpu->arch.sipi_vector = events->sipi_vector;
2500
2501         kvm_make_request(KVM_REQ_EVENT, vcpu);
2502
2503         return 0;
2504 }
2505
2506 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2507                                              struct kvm_debugregs *dbgregs)
2508 {
2509         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2510         dbgregs->dr6 = vcpu->arch.dr6;
2511         dbgregs->dr7 = vcpu->arch.dr7;
2512         dbgregs->flags = 0;
2513         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2514 }
2515
2516 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2517                                             struct kvm_debugregs *dbgregs)
2518 {
2519         if (dbgregs->flags)
2520                 return -EINVAL;
2521
2522         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2523         vcpu->arch.dr6 = dbgregs->dr6;
2524         vcpu->arch.dr7 = dbgregs->dr7;
2525
2526         return 0;
2527 }
2528
2529 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2530                                          struct kvm_xsave *guest_xsave)
2531 {
2532         if (cpu_has_xsave)
2533                 memcpy(guest_xsave->region,
2534                         &vcpu->arch.guest_fpu.state->xsave,
2535                         xstate_size);
2536         else {
2537                 memcpy(guest_xsave->region,
2538                         &vcpu->arch.guest_fpu.state->fxsave,
2539                         sizeof(struct i387_fxsave_struct));
2540                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2541                         XSTATE_FPSSE;
2542         }
2543 }
2544
2545 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2546                                         struct kvm_xsave *guest_xsave)
2547 {
2548         u64 xstate_bv =
2549                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2550
2551         if (cpu_has_xsave)
2552                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2553                         guest_xsave->region, xstate_size);
2554         else {
2555                 if (xstate_bv & ~XSTATE_FPSSE)
2556                         return -EINVAL;
2557                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2558                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
2559         }
2560         return 0;
2561 }
2562
2563 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2564                                         struct kvm_xcrs *guest_xcrs)
2565 {
2566         if (!cpu_has_xsave) {
2567                 guest_xcrs->nr_xcrs = 0;
2568                 return;
2569         }
2570
2571         guest_xcrs->nr_xcrs = 1;
2572         guest_xcrs->flags = 0;
2573         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2574         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2575 }
2576
2577 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2578                                        struct kvm_xcrs *guest_xcrs)
2579 {
2580         int i, r = 0;
2581
2582         if (!cpu_has_xsave)
2583                 return -EINVAL;
2584
2585         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2586                 return -EINVAL;
2587
2588         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2589                 /* Only support XCR0 currently */
2590                 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2591                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2592                                 guest_xcrs->xcrs[0].value);
2593                         break;
2594                 }
2595         if (r)
2596                 r = -EINVAL;
2597         return r;
2598 }
2599
2600 long kvm_arch_vcpu_ioctl(struct file *filp,
2601                          unsigned int ioctl, unsigned long arg)
2602 {
2603         struct kvm_vcpu *vcpu = filp->private_data;
2604         void __user *argp = (void __user *)arg;
2605         int r;
2606         union {
2607                 struct kvm_lapic_state *lapic;
2608                 struct kvm_xsave *xsave;
2609                 struct kvm_xcrs *xcrs;
2610                 void *buffer;
2611         } u;
2612
2613         u.buffer = NULL;
2614         switch (ioctl) {
2615         case KVM_GET_LAPIC: {
2616                 r = -EINVAL;
2617                 if (!vcpu->arch.apic)
2618                         goto out;
2619                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2620
2621                 r = -ENOMEM;
2622                 if (!u.lapic)
2623                         goto out;
2624                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2625                 if (r)
2626                         goto out;
2627                 r = -EFAULT;
2628                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2629                         goto out;
2630                 r = 0;
2631                 break;
2632         }
2633         case KVM_SET_LAPIC: {
2634                 r = -EINVAL;
2635                 if (!vcpu->arch.apic)
2636                         goto out;
2637                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2638                 if (IS_ERR(u.lapic)) {
2639                         r = PTR_ERR(u.lapic);
2640                         goto out;
2641                 }
2642
2643                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2644                 if (r)
2645                         goto out;
2646                 r = 0;
2647                 break;
2648         }
2649         case KVM_INTERRUPT: {
2650                 struct kvm_interrupt irq;
2651
2652                 r = -EFAULT;
2653                 if (copy_from_user(&irq, argp, sizeof irq))
2654                         goto out;
2655                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2656                 if (r)
2657                         goto out;
2658                 r = 0;
2659                 break;
2660         }
2661         case KVM_NMI: {
2662                 r = kvm_vcpu_ioctl_nmi(vcpu);
2663                 if (r)
2664                         goto out;
2665                 r = 0;
2666                 break;
2667         }
2668         case KVM_SET_CPUID: {
2669                 struct kvm_cpuid __user *cpuid_arg = argp;
2670                 struct kvm_cpuid cpuid;
2671
2672                 r = -EFAULT;
2673                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2674                         goto out;
2675                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2676                 if (r)
2677                         goto out;
2678                 break;
2679         }
2680         case KVM_SET_CPUID2: {
2681                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2682                 struct kvm_cpuid2 cpuid;
2683
2684                 r = -EFAULT;
2685                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2686                         goto out;
2687                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2688                                               cpuid_arg->entries);
2689                 if (r)
2690                         goto out;
2691                 break;
2692         }
2693         case KVM_GET_CPUID2: {
2694                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2695                 struct kvm_cpuid2 cpuid;
2696
2697                 r = -EFAULT;
2698                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2699                         goto out;
2700                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2701                                               cpuid_arg->entries);
2702                 if (r)
2703                         goto out;
2704                 r = -EFAULT;
2705                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2706                         goto out;
2707                 r = 0;
2708                 break;
2709         }
2710         case KVM_GET_MSRS:
2711                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2712                 break;
2713         case KVM_SET_MSRS:
2714                 r = msr_io(vcpu, argp, do_set_msr, 0);
2715                 break;
2716         case KVM_TPR_ACCESS_REPORTING: {
2717                 struct kvm_tpr_access_ctl tac;
2718
2719                 r = -EFAULT;
2720                 if (copy_from_user(&tac, argp, sizeof tac))
2721                         goto out;
2722                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2723                 if (r)
2724                         goto out;
2725                 r = -EFAULT;
2726                 if (copy_to_user(argp, &tac, sizeof tac))
2727                         goto out;
2728                 r = 0;
2729                 break;
2730         };
2731         case KVM_SET_VAPIC_ADDR: {
2732                 struct kvm_vapic_addr va;
2733
2734                 r = -EINVAL;
2735                 if (!irqchip_in_kernel(vcpu->kvm))
2736                         goto out;
2737                 r = -EFAULT;
2738                 if (copy_from_user(&va, argp, sizeof va))
2739                         goto out;
2740                 r = 0;
2741                 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2742                 break;
2743         }
2744         case KVM_X86_SETUP_MCE: {
2745                 u64 mcg_cap;
2746
2747                 r = -EFAULT;
2748                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2749                         goto out;
2750                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2751                 break;
2752         }
2753         case KVM_X86_SET_MCE: {
2754                 struct kvm_x86_mce mce;
2755
2756                 r = -EFAULT;
2757                 if (copy_from_user(&mce, argp, sizeof mce))
2758                         goto out;
2759                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2760                 break;
2761         }
2762         case KVM_GET_VCPU_EVENTS: {
2763                 struct kvm_vcpu_events events;
2764
2765                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2766
2767                 r = -EFAULT;
2768                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2769                         break;
2770                 r = 0;
2771                 break;
2772         }
2773         case KVM_SET_VCPU_EVENTS: {
2774                 struct kvm_vcpu_events events;
2775
2776                 r = -EFAULT;
2777                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2778                         break;
2779
2780                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2781                 break;
2782         }
2783         case KVM_GET_DEBUGREGS: {
2784                 struct kvm_debugregs dbgregs;
2785
2786                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2787
2788                 r = -EFAULT;
2789                 if (copy_to_user(argp, &dbgregs,
2790                                  sizeof(struct kvm_debugregs)))
2791                         break;
2792                 r = 0;
2793                 break;
2794         }
2795         case KVM_SET_DEBUGREGS: {
2796                 struct kvm_debugregs dbgregs;
2797
2798                 r = -EFAULT;
2799                 if (copy_from_user(&dbgregs, argp,
2800                                    sizeof(struct kvm_debugregs)))
2801                         break;
2802
2803                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2804                 break;
2805         }
2806         case KVM_GET_XSAVE: {
2807                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2808                 r = -ENOMEM;
2809                 if (!u.xsave)
2810                         break;
2811
2812                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2813
2814                 r = -EFAULT;
2815                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2816                         break;
2817                 r = 0;
2818                 break;
2819         }
2820         case KVM_SET_XSAVE: {
2821                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2822                 if (IS_ERR(u.xsave)) {
2823                         r = PTR_ERR(u.xsave);
2824                         goto out;
2825                 }
2826
2827                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2828                 break;
2829         }
2830         case KVM_GET_XCRS: {
2831                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2832                 r = -ENOMEM;
2833                 if (!u.xcrs)
2834                         break;
2835
2836                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2837
2838                 r = -EFAULT;
2839                 if (copy_to_user(argp, u.xcrs,
2840                                  sizeof(struct kvm_xcrs)))
2841                         break;
2842                 r = 0;
2843                 break;
2844         }
2845         case KVM_SET_XCRS: {
2846                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2847                 if (IS_ERR(u.xcrs)) {
2848                         r = PTR_ERR(u.xcrs);
2849                         goto out;
2850                 }
2851
2852                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2853                 break;
2854         }
2855         case KVM_SET_TSC_KHZ: {
2856                 u32 user_tsc_khz;
2857
2858                 r = -EINVAL;
2859                 user_tsc_khz = (u32)arg;
2860
2861                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2862                         goto out;
2863
2864                 if (user_tsc_khz == 0)
2865                         user_tsc_khz = tsc_khz;
2866
2867                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2868
2869                 r = 0;
2870                 goto out;
2871         }
2872         case KVM_GET_TSC_KHZ: {
2873                 r = vcpu->arch.virtual_tsc_khz;
2874                 goto out;
2875         }
2876         default:
2877                 r = -EINVAL;
2878         }
2879 out:
2880         kfree(u.buffer);
2881         return r;
2882 }
2883
2884 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2885 {
2886         return VM_FAULT_SIGBUS;
2887 }
2888
2889 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2890 {
2891         int ret;
2892
2893         if (addr > (unsigned int)(-3 * PAGE_SIZE))
2894                 return -1;
2895         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2896         return ret;
2897 }
2898
2899 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2900                                               u64 ident_addr)
2901 {
2902         kvm->arch.ept_identity_map_addr = ident_addr;
2903         return 0;
2904 }
2905
2906 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2907                                           u32 kvm_nr_mmu_pages)
2908 {
2909         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2910                 return -EINVAL;
2911
2912         mutex_lock(&kvm->slots_lock);
2913         spin_lock(&kvm->mmu_lock);
2914
2915         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2916         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2917
2918         spin_unlock(&kvm->mmu_lock);
2919         mutex_unlock(&kvm->slots_lock);
2920         return 0;
2921 }
2922
2923 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2924 {
2925         return kvm->arch.n_max_mmu_pages;
2926 }
2927
2928 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2929 {
2930         int r;
2931
2932         r = 0;
2933         switch (chip->chip_id) {
2934         case KVM_IRQCHIP_PIC_MASTER:
2935                 memcpy(&chip->chip.pic,
2936                         &pic_irqchip(kvm)->pics[0],
2937                         sizeof(struct kvm_pic_state));
2938                 break;
2939         case KVM_IRQCHIP_PIC_SLAVE:
2940                 memcpy(&chip->chip.pic,
2941                         &pic_irqchip(kvm)->pics[1],
2942                         sizeof(struct kvm_pic_state));
2943                 break;
2944         case KVM_IRQCHIP_IOAPIC:
2945                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2946                 break;
2947         default:
2948                 r = -EINVAL;
2949                 break;
2950         }
2951         return r;
2952 }
2953
2954 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2955 {
2956         int r;
2957
2958         r = 0;
2959         switch (chip->chip_id) {
2960         case KVM_IRQCHIP_PIC_MASTER:
2961                 spin_lock(&pic_irqchip(kvm)->lock);
2962                 memcpy(&pic_irqchip(kvm)->pics[0],
2963                         &chip->chip.pic,
2964                         sizeof(struct kvm_pic_state));
2965                 spin_unlock(&pic_irqchip(kvm)->lock);
2966                 break;
2967         case KVM_IRQCHIP_PIC_SLAVE:
2968                 spin_lock(&pic_irqchip(kvm)->lock);
2969                 memcpy(&pic_irqchip(kvm)->pics[1],
2970                         &chip->chip.pic,
2971                         sizeof(struct kvm_pic_state));
2972                 spin_unlock(&pic_irqchip(kvm)->lock);
2973                 break;
2974         case KVM_IRQCHIP_IOAPIC:
2975                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
2976                 break;
2977         default:
2978                 r = -EINVAL;
2979                 break;
2980         }
2981         kvm_pic_update_irq(pic_irqchip(kvm));
2982         return r;
2983 }
2984
2985 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2986 {
2987         int r = 0;
2988
2989         mutex_lock(&kvm->arch.vpit->pit_state.lock);
2990         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2991         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2992         return r;
2993 }
2994
2995 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2996 {
2997         int r = 0;
2998
2999         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3000         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3001         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3002         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3003         return r;
3004 }
3005
3006 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3007 {
3008         int r = 0;
3009
3010         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3011         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3012                 sizeof(ps->channels));
3013         ps->flags = kvm->arch.vpit->pit_state.flags;
3014         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3015         memset(&ps->reserved, 0, sizeof(ps->reserved));
3016         return r;
3017 }
3018
3019 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3020 {
3021         int r = 0, start = 0;
3022         u32 prev_legacy, cur_legacy;
3023         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3024         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3025         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3026         if (!prev_legacy && cur_legacy)
3027                 start = 1;
3028         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3029                sizeof(kvm->arch.vpit->pit_state.channels));
3030         kvm->arch.vpit->pit_state.flags = ps->flags;
3031         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3032         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3033         return r;
3034 }
3035
3036 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3037                                  struct kvm_reinject_control *control)
3038 {
3039         if (!kvm->arch.vpit)
3040                 return -ENXIO;
3041         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3042         kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3043         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3044         return 0;
3045 }
3046
3047 /**
3048  * write_protect_slot - write protect a slot for dirty logging
3049  * @kvm: the kvm instance
3050  * @memslot: the slot we protect
3051  * @dirty_bitmap: the bitmap indicating which pages are dirty
3052  * @nr_dirty_pages: the number of dirty pages
3053  *
3054  * We have two ways to find all sptes to protect:
3055  * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
3056  *    checks ones that have a spte mapping a page in the slot.
3057  * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
3058  *
3059  * Generally speaking, if there are not so many dirty pages compared to the
3060  * number of shadow pages, we should use the latter.
3061  *
3062  * Note that letting others write into a page marked dirty in the old bitmap
3063  * by using the remaining tlb entry is not a problem.  That page will become
3064  * write protected again when we flush the tlb and then be reported dirty to
3065  * the user space by copying the old bitmap.
3066  */
3067 static void write_protect_slot(struct kvm *kvm,
3068                                struct kvm_memory_slot *memslot,
3069                                unsigned long *dirty_bitmap,
3070                                unsigned long nr_dirty_pages)
3071 {
3072         spin_lock(&kvm->mmu_lock);
3073
3074         /* Not many dirty pages compared to # of shadow pages. */
3075         if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
3076                 unsigned long gfn_offset;
3077
3078                 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
3079                         unsigned long gfn = memslot->base_gfn + gfn_offset;
3080
3081                         kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
3082                 }
3083                 kvm_flush_remote_tlbs(kvm);
3084         } else
3085                 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
3086
3087         spin_unlock(&kvm->mmu_lock);
3088 }
3089
3090 /*
3091  * Get (and clear) the dirty memory log for a memory slot.
3092  */
3093 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3094                                       struct kvm_dirty_log *log)
3095 {
3096         int r;
3097         struct kvm_memory_slot *memslot;
3098         unsigned long n, nr_dirty_pages;
3099
3100         mutex_lock(&kvm->slots_lock);
3101
3102         r = -EINVAL;
3103         if (log->slot >= KVM_MEMORY_SLOTS)
3104                 goto out;
3105
3106         memslot = id_to_memslot(kvm->memslots, log->slot);
3107         r = -ENOENT;
3108         if (!memslot->dirty_bitmap)
3109                 goto out;
3110
3111         n = kvm_dirty_bitmap_bytes(memslot);
3112         nr_dirty_pages = memslot->nr_dirty_pages;
3113
3114         /* If nothing is dirty, don't bother messing with page tables. */
3115         if (nr_dirty_pages) {
3116                 struct kvm_memslots *slots, *old_slots;
3117                 unsigned long *dirty_bitmap, *dirty_bitmap_head;
3118
3119                 dirty_bitmap = memslot->dirty_bitmap;
3120                 dirty_bitmap_head = memslot->dirty_bitmap_head;
3121                 if (dirty_bitmap == dirty_bitmap_head)
3122                         dirty_bitmap_head += n / sizeof(long);
3123                 memset(dirty_bitmap_head, 0, n);
3124
3125                 r = -ENOMEM;
3126                 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
3127                 if (!slots)
3128                         goto out;
3129
3130                 memslot = id_to_memslot(slots, log->slot);
3131                 memslot->nr_dirty_pages = 0;
3132                 memslot->dirty_bitmap = dirty_bitmap_head;
3133                 update_memslots(slots, NULL);
3134
3135                 old_slots = kvm->memslots;
3136                 rcu_assign_pointer(kvm->memslots, slots);
3137                 synchronize_srcu_expedited(&kvm->srcu);
3138                 kfree(old_slots);
3139
3140                 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
3141
3142                 r = -EFAULT;
3143                 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
3144                         goto out;
3145         } else {
3146                 r = -EFAULT;
3147                 if (clear_user(log->dirty_bitmap, n))
3148                         goto out;
3149         }
3150
3151         r = 0;
3152 out:
3153         mutex_unlock(&kvm->slots_lock);
3154         return r;
3155 }
3156
3157 long kvm_arch_vm_ioctl(struct file *filp,
3158                        unsigned int ioctl, unsigned long arg)
3159 {
3160         struct kvm *kvm = filp->private_data;
3161         void __user *argp = (void __user *)arg;
3162         int r = -ENOTTY;
3163         /*
3164          * This union makes it completely explicit to gcc-3.x
3165          * that these two variables' stack usage should be
3166          * combined, not added together.
3167          */
3168         union {
3169                 struct kvm_pit_state ps;
3170                 struct kvm_pit_state2 ps2;
3171                 struct kvm_pit_config pit_config;
3172         } u;
3173
3174         switch (ioctl) {
3175         case KVM_SET_TSS_ADDR:
3176                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3177                 if (r < 0)
3178                         goto out;
3179                 break;
3180         case KVM_SET_IDENTITY_MAP_ADDR: {
3181                 u64 ident_addr;
3182
3183                 r = -EFAULT;
3184                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3185                         goto out;
3186                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3187                 if (r < 0)
3188                         goto out;
3189                 break;
3190         }
3191         case KVM_SET_NR_MMU_PAGES:
3192                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3193                 if (r)
3194                         goto out;
3195                 break;
3196         case KVM_GET_NR_MMU_PAGES:
3197                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3198                 break;
3199         case KVM_CREATE_IRQCHIP: {
3200                 struct kvm_pic *vpic;
3201
3202                 mutex_lock(&kvm->lock);
3203                 r = -EEXIST;
3204                 if (kvm->arch.vpic)
3205                         goto create_irqchip_unlock;
3206                 r = -EINVAL;
3207                 if (atomic_read(&kvm->online_vcpus))
3208                         goto create_irqchip_unlock;
3209                 r = -ENOMEM;
3210                 vpic = kvm_create_pic(kvm);
3211                 if (vpic) {
3212                         r = kvm_ioapic_init(kvm);
3213                         if (r) {
3214                                 mutex_lock(&kvm->slots_lock);
3215                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3216                                                           &vpic->dev_master);
3217                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3218                                                           &vpic->dev_slave);
3219                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3220                                                           &vpic->dev_eclr);
3221                                 mutex_unlock(&kvm->slots_lock);
3222                                 kfree(vpic);
3223                                 goto create_irqchip_unlock;
3224                         }
3225                 } else
3226                         goto create_irqchip_unlock;
3227                 smp_wmb();
3228                 kvm->arch.vpic = vpic;
3229                 smp_wmb();
3230                 r = kvm_setup_default_irq_routing(kvm);
3231                 if (r) {
3232                         mutex_lock(&kvm->slots_lock);
3233                         mutex_lock(&kvm->irq_lock);
3234                         kvm_ioapic_destroy(kvm);
3235                         kvm_destroy_pic(kvm);
3236                         mutex_unlock(&kvm->irq_lock);
3237                         mutex_unlock(&kvm->slots_lock);
3238                 }
3239         create_irqchip_unlock:
3240                 mutex_unlock(&kvm->lock);
3241                 break;
3242         }
3243         case KVM_CREATE_PIT:
3244                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3245                 goto create_pit;
3246         case KVM_CREATE_PIT2:
3247                 r = -EFAULT;
3248                 if (copy_from_user(&u.pit_config, argp,
3249                                    sizeof(struct kvm_pit_config)))
3250                         goto out;
3251         create_pit:
3252                 mutex_lock(&kvm->slots_lock);
3253                 r = -EEXIST;
3254                 if (kvm->arch.vpit)
3255                         goto create_pit_unlock;
3256                 r = -ENOMEM;
3257                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3258                 if (kvm->arch.vpit)
3259                         r = 0;
3260         create_pit_unlock:
3261                 mutex_unlock(&kvm->slots_lock);
3262                 break;
3263         case KVM_IRQ_LINE_STATUS:
3264         case KVM_IRQ_LINE: {
3265                 struct kvm_irq_level irq_event;
3266
3267                 r = -EFAULT;
3268                 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3269                         goto out;
3270                 r = -ENXIO;
3271                 if (irqchip_in_kernel(kvm)) {
3272                         __s32 status;
3273                         status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3274                                         irq_event.irq, irq_event.level);
3275                         if (ioctl == KVM_IRQ_LINE_STATUS) {
3276                                 r = -EFAULT;
3277                                 irq_event.status = status;
3278                                 if (copy_to_user(argp, &irq_event,
3279                                                         sizeof irq_event))
3280                                         goto out;
3281                         }
3282                         r = 0;
3283                 }
3284                 break;
3285         }
3286         case KVM_GET_IRQCHIP: {
3287                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3288                 struct kvm_irqchip *chip;
3289
3290                 chip = memdup_user(argp, sizeof(*chip));
3291                 if (IS_ERR(chip)) {
3292                         r = PTR_ERR(chip);
3293                         goto out;
3294                 }
3295
3296                 r = -ENXIO;
3297                 if (!irqchip_in_kernel(kvm))
3298                         goto get_irqchip_out;
3299                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3300                 if (r)
3301                         goto get_irqchip_out;
3302                 r = -EFAULT;
3303                 if (copy_to_user(argp, chip, sizeof *chip))
3304                         goto get_irqchip_out;
3305                 r = 0;
3306         get_irqchip_out:
3307                 kfree(chip);
3308                 if (r)
3309                         goto out;
3310                 break;
3311         }
3312         case KVM_SET_IRQCHIP: {
3313                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3314                 struct kvm_irqchip *chip;
3315
3316                 chip = memdup_user(argp, sizeof(*chip));
3317                 if (IS_ERR(chip)) {
3318                         r = PTR_ERR(chip);
3319                         goto out;
3320                 }
3321
3322                 r = -ENXIO;
3323                 if (!irqchip_in_kernel(kvm))
3324                         goto set_irqchip_out;
3325                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3326                 if (r)
3327                         goto set_irqchip_out;
3328                 r = 0;
3329         set_irqchip_out:
3330                 kfree(chip);
3331                 if (r)
3332                         goto out;
3333                 break;
3334         }
3335         case KVM_GET_PIT: {
3336                 r = -EFAULT;
3337                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3338                         goto out;
3339                 r = -ENXIO;
3340                 if (!kvm->arch.vpit)
3341                         goto out;
3342                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3343                 if (r)
3344                         goto out;
3345                 r = -EFAULT;
3346                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3347                         goto out;
3348                 r = 0;
3349                 break;
3350         }
3351         case KVM_SET_PIT: {
3352                 r = -EFAULT;
3353                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3354                         goto out;
3355                 r = -ENXIO;
3356                 if (!kvm->arch.vpit)
3357                         goto out;
3358                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3359                 if (r)
3360                         goto out;
3361                 r = 0;
3362                 break;
3363         }
3364         case KVM_GET_PIT2: {
3365                 r = -ENXIO;
3366                 if (!kvm->arch.vpit)
3367                         goto out;
3368                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3369                 if (r)
3370                         goto out;
3371                 r = -EFAULT;
3372                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3373                         goto out;
3374                 r = 0;
3375                 break;
3376         }
3377         case KVM_SET_PIT2: {
3378  &