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1 /*
2  * @file op_model_amd.c
3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
4  *
5  * @remark Copyright 2002-2009 OProfile authors
6  * @remark Read the file COPYING
7  *
8  * @author John Levon
9  * @author Philippe Elie
10  * @author Graydon Hoare
11  * @author Robert Richter <robert.richter@amd.com>
12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
13  * @author Jason Yeh <jason.yeh@amd.com>
14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
15  */
16
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
21
22 #include <asm/ptrace.h>
23 #include <asm/msr.h>
24 #include <asm/nmi.h>
25 #include <asm/apic.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
28
29 #include "op_x86_model.h"
30 #include "op_counter.h"
31
32 #define NUM_COUNTERS 4
33 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
34 #define NUM_VIRT_COUNTERS 32
35 #else
36 #define NUM_VIRT_COUNTERS NUM_COUNTERS
37 #endif
38
39 #define OP_EVENT_MASK                   0x0FFF
40 #define OP_CTR_OVERFLOW                 (1ULL<<31)
41
42 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
43
44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
45
46 #define IBS_FETCH_SIZE                  6
47 #define IBS_OP_SIZE                     12
48
49 static u32 ibs_caps;
50
51 struct op_ibs_config {
52         unsigned long op_enabled;
53         unsigned long fetch_enabled;
54         unsigned long max_cnt_fetch;
55         unsigned long max_cnt_op;
56         unsigned long rand_en;
57         unsigned long dispatched_ops;
58 };
59
60 static struct op_ibs_config ibs_config;
61 static u64 ibs_op_ctl;
62
63 /*
64  * IBS cpuid feature detection
65  */
66
67 #define IBS_CPUID_FEATURES              0x8000001b
68
69 /*
70  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
71  * bit 0 is used to indicate the existence of IBS.
72  */
73 #define IBS_CAPS_AVAIL                  (1U<<0)
74 #define IBS_CAPS_RDWROPCNT              (1U<<3)
75 #define IBS_CAPS_OPCNT                  (1U<<4)
76
77 /*
78  * IBS APIC setup
79  */
80 #define IBSCTL                          0x1cc
81 #define IBSCTL_LVT_OFFSET_VALID         (1ULL<<8)
82 #define IBSCTL_LVT_OFFSET_MASK          0x0F
83
84 /*
85  * IBS randomization macros
86  */
87 #define IBS_RANDOM_BITS                 12
88 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
89 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
90
91 static u32 get_ibs_caps(void)
92 {
93         u32 ibs_caps;
94         unsigned int max_level;
95
96         if (!boot_cpu_has(X86_FEATURE_IBS))
97                 return 0;
98
99         /* check IBS cpuid feature flags */
100         max_level = cpuid_eax(0x80000000);
101         if (max_level < IBS_CPUID_FEATURES)
102                 return IBS_CAPS_AVAIL;
103
104         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
105         if (!(ibs_caps & IBS_CAPS_AVAIL))
106                 /* cpuid flags not valid */
107                 return IBS_CAPS_AVAIL;
108
109         return ibs_caps;
110 }
111
112 /*
113  * 16-bit Linear Feedback Shift Register (LFSR)
114  *
115  *                       16   14   13    11
116  * Feedback polynomial = X  + X  + X  +  X  + 1
117  */
118 static unsigned int lfsr_random(void)
119 {
120         static unsigned int lfsr_value = 0xF00D;
121         unsigned int bit;
122
123         /* Compute next bit to shift in */
124         bit = ((lfsr_value >> 0) ^
125                (lfsr_value >> 2) ^
126                (lfsr_value >> 3) ^
127                (lfsr_value >> 5)) & 0x0001;
128
129         /* Advance to next register value */
130         lfsr_value = (lfsr_value >> 1) | (bit << 15);
131
132         return lfsr_value;
133 }
134
135 /*
136  * IBS software randomization
137  *
138  * The IBS periodic op counter is randomized in software. The lower 12
139  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
140  * initialized with a 12 bit random value.
141  */
142 static inline u64 op_amd_randomize_ibs_op(u64 val)
143 {
144         unsigned int random = lfsr_random();
145
146         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
147                 /*
148                  * Work around if the hw can not write to IbsOpCurCnt
149                  *
150                  * Randomize the lower 8 bits of the 16 bit
151                  * IbsOpMaxCnt [15:0] value in the range of -128 to
152                  * +127 by adding/subtracting an offset to the
153                  * maximum count (IbsOpMaxCnt).
154                  *
155                  * To avoid over or underflows and protect upper bits
156                  * starting at bit 16, the initial value for
157                  * IbsOpMaxCnt must fit in the range from 0x0081 to
158                  * 0xff80.
159                  */
160                 val += (s8)(random >> 4);
161         else
162                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
163
164         return val;
165 }
166
167 static inline void
168 op_amd_handle_ibs(struct pt_regs * const regs,
169                   struct op_msrs const * const msrs)
170 {
171         u64 val, ctl;
172         struct op_entry entry;
173
174         if (!ibs_caps)
175                 return;
176
177         if (ibs_config.fetch_enabled) {
178                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
179                 if (ctl & IBS_FETCH_VAL) {
180                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
181                         oprofile_write_reserve(&entry, regs, val,
182                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
183                         oprofile_add_data64(&entry, val);
184                         oprofile_add_data64(&entry, ctl);
185                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
186                         oprofile_add_data64(&entry, val);
187                         oprofile_write_commit(&entry);
188
189                         /* reenable the IRQ */
190                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
191                         ctl |= IBS_FETCH_ENABLE;
192                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
193                 }
194         }
195
196         if (ibs_config.op_enabled) {
197                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
198                 if (ctl & IBS_OP_VAL) {
199                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
200                         oprofile_write_reserve(&entry, regs, val,
201                                                IBS_OP_CODE, IBS_OP_SIZE);
202                         oprofile_add_data64(&entry, val);
203                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
204                         oprofile_add_data64(&entry, val);
205                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
206                         oprofile_add_data64(&entry, val);
207                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
208                         oprofile_add_data64(&entry, val);
209                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
210                         oprofile_add_data64(&entry, val);
211                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
212                         oprofile_add_data64(&entry, val);
213                         oprofile_write_commit(&entry);
214
215                         /* reenable the IRQ */
216                         ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
217                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
218                 }
219         }
220 }
221
222 static inline void op_amd_start_ibs(void)
223 {
224         u64 val;
225
226         if (!ibs_caps)
227                 return;
228
229         if (ibs_config.fetch_enabled) {
230                 val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
231                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
232                 val |= IBS_FETCH_ENABLE;
233                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
234         }
235
236         if (ibs_config.op_enabled) {
237                 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
238                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
239                         /*
240                          * IbsOpCurCnt not supported.  See
241                          * op_amd_randomize_ibs_op() for details.
242                          */
243                         ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
244                 } else {
245                         /*
246                          * The start value is randomized with a
247                          * positive offset, we need to compensate it
248                          * with the half of the randomized range. Also
249                          * avoid underflows.
250                          */
251                         ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
252                                          IBS_OP_MAX_CNT);
253                 }
254                 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
255                         ibs_op_ctl |= IBS_OP_CNT_CTL;
256                 ibs_op_ctl |= IBS_OP_ENABLE;
257                 val = op_amd_randomize_ibs_op(ibs_op_ctl);
258                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
259         }
260 }
261
262 static void op_amd_stop_ibs(void)
263 {
264         if (!ibs_caps)
265                 return;
266
267         if (ibs_config.fetch_enabled)
268                 /* clear max count and enable */
269                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
270
271         if (ibs_config.op_enabled)
272                 /* clear max count and enable */
273                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
274 }
275
276 static inline int eilvt_is_available(int offset)
277 {
278         /* check if we may assign a vector */
279         return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
280 }
281
282 static inline int ibs_eilvt_valid(void)
283 {
284         u64 val;
285         int offset;
286
287         rdmsrl(MSR_AMD64_IBSCTL, val);
288         if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
289                 pr_err(FW_BUG "cpu %d, invalid IBS "
290                        "interrupt offset %d (MSR%08X=0x%016llx)",
291                        smp_processor_id(), offset,
292                        MSR_AMD64_IBSCTL, val);
293                 return 0;
294         }
295
296         offset = val & IBSCTL_LVT_OFFSET_MASK;
297
298         if (eilvt_is_available(offset))
299                 return !0;
300
301         pr_err(FW_BUG "cpu %d, IBS interrupt offset %d "
302                "not available (MSR%08X=0x%016llx)",
303                smp_processor_id(), offset,
304                MSR_AMD64_IBSCTL, val);
305
306         return 0;
307 }
308
309 static inline int get_ibs_offset(void)
310 {
311         u64 val;
312
313         rdmsrl(MSR_AMD64_IBSCTL, val);
314         if (!(val & IBSCTL_LVT_OFFSET_VALID))
315                 return -EINVAL;
316
317         return val & IBSCTL_LVT_OFFSET_MASK;
318 }
319
320 static void setup_APIC_ibs(void)
321 {
322         int offset;
323
324         offset = get_ibs_offset();
325         if (offset < 0)
326                 goto failed;
327
328         if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
329                 return;
330 failed:
331         pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n",
332                 smp_processor_id());
333 }
334
335 static void clear_APIC_ibs(void)
336 {
337         int offset;
338
339         offset = get_ibs_offset();
340         if (offset >= 0)
341                 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
342 }
343
344 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
345
346 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
347                                struct op_msrs const * const msrs)
348 {
349         u64 val;
350         int i;
351
352         /* enable active counters */
353         for (i = 0; i < NUM_COUNTERS; ++i) {
354                 int virt = op_x86_phys_to_virt(i);
355                 if (!reset_value[virt])
356                         continue;
357                 rdmsrl(msrs->controls[i].addr, val);
358                 val &= model->reserved;
359                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
360                 wrmsrl(msrs->controls[i].addr, val);
361         }
362 }
363
364 #endif
365
366 /* functions for op_amd_spec */
367
368 static void op_amd_shutdown(struct op_msrs const * const msrs)
369 {
370         int i;
371
372         for (i = 0; i < NUM_COUNTERS; ++i) {
373                 if (!msrs->counters[i].addr)
374                         continue;
375                 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
376                 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
377         }
378 }
379
380 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
381 {
382         int i;
383
384         for (i = 0; i < NUM_COUNTERS; i++) {
385                 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
386                         goto fail;
387                 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
388                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
389                         goto fail;
390                 }
391                 /* both registers must be reserved */
392                 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
393                 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
394                 continue;
395         fail:
396                 if (!counter_config[i].enabled)
397                         continue;
398                 op_x86_warn_reserved(i);
399                 op_amd_shutdown(msrs);
400                 return -EBUSY;
401         }
402
403         return 0;
404 }
405
406 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
407                               struct op_msrs const * const msrs)
408 {
409         u64 val;
410         int i;
411
412         /* setup reset_value */
413         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
414                 if (counter_config[i].enabled
415                     && msrs->counters[op_x86_virt_to_phys(i)].addr)
416                         reset_value[i] = counter_config[i].count;
417                 else
418                         reset_value[i] = 0;
419         }
420
421         /* clear all counters */
422         for (i = 0; i < NUM_COUNTERS; ++i) {
423                 if (!msrs->controls[i].addr)
424                         continue;
425                 rdmsrl(msrs->controls[i].addr, val);
426                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
427                         op_x86_warn_in_use(i);
428                 val &= model->reserved;
429                 wrmsrl(msrs->controls[i].addr, val);
430                 /*
431                  * avoid a false detection of ctr overflows in NMI
432                  * handler
433                  */
434                 wrmsrl(msrs->counters[i].addr, -1LL);
435         }
436
437         /* enable active counters */
438         for (i = 0; i < NUM_COUNTERS; ++i) {
439                 int virt = op_x86_phys_to_virt(i);
440                 if (!reset_value[virt])
441                         continue;
442
443                 /* setup counter registers */
444                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
445
446                 /* setup control registers */
447                 rdmsrl(msrs->controls[i].addr, val);
448                 val &= model->reserved;
449                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
450                 wrmsrl(msrs->controls[i].addr, val);
451         }
452
453         if (ibs_caps)
454                 setup_APIC_ibs();
455 }
456
457 static void op_amd_cpu_shutdown(void)
458 {
459         if (ibs_caps)
460                 clear_APIC_ibs();
461 }
462
463 static int op_amd_check_ctrs(struct pt_regs * const regs,
464                              struct op_msrs const * const msrs)
465 {
466         u64 val;
467         int i;
468
469         for (i = 0; i < NUM_COUNTERS; ++i) {
470                 int virt = op_x86_phys_to_virt(i);
471                 if (!reset_value[virt])
472                         continue;
473                 rdmsrl(msrs->counters[i].addr, val);
474                 /* bit is clear if overflowed: */
475                 if (val & OP_CTR_OVERFLOW)
476                         continue;
477                 oprofile_add_sample(regs, virt);
478                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
479         }
480
481         op_amd_handle_ibs(regs, msrs);
482
483         /* See op_model_ppro.c */
484         return 1;
485 }
486
487 static void op_amd_start(struct op_msrs const * const msrs)
488 {
489         u64 val;
490         int i;
491
492         for (i = 0; i < NUM_COUNTERS; ++i) {
493                 if (!reset_value[op_x86_phys_to_virt(i)])
494                         continue;
495                 rdmsrl(msrs->controls[i].addr, val);
496                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
497                 wrmsrl(msrs->controls[i].addr, val);
498         }
499
500         op_amd_start_ibs();
501 }
502
503 static void op_amd_stop(struct op_msrs const * const msrs)
504 {
505         u64 val;
506         int i;
507
508         /*
509          * Subtle: stop on all counters to avoid race with setting our
510          * pm callback
511          */
512         for (i = 0; i < NUM_COUNTERS; ++i) {
513                 if (!reset_value[op_x86_phys_to_virt(i)])
514                         continue;
515                 rdmsrl(msrs->controls[i].addr, val);
516                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
517                 wrmsrl(msrs->controls[i].addr, val);
518         }
519
520         op_amd_stop_ibs();
521 }
522
523 static int setup_ibs_ctl(int ibs_eilvt_off)
524 {
525         struct pci_dev *cpu_cfg;
526         int nodes;
527         u32 value = 0;
528
529         nodes = 0;
530         cpu_cfg = NULL;
531         do {
532                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
533                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
534                                          cpu_cfg);
535                 if (!cpu_cfg)
536                         break;
537                 ++nodes;
538                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
539                                        | IBSCTL_LVT_OFFSET_VALID);
540                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
541                 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
542                         pci_dev_put(cpu_cfg);
543                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
544                                "IBSCTL = 0x%08x\n", value);
545                         return -EINVAL;
546                 }
547         } while (1);
548
549         if (!nodes) {
550                 printk(KERN_DEBUG "No CPU node configured for IBS\n");
551                 return -ENODEV;
552         }
553
554         return 0;
555 }
556
557 static int force_ibs_eilvt_setup(void)
558 {
559         int i;
560         int ret;
561
562         /* find the next free available EILVT entry */
563         for (i = 1; i < 4; i++) {
564                 if (!eilvt_is_available(i))
565                         continue;
566                 ret = setup_ibs_ctl(i);
567                 if (ret)
568                         return ret;
569                 return 0;
570         }
571
572         printk(KERN_DEBUG "No EILVT entry available\n");
573
574         return -EBUSY;
575 }
576
577 static int __init_ibs_nmi(void)
578 {
579         int ret;
580
581         if (ibs_eilvt_valid())
582                 return 0;
583
584         ret = force_ibs_eilvt_setup();
585         if (ret)
586                 return ret;
587
588         if (!ibs_eilvt_valid())
589                 return -EFAULT;
590
591         pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
592
593         return 0;
594 }
595
596 /* initialize the APIC for the IBS interrupts if available */
597 static void init_ibs(void)
598 {
599         ibs_caps = get_ibs_caps();
600
601         if (!ibs_caps)
602                 return;
603
604         if (__init_ibs_nmi()) {
605                 ibs_caps = 0;
606                 return;
607         }
608
609         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
610                (unsigned)ibs_caps);
611 }
612
613 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
614
615 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
616 {
617         struct dentry *dir;
618         int ret = 0;
619
620         /* architecture specific files */
621         if (create_arch_files)
622                 ret = create_arch_files(sb, root);
623
624         if (ret)
625                 return ret;
626
627         if (!ibs_caps)
628                 return ret;
629
630         /* model specific files */
631
632         /* setup some reasonable defaults */
633         ibs_config.max_cnt_fetch = 250000;
634         ibs_config.fetch_enabled = 0;
635         ibs_config.max_cnt_op = 250000;
636         ibs_config.op_enabled = 0;
637         ibs_config.dispatched_ops = 0;
638
639         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
640         oprofilefs_create_ulong(sb, dir, "enable",
641                                 &ibs_config.fetch_enabled);
642         oprofilefs_create_ulong(sb, dir, "max_count",
643                                 &ibs_config.max_cnt_fetch);
644         oprofilefs_create_ulong(sb, dir, "rand_enable",
645                                 &ibs_config.rand_en);
646
647         dir = oprofilefs_mkdir(sb, root, "ibs_op");
648         oprofilefs_create_ulong(sb, dir, "enable",
649                                 &ibs_config.op_enabled);
650         oprofilefs_create_ulong(sb, dir, "max_count",
651                                 &ibs_config.max_cnt_op);
652         if (ibs_caps & IBS_CAPS_OPCNT)
653                 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
654                                         &ibs_config.dispatched_ops);
655
656         return 0;
657 }
658
659 static int op_amd_init(struct oprofile_operations *ops)
660 {
661         init_ibs();
662         create_arch_files = ops->create_files;
663         ops->create_files = setup_ibs_files;
664         return 0;
665 }
666
667 struct op_x86_model_spec op_amd_spec = {
668         .num_counters           = NUM_COUNTERS,
669         .num_controls           = NUM_COUNTERS,
670         .num_virt_counters      = NUM_VIRT_COUNTERS,
671         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
672         .event_mask             = OP_EVENT_MASK,
673         .init                   = op_amd_init,
674         .fill_in_addresses      = &op_amd_fill_in_addresses,
675         .setup_ctrs             = &op_amd_setup_ctrs,
676         .cpu_down               = &op_amd_cpu_shutdown,
677         .check_ctrs             = &op_amd_check_ctrs,
678         .start                  = &op_amd_start,
679         .stop                   = &op_amd_stop,
680         .shutdown               = &op_amd_shutdown,
681 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
682         .switch_ctrl            = &op_mux_switch_ctrl,
683 #endif
684 };