x86/iommu/intel: Increase the number of iommus supported to MAX_IO_APICS
[~shefty/rdma-dev.git] / drivers / block / DAC960.c
1 /*
2
3   Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
4
5   Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
6   Portions Copyright 2002 by Mylex (An IBM Business Unit)
7
8   This program is free software; you may redistribute and/or modify it under
9   the terms of the GNU General Public License Version 2 as published by the
10   Free Software Foundation.
11
12   This program is distributed in the hope that it will be useful, but
13   WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
14   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15   for complete details.
16
17 */
18
19
20 #define DAC960_DriverVersion                    "2.5.49"
21 #define DAC960_DriverDate                       "21 Aug 2007"
22
23
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/miscdevice.h>
27 #include <linux/blkdev.h>
28 #include <linux/bio.h>
29 #include <linux/completion.h>
30 #include <linux/delay.h>
31 #include <linux/genhd.h>
32 #include <linux/hdreg.h>
33 #include <linux/blkpg.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/interrupt.h>
36 #include <linux/ioport.h>
37 #include <linux/mm.h>
38 #include <linux/slab.h>
39 #include <linux/mutex.h>
40 #include <linux/proc_fs.h>
41 #include <linux/seq_file.h>
42 #include <linux/reboot.h>
43 #include <linux/spinlock.h>
44 #include <linux/timer.h>
45 #include <linux/pci.h>
46 #include <linux/init.h>
47 #include <linux/jiffies.h>
48 #include <linux/random.h>
49 #include <linux/scatterlist.h>
50 #include <asm/io.h>
51 #include <asm/uaccess.h>
52 #include "DAC960.h"
53
54 #define DAC960_GAM_MINOR        252
55
56
57 static DEFINE_MUTEX(DAC960_mutex);
58 static DAC960_Controller_T *DAC960_Controllers[DAC960_MaxControllers];
59 static int DAC960_ControllerCount;
60 static struct proc_dir_entry *DAC960_ProcDirectoryEntry;
61
62 static long disk_size(DAC960_Controller_T *p, int drive_nr)
63 {
64         if (p->FirmwareType == DAC960_V1_Controller) {
65                 if (drive_nr >= p->LogicalDriveCount)
66                         return 0;
67                 return p->V1.LogicalDriveInformation[drive_nr].
68                         LogicalDriveSize;
69         } else {
70                 DAC960_V2_LogicalDeviceInfo_T *i =
71                         p->V2.LogicalDeviceInformation[drive_nr];
72                 if (i == NULL)
73                         return 0;
74                 return i->ConfigurableDeviceSize;
75         }
76 }
77
78 static int DAC960_open(struct block_device *bdev, fmode_t mode)
79 {
80         struct gendisk *disk = bdev->bd_disk;
81         DAC960_Controller_T *p = disk->queue->queuedata;
82         int drive_nr = (long)disk->private_data;
83         int ret = -ENXIO;
84
85         mutex_lock(&DAC960_mutex);
86         if (p->FirmwareType == DAC960_V1_Controller) {
87                 if (p->V1.LogicalDriveInformation[drive_nr].
88                     LogicalDriveState == DAC960_V1_LogicalDrive_Offline)
89                         goto out;
90         } else {
91                 DAC960_V2_LogicalDeviceInfo_T *i =
92                         p->V2.LogicalDeviceInformation[drive_nr];
93                 if (!i || i->LogicalDeviceState == DAC960_V2_LogicalDevice_Offline)
94                         goto out;
95         }
96
97         check_disk_change(bdev);
98
99         if (!get_capacity(p->disks[drive_nr]))
100                 goto out;
101         ret = 0;
102 out:
103         mutex_unlock(&DAC960_mutex);
104         return ret;
105 }
106
107 static int DAC960_getgeo(struct block_device *bdev, struct hd_geometry *geo)
108 {
109         struct gendisk *disk = bdev->bd_disk;
110         DAC960_Controller_T *p = disk->queue->queuedata;
111         int drive_nr = (long)disk->private_data;
112
113         if (p->FirmwareType == DAC960_V1_Controller) {
114                 geo->heads = p->V1.GeometryTranslationHeads;
115                 geo->sectors = p->V1.GeometryTranslationSectors;
116                 geo->cylinders = p->V1.LogicalDriveInformation[drive_nr].
117                         LogicalDriveSize / (geo->heads * geo->sectors);
118         } else {
119                 DAC960_V2_LogicalDeviceInfo_T *i =
120                         p->V2.LogicalDeviceInformation[drive_nr];
121                 switch (i->DriveGeometry) {
122                 case DAC960_V2_Geometry_128_32:
123                         geo->heads = 128;
124                         geo->sectors = 32;
125                         break;
126                 case DAC960_V2_Geometry_255_63:
127                         geo->heads = 255;
128                         geo->sectors = 63;
129                         break;
130                 default:
131                         DAC960_Error("Illegal Logical Device Geometry %d\n",
132                                         p, i->DriveGeometry);
133                         return -EINVAL;
134                 }
135
136                 geo->cylinders = i->ConfigurableDeviceSize /
137                         (geo->heads * geo->sectors);
138         }
139         
140         return 0;
141 }
142
143 static unsigned int DAC960_check_events(struct gendisk *disk,
144                                         unsigned int clearing)
145 {
146         DAC960_Controller_T *p = disk->queue->queuedata;
147         int drive_nr = (long)disk->private_data;
148
149         if (!p->LogicalDriveInitiallyAccessible[drive_nr])
150                 return DISK_EVENT_MEDIA_CHANGE;
151         return 0;
152 }
153
154 static int DAC960_revalidate_disk(struct gendisk *disk)
155 {
156         DAC960_Controller_T *p = disk->queue->queuedata;
157         int unit = (long)disk->private_data;
158
159         set_capacity(disk, disk_size(p, unit));
160         return 0;
161 }
162
163 static const struct block_device_operations DAC960_BlockDeviceOperations = {
164         .owner                  = THIS_MODULE,
165         .open                   = DAC960_open,
166         .getgeo                 = DAC960_getgeo,
167         .check_events           = DAC960_check_events,
168         .revalidate_disk        = DAC960_revalidate_disk,
169 };
170
171
172 /*
173   DAC960_AnnounceDriver announces the Driver Version and Date, Author's Name,
174   Copyright Notice, and Electronic Mail Address.
175 */
176
177 static void DAC960_AnnounceDriver(DAC960_Controller_T *Controller)
178 {
179   DAC960_Announce("***** DAC960 RAID Driver Version "
180                   DAC960_DriverVersion " of "
181                   DAC960_DriverDate " *****\n", Controller);
182   DAC960_Announce("Copyright 1998-2001 by Leonard N. Zubkoff "
183                   "<lnz@dandelion.com>\n", Controller);
184 }
185
186
187 /*
188   DAC960_Failure prints a standardized error message, and then returns false.
189 */
190
191 static bool DAC960_Failure(DAC960_Controller_T *Controller,
192                               unsigned char *ErrorMessage)
193 {
194   DAC960_Error("While configuring DAC960 PCI RAID Controller at\n",
195                Controller);
196   if (Controller->IO_Address == 0)
197     DAC960_Error("PCI Bus %d Device %d Function %d I/O Address N/A "
198                  "PCI Address 0x%X\n", Controller,
199                  Controller->Bus, Controller->Device,
200                  Controller->Function, Controller->PCI_Address);
201   else DAC960_Error("PCI Bus %d Device %d Function %d I/O Address "
202                     "0x%X PCI Address 0x%X\n", Controller,
203                     Controller->Bus, Controller->Device,
204                     Controller->Function, Controller->IO_Address,
205                     Controller->PCI_Address);
206   DAC960_Error("%s FAILED - DETACHING\n", Controller, ErrorMessage);
207   return false;
208 }
209
210 /*
211   init_dma_loaf() and slice_dma_loaf() are helper functions for
212   aggregating the dma-mapped memory for a well-known collection of
213   data structures that are of different lengths.
214
215   These routines don't guarantee any alignment.  The caller must
216   include any space needed for alignment in the sizes of the structures
217   that are passed in.
218  */
219
220 static bool init_dma_loaf(struct pci_dev *dev, struct dma_loaf *loaf,
221                                                                  size_t len)
222 {
223         void *cpu_addr;
224         dma_addr_t dma_handle;
225
226         cpu_addr = pci_alloc_consistent(dev, len, &dma_handle);
227         if (cpu_addr == NULL)
228                 return false;
229         
230         loaf->cpu_free = loaf->cpu_base = cpu_addr;
231         loaf->dma_free =loaf->dma_base = dma_handle;
232         loaf->length = len;
233         memset(cpu_addr, 0, len);
234         return true;
235 }
236
237 static void *slice_dma_loaf(struct dma_loaf *loaf, size_t len,
238                                         dma_addr_t *dma_handle)
239 {
240         void *cpu_end = loaf->cpu_free + len;
241         void *cpu_addr = loaf->cpu_free;
242
243         BUG_ON(cpu_end > loaf->cpu_base + loaf->length);
244         *dma_handle = loaf->dma_free;
245         loaf->cpu_free = cpu_end;
246         loaf->dma_free += len;
247         return cpu_addr;
248 }
249
250 static void free_dma_loaf(struct pci_dev *dev, struct dma_loaf *loaf_handle)
251 {
252         if (loaf_handle->cpu_base != NULL)
253                 pci_free_consistent(dev, loaf_handle->length,
254                         loaf_handle->cpu_base, loaf_handle->dma_base);
255 }
256
257
258 /*
259   DAC960_CreateAuxiliaryStructures allocates and initializes the auxiliary
260   data structures for Controller.  It returns true on success and false on
261   failure.
262 */
263
264 static bool DAC960_CreateAuxiliaryStructures(DAC960_Controller_T *Controller)
265 {
266   int CommandAllocationLength, CommandAllocationGroupSize;
267   int CommandsRemaining = 0, CommandIdentifier, CommandGroupByteCount;
268   void *AllocationPointer = NULL;
269   void *ScatterGatherCPU = NULL;
270   dma_addr_t ScatterGatherDMA;
271   struct pci_pool *ScatterGatherPool;
272   void *RequestSenseCPU = NULL;
273   dma_addr_t RequestSenseDMA;
274   struct pci_pool *RequestSensePool = NULL;
275
276   if (Controller->FirmwareType == DAC960_V1_Controller)
277     {
278       CommandAllocationLength = offsetof(DAC960_Command_T, V1.EndMarker);
279       CommandAllocationGroupSize = DAC960_V1_CommandAllocationGroupSize;
280       ScatterGatherPool = pci_pool_create("DAC960_V1_ScatterGather",
281                 Controller->PCIDevice,
282         DAC960_V1_ScatterGatherLimit * sizeof(DAC960_V1_ScatterGatherSegment_T),
283         sizeof(DAC960_V1_ScatterGatherSegment_T), 0);
284       if (ScatterGatherPool == NULL)
285             return DAC960_Failure(Controller,
286                         "AUXILIARY STRUCTURE CREATION (SG)");
287       Controller->ScatterGatherPool = ScatterGatherPool;
288     }
289   else
290     {
291       CommandAllocationLength = offsetof(DAC960_Command_T, V2.EndMarker);
292       CommandAllocationGroupSize = DAC960_V2_CommandAllocationGroupSize;
293       ScatterGatherPool = pci_pool_create("DAC960_V2_ScatterGather",
294                 Controller->PCIDevice,
295         DAC960_V2_ScatterGatherLimit * sizeof(DAC960_V2_ScatterGatherSegment_T),
296         sizeof(DAC960_V2_ScatterGatherSegment_T), 0);
297       if (ScatterGatherPool == NULL)
298             return DAC960_Failure(Controller,
299                         "AUXILIARY STRUCTURE CREATION (SG)");
300       RequestSensePool = pci_pool_create("DAC960_V2_RequestSense",
301                 Controller->PCIDevice, sizeof(DAC960_SCSI_RequestSense_T),
302                 sizeof(int), 0);
303       if (RequestSensePool == NULL) {
304             pci_pool_destroy(ScatterGatherPool);
305             return DAC960_Failure(Controller,
306                         "AUXILIARY STRUCTURE CREATION (SG)");
307       }
308       Controller->ScatterGatherPool = ScatterGatherPool;
309       Controller->V2.RequestSensePool = RequestSensePool;
310     }
311   Controller->CommandAllocationGroupSize = CommandAllocationGroupSize;
312   Controller->FreeCommands = NULL;
313   for (CommandIdentifier = 1;
314        CommandIdentifier <= Controller->DriverQueueDepth;
315        CommandIdentifier++)
316     {
317       DAC960_Command_T *Command;
318       if (--CommandsRemaining <= 0)
319         {
320           CommandsRemaining =
321                 Controller->DriverQueueDepth - CommandIdentifier + 1;
322           if (CommandsRemaining > CommandAllocationGroupSize)
323                 CommandsRemaining = CommandAllocationGroupSize;
324           CommandGroupByteCount =
325                 CommandsRemaining * CommandAllocationLength;
326           AllocationPointer = kzalloc(CommandGroupByteCount, GFP_ATOMIC);
327           if (AllocationPointer == NULL)
328                 return DAC960_Failure(Controller,
329                                         "AUXILIARY STRUCTURE CREATION");
330          }
331       Command = (DAC960_Command_T *) AllocationPointer;
332       AllocationPointer += CommandAllocationLength;
333       Command->CommandIdentifier = CommandIdentifier;
334       Command->Controller = Controller;
335       Command->Next = Controller->FreeCommands;
336       Controller->FreeCommands = Command;
337       Controller->Commands[CommandIdentifier-1] = Command;
338       ScatterGatherCPU = pci_pool_alloc(ScatterGatherPool, GFP_ATOMIC,
339                                                         &ScatterGatherDMA);
340       if (ScatterGatherCPU == NULL)
341           return DAC960_Failure(Controller, "AUXILIARY STRUCTURE CREATION");
342
343       if (RequestSensePool != NULL) {
344           RequestSenseCPU = pci_pool_alloc(RequestSensePool, GFP_ATOMIC,
345                                                 &RequestSenseDMA);
346           if (RequestSenseCPU == NULL) {
347                 pci_pool_free(ScatterGatherPool, ScatterGatherCPU,
348                                 ScatterGatherDMA);
349                 return DAC960_Failure(Controller,
350                                         "AUXILIARY STRUCTURE CREATION");
351           }
352         }
353      if (Controller->FirmwareType == DAC960_V1_Controller) {
354         Command->cmd_sglist = Command->V1.ScatterList;
355         Command->V1.ScatterGatherList =
356                 (DAC960_V1_ScatterGatherSegment_T *)ScatterGatherCPU;
357         Command->V1.ScatterGatherListDMA = ScatterGatherDMA;
358         sg_init_table(Command->cmd_sglist, DAC960_V1_ScatterGatherLimit);
359       } else {
360         Command->cmd_sglist = Command->V2.ScatterList;
361         Command->V2.ScatterGatherList =
362                 (DAC960_V2_ScatterGatherSegment_T *)ScatterGatherCPU;
363         Command->V2.ScatterGatherListDMA = ScatterGatherDMA;
364         Command->V2.RequestSense =
365                                 (DAC960_SCSI_RequestSense_T *)RequestSenseCPU;
366         Command->V2.RequestSenseDMA = RequestSenseDMA;
367         sg_init_table(Command->cmd_sglist, DAC960_V2_ScatterGatherLimit);
368       }
369     }
370   return true;
371 }
372
373
374 /*
375   DAC960_DestroyAuxiliaryStructures deallocates the auxiliary data
376   structures for Controller.
377 */
378
379 static void DAC960_DestroyAuxiliaryStructures(DAC960_Controller_T *Controller)
380 {
381   int i;
382   struct pci_pool *ScatterGatherPool = Controller->ScatterGatherPool;
383   struct pci_pool *RequestSensePool = NULL;
384   void *ScatterGatherCPU;
385   dma_addr_t ScatterGatherDMA;
386   void *RequestSenseCPU;
387   dma_addr_t RequestSenseDMA;
388   DAC960_Command_T *CommandGroup = NULL;
389   
390
391   if (Controller->FirmwareType == DAC960_V2_Controller)
392         RequestSensePool = Controller->V2.RequestSensePool;
393
394   Controller->FreeCommands = NULL;
395   for (i = 0; i < Controller->DriverQueueDepth; i++)
396     {
397       DAC960_Command_T *Command = Controller->Commands[i];
398
399       if (Command == NULL)
400           continue;
401
402       if (Controller->FirmwareType == DAC960_V1_Controller) {
403           ScatterGatherCPU = (void *)Command->V1.ScatterGatherList;
404           ScatterGatherDMA = Command->V1.ScatterGatherListDMA;
405           RequestSenseCPU = NULL;
406           RequestSenseDMA = (dma_addr_t)0;
407       } else {
408           ScatterGatherCPU = (void *)Command->V2.ScatterGatherList;
409           ScatterGatherDMA = Command->V2.ScatterGatherListDMA;
410           RequestSenseCPU = (void *)Command->V2.RequestSense;
411           RequestSenseDMA = Command->V2.RequestSenseDMA;
412       }
413       if (ScatterGatherCPU != NULL)
414           pci_pool_free(ScatterGatherPool, ScatterGatherCPU, ScatterGatherDMA);
415       if (RequestSenseCPU != NULL)
416           pci_pool_free(RequestSensePool, RequestSenseCPU, RequestSenseDMA);
417
418       if ((Command->CommandIdentifier
419            % Controller->CommandAllocationGroupSize) == 1) {
420            /*
421             * We can't free the group of commands until all of the
422             * request sense and scatter gather dma structures are free.
423             * Remember the beginning of the group, but don't free it
424             * until we've reached the beginning of the next group.
425             */
426            kfree(CommandGroup);
427            CommandGroup = Command;
428       }
429       Controller->Commands[i] = NULL;
430     }
431   kfree(CommandGroup);
432
433   if (Controller->CombinedStatusBuffer != NULL)
434     {
435       kfree(Controller->CombinedStatusBuffer);
436       Controller->CombinedStatusBuffer = NULL;
437       Controller->CurrentStatusBuffer = NULL;
438     }
439
440   if (ScatterGatherPool != NULL)
441         pci_pool_destroy(ScatterGatherPool);
442   if (Controller->FirmwareType == DAC960_V1_Controller)
443         return;
444
445   if (RequestSensePool != NULL)
446         pci_pool_destroy(RequestSensePool);
447
448   for (i = 0; i < DAC960_MaxLogicalDrives; i++) {
449         kfree(Controller->V2.LogicalDeviceInformation[i]);
450         Controller->V2.LogicalDeviceInformation[i] = NULL;
451   }
452
453   for (i = 0; i < DAC960_V2_MaxPhysicalDevices; i++)
454     {
455       kfree(Controller->V2.PhysicalDeviceInformation[i]);
456       Controller->V2.PhysicalDeviceInformation[i] = NULL;
457       kfree(Controller->V2.InquiryUnitSerialNumber[i]);
458       Controller->V2.InquiryUnitSerialNumber[i] = NULL;
459     }
460 }
461
462
463 /*
464   DAC960_V1_ClearCommand clears critical fields of Command for DAC960 V1
465   Firmware Controllers.
466 */
467
468 static inline void DAC960_V1_ClearCommand(DAC960_Command_T *Command)
469 {
470   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
471   memset(CommandMailbox, 0, sizeof(DAC960_V1_CommandMailbox_T));
472   Command->V1.CommandStatus = 0;
473 }
474
475
476 /*
477   DAC960_V2_ClearCommand clears critical fields of Command for DAC960 V2
478   Firmware Controllers.
479 */
480
481 static inline void DAC960_V2_ClearCommand(DAC960_Command_T *Command)
482 {
483   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
484   memset(CommandMailbox, 0, sizeof(DAC960_V2_CommandMailbox_T));
485   Command->V2.CommandStatus = 0;
486 }
487
488
489 /*
490   DAC960_AllocateCommand allocates a Command structure from Controller's
491   free list.  During driver initialization, a special initialization command
492   has been placed on the free list to guarantee that command allocation can
493   never fail.
494 */
495
496 static inline DAC960_Command_T *DAC960_AllocateCommand(DAC960_Controller_T
497                                                        *Controller)
498 {
499   DAC960_Command_T *Command = Controller->FreeCommands;
500   if (Command == NULL) return NULL;
501   Controller->FreeCommands = Command->Next;
502   Command->Next = NULL;
503   return Command;
504 }
505
506
507 /*
508   DAC960_DeallocateCommand deallocates Command, returning it to Controller's
509   free list.
510 */
511
512 static inline void DAC960_DeallocateCommand(DAC960_Command_T *Command)
513 {
514   DAC960_Controller_T *Controller = Command->Controller;
515
516   Command->Request = NULL;
517   Command->Next = Controller->FreeCommands;
518   Controller->FreeCommands = Command;
519 }
520
521
522 /*
523   DAC960_WaitForCommand waits for a wake_up on Controller's Command Wait Queue.
524 */
525
526 static void DAC960_WaitForCommand(DAC960_Controller_T *Controller)
527 {
528   spin_unlock_irq(&Controller->queue_lock);
529   __wait_event(Controller->CommandWaitQueue, Controller->FreeCommands);
530   spin_lock_irq(&Controller->queue_lock);
531 }
532
533 /*
534   DAC960_GEM_QueueCommand queues Command for DAC960 GEM Series Controllers.
535 */
536
537 static void DAC960_GEM_QueueCommand(DAC960_Command_T *Command)
538 {
539   DAC960_Controller_T *Controller = Command->Controller;
540   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
541   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
542   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
543       Controller->V2.NextCommandMailbox;
544
545   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
546   DAC960_GEM_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
547
548   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
549       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
550       DAC960_GEM_MemoryMailboxNewCommand(ControllerBaseAddress);
551
552   Controller->V2.PreviousCommandMailbox2 =
553       Controller->V2.PreviousCommandMailbox1;
554   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
555
556   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
557       NextCommandMailbox = Controller->V2.FirstCommandMailbox;
558
559   Controller->V2.NextCommandMailbox = NextCommandMailbox;
560 }
561
562 /*
563   DAC960_BA_QueueCommand queues Command for DAC960 BA Series Controllers.
564 */
565
566 static void DAC960_BA_QueueCommand(DAC960_Command_T *Command)
567 {
568   DAC960_Controller_T *Controller = Command->Controller;
569   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
570   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
571   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
572     Controller->V2.NextCommandMailbox;
573   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
574   DAC960_BA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
575   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
576       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
577     DAC960_BA_MemoryMailboxNewCommand(ControllerBaseAddress);
578   Controller->V2.PreviousCommandMailbox2 =
579     Controller->V2.PreviousCommandMailbox1;
580   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
581   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
582     NextCommandMailbox = Controller->V2.FirstCommandMailbox;
583   Controller->V2.NextCommandMailbox = NextCommandMailbox;
584 }
585
586
587 /*
588   DAC960_LP_QueueCommand queues Command for DAC960 LP Series Controllers.
589 */
590
591 static void DAC960_LP_QueueCommand(DAC960_Command_T *Command)
592 {
593   DAC960_Controller_T *Controller = Command->Controller;
594   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
595   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
596   DAC960_V2_CommandMailbox_T *NextCommandMailbox =
597     Controller->V2.NextCommandMailbox;
598   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
599   DAC960_LP_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
600   if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
601       Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
602     DAC960_LP_MemoryMailboxNewCommand(ControllerBaseAddress);
603   Controller->V2.PreviousCommandMailbox2 =
604     Controller->V2.PreviousCommandMailbox1;
605   Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
606   if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
607     NextCommandMailbox = Controller->V2.FirstCommandMailbox;
608   Controller->V2.NextCommandMailbox = NextCommandMailbox;
609 }
610
611
612 /*
613   DAC960_LA_QueueCommandDualMode queues Command for DAC960 LA Series
614   Controllers with Dual Mode Firmware.
615 */
616
617 static void DAC960_LA_QueueCommandDualMode(DAC960_Command_T *Command)
618 {
619   DAC960_Controller_T *Controller = Command->Controller;
620   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
621   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
622   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
623     Controller->V1.NextCommandMailbox;
624   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
625   DAC960_LA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
626   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
627       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
628     DAC960_LA_MemoryMailboxNewCommand(ControllerBaseAddress);
629   Controller->V1.PreviousCommandMailbox2 =
630     Controller->V1.PreviousCommandMailbox1;
631   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
632   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
633     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
634   Controller->V1.NextCommandMailbox = NextCommandMailbox;
635 }
636
637
638 /*
639   DAC960_LA_QueueCommandSingleMode queues Command for DAC960 LA Series
640   Controllers with Single Mode Firmware.
641 */
642
643 static void DAC960_LA_QueueCommandSingleMode(DAC960_Command_T *Command)
644 {
645   DAC960_Controller_T *Controller = Command->Controller;
646   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
647   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
648   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
649     Controller->V1.NextCommandMailbox;
650   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
651   DAC960_LA_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
652   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
653       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
654     DAC960_LA_HardwareMailboxNewCommand(ControllerBaseAddress);
655   Controller->V1.PreviousCommandMailbox2 =
656     Controller->V1.PreviousCommandMailbox1;
657   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
658   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
659     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
660   Controller->V1.NextCommandMailbox = NextCommandMailbox;
661 }
662
663
664 /*
665   DAC960_PG_QueueCommandDualMode queues Command for DAC960 PG Series
666   Controllers with Dual Mode Firmware.
667 */
668
669 static void DAC960_PG_QueueCommandDualMode(DAC960_Command_T *Command)
670 {
671   DAC960_Controller_T *Controller = Command->Controller;
672   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
673   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
674   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
675     Controller->V1.NextCommandMailbox;
676   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
677   DAC960_PG_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
678   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
679       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
680     DAC960_PG_MemoryMailboxNewCommand(ControllerBaseAddress);
681   Controller->V1.PreviousCommandMailbox2 =
682     Controller->V1.PreviousCommandMailbox1;
683   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
684   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
685     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
686   Controller->V1.NextCommandMailbox = NextCommandMailbox;
687 }
688
689
690 /*
691   DAC960_PG_QueueCommandSingleMode queues Command for DAC960 PG Series
692   Controllers with Single Mode Firmware.
693 */
694
695 static void DAC960_PG_QueueCommandSingleMode(DAC960_Command_T *Command)
696 {
697   DAC960_Controller_T *Controller = Command->Controller;
698   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
699   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
700   DAC960_V1_CommandMailbox_T *NextCommandMailbox =
701     Controller->V1.NextCommandMailbox;
702   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
703   DAC960_PG_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
704   if (Controller->V1.PreviousCommandMailbox1->Words[0] == 0 ||
705       Controller->V1.PreviousCommandMailbox2->Words[0] == 0)
706     DAC960_PG_HardwareMailboxNewCommand(ControllerBaseAddress);
707   Controller->V1.PreviousCommandMailbox2 =
708     Controller->V1.PreviousCommandMailbox1;
709   Controller->V1.PreviousCommandMailbox1 = NextCommandMailbox;
710   if (++NextCommandMailbox > Controller->V1.LastCommandMailbox)
711     NextCommandMailbox = Controller->V1.FirstCommandMailbox;
712   Controller->V1.NextCommandMailbox = NextCommandMailbox;
713 }
714
715
716 /*
717   DAC960_PD_QueueCommand queues Command for DAC960 PD Series Controllers.
718 */
719
720 static void DAC960_PD_QueueCommand(DAC960_Command_T *Command)
721 {
722   DAC960_Controller_T *Controller = Command->Controller;
723   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
724   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
725   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
726   while (DAC960_PD_MailboxFullP(ControllerBaseAddress))
727     udelay(1);
728   DAC960_PD_WriteCommandMailbox(ControllerBaseAddress, CommandMailbox);
729   DAC960_PD_NewCommand(ControllerBaseAddress);
730 }
731
732
733 /*
734   DAC960_P_QueueCommand queues Command for DAC960 P Series Controllers.
735 */
736
737 static void DAC960_P_QueueCommand(DAC960_Command_T *Command)
738 {
739   DAC960_Controller_T *Controller = Command->Controller;
740   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
741   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
742   CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
743   switch (CommandMailbox->Common.CommandOpcode)
744     {
745     case DAC960_V1_Enquiry:
746       CommandMailbox->Common.CommandOpcode = DAC960_V1_Enquiry_Old;
747       break;
748     case DAC960_V1_GetDeviceState:
749       CommandMailbox->Common.CommandOpcode = DAC960_V1_GetDeviceState_Old;
750       break;
751     case DAC960_V1_Read:
752       CommandMailbox->Common.CommandOpcode = DAC960_V1_Read_Old;
753       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
754       break;
755     case DAC960_V1_Write:
756       CommandMailbox->Common.CommandOpcode = DAC960_V1_Write_Old;
757       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
758       break;
759     case DAC960_V1_ReadWithScatterGather:
760       CommandMailbox->Common.CommandOpcode =
761         DAC960_V1_ReadWithScatterGather_Old;
762       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
763       break;
764     case DAC960_V1_WriteWithScatterGather:
765       CommandMailbox->Common.CommandOpcode =
766         DAC960_V1_WriteWithScatterGather_Old;
767       DAC960_PD_To_P_TranslateReadWriteCommand(CommandMailbox);
768       break;
769     default:
770       break;
771     }
772   while (DAC960_PD_MailboxFullP(ControllerBaseAddress))
773     udelay(1);
774   DAC960_PD_WriteCommandMailbox(ControllerBaseAddress, CommandMailbox);
775   DAC960_PD_NewCommand(ControllerBaseAddress);
776 }
777
778
779 /*
780   DAC960_ExecuteCommand executes Command and waits for completion.
781 */
782
783 static void DAC960_ExecuteCommand(DAC960_Command_T *Command)
784 {
785   DAC960_Controller_T *Controller = Command->Controller;
786   DECLARE_COMPLETION_ONSTACK(Completion);
787   unsigned long flags;
788   Command->Completion = &Completion;
789
790   spin_lock_irqsave(&Controller->queue_lock, flags);
791   DAC960_QueueCommand(Command);
792   spin_unlock_irqrestore(&Controller->queue_lock, flags);
793  
794   if (in_interrupt())
795           return;
796   wait_for_completion(&Completion);
797 }
798
799
800 /*
801   DAC960_V1_ExecuteType3 executes a DAC960 V1 Firmware Controller Type 3
802   Command and waits for completion.  It returns true on success and false
803   on failure.
804 */
805
806 static bool DAC960_V1_ExecuteType3(DAC960_Controller_T *Controller,
807                                       DAC960_V1_CommandOpcode_T CommandOpcode,
808                                       dma_addr_t DataDMA)
809 {
810   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
811   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
812   DAC960_V1_CommandStatus_T CommandStatus;
813   DAC960_V1_ClearCommand(Command);
814   Command->CommandType = DAC960_ImmediateCommand;
815   CommandMailbox->Type3.CommandOpcode = CommandOpcode;
816   CommandMailbox->Type3.BusAddress = DataDMA;
817   DAC960_ExecuteCommand(Command);
818   CommandStatus = Command->V1.CommandStatus;
819   DAC960_DeallocateCommand(Command);
820   return (CommandStatus == DAC960_V1_NormalCompletion);
821 }
822
823
824 /*
825   DAC960_V1_ExecuteTypeB executes a DAC960 V1 Firmware Controller Type 3B
826   Command and waits for completion.  It returns true on success and false
827   on failure.
828 */
829
830 static bool DAC960_V1_ExecuteType3B(DAC960_Controller_T *Controller,
831                                        DAC960_V1_CommandOpcode_T CommandOpcode,
832                                        unsigned char CommandOpcode2,
833                                        dma_addr_t DataDMA)
834 {
835   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
836   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
837   DAC960_V1_CommandStatus_T CommandStatus;
838   DAC960_V1_ClearCommand(Command);
839   Command->CommandType = DAC960_ImmediateCommand;
840   CommandMailbox->Type3B.CommandOpcode = CommandOpcode;
841   CommandMailbox->Type3B.CommandOpcode2 = CommandOpcode2;
842   CommandMailbox->Type3B.BusAddress = DataDMA;
843   DAC960_ExecuteCommand(Command);
844   CommandStatus = Command->V1.CommandStatus;
845   DAC960_DeallocateCommand(Command);
846   return (CommandStatus == DAC960_V1_NormalCompletion);
847 }
848
849
850 /*
851   DAC960_V1_ExecuteType3D executes a DAC960 V1 Firmware Controller Type 3D
852   Command and waits for completion.  It returns true on success and false
853   on failure.
854 */
855
856 static bool DAC960_V1_ExecuteType3D(DAC960_Controller_T *Controller,
857                                        DAC960_V1_CommandOpcode_T CommandOpcode,
858                                        unsigned char Channel,
859                                        unsigned char TargetID,
860                                        dma_addr_t DataDMA)
861 {
862   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
863   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
864   DAC960_V1_CommandStatus_T CommandStatus;
865   DAC960_V1_ClearCommand(Command);
866   Command->CommandType = DAC960_ImmediateCommand;
867   CommandMailbox->Type3D.CommandOpcode = CommandOpcode;
868   CommandMailbox->Type3D.Channel = Channel;
869   CommandMailbox->Type3D.TargetID = TargetID;
870   CommandMailbox->Type3D.BusAddress = DataDMA;
871   DAC960_ExecuteCommand(Command);
872   CommandStatus = Command->V1.CommandStatus;
873   DAC960_DeallocateCommand(Command);
874   return (CommandStatus == DAC960_V1_NormalCompletion);
875 }
876
877
878 /*
879   DAC960_V2_GeneralInfo executes a DAC960 V2 Firmware General Information
880   Reading IOCTL Command and waits for completion.  It returns true on success
881   and false on failure.
882
883   Return data in The controller's HealthStatusBuffer, which is dma-able memory
884 */
885
886 static bool DAC960_V2_GeneralInfo(DAC960_Controller_T *Controller)
887 {
888   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
889   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
890   DAC960_V2_CommandStatus_T CommandStatus;
891   DAC960_V2_ClearCommand(Command);
892   Command->CommandType = DAC960_ImmediateCommand;
893   CommandMailbox->Common.CommandOpcode = DAC960_V2_IOCTL;
894   CommandMailbox->Common.CommandControlBits
895                         .DataTransferControllerToHost = true;
896   CommandMailbox->Common.CommandControlBits
897                         .NoAutoRequestSense = true;
898   CommandMailbox->Common.DataTransferSize = sizeof(DAC960_V2_HealthStatusBuffer_T);
899   CommandMailbox->Common.IOCTL_Opcode = DAC960_V2_GetHealthStatus;
900   CommandMailbox->Common.DataTransferMemoryAddress
901                         .ScatterGatherSegments[0]
902                         .SegmentDataPointer =
903     Controller->V2.HealthStatusBufferDMA;
904   CommandMailbox->Common.DataTransferMemoryAddress
905                         .ScatterGatherSegments[0]
906                         .SegmentByteCount =
907     CommandMailbox->Common.DataTransferSize;
908   DAC960_ExecuteCommand(Command);
909   CommandStatus = Command->V2.CommandStatus;
910   DAC960_DeallocateCommand(Command);
911   return (CommandStatus == DAC960_V2_NormalCompletion);
912 }
913
914
915 /*
916   DAC960_V2_ControllerInfo executes a DAC960 V2 Firmware Controller
917   Information Reading IOCTL Command and waits for completion.  It returns
918   true on success and false on failure.
919
920   Data is returned in the controller's V2.NewControllerInformation dma-able
921   memory buffer.
922 */
923
924 static bool DAC960_V2_NewControllerInfo(DAC960_Controller_T *Controller)
925 {
926   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
927   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
928   DAC960_V2_CommandStatus_T CommandStatus;
929   DAC960_V2_ClearCommand(Command);
930   Command->CommandType = DAC960_ImmediateCommand;
931   CommandMailbox->ControllerInfo.CommandOpcode = DAC960_V2_IOCTL;
932   CommandMailbox->ControllerInfo.CommandControlBits
933                                 .DataTransferControllerToHost = true;
934   CommandMailbox->ControllerInfo.CommandControlBits
935                                 .NoAutoRequestSense = true;
936   CommandMailbox->ControllerInfo.DataTransferSize = sizeof(DAC960_V2_ControllerInfo_T);
937   CommandMailbox->ControllerInfo.ControllerNumber = 0;
938   CommandMailbox->ControllerInfo.IOCTL_Opcode = DAC960_V2_GetControllerInfo;
939   CommandMailbox->ControllerInfo.DataTransferMemoryAddress
940                                 .ScatterGatherSegments[0]
941                                 .SegmentDataPointer =
942         Controller->V2.NewControllerInformationDMA;
943   CommandMailbox->ControllerInfo.DataTransferMemoryAddress
944                                 .ScatterGatherSegments[0]
945                                 .SegmentByteCount =
946     CommandMailbox->ControllerInfo.DataTransferSize;
947   DAC960_ExecuteCommand(Command);
948   CommandStatus = Command->V2.CommandStatus;
949   DAC960_DeallocateCommand(Command);
950   return (CommandStatus == DAC960_V2_NormalCompletion);
951 }
952
953
954 /*
955   DAC960_V2_LogicalDeviceInfo executes a DAC960 V2 Firmware Controller Logical
956   Device Information Reading IOCTL Command and waits for completion.  It
957   returns true on success and false on failure.
958
959   Data is returned in the controller's V2.NewLogicalDeviceInformation
960 */
961
962 static bool DAC960_V2_NewLogicalDeviceInfo(DAC960_Controller_T *Controller,
963                                            unsigned short LogicalDeviceNumber)
964 {
965   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
966   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
967   DAC960_V2_CommandStatus_T CommandStatus;
968
969   DAC960_V2_ClearCommand(Command);
970   Command->CommandType = DAC960_ImmediateCommand;
971   CommandMailbox->LogicalDeviceInfo.CommandOpcode =
972                                 DAC960_V2_IOCTL;
973   CommandMailbox->LogicalDeviceInfo.CommandControlBits
974                                    .DataTransferControllerToHost = true;
975   CommandMailbox->LogicalDeviceInfo.CommandControlBits
976                                    .NoAutoRequestSense = true;
977   CommandMailbox->LogicalDeviceInfo.DataTransferSize = 
978                                 sizeof(DAC960_V2_LogicalDeviceInfo_T);
979   CommandMailbox->LogicalDeviceInfo.LogicalDevice.LogicalDeviceNumber =
980     LogicalDeviceNumber;
981   CommandMailbox->LogicalDeviceInfo.IOCTL_Opcode = DAC960_V2_GetLogicalDeviceInfoValid;
982   CommandMailbox->LogicalDeviceInfo.DataTransferMemoryAddress
983                                    .ScatterGatherSegments[0]
984                                    .SegmentDataPointer =
985         Controller->V2.NewLogicalDeviceInformationDMA;
986   CommandMailbox->LogicalDeviceInfo.DataTransferMemoryAddress
987                                    .ScatterGatherSegments[0]
988                                    .SegmentByteCount =
989     CommandMailbox->LogicalDeviceInfo.DataTransferSize;
990   DAC960_ExecuteCommand(Command);
991   CommandStatus = Command->V2.CommandStatus;
992   DAC960_DeallocateCommand(Command);
993   return (CommandStatus == DAC960_V2_NormalCompletion);
994 }
995
996
997 /*
998   DAC960_V2_PhysicalDeviceInfo executes a DAC960 V2 Firmware Controller "Read
999   Physical Device Information" IOCTL Command and waits for completion.  It
1000   returns true on success and false on failure.
1001
1002   The Channel, TargetID, LogicalUnit arguments should be 0 the first time
1003   this function is called for a given controller.  This will return data
1004   for the "first" device on that controller.  The returned data includes a
1005   Channel, TargetID, LogicalUnit that can be passed in to this routine to
1006   get data for the NEXT device on that controller.
1007
1008   Data is stored in the controller's V2.NewPhysicalDeviceInfo dma-able
1009   memory buffer.
1010
1011 */
1012
1013 static bool DAC960_V2_NewPhysicalDeviceInfo(DAC960_Controller_T *Controller,
1014                                             unsigned char Channel,
1015                                             unsigned char TargetID,
1016                                             unsigned char LogicalUnit)
1017 {
1018   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
1019   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
1020   DAC960_V2_CommandStatus_T CommandStatus;
1021
1022   DAC960_V2_ClearCommand(Command);
1023   Command->CommandType = DAC960_ImmediateCommand;
1024   CommandMailbox->PhysicalDeviceInfo.CommandOpcode = DAC960_V2_IOCTL;
1025   CommandMailbox->PhysicalDeviceInfo.CommandControlBits
1026                                     .DataTransferControllerToHost = true;
1027   CommandMailbox->PhysicalDeviceInfo.CommandControlBits
1028                                     .NoAutoRequestSense = true;
1029   CommandMailbox->PhysicalDeviceInfo.DataTransferSize =
1030                                 sizeof(DAC960_V2_PhysicalDeviceInfo_T);
1031   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.LogicalUnit = LogicalUnit;
1032   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.TargetID = TargetID;
1033   CommandMailbox->PhysicalDeviceInfo.PhysicalDevice.Channel = Channel;
1034   CommandMailbox->PhysicalDeviceInfo.IOCTL_Opcode =
1035                                         DAC960_V2_GetPhysicalDeviceInfoValid;
1036   CommandMailbox->PhysicalDeviceInfo.DataTransferMemoryAddress
1037                                     .ScatterGatherSegments[0]
1038                                     .SegmentDataPointer =
1039                                         Controller->V2.NewPhysicalDeviceInformationDMA;
1040   CommandMailbox->PhysicalDeviceInfo.DataTransferMemoryAddress
1041                                     .ScatterGatherSegments[0]
1042                                     .SegmentByteCount =
1043     CommandMailbox->PhysicalDeviceInfo.DataTransferSize;
1044   DAC960_ExecuteCommand(Command);
1045   CommandStatus = Command->V2.CommandStatus;
1046   DAC960_DeallocateCommand(Command);
1047   return (CommandStatus == DAC960_V2_NormalCompletion);
1048 }
1049
1050
1051 static void DAC960_V2_ConstructNewUnitSerialNumber(
1052         DAC960_Controller_T *Controller,
1053         DAC960_V2_CommandMailbox_T *CommandMailbox, int Channel, int TargetID,
1054         int LogicalUnit)
1055 {
1056       CommandMailbox->SCSI_10.CommandOpcode = DAC960_V2_SCSI_10_Passthru;
1057       CommandMailbox->SCSI_10.CommandControlBits
1058                              .DataTransferControllerToHost = true;
1059       CommandMailbox->SCSI_10.CommandControlBits
1060                              .NoAutoRequestSense = true;
1061       CommandMailbox->SCSI_10.DataTransferSize =
1062         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1063       CommandMailbox->SCSI_10.PhysicalDevice.LogicalUnit = LogicalUnit;
1064       CommandMailbox->SCSI_10.PhysicalDevice.TargetID = TargetID;
1065       CommandMailbox->SCSI_10.PhysicalDevice.Channel = Channel;
1066       CommandMailbox->SCSI_10.CDBLength = 6;
1067       CommandMailbox->SCSI_10.SCSI_CDB[0] = 0x12; /* INQUIRY */
1068       CommandMailbox->SCSI_10.SCSI_CDB[1] = 1; /* EVPD = 1 */
1069       CommandMailbox->SCSI_10.SCSI_CDB[2] = 0x80; /* Page Code */
1070       CommandMailbox->SCSI_10.SCSI_CDB[3] = 0; /* Reserved */
1071       CommandMailbox->SCSI_10.SCSI_CDB[4] =
1072         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1073       CommandMailbox->SCSI_10.SCSI_CDB[5] = 0; /* Control */
1074       CommandMailbox->SCSI_10.DataTransferMemoryAddress
1075                              .ScatterGatherSegments[0]
1076                              .SegmentDataPointer =
1077                 Controller->V2.NewInquiryUnitSerialNumberDMA;
1078       CommandMailbox->SCSI_10.DataTransferMemoryAddress
1079                              .ScatterGatherSegments[0]
1080                              .SegmentByteCount =
1081                 CommandMailbox->SCSI_10.DataTransferSize;
1082 }
1083
1084
1085 /*
1086   DAC960_V2_NewUnitSerialNumber executes an SCSI pass-through
1087   Inquiry command to a SCSI device identified by Channel number,
1088   Target id, Logical Unit Number.  This function Waits for completion
1089   of the command.
1090
1091   The return data includes Unit Serial Number information for the
1092   specified device.
1093
1094   Data is stored in the controller's V2.NewPhysicalDeviceInfo dma-able
1095   memory buffer.
1096 */
1097
1098 static bool DAC960_V2_NewInquiryUnitSerialNumber(DAC960_Controller_T *Controller,
1099                         int Channel, int TargetID, int LogicalUnit)
1100 {
1101       DAC960_Command_T *Command;
1102       DAC960_V2_CommandMailbox_T *CommandMailbox;
1103       DAC960_V2_CommandStatus_T CommandStatus;
1104
1105       Command = DAC960_AllocateCommand(Controller);
1106       CommandMailbox = &Command->V2.CommandMailbox;
1107       DAC960_V2_ClearCommand(Command);
1108       Command->CommandType = DAC960_ImmediateCommand;
1109
1110       DAC960_V2_ConstructNewUnitSerialNumber(Controller, CommandMailbox,
1111                         Channel, TargetID, LogicalUnit);
1112
1113       DAC960_ExecuteCommand(Command);
1114       CommandStatus = Command->V2.CommandStatus;
1115       DAC960_DeallocateCommand(Command);
1116       return (CommandStatus == DAC960_V2_NormalCompletion);
1117 }
1118
1119
1120 /*
1121   DAC960_V2_DeviceOperation executes a DAC960 V2 Firmware Controller Device
1122   Operation IOCTL Command and waits for completion.  It returns true on
1123   success and false on failure.
1124 */
1125
1126 static bool DAC960_V2_DeviceOperation(DAC960_Controller_T *Controller,
1127                                          DAC960_V2_IOCTL_Opcode_T IOCTL_Opcode,
1128                                          DAC960_V2_OperationDevice_T
1129                                            OperationDevice)
1130 {
1131   DAC960_Command_T *Command = DAC960_AllocateCommand(Controller);
1132   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
1133   DAC960_V2_CommandStatus_T CommandStatus;
1134   DAC960_V2_ClearCommand(Command);
1135   Command->CommandType = DAC960_ImmediateCommand;
1136   CommandMailbox->DeviceOperation.CommandOpcode = DAC960_V2_IOCTL;
1137   CommandMailbox->DeviceOperation.CommandControlBits
1138                                  .DataTransferControllerToHost = true;
1139   CommandMailbox->DeviceOperation.CommandControlBits
1140                                  .NoAutoRequestSense = true;
1141   CommandMailbox->DeviceOperation.IOCTL_Opcode = IOCTL_Opcode;
1142   CommandMailbox->DeviceOperation.OperationDevice = OperationDevice;
1143   DAC960_ExecuteCommand(Command);
1144   CommandStatus = Command->V2.CommandStatus;
1145   DAC960_DeallocateCommand(Command);
1146   return (CommandStatus == DAC960_V2_NormalCompletion);
1147 }
1148
1149
1150 /*
1151   DAC960_V1_EnableMemoryMailboxInterface enables the Memory Mailbox Interface
1152   for DAC960 V1 Firmware Controllers.
1153
1154   PD and P controller types have no memory mailbox, but still need the
1155   other dma mapped memory.
1156 */
1157
1158 static bool DAC960_V1_EnableMemoryMailboxInterface(DAC960_Controller_T
1159                                                       *Controller)
1160 {
1161   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
1162   DAC960_HardwareType_T hw_type = Controller->HardwareType;
1163   struct pci_dev *PCI_Device = Controller->PCIDevice;
1164   struct dma_loaf *DmaPages = &Controller->DmaPages;
1165   size_t DmaPagesSize;
1166   size_t CommandMailboxesSize;
1167   size_t StatusMailboxesSize;
1168
1169   DAC960_V1_CommandMailbox_T *CommandMailboxesMemory;
1170   dma_addr_t CommandMailboxesMemoryDMA;
1171
1172   DAC960_V1_StatusMailbox_T *StatusMailboxesMemory;
1173   dma_addr_t StatusMailboxesMemoryDMA;
1174
1175   DAC960_V1_CommandMailbox_T CommandMailbox;
1176   DAC960_V1_CommandStatus_T CommandStatus;
1177   int TimeoutCounter;
1178   int i;
1179
1180   
1181   if (pci_set_dma_mask(Controller->PCIDevice, DMA_BIT_MASK(32)))
1182         return DAC960_Failure(Controller, "DMA mask out of range");
1183   Controller->BounceBufferLimit = DMA_BIT_MASK(32);
1184
1185   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller)) {
1186     CommandMailboxesSize =  0;
1187     StatusMailboxesSize = 0;
1188   } else {
1189     CommandMailboxesSize =  DAC960_V1_CommandMailboxCount * sizeof(DAC960_V1_CommandMailbox_T);
1190     StatusMailboxesSize = DAC960_V1_StatusMailboxCount * sizeof(DAC960_V1_StatusMailbox_T);
1191   }
1192   DmaPagesSize = CommandMailboxesSize + StatusMailboxesSize + 
1193         sizeof(DAC960_V1_DCDB_T) + sizeof(DAC960_V1_Enquiry_T) +
1194         sizeof(DAC960_V1_ErrorTable_T) + sizeof(DAC960_V1_EventLogEntry_T) +
1195         sizeof(DAC960_V1_RebuildProgress_T) +
1196         sizeof(DAC960_V1_LogicalDriveInformationArray_T) +
1197         sizeof(DAC960_V1_BackgroundInitializationStatus_T) +
1198         sizeof(DAC960_V1_DeviceState_T) + sizeof(DAC960_SCSI_Inquiry_T) +
1199         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
1200
1201   if (!init_dma_loaf(PCI_Device, DmaPages, DmaPagesSize))
1202         return false;
1203
1204
1205   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller)) 
1206         goto skip_mailboxes;
1207
1208   CommandMailboxesMemory = slice_dma_loaf(DmaPages,
1209                 CommandMailboxesSize, &CommandMailboxesMemoryDMA);
1210   
1211   /* These are the base addresses for the command memory mailbox array */
1212   Controller->V1.FirstCommandMailbox = CommandMailboxesMemory;
1213   Controller->V1.FirstCommandMailboxDMA = CommandMailboxesMemoryDMA;
1214
1215   CommandMailboxesMemory += DAC960_V1_CommandMailboxCount - 1;
1216   Controller->V1.LastCommandMailbox = CommandMailboxesMemory;
1217   Controller->V1.NextCommandMailbox = Controller->V1.FirstCommandMailbox;
1218   Controller->V1.PreviousCommandMailbox1 = Controller->V1.LastCommandMailbox;
1219   Controller->V1.PreviousCommandMailbox2 =
1220                                         Controller->V1.LastCommandMailbox - 1;
1221
1222   /* These are the base addresses for the status memory mailbox array */
1223   StatusMailboxesMemory = slice_dma_loaf(DmaPages,
1224                 StatusMailboxesSize, &StatusMailboxesMemoryDMA);
1225
1226   Controller->V1.FirstStatusMailbox = StatusMailboxesMemory;
1227   Controller->V1.FirstStatusMailboxDMA = StatusMailboxesMemoryDMA;
1228   StatusMailboxesMemory += DAC960_V1_StatusMailboxCount - 1;
1229   Controller->V1.LastStatusMailbox = StatusMailboxesMemory;
1230   Controller->V1.NextStatusMailbox = Controller->V1.FirstStatusMailbox;
1231
1232 skip_mailboxes:
1233   Controller->V1.MonitoringDCDB = slice_dma_loaf(DmaPages,
1234                 sizeof(DAC960_V1_DCDB_T),
1235                 &Controller->V1.MonitoringDCDB_DMA);
1236
1237   Controller->V1.NewEnquiry = slice_dma_loaf(DmaPages,
1238                 sizeof(DAC960_V1_Enquiry_T),
1239                 &Controller->V1.NewEnquiryDMA);
1240
1241   Controller->V1.NewErrorTable = slice_dma_loaf(DmaPages,
1242                 sizeof(DAC960_V1_ErrorTable_T),
1243                 &Controller->V1.NewErrorTableDMA);
1244
1245   Controller->V1.EventLogEntry = slice_dma_loaf(DmaPages,
1246                 sizeof(DAC960_V1_EventLogEntry_T),
1247                 &Controller->V1.EventLogEntryDMA);
1248
1249   Controller->V1.RebuildProgress = slice_dma_loaf(DmaPages,
1250                 sizeof(DAC960_V1_RebuildProgress_T),
1251                 &Controller->V1.RebuildProgressDMA);
1252
1253   Controller->V1.NewLogicalDriveInformation = slice_dma_loaf(DmaPages,
1254                 sizeof(DAC960_V1_LogicalDriveInformationArray_T),
1255                 &Controller->V1.NewLogicalDriveInformationDMA);
1256
1257   Controller->V1.BackgroundInitializationStatus = slice_dma_loaf(DmaPages,
1258                 sizeof(DAC960_V1_BackgroundInitializationStatus_T),
1259                 &Controller->V1.BackgroundInitializationStatusDMA);
1260
1261   Controller->V1.NewDeviceState = slice_dma_loaf(DmaPages,
1262                 sizeof(DAC960_V1_DeviceState_T),
1263                 &Controller->V1.NewDeviceStateDMA);
1264
1265   Controller->V1.NewInquiryStandardData = slice_dma_loaf(DmaPages,
1266                 sizeof(DAC960_SCSI_Inquiry_T),
1267                 &Controller->V1.NewInquiryStandardDataDMA);
1268
1269   Controller->V1.NewInquiryUnitSerialNumber = slice_dma_loaf(DmaPages,
1270                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1271                 &Controller->V1.NewInquiryUnitSerialNumberDMA);
1272
1273   if ((hw_type == DAC960_PD_Controller) || (hw_type == DAC960_P_Controller))
1274         return true;
1275  
1276   /* Enable the Memory Mailbox Interface. */
1277   Controller->V1.DualModeMemoryMailboxInterface = true;
1278   CommandMailbox.TypeX.CommandOpcode = 0x2B;
1279   CommandMailbox.TypeX.CommandIdentifier = 0;
1280   CommandMailbox.TypeX.CommandOpcode2 = 0x14;
1281   CommandMailbox.TypeX.CommandMailboxesBusAddress =
1282                                 Controller->V1.FirstCommandMailboxDMA;
1283   CommandMailbox.TypeX.StatusMailboxesBusAddress =
1284                                 Controller->V1.FirstStatusMailboxDMA;
1285 #define TIMEOUT_COUNT 1000000
1286
1287   for (i = 0; i < 2; i++)
1288     switch (Controller->HardwareType)
1289       {
1290       case DAC960_LA_Controller:
1291         TimeoutCounter = TIMEOUT_COUNT;
1292         while (--TimeoutCounter >= 0)
1293           {
1294             if (!DAC960_LA_HardwareMailboxFullP(ControllerBaseAddress))
1295               break;
1296             udelay(10);
1297           }
1298         if (TimeoutCounter < 0) return false;
1299         DAC960_LA_WriteHardwareMailbox(ControllerBaseAddress, &CommandMailbox);
1300         DAC960_LA_HardwareMailboxNewCommand(ControllerBaseAddress);
1301         TimeoutCounter = TIMEOUT_COUNT;
1302         while (--TimeoutCounter >= 0)
1303           {
1304             if (DAC960_LA_HardwareMailboxStatusAvailableP(
1305                   ControllerBaseAddress))
1306               break;
1307             udelay(10);
1308           }
1309         if (TimeoutCounter < 0) return false;
1310         CommandStatus = DAC960_LA_ReadStatusRegister(ControllerBaseAddress);
1311         DAC960_LA_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1312         DAC960_LA_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1313         if (CommandStatus == DAC960_V1_NormalCompletion) return true;
1314         Controller->V1.DualModeMemoryMailboxInterface = false;
1315         CommandMailbox.TypeX.CommandOpcode2 = 0x10;
1316         break;
1317       case DAC960_PG_Controller:
1318         TimeoutCounter = TIMEOUT_COUNT;
1319         while (--TimeoutCounter >= 0)
1320           {
1321             if (!DAC960_PG_HardwareMailboxFullP(ControllerBaseAddress))
1322               break;
1323             udelay(10);
1324           }
1325         if (TimeoutCounter < 0) return false;
1326         DAC960_PG_WriteHardwareMailbox(ControllerBaseAddress, &CommandMailbox);
1327         DAC960_PG_HardwareMailboxNewCommand(ControllerBaseAddress);
1328
1329         TimeoutCounter = TIMEOUT_COUNT;
1330         while (--TimeoutCounter >= 0)
1331           {
1332             if (DAC960_PG_HardwareMailboxStatusAvailableP(
1333                   ControllerBaseAddress))
1334               break;
1335             udelay(10);
1336           }
1337         if (TimeoutCounter < 0) return false;
1338         CommandStatus = DAC960_PG_ReadStatusRegister(ControllerBaseAddress);
1339         DAC960_PG_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1340         DAC960_PG_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1341         if (CommandStatus == DAC960_V1_NormalCompletion) return true;
1342         Controller->V1.DualModeMemoryMailboxInterface = false;
1343         CommandMailbox.TypeX.CommandOpcode2 = 0x10;
1344         break;
1345       default:
1346         DAC960_Failure(Controller, "Unknown Controller Type\n");
1347         break;
1348       }
1349   return false;
1350 }
1351
1352
1353 /*
1354   DAC960_V2_EnableMemoryMailboxInterface enables the Memory Mailbox Interface
1355   for DAC960 V2 Firmware Controllers.
1356
1357   Aggregate the space needed for the controller's memory mailbox and
1358   the other data structures that will be targets of dma transfers with
1359   the controller.  Allocate a dma-mapped region of memory to hold these
1360   structures.  Then, save CPU pointers and dma_addr_t values to reference
1361   the structures that are contained in that region.
1362 */
1363
1364 static bool DAC960_V2_EnableMemoryMailboxInterface(DAC960_Controller_T
1365                                                       *Controller)
1366 {
1367   void __iomem *ControllerBaseAddress = Controller->BaseAddress;
1368   struct pci_dev *PCI_Device = Controller->PCIDevice;
1369   struct dma_loaf *DmaPages = &Controller->DmaPages;
1370   size_t DmaPagesSize;
1371   size_t CommandMailboxesSize;
1372   size_t StatusMailboxesSize;
1373
1374   DAC960_V2_CommandMailbox_T *CommandMailboxesMemory;
1375   dma_addr_t CommandMailboxesMemoryDMA;
1376
1377   DAC960_V2_StatusMailbox_T *StatusMailboxesMemory;
1378   dma_addr_t StatusMailboxesMemoryDMA;
1379
1380   DAC960_V2_CommandMailbox_T *CommandMailbox;
1381   dma_addr_t    CommandMailboxDMA;
1382   DAC960_V2_CommandStatus_T CommandStatus;
1383
1384         if (!pci_set_dma_mask(Controller->PCIDevice, DMA_BIT_MASK(64)))
1385                 Controller->BounceBufferLimit = DMA_BIT_MASK(64);
1386         else if (!pci_set_dma_mask(Controller->PCIDevice, DMA_BIT_MASK(32)))
1387                 Controller->BounceBufferLimit = DMA_BIT_MASK(32);
1388         else
1389                 return DAC960_Failure(Controller, "DMA mask out of range");
1390
1391   /* This is a temporary dma mapping, used only in the scope of this function */
1392   CommandMailbox = pci_alloc_consistent(PCI_Device,
1393                 sizeof(DAC960_V2_CommandMailbox_T), &CommandMailboxDMA);
1394   if (CommandMailbox == NULL)
1395           return false;
1396
1397   CommandMailboxesSize = DAC960_V2_CommandMailboxCount * sizeof(DAC960_V2_CommandMailbox_T);
1398   StatusMailboxesSize = DAC960_V2_StatusMailboxCount * sizeof(DAC960_V2_StatusMailbox_T);
1399   DmaPagesSize =
1400     CommandMailboxesSize + StatusMailboxesSize +
1401     sizeof(DAC960_V2_HealthStatusBuffer_T) +
1402     sizeof(DAC960_V2_ControllerInfo_T) +
1403     sizeof(DAC960_V2_LogicalDeviceInfo_T) +
1404     sizeof(DAC960_V2_PhysicalDeviceInfo_T) +
1405     sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T) +
1406     sizeof(DAC960_V2_Event_T) +
1407     sizeof(DAC960_V2_PhysicalToLogicalDevice_T);
1408
1409   if (!init_dma_loaf(PCI_Device, DmaPages, DmaPagesSize)) {
1410         pci_free_consistent(PCI_Device, sizeof(DAC960_V2_CommandMailbox_T),
1411                                         CommandMailbox, CommandMailboxDMA);
1412         return false;
1413   }
1414
1415   CommandMailboxesMemory = slice_dma_loaf(DmaPages,
1416                 CommandMailboxesSize, &CommandMailboxesMemoryDMA);
1417
1418   /* These are the base addresses for the command memory mailbox array */
1419   Controller->V2.FirstCommandMailbox = CommandMailboxesMemory;
1420   Controller->V2.FirstCommandMailboxDMA = CommandMailboxesMemoryDMA;
1421
1422   CommandMailboxesMemory += DAC960_V2_CommandMailboxCount - 1;
1423   Controller->V2.LastCommandMailbox = CommandMailboxesMemory;
1424   Controller->V2.NextCommandMailbox = Controller->V2.FirstCommandMailbox;
1425   Controller->V2.PreviousCommandMailbox1 = Controller->V2.LastCommandMailbox;
1426   Controller->V2.PreviousCommandMailbox2 =
1427                                         Controller->V2.LastCommandMailbox - 1;
1428
1429   /* These are the base addresses for the status memory mailbox array */
1430   StatusMailboxesMemory = slice_dma_loaf(DmaPages,
1431                 StatusMailboxesSize, &StatusMailboxesMemoryDMA);
1432
1433   Controller->V2.FirstStatusMailbox = StatusMailboxesMemory;
1434   Controller->V2.FirstStatusMailboxDMA = StatusMailboxesMemoryDMA;
1435   StatusMailboxesMemory += DAC960_V2_StatusMailboxCount - 1;
1436   Controller->V2.LastStatusMailbox = StatusMailboxesMemory;
1437   Controller->V2.NextStatusMailbox = Controller->V2.FirstStatusMailbox;
1438
1439   Controller->V2.HealthStatusBuffer = slice_dma_loaf(DmaPages,
1440                 sizeof(DAC960_V2_HealthStatusBuffer_T),
1441                 &Controller->V2.HealthStatusBufferDMA);
1442
1443   Controller->V2.NewControllerInformation = slice_dma_loaf(DmaPages,
1444                 sizeof(DAC960_V2_ControllerInfo_T), 
1445                 &Controller->V2.NewControllerInformationDMA);
1446
1447   Controller->V2.NewLogicalDeviceInformation =  slice_dma_loaf(DmaPages,
1448                 sizeof(DAC960_V2_LogicalDeviceInfo_T),
1449                 &Controller->V2.NewLogicalDeviceInformationDMA);
1450
1451   Controller->V2.NewPhysicalDeviceInformation = slice_dma_loaf(DmaPages,
1452                 sizeof(DAC960_V2_PhysicalDeviceInfo_T),
1453                 &Controller->V2.NewPhysicalDeviceInformationDMA);
1454
1455   Controller->V2.NewInquiryUnitSerialNumber = slice_dma_loaf(DmaPages,
1456                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1457                 &Controller->V2.NewInquiryUnitSerialNumberDMA);
1458
1459   Controller->V2.Event = slice_dma_loaf(DmaPages,
1460                 sizeof(DAC960_V2_Event_T),
1461                 &Controller->V2.EventDMA);
1462
1463   Controller->V2.PhysicalToLogicalDevice = slice_dma_loaf(DmaPages,
1464                 sizeof(DAC960_V2_PhysicalToLogicalDevice_T),
1465                 &Controller->V2.PhysicalToLogicalDeviceDMA);
1466
1467   /*
1468     Enable the Memory Mailbox Interface.
1469     
1470     I don't know why we can't just use one of the memory mailboxes
1471     we just allocated to do this, instead of using this temporary one.
1472     Try this change later.
1473   */
1474   memset(CommandMailbox, 0, sizeof(DAC960_V2_CommandMailbox_T));
1475   CommandMailbox->SetMemoryMailbox.CommandIdentifier = 1;
1476   CommandMailbox->SetMemoryMailbox.CommandOpcode = DAC960_V2_IOCTL;
1477   CommandMailbox->SetMemoryMailbox.CommandControlBits.NoAutoRequestSense = true;
1478   CommandMailbox->SetMemoryMailbox.FirstCommandMailboxSizeKB =
1479     (DAC960_V2_CommandMailboxCount * sizeof(DAC960_V2_CommandMailbox_T)) >> 10;
1480   CommandMailbox->SetMemoryMailbox.FirstStatusMailboxSizeKB =
1481     (DAC960_V2_StatusMailboxCount * sizeof(DAC960_V2_StatusMailbox_T)) >> 10;
1482   CommandMailbox->SetMemoryMailbox.SecondCommandMailboxSizeKB = 0;
1483   CommandMailbox->SetMemoryMailbox.SecondStatusMailboxSizeKB = 0;
1484   CommandMailbox->SetMemoryMailbox.RequestSenseSize = 0;
1485   CommandMailbox->SetMemoryMailbox.IOCTL_Opcode = DAC960_V2_SetMemoryMailbox;
1486   CommandMailbox->SetMemoryMailbox.HealthStatusBufferSizeKB = 1;
1487   CommandMailbox->SetMemoryMailbox.HealthStatusBufferBusAddress =
1488                                         Controller->V2.HealthStatusBufferDMA;
1489   CommandMailbox->SetMemoryMailbox.FirstCommandMailboxBusAddress =
1490                                         Controller->V2.FirstCommandMailboxDMA;
1491   CommandMailbox->SetMemoryMailbox.FirstStatusMailboxBusAddress =
1492                                         Controller->V2.FirstStatusMailboxDMA;
1493   switch (Controller->HardwareType)
1494     {
1495     case DAC960_GEM_Controller:
1496       while (DAC960_GEM_HardwareMailboxFullP(ControllerBaseAddress))
1497         udelay(1);
1498       DAC960_GEM_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1499       DAC960_GEM_HardwareMailboxNewCommand(ControllerBaseAddress);
1500       while (!DAC960_GEM_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1501         udelay(1);
1502       CommandStatus = DAC960_GEM_ReadCommandStatus(ControllerBaseAddress);
1503       DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1504       DAC960_GEM_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1505       break;
1506     case DAC960_BA_Controller:
1507       while (DAC960_BA_HardwareMailboxFullP(ControllerBaseAddress))
1508         udelay(1);
1509       DAC960_BA_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1510       DAC960_BA_HardwareMailboxNewCommand(ControllerBaseAddress);
1511       while (!DAC960_BA_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1512         udelay(1);
1513       CommandStatus = DAC960_BA_ReadCommandStatus(ControllerBaseAddress);
1514       DAC960_BA_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1515       DAC960_BA_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1516       break;
1517     case DAC960_LP_Controller:
1518       while (DAC960_LP_HardwareMailboxFullP(ControllerBaseAddress))
1519         udelay(1);
1520       DAC960_LP_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1521       DAC960_LP_HardwareMailboxNewCommand(ControllerBaseAddress);
1522       while (!DAC960_LP_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1523         udelay(1);
1524       CommandStatus = DAC960_LP_ReadCommandStatus(ControllerBaseAddress);
1525       DAC960_LP_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1526       DAC960_LP_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1527       break;
1528     default:
1529       DAC960_Failure(Controller, "Unknown Controller Type\n");
1530       CommandStatus = DAC960_V2_AbormalCompletion;
1531       break;
1532     }
1533   pci_free_consistent(PCI_Device, sizeof(DAC960_V2_CommandMailbox_T),
1534                                         CommandMailbox, CommandMailboxDMA);
1535   return (CommandStatus == DAC960_V2_NormalCompletion);
1536 }
1537
1538
1539 /*
1540   DAC960_V1_ReadControllerConfiguration reads the Configuration Information
1541   from DAC960 V1 Firmware Controllers and initializes the Controller structure.
1542 */
1543
1544 static bool DAC960_V1_ReadControllerConfiguration(DAC960_Controller_T
1545                                                      *Controller)
1546 {
1547   DAC960_V1_Enquiry2_T *Enquiry2;
1548   dma_addr_t Enquiry2DMA;
1549   DAC960_V1_Config2_T *Config2;
1550   dma_addr_t Config2DMA;
1551   int LogicalDriveNumber, Channel, TargetID;
1552   struct dma_loaf local_dma;
1553
1554   if (!init_dma_loaf(Controller->PCIDevice, &local_dma,
1555                 sizeof(DAC960_V1_Enquiry2_T) + sizeof(DAC960_V1_Config2_T)))
1556         return DAC960_Failure(Controller, "LOGICAL DEVICE ALLOCATION");
1557
1558   Enquiry2 = slice_dma_loaf(&local_dma, sizeof(DAC960_V1_Enquiry2_T), &Enquiry2DMA);
1559   Config2 = slice_dma_loaf(&local_dma, sizeof(DAC960_V1_Config2_T), &Config2DMA);
1560
1561   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_Enquiry,
1562                               Controller->V1.NewEnquiryDMA)) {
1563     free_dma_loaf(Controller->PCIDevice, &local_dma);
1564     return DAC960_Failure(Controller, "ENQUIRY");
1565   }
1566   memcpy(&Controller->V1.Enquiry, Controller->V1.NewEnquiry,
1567                                                 sizeof(DAC960_V1_Enquiry_T));
1568
1569   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_Enquiry2, Enquiry2DMA)) {
1570     free_dma_loaf(Controller->PCIDevice, &local_dma);
1571     return DAC960_Failure(Controller, "ENQUIRY2");
1572   }
1573
1574   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_ReadConfig2, Config2DMA)) {
1575     free_dma_loaf(Controller->PCIDevice, &local_dma);
1576     return DAC960_Failure(Controller, "READ CONFIG2");
1577   }
1578
1579   if (!DAC960_V1_ExecuteType3(Controller, DAC960_V1_GetLogicalDriveInformation,
1580                               Controller->V1.NewLogicalDriveInformationDMA)) {
1581     free_dma_loaf(Controller->PCIDevice, &local_dma);
1582     return DAC960_Failure(Controller, "GET LOGICAL DRIVE INFORMATION");
1583   }
1584   memcpy(&Controller->V1.LogicalDriveInformation,
1585                 Controller->V1.NewLogicalDriveInformation,
1586                 sizeof(DAC960_V1_LogicalDriveInformationArray_T));
1587
1588   for (Channel = 0; Channel < Enquiry2->ActualChannels; Channel++)
1589     for (TargetID = 0; TargetID < Enquiry2->MaxTargets; TargetID++) {
1590       if (!DAC960_V1_ExecuteType3D(Controller, DAC960_V1_GetDeviceState,
1591                                    Channel, TargetID,
1592                                    Controller->V1.NewDeviceStateDMA)) {
1593                 free_dma_loaf(Controller->PCIDevice, &local_dma);
1594                 return DAC960_Failure(Controller, "GET DEVICE STATE");
1595         }
1596         memcpy(&Controller->V1.DeviceState[Channel][TargetID],
1597                 Controller->V1.NewDeviceState, sizeof(DAC960_V1_DeviceState_T));
1598      }
1599   /*
1600     Initialize the Controller Model Name and Full Model Name fields.
1601   */
1602   switch (Enquiry2->HardwareID.SubModel)
1603     {
1604     case DAC960_V1_P_PD_PU:
1605       if (Enquiry2->SCSICapability.BusSpeed == DAC960_V1_Ultra)
1606         strcpy(Controller->ModelName, "DAC960PU");
1607       else strcpy(Controller->ModelName, "DAC960PD");
1608       break;
1609     case DAC960_V1_PL:
1610       strcpy(Controller->ModelName, "DAC960PL");
1611       break;
1612     case DAC960_V1_PG:
1613       strcpy(Controller->ModelName, "DAC960PG");
1614       break;
1615     case DAC960_V1_PJ:
1616       strcpy(Controller->ModelName, "DAC960PJ");
1617       break;
1618     case DAC960_V1_PR:
1619       strcpy(Controller->ModelName, "DAC960PR");
1620       break;
1621     case DAC960_V1_PT:
1622       strcpy(Controller->ModelName, "DAC960PT");
1623       break;
1624     case DAC960_V1_PTL0:
1625       strcpy(Controller->ModelName, "DAC960PTL0");
1626       break;
1627     case DAC960_V1_PRL:
1628       strcpy(Controller->ModelName, "DAC960PRL");
1629       break;
1630     case DAC960_V1_PTL1:
1631       strcpy(Controller->ModelName, "DAC960PTL1");
1632       break;
1633     case DAC960_V1_1164P:
1634       strcpy(Controller->ModelName, "DAC1164P");
1635       break;
1636     default:
1637       free_dma_loaf(Controller->PCIDevice, &local_dma);
1638       return DAC960_Failure(Controller, "MODEL VERIFICATION");
1639     }
1640   strcpy(Controller->FullModelName, "Mylex ");
1641   strcat(Controller->FullModelName, Controller->ModelName);
1642   /*
1643     Initialize the Controller Firmware Version field and verify that it
1644     is a supported firmware version.  The supported firmware versions are:
1645
1646     DAC1164P                5.06 and above
1647     DAC960PTL/PRL/PJ/PG     4.06 and above
1648     DAC960PU/PD/PL          3.51 and above
1649     DAC960PU/PD/PL/P        2.73 and above
1650   */
1651 #if defined(CONFIG_ALPHA)
1652   /*
1653     DEC Alpha machines were often equipped with DAC960 cards that were
1654     OEMed from Mylex, and had their own custom firmware. Version 2.70,
1655     the last custom FW revision to be released by DEC for these older
1656     controllers, appears to work quite well with this driver.
1657
1658     Cards tested successfully were several versions each of the PD and
1659     PU, called by DEC the KZPSC and KZPAC, respectively, and having
1660     the Manufacturer Numbers (from Mylex), usually on a sticker on the
1661     back of the board, of:
1662
1663     KZPSC:  D040347 (1-channel) or D040348 (2-channel) or D040349 (3-channel)
1664     KZPAC:  D040395 (1-channel) or D040396 (2-channel) or D040397 (3-channel)
1665   */
1666 # define FIRMWARE_27X   "2.70"
1667 #else
1668 # define FIRMWARE_27X   "2.73"
1669 #endif
1670
1671   if (Enquiry2->FirmwareID.MajorVersion == 0)
1672     {
1673       Enquiry2->FirmwareID.MajorVersion =
1674         Controller->V1.Enquiry.MajorFirmwareVersion;
1675       Enquiry2->FirmwareID.MinorVersion =
1676         Controller->V1.Enquiry.MinorFirmwareVersion;
1677       Enquiry2->FirmwareID.FirmwareType = '0';
1678       Enquiry2->FirmwareID.TurnID = 0;
1679     }
1680   sprintf(Controller->FirmwareVersion, "%d.%02d-%c-%02d",
1681           Enquiry2->FirmwareID.MajorVersion, Enquiry2->FirmwareID.MinorVersion,
1682           Enquiry2->FirmwareID.FirmwareType, Enquiry2->FirmwareID.TurnID);
1683   if (!((Controller->FirmwareVersion[0] == '5' &&
1684          strcmp(Controller->FirmwareVersion, "5.06") >= 0) ||
1685         (Controller->FirmwareVersion[0] == '4' &&
1686          strcmp(Controller->FirmwareVersion, "4.06") >= 0) ||
1687         (Controller->FirmwareVersion[0] == '3' &&
1688          strcmp(Controller->FirmwareVersion, "3.51") >= 0) ||
1689         (Controller->FirmwareVersion[0] == '2' &&
1690          strcmp(Controller->FirmwareVersion, FIRMWARE_27X) >= 0)))
1691     {
1692       DAC960_Failure(Controller, "FIRMWARE VERSION VERIFICATION");
1693       DAC960_Error("Firmware Version = '%s'\n", Controller,
1694                    Controller->FirmwareVersion);
1695       free_dma_loaf(Controller->PCIDevice, &local_dma);
1696       return false;
1697     }
1698   /*
1699     Initialize the Controller Channels, Targets, Memory Size, and SAF-TE
1700     Enclosure Management Enabled fields.
1701   */
1702   Controller->Channels = Enquiry2->ActualChannels;
1703   Controller->Targets = Enquiry2->MaxTargets;
1704   Controller->MemorySize = Enquiry2->MemorySize >> 20;
1705   Controller->V1.SAFTE_EnclosureManagementEnabled =
1706     (Enquiry2->FaultManagementType == DAC960_V1_SAFTE);
1707   /*
1708     Initialize the Controller Queue Depth, Driver Queue Depth, Logical Drive
1709     Count, Maximum Blocks per Command, Controller Scatter/Gather Limit, and
1710     Driver Scatter/Gather Limit.  The Driver Queue Depth must be at most one
1711     less than the Controller Queue Depth to allow for an automatic drive
1712     rebuild operation.
1713   */
1714   Controller->ControllerQueueDepth = Controller->V1.Enquiry.MaxCommands;
1715   Controller->DriverQueueDepth = Controller->ControllerQueueDepth - 1;
1716   if (Controller->DriverQueueDepth > DAC960_MaxDriverQueueDepth)
1717     Controller->DriverQueueDepth = DAC960_MaxDriverQueueDepth;
1718   Controller->LogicalDriveCount =
1719     Controller->V1.Enquiry.NumberOfLogicalDrives;
1720   Controller->MaxBlocksPerCommand = Enquiry2->MaxBlocksPerCommand;
1721   Controller->ControllerScatterGatherLimit = Enquiry2->MaxScatterGatherEntries;
1722   Controller->DriverScatterGatherLimit =
1723     Controller->ControllerScatterGatherLimit;
1724   if (Controller->DriverScatterGatherLimit > DAC960_V1_ScatterGatherLimit)
1725     Controller->DriverScatterGatherLimit = DAC960_V1_ScatterGatherLimit;
1726   /*
1727     Initialize the Stripe Size, Segment Size, and Geometry Translation.
1728   */
1729   Controller->V1.StripeSize = Config2->BlocksPerStripe * Config2->BlockFactor
1730                               >> (10 - DAC960_BlockSizeBits);
1731   Controller->V1.SegmentSize = Config2->BlocksPerCacheLine * Config2->BlockFactor
1732                                >> (10 - DAC960_BlockSizeBits);
1733   switch (Config2->DriveGeometry)
1734     {
1735     case DAC960_V1_Geometry_128_32:
1736       Controller->V1.GeometryTranslationHeads = 128;
1737       Controller->V1.GeometryTranslationSectors = 32;
1738       break;
1739     case DAC960_V1_Geometry_255_63:
1740       Controller->V1.GeometryTranslationHeads = 255;
1741       Controller->V1.GeometryTranslationSectors = 63;
1742       break;
1743     default:
1744       free_dma_loaf(Controller->PCIDevice, &local_dma);
1745       return DAC960_Failure(Controller, "CONFIG2 DRIVE GEOMETRY");
1746     }
1747   /*
1748     Initialize the Background Initialization Status.
1749   */
1750   if ((Controller->FirmwareVersion[0] == '4' &&
1751       strcmp(Controller->FirmwareVersion, "4.08") >= 0) ||
1752       (Controller->FirmwareVersion[0] == '5' &&
1753        strcmp(Controller->FirmwareVersion, "5.08") >= 0))
1754     {
1755       Controller->V1.BackgroundInitializationStatusSupported = true;
1756       DAC960_V1_ExecuteType3B(Controller,
1757                               DAC960_V1_BackgroundInitializationControl, 0x20,
1758                               Controller->
1759                                V1.BackgroundInitializationStatusDMA);
1760       memcpy(&Controller->V1.LastBackgroundInitializationStatus,
1761                 Controller->V1.BackgroundInitializationStatus,
1762                 sizeof(DAC960_V1_BackgroundInitializationStatus_T));
1763     }
1764   /*
1765     Initialize the Logical Drive Initially Accessible flag.
1766   */
1767   for (LogicalDriveNumber = 0;
1768        LogicalDriveNumber < Controller->LogicalDriveCount;
1769        LogicalDriveNumber++)
1770     if (Controller->V1.LogicalDriveInformation
1771                        [LogicalDriveNumber].LogicalDriveState !=
1772         DAC960_V1_LogicalDrive_Offline)
1773       Controller->LogicalDriveInitiallyAccessible[LogicalDriveNumber] = true;
1774   Controller->V1.LastRebuildStatus = DAC960_V1_NoRebuildOrCheckInProgress;
1775   free_dma_loaf(Controller->PCIDevice, &local_dma);
1776   return true;
1777 }
1778
1779
1780 /*
1781   DAC960_V2_ReadControllerConfiguration reads the Configuration Information
1782   from DAC960 V2 Firmware Controllers and initializes the Controller structure.
1783 */
1784
1785 static bool DAC960_V2_ReadControllerConfiguration(DAC960_Controller_T
1786                                                      *Controller)
1787 {
1788   DAC960_V2_ControllerInfo_T *ControllerInfo =
1789                 &Controller->V2.ControllerInformation;
1790   unsigned short LogicalDeviceNumber = 0;
1791   int ModelNameLength;
1792
1793   /* Get data into dma-able area, then copy into permanent location */
1794   if (!DAC960_V2_NewControllerInfo(Controller))
1795     return DAC960_Failure(Controller, "GET CONTROLLER INFO");
1796   memcpy(ControllerInfo, Controller->V2.NewControllerInformation,
1797                         sizeof(DAC960_V2_ControllerInfo_T));
1798          
1799   
1800   if (!DAC960_V2_GeneralInfo(Controller))
1801     return DAC960_Failure(Controller, "GET HEALTH STATUS");
1802
1803   /*
1804     Initialize the Controller Model Name and Full Model Name fields.
1805   */
1806   ModelNameLength = sizeof(ControllerInfo->ControllerName);
1807   if (ModelNameLength > sizeof(Controller->ModelName)-1)
1808     ModelNameLength = sizeof(Controller->ModelName)-1;
1809   memcpy(Controller->ModelName, ControllerInfo->ControllerName,
1810          ModelNameLength);
1811   ModelNameLength--;
1812   while (Controller->ModelName[ModelNameLength] == ' ' ||
1813          Controller->ModelName[ModelNameLength] == '\0')
1814     ModelNameLength--;
1815   Controller->ModelName[++ModelNameLength] = '\0';
1816   strcpy(Controller->FullModelName, "Mylex ");
1817   strcat(Controller->FullModelName, Controller->ModelName);
1818   /*
1819     Initialize the Controller Firmware Version field.
1820   */
1821   sprintf(Controller->FirmwareVersion, "%d.%02d-%02d",
1822           ControllerInfo->FirmwareMajorVersion,
1823           ControllerInfo->FirmwareMinorVersion,
1824           ControllerInfo->FirmwareTurnNumber);
1825   if (ControllerInfo->FirmwareMajorVersion == 6 &&
1826       ControllerInfo->FirmwareMinorVersion == 0 &&
1827       ControllerInfo->FirmwareTurnNumber < 1)
1828     {
1829       DAC960_Info("FIRMWARE VERSION %s DOES NOT PROVIDE THE CONTROLLER\n",
1830                   Controller, Controller->FirmwareVersion);
1831       DAC960_Info("STATUS MONITORING FUNCTIONALITY NEEDED BY THIS DRIVER.\n",
1832                   Controller);
1833       DAC960_Info("PLEASE UPGRADE TO VERSION 6.00-01 OR ABOVE.\n",
1834                   Controller);
1835     }
1836   /*
1837     Initialize the Controller Channels, Targets, and Memory Size.
1838   */
1839   Controller->Channels = ControllerInfo->NumberOfPhysicalChannelsPresent;
1840   Controller->Targets =
1841     ControllerInfo->MaximumTargetsPerChannel
1842                     [ControllerInfo->NumberOfPhysicalChannelsPresent-1];
1843   Controller->MemorySize = ControllerInfo->MemorySizeMB;
1844   /*
1845     Initialize the Controller Queue Depth, Driver Queue Depth, Logical Drive
1846     Count, Maximum Blocks per Command, Controller Scatter/Gather Limit, and
1847     Driver Scatter/Gather Limit.  The Driver Queue Depth must be at most one
1848     less than the Controller Queue Depth to allow for an automatic drive
1849     rebuild operation.
1850   */
1851   Controller->ControllerQueueDepth = ControllerInfo->MaximumParallelCommands;
1852   Controller->DriverQueueDepth = Controller->ControllerQueueDepth - 1;
1853   if (Controller->DriverQueueDepth > DAC960_MaxDriverQueueDepth)
1854     Controller->DriverQueueDepth = DAC960_MaxDriverQueueDepth;
1855   Controller->LogicalDriveCount = ControllerInfo->LogicalDevicesPresent;
1856   Controller->MaxBlocksPerCommand =
1857     ControllerInfo->MaximumDataTransferSizeInBlocks;
1858   Controller->ControllerScatterGatherLimit =
1859     ControllerInfo->MaximumScatterGatherEntries;
1860   Controller->DriverScatterGatherLimit =
1861     Controller->ControllerScatterGatherLimit;
1862   if (Controller->DriverScatterGatherLimit > DAC960_V2_ScatterGatherLimit)
1863     Controller->DriverScatterGatherLimit = DAC960_V2_ScatterGatherLimit;
1864   /*
1865     Initialize the Logical Device Information.
1866   */
1867   while (true)
1868     {
1869       DAC960_V2_LogicalDeviceInfo_T *NewLogicalDeviceInfo =
1870         Controller->V2.NewLogicalDeviceInformation;
1871       DAC960_V2_LogicalDeviceInfo_T *LogicalDeviceInfo;
1872       DAC960_V2_PhysicalDevice_T PhysicalDevice;
1873
1874       if (!DAC960_V2_NewLogicalDeviceInfo(Controller, LogicalDeviceNumber))
1875         break;
1876       LogicalDeviceNumber = NewLogicalDeviceInfo->LogicalDeviceNumber;
1877       if (LogicalDeviceNumber >= DAC960_MaxLogicalDrives) {
1878         DAC960_Error("DAC960: Logical Drive Number %d not supported\n",
1879                        Controller, LogicalDeviceNumber);
1880                 break;
1881       }
1882       if (NewLogicalDeviceInfo->DeviceBlockSizeInBytes != DAC960_BlockSize) {
1883         DAC960_Error("DAC960: Logical Drive Block Size %d not supported\n",
1884               Controller, NewLogicalDeviceInfo->DeviceBlockSizeInBytes);
1885         LogicalDeviceNumber++;
1886         continue;
1887       }
1888       PhysicalDevice.Controller = 0;
1889       PhysicalDevice.Channel = NewLogicalDeviceInfo->Channel;
1890       PhysicalDevice.TargetID = NewLogicalDeviceInfo->TargetID;
1891       PhysicalDevice.LogicalUnit = NewLogicalDeviceInfo->LogicalUnit;
1892       Controller->V2.LogicalDriveToVirtualDevice[LogicalDeviceNumber] =
1893         PhysicalDevice;
1894       if (NewLogicalDeviceInfo->LogicalDeviceState !=
1895           DAC960_V2_LogicalDevice_Offline)
1896         Controller->LogicalDriveInitiallyAccessible[LogicalDeviceNumber] = true;
1897       LogicalDeviceInfo = kmalloc(sizeof(DAC960_V2_LogicalDeviceInfo_T),
1898                                    GFP_ATOMIC);
1899       if (LogicalDeviceInfo == NULL)
1900         return DAC960_Failure(Controller, "LOGICAL DEVICE ALLOCATION");
1901       Controller->V2.LogicalDeviceInformation[LogicalDeviceNumber] =
1902         LogicalDeviceInfo;
1903       memcpy(LogicalDeviceInfo, NewLogicalDeviceInfo,
1904              sizeof(DAC960_V2_LogicalDeviceInfo_T));
1905       LogicalDeviceNumber++;
1906     }
1907   return true;
1908 }
1909
1910
1911 /*
1912   DAC960_ReportControllerConfiguration reports the Configuration Information
1913   for Controller.
1914 */
1915
1916 static bool DAC960_ReportControllerConfiguration(DAC960_Controller_T
1917                                                     *Controller)
1918 {
1919   DAC960_Info("Configuring Mylex %s PCI RAID Controller\n",
1920               Controller, Controller->ModelName);
1921   DAC960_Info("  Firmware Version: %s, Channels: %d, Memory Size: %dMB\n",
1922               Controller, Controller->FirmwareVersion,
1923               Controller->Channels, Controller->MemorySize);
1924   DAC960_Info("  PCI Bus: %d, Device: %d, Function: %d, I/O Address: ",
1925               Controller, Controller->Bus,
1926               Controller->Device, Controller->Function);
1927   if (Controller->IO_Address == 0)
1928     DAC960_Info("Unassigned\n", Controller);
1929   else DAC960_Info("0x%X\n", Controller, Controller->IO_Address);
1930   DAC960_Info("  PCI Address: 0x%X mapped at 0x%lX, IRQ Channel: %d\n",
1931               Controller, Controller->PCI_Address,
1932               (unsigned long) Controller->BaseAddress,
1933               Controller->IRQ_Channel);
1934   DAC960_Info("  Controller Queue Depth: %d, "
1935               "Maximum Blocks per Command: %d\n",
1936               Controller, Controller->ControllerQueueDepth,
1937               Controller->MaxBlocksPerCommand);
1938   DAC960_Info("  Driver Queue Depth: %d, "
1939               "Scatter/Gather Limit: %d of %d Segments\n",
1940               Controller, Controller->DriverQueueDepth,
1941               Controller->DriverScatterGatherLimit,
1942               Controller->ControllerScatterGatherLimit);
1943   if (Controller->FirmwareType == DAC960_V1_Controller)
1944     {
1945       DAC960_Info("  Stripe Size: %dKB, Segment Size: %dKB, "
1946                   "BIOS Geometry: %d/%d\n", Controller,
1947                   Controller->V1.StripeSize,
1948                   Controller->V1.SegmentSize,
1949                   Controller->V1.GeometryTranslationHeads,
1950                   Controller->V1.GeometryTranslationSectors);
1951       if (Controller->V1.SAFTE_EnclosureManagementEnabled)
1952         DAC960_Info("  SAF-TE Enclosure Management Enabled\n", Controller);
1953     }
1954   return true;
1955 }
1956
1957
1958 /*
1959   DAC960_V1_ReadDeviceConfiguration reads the Device Configuration Information
1960   for DAC960 V1 Firmware Controllers by requesting the SCSI Inquiry and SCSI
1961   Inquiry Unit Serial Number information for each device connected to
1962   Controller.
1963 */
1964
1965 static bool DAC960_V1_ReadDeviceConfiguration(DAC960_Controller_T
1966                                                  *Controller)
1967 {
1968   struct dma_loaf local_dma;
1969
1970   dma_addr_t DCDBs_dma[DAC960_V1_MaxChannels];
1971   DAC960_V1_DCDB_T *DCDBs_cpu[DAC960_V1_MaxChannels];
1972
1973   dma_addr_t SCSI_Inquiry_dma[DAC960_V1_MaxChannels];
1974   DAC960_SCSI_Inquiry_T *SCSI_Inquiry_cpu[DAC960_V1_MaxChannels];
1975
1976   dma_addr_t SCSI_NewInquiryUnitSerialNumberDMA[DAC960_V1_MaxChannels];
1977   DAC960_SCSI_Inquiry_UnitSerialNumber_T *SCSI_NewInquiryUnitSerialNumberCPU[DAC960_V1_MaxChannels];
1978
1979   struct completion Completions[DAC960_V1_MaxChannels];
1980   unsigned long flags;
1981   int Channel, TargetID;
1982
1983   if (!init_dma_loaf(Controller->PCIDevice, &local_dma, 
1984                 DAC960_V1_MaxChannels*(sizeof(DAC960_V1_DCDB_T) +
1985                         sizeof(DAC960_SCSI_Inquiry_T) +
1986                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T))))
1987      return DAC960_Failure(Controller,
1988                         "DMA ALLOCATION FAILED IN ReadDeviceConfiguration"); 
1989    
1990   for (Channel = 0; Channel < Controller->Channels; Channel++) {
1991         DCDBs_cpu[Channel] = slice_dma_loaf(&local_dma,
1992                         sizeof(DAC960_V1_DCDB_T), DCDBs_dma + Channel);
1993         SCSI_Inquiry_cpu[Channel] = slice_dma_loaf(&local_dma,
1994                         sizeof(DAC960_SCSI_Inquiry_T),
1995                         SCSI_Inquiry_dma + Channel);
1996         SCSI_NewInquiryUnitSerialNumberCPU[Channel] = slice_dma_loaf(&local_dma,
1997                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T),
1998                         SCSI_NewInquiryUnitSerialNumberDMA + Channel);
1999   }
2000                 
2001   for (TargetID = 0; TargetID < Controller->Targets; TargetID++)
2002     {
2003       /*
2004        * For each channel, submit a probe for a device on that channel.
2005        * The timeout interval for a device that is present is 10 seconds.
2006        * With this approach, the timeout periods can elapse in parallel
2007        * on each channel.
2008        */
2009       for (Channel = 0; Channel < Controller->Channels; Channel++)
2010         {
2011           dma_addr_t NewInquiryStandardDataDMA = SCSI_Inquiry_dma[Channel];
2012           DAC960_V1_DCDB_T *DCDB = DCDBs_cpu[Channel];
2013           dma_addr_t DCDB_dma = DCDBs_dma[Channel];
2014           DAC960_Command_T *Command = Controller->Commands[Channel];
2015           struct completion *Completion = &Completions[Channel];
2016
2017           init_completion(Completion);
2018           DAC960_V1_ClearCommand(Command);
2019           Command->CommandType = DAC960_ImmediateCommand;
2020           Command->Completion = Completion;
2021           Command->V1.CommandMailbox.Type3.CommandOpcode = DAC960_V1_DCDB;
2022           Command->V1.CommandMailbox.Type3.BusAddress = DCDB_dma;
2023           DCDB->Channel = Channel;
2024           DCDB->TargetID = TargetID;
2025           DCDB->Direction = DAC960_V1_DCDB_DataTransferDeviceToSystem;
2026           DCDB->EarlyStatus = false;
2027           DCDB->Timeout = DAC960_V1_DCDB_Timeout_10_seconds;
2028           DCDB->NoAutomaticRequestSense = false;
2029           DCDB->DisconnectPermitted = true;
2030           DCDB->TransferLength = sizeof(DAC960_SCSI_Inquiry_T);
2031           DCDB->BusAddress = NewInquiryStandardDataDMA;
2032           DCDB->CDBLength = 6;
2033           DCDB->TransferLengthHigh4 = 0;
2034           DCDB->SenseLength = sizeof(DCDB->SenseData);
2035           DCDB->CDB[0] = 0x12; /* INQUIRY */
2036           DCDB->CDB[1] = 0; /* EVPD = 0 */
2037           DCDB->CDB[2] = 0; /* Page Code */
2038           DCDB->CDB[3] = 0; /* Reserved */
2039           DCDB->CDB[4] = sizeof(DAC960_SCSI_Inquiry_T);
2040           DCDB->CDB[5] = 0; /* Control */
2041
2042           spin_lock_irqsave(&Controller->queue_lock, flags);
2043           DAC960_QueueCommand(Command);
2044           spin_unlock_irqrestore(&Controller->queue_lock, flags);
2045         }
2046       /*
2047        * Wait for the problems submitted in the previous loop
2048        * to complete.  On the probes that are successful, 
2049        * get the serial number of the device that was found.
2050        */
2051       for (Channel = 0; Channel < Controller->Channels; Channel++)
2052         {
2053           DAC960_SCSI_Inquiry_T *InquiryStandardData =
2054             &Controller->V1.InquiryStandardData[Channel][TargetID];
2055           DAC960_SCSI_Inquiry_T *NewInquiryStandardData = SCSI_Inquiry_cpu[Channel];
2056           dma_addr_t NewInquiryUnitSerialNumberDMA =
2057                         SCSI_NewInquiryUnitSerialNumberDMA[Channel];
2058           DAC960_SCSI_Inquiry_UnitSerialNumber_T *NewInquiryUnitSerialNumber =
2059                         SCSI_NewInquiryUnitSerialNumberCPU[Channel];
2060           DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2061             &Controller->V1.InquiryUnitSerialNumber[Channel][TargetID];
2062           DAC960_Command_T *Command = Controller->Commands[Channel];
2063           DAC960_V1_DCDB_T *DCDB = DCDBs_cpu[Channel];
2064           struct completion *Completion = &Completions[Channel];
2065
2066           wait_for_completion(Completion);
2067
2068           if (Command->V1.CommandStatus != DAC960_V1_NormalCompletion) {
2069             memset(InquiryStandardData, 0, sizeof(DAC960_SCSI_Inquiry_T));
2070             InquiryStandardData->PeripheralDeviceType = 0x1F;
2071             continue;
2072           } else
2073             memcpy(InquiryStandardData, NewInquiryStandardData, sizeof(DAC960_SCSI_Inquiry_T));
2074         
2075           /* Preserve Channel and TargetID values from the previous loop */
2076           Command->Completion = Completion;
2077           DCDB->TransferLength = sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
2078           DCDB->BusAddress = NewInquiryUnitSerialNumberDMA;
2079           DCDB->SenseLength = sizeof(DCDB->SenseData);
2080           DCDB->CDB[0] = 0x12; /* INQUIRY */
2081           DCDB->CDB[1] = 1; /* EVPD = 1 */
2082           DCDB->CDB[2] = 0x80; /* Page Code */
2083           DCDB->CDB[3] = 0; /* Reserved */
2084           DCDB->CDB[4] = sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T);
2085           DCDB->CDB[5] = 0; /* Control */
2086
2087           spin_lock_irqsave(&Controller->queue_lock, flags);
2088           DAC960_QueueCommand(Command);
2089           spin_unlock_irqrestore(&Controller->queue_lock, flags);
2090           wait_for_completion(Completion);
2091
2092           if (Command->V1.CommandStatus != DAC960_V1_NormalCompletion) {
2093                 memset(InquiryUnitSerialNumber, 0,
2094                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2095                 InquiryUnitSerialNumber->PeripheralDeviceType = 0x1F;
2096           } else
2097                 memcpy(InquiryUnitSerialNumber, NewInquiryUnitSerialNumber,
2098                         sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2099         }
2100     }
2101     free_dma_loaf(Controller->PCIDevice, &local_dma);
2102   return true;
2103 }
2104
2105
2106 /*
2107   DAC960_V2_ReadDeviceConfiguration reads the Device Configuration Information
2108   for DAC960 V2 Firmware Controllers by requesting the Physical Device
2109   Information and SCSI Inquiry Unit Serial Number information for each
2110   device connected to Controller.
2111 */
2112
2113 static bool DAC960_V2_ReadDeviceConfiguration(DAC960_Controller_T
2114                                                  *Controller)
2115 {
2116   unsigned char Channel = 0, TargetID = 0, LogicalUnit = 0;
2117   unsigned short PhysicalDeviceIndex = 0;
2118
2119   while (true)
2120     {
2121       DAC960_V2_PhysicalDeviceInfo_T *NewPhysicalDeviceInfo =
2122                 Controller->V2.NewPhysicalDeviceInformation;
2123       DAC960_V2_PhysicalDeviceInfo_T *PhysicalDeviceInfo;
2124       DAC960_SCSI_Inquiry_UnitSerialNumber_T *NewInquiryUnitSerialNumber =
2125                 Controller->V2.NewInquiryUnitSerialNumber;
2126       DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber;
2127
2128       if (!DAC960_V2_NewPhysicalDeviceInfo(Controller, Channel, TargetID, LogicalUnit))
2129           break;
2130
2131       PhysicalDeviceInfo = kmalloc(sizeof(DAC960_V2_PhysicalDeviceInfo_T),
2132                                     GFP_ATOMIC);
2133       if (PhysicalDeviceInfo == NULL)
2134                 return DAC960_Failure(Controller, "PHYSICAL DEVICE ALLOCATION");
2135       Controller->V2.PhysicalDeviceInformation[PhysicalDeviceIndex] =
2136                 PhysicalDeviceInfo;
2137       memcpy(PhysicalDeviceInfo, NewPhysicalDeviceInfo,
2138                 sizeof(DAC960_V2_PhysicalDeviceInfo_T));
2139
2140       InquiryUnitSerialNumber = kmalloc(
2141               sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T), GFP_ATOMIC);
2142       if (InquiryUnitSerialNumber == NULL) {
2143         kfree(PhysicalDeviceInfo);
2144         return DAC960_Failure(Controller, "SERIAL NUMBER ALLOCATION");
2145       }
2146       Controller->V2.InquiryUnitSerialNumber[PhysicalDeviceIndex] =
2147                 InquiryUnitSerialNumber;
2148
2149       Channel = NewPhysicalDeviceInfo->Channel;
2150       TargetID = NewPhysicalDeviceInfo->TargetID;
2151       LogicalUnit = NewPhysicalDeviceInfo->LogicalUnit;
2152
2153       /*
2154          Some devices do NOT have Unit Serial Numbers.
2155          This command fails for them.  But, we still want to
2156          remember those devices are there.  Construct a
2157          UnitSerialNumber structure for the failure case.
2158       */
2159       if (!DAC960_V2_NewInquiryUnitSerialNumber(Controller, Channel, TargetID, LogicalUnit)) {
2160         memset(InquiryUnitSerialNumber, 0,
2161              sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2162         InquiryUnitSerialNumber->PeripheralDeviceType = 0x1F;
2163       } else
2164         memcpy(InquiryUnitSerialNumber, NewInquiryUnitSerialNumber,
2165                 sizeof(DAC960_SCSI_Inquiry_UnitSerialNumber_T));
2166
2167       PhysicalDeviceIndex++;
2168       LogicalUnit++;
2169     }
2170   return true;
2171 }
2172
2173
2174 /*
2175   DAC960_SanitizeInquiryData sanitizes the Vendor, Model, Revision, and
2176   Product Serial Number fields of the Inquiry Standard Data and Inquiry
2177   Unit Serial Number structures.
2178 */
2179
2180 static void DAC960_SanitizeInquiryData(DAC960_SCSI_Inquiry_T
2181                                          *InquiryStandardData,
2182                                        DAC960_SCSI_Inquiry_UnitSerialNumber_T
2183                                          *InquiryUnitSerialNumber,
2184                                        unsigned char *Vendor,
2185                                        unsigned char *Model,
2186                                        unsigned char *Revision,
2187                                        unsigned char *SerialNumber)
2188 {
2189   int SerialNumberLength, i;
2190   if (InquiryStandardData->PeripheralDeviceType == 0x1F) return;
2191   for (i = 0; i < sizeof(InquiryStandardData->VendorIdentification); i++)
2192     {
2193       unsigned char VendorCharacter =
2194         InquiryStandardData->VendorIdentification[i];
2195       Vendor[i] = (VendorCharacter >= ' ' && VendorCharacter <= '~'
2196                    ? VendorCharacter : ' ');
2197     }
2198   Vendor[sizeof(InquiryStandardData->VendorIdentification)] = '\0';
2199   for (i = 0; i < sizeof(InquiryStandardData->ProductIdentification); i++)
2200     {
2201       unsigned char ModelCharacter =
2202         InquiryStandardData->ProductIdentification[i];
2203       Model[i] = (ModelCharacter >= ' ' && ModelCharacter <= '~'
2204                   ? ModelCharacter : ' ');
2205     }
2206   Model[sizeof(InquiryStandardData->ProductIdentification)] = '\0';
2207   for (i = 0; i < sizeof(InquiryStandardData->ProductRevisionLevel); i++)
2208     {
2209       unsigned char RevisionCharacter =
2210         InquiryStandardData->ProductRevisionLevel[i];
2211       Revision[i] = (RevisionCharacter >= ' ' && RevisionCharacter <= '~'
2212                      ? RevisionCharacter : ' ');
2213     }
2214   Revision[sizeof(InquiryStandardData->ProductRevisionLevel)] = '\0';
2215   if (InquiryUnitSerialNumber->PeripheralDeviceType == 0x1F) return;
2216   SerialNumberLength = InquiryUnitSerialNumber->PageLength;
2217   if (SerialNumberLength >
2218       sizeof(InquiryUnitSerialNumber->ProductSerialNumber))
2219     SerialNumberLength = sizeof(InquiryUnitSerialNumber->ProductSerialNumber);
2220   for (i = 0; i < SerialNumberLength; i++)
2221     {
2222       unsigned char SerialNumberCharacter =
2223         InquiryUnitSerialNumber->ProductSerialNumber[i];
2224       SerialNumber[i] =
2225         (SerialNumberCharacter >= ' ' && SerialNumberCharacter <= '~'
2226          ? SerialNumberCharacter : ' ');
2227     }
2228   SerialNumber[SerialNumberLength] = '\0';
2229 }
2230
2231
2232 /*
2233   DAC960_V1_ReportDeviceConfiguration reports the Device Configuration
2234   Information for DAC960 V1 Firmware Controllers.
2235 */
2236
2237 static bool DAC960_V1_ReportDeviceConfiguration(DAC960_Controller_T
2238                                                    *Controller)
2239 {
2240   int LogicalDriveNumber, Channel, TargetID;
2241   DAC960_Info("  Physical Devices:\n", Controller);
2242   for (Channel = 0; Channel < Controller->Channels; Channel++)
2243     for (TargetID = 0; TargetID < Controller->Targets; TargetID++)
2244       {
2245         DAC960_SCSI_Inquiry_T *InquiryStandardData =
2246           &Controller->V1.InquiryStandardData[Channel][TargetID];
2247         DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2248           &Controller->V1.InquiryUnitSerialNumber[Channel][TargetID];
2249         DAC960_V1_DeviceState_T *DeviceState =
2250           &Controller->V1.DeviceState[Channel][TargetID];
2251         DAC960_V1_ErrorTableEntry_T *ErrorEntry =
2252           &Controller->V1.ErrorTable.ErrorTableEntries[Channel][TargetID];
2253         char Vendor[1+sizeof(InquiryStandardData->VendorIdentification)];
2254         char Model[1+sizeof(InquiryStandardData->ProductIdentification)];
2255         char Revision[1+sizeof(InquiryStandardData->ProductRevisionLevel)];
2256         char SerialNumber[1+sizeof(InquiryUnitSerialNumber
2257                                    ->ProductSerialNumber)];
2258         if (InquiryStandardData->PeripheralDeviceType == 0x1F) continue;
2259         DAC960_SanitizeInquiryData(InquiryStandardData, InquiryUnitSerialNumber,
2260                                    Vendor, Model, Revision, SerialNumber);
2261         DAC960_Info("    %d:%d%s Vendor: %s  Model: %s  Revision: %s\n",
2262                     Controller, Channel, TargetID, (TargetID < 10 ? " " : ""),
2263                     Vendor, Model, Revision);
2264         if (InquiryUnitSerialNumber->PeripheralDeviceType != 0x1F)
2265           DAC960_Info("         Serial Number: %s\n", Controller, SerialNumber);
2266         if (DeviceState->Present &&
2267             DeviceState->DeviceType == DAC960_V1_DiskType)
2268           {
2269             if (Controller->V1.DeviceResetCount[Channel][TargetID] > 0)
2270               DAC960_Info("         Disk Status: %s, %u blocks, %d resets\n",
2271                           Controller,
2272                           (DeviceState->DeviceState == DAC960_V1_Device_Dead
2273                            ? "Dead"
2274                            : DeviceState->DeviceState
2275                              == DAC960_V1_Device_WriteOnly
2276                              ? "Write-Only"
2277                              : DeviceState->DeviceState
2278                                == DAC960_V1_Device_Online
2279                                ? "Online" : "Standby"),
2280                           DeviceState->DiskSize,
2281                           Controller->V1.DeviceResetCount[Channel][TargetID]);
2282             else
2283               DAC960_Info("         Disk Status: %s, %u blocks\n", Controller,
2284                           (DeviceState->DeviceState == DAC960_V1_Device_Dead
2285                            ? "Dead"
2286                            : DeviceState->DeviceState
2287                              == DAC960_V1_Device_WriteOnly
2288                              ? "Write-Only"
2289                              : DeviceState->DeviceState
2290                                == DAC960_V1_Device_Online
2291                                ? "Online" : "Standby"),
2292                           DeviceState->DiskSize);
2293           }
2294         if (ErrorEntry->ParityErrorCount > 0 ||
2295             ErrorEntry->SoftErrorCount > 0 ||
2296             ErrorEntry->HardErrorCount > 0 ||
2297             ErrorEntry->MiscErrorCount > 0)
2298           DAC960_Info("         Errors - Parity: %d, Soft: %d, "
2299                       "Hard: %d, Misc: %d\n", Controller,
2300                       ErrorEntry->ParityErrorCount,
2301                       ErrorEntry->SoftErrorCount,
2302                       ErrorEntry->HardErrorCount,
2303                       ErrorEntry->MiscErrorCount);
2304       }
2305   DAC960_Info("  Logical Drives:\n", Controller);
2306   for (LogicalDriveNumber = 0;
2307        LogicalDriveNumber < Controller->LogicalDriveCount;
2308        LogicalDriveNumber++)
2309     {
2310       DAC960_V1_LogicalDriveInformation_T *LogicalDriveInformation =
2311         &Controller->V1.LogicalDriveInformation[LogicalDriveNumber];
2312       DAC960_Info("    /dev/rd/c%dd%d: RAID-%d, %s, %u blocks, %s\n",
2313                   Controller, Controller->ControllerNumber, LogicalDriveNumber,
2314                   LogicalDriveInformation->RAIDLevel,
2315                   (LogicalDriveInformation->LogicalDriveState
2316                    == DAC960_V1_LogicalDrive_Online
2317                    ? "Online"
2318                    : LogicalDriveInformation->LogicalDriveState
2319                      == DAC960_V1_LogicalDrive_Critical
2320                      ? "Critical" : "Offline"),
2321                   LogicalDriveInformation->LogicalDriveSize,
2322                   (LogicalDriveInformation->WriteBack
2323                    ? "Write Back" : "Write Thru"));
2324     }
2325   return true;
2326 }
2327
2328
2329 /*
2330   DAC960_V2_ReportDeviceConfiguration reports the Device Configuration
2331   Information for DAC960 V2 Firmware Controllers.
2332 */
2333
2334 static bool DAC960_V2_ReportDeviceConfiguration(DAC960_Controller_T
2335                                                    *Controller)
2336 {
2337   int PhysicalDeviceIndex, LogicalDriveNumber;
2338   DAC960_Info("  Physical Devices:\n", Controller);
2339   for (PhysicalDeviceIndex = 0;
2340        PhysicalDeviceIndex < DAC960_V2_MaxPhysicalDevices;
2341        PhysicalDeviceIndex++)
2342     {
2343       DAC960_V2_PhysicalDeviceInfo_T *PhysicalDeviceInfo =
2344         Controller->V2.PhysicalDeviceInformation[PhysicalDeviceIndex];
2345       DAC960_SCSI_Inquiry_T *InquiryStandardData =
2346         (DAC960_SCSI_Inquiry_T *) &PhysicalDeviceInfo->SCSI_InquiryData;
2347       DAC960_SCSI_Inquiry_UnitSerialNumber_T *InquiryUnitSerialNumber =
2348         Controller->V2.InquiryUnitSerialNumber[PhysicalDeviceIndex];
2349       char Vendor[1+sizeof(InquiryStandardData->VendorIdentification)];
2350       char Model[1+sizeof(InquiryStandardData->ProductIdentification)];
2351       char Revision[1+sizeof(InquiryStandardData->ProductRevisionLevel)];
2352       char SerialNumber[1+sizeof(InquiryUnitSerialNumber->ProductSerialNumber)];
2353       if (PhysicalDeviceInfo == NULL) break;
2354       DAC960_SanitizeInquiryData(InquiryStandardData, InquiryUnitSerialNumber,
2355                                  Vendor, Model, Revision, SerialNumber);
2356       DAC960_Info("    %d:%d%s Vendor: %s  Model: %s  Revision: %s\n",
2357                   Controller,
2358                   PhysicalDeviceInfo->Channel,
2359                   PhysicalDeviceInfo->TargetID,
2360                   (PhysicalDeviceInfo->TargetID < 10 ? " " : ""),
2361                   Vendor, Model, Revision);
2362       if (PhysicalDeviceInfo->NegotiatedSynchronousMegaTransfers == 0)
2363         DAC960_Info("         %sAsynchronous\n", Controller,
2364                     (PhysicalDeviceInfo->NegotiatedDataWidthBits == 16
2365                      ? "Wide " :""));
2366       else
2367         DAC960_Info("         %sSynchronous at %d MB/sec\n", Controller,
2368                     (PhysicalDeviceInfo->NegotiatedDataWidthBits == 16
2369                      ? "Wide " :""),
2370                     (PhysicalDeviceInfo->NegotiatedSynchronousMegaTransfers
2371                      * PhysicalDeviceInfo->NegotiatedDataWidthBits/8));
2372       if (InquiryUnitSerialNumber->PeripheralDeviceType != 0x1F)
2373         DAC960_Info("         Serial Number: %s\n", Controller, SerialNumber);
2374       if (PhysicalDeviceInfo->PhysicalDeviceState ==
2375           DAC960_V2_Device_Unconfigured)
2376         continue;
2377       DAC960_Info("         Disk Status: %s, %u blocks\n", Controller,
2378                   (PhysicalDeviceInfo->PhysicalDeviceState
2379                    == DAC960_V2_Device_Online
2380                    ? "Online"
2381                    : PhysicalDeviceInfo->PhysicalDeviceState
2382                      == DAC960_V2_Device_Rebuild
2383                      ? "Rebuild"
2384                      : PhysicalDeviceInfo->PhysicalDeviceState
2385                        == DAC960_V2_Device_Missing
2386                        ? "Missing"
2387                        : PhysicalDeviceInfo->PhysicalDeviceState
2388                          == DAC960_V2_Device_Critical
2389                          ? "Critical"
2390                          : PhysicalDeviceInfo->PhysicalDeviceState
2391                            == DAC960_V2_Device_Dead
2392                            ? "Dead"
2393                            : PhysicalDeviceInfo->PhysicalDeviceState
2394                              == DAC960_V2_Device_SuspectedDead
2395                              ? "Suspected-Dead"
2396                              : PhysicalDeviceInfo->PhysicalDeviceState
2397                                == DAC960_V2_Device_CommandedOffline
2398                                ? "Commanded-Offline"
2399                                : PhysicalDeviceInfo->PhysicalDeviceState
2400                                  == DAC960_V2_Device_Standby
2401                                  ? "Standby" : "Unknown"),
2402                   PhysicalDeviceInfo->ConfigurableDeviceSize);
2403       if (PhysicalDeviceInfo->ParityErrors == 0 &&
2404           PhysicalDeviceInfo->SoftErrors == 0 &&
2405           PhysicalDeviceInfo->HardErrors == 0 &&
2406           PhysicalDeviceInfo->MiscellaneousErrors == 0 &&
2407           PhysicalDeviceInfo->CommandTimeouts == 0 &&
2408           PhysicalDeviceInfo->Retries == 0 &&
2409           PhysicalDeviceInfo->Aborts == 0 &&
2410           PhysicalDeviceInfo->PredictedFailuresDetected == 0)
2411         continue;
2412       DAC960_Info("         Errors - Parity: %d, Soft: %d, "
2413                   "Hard: %d, Misc: %d\n", Controller,
2414                   PhysicalDeviceInfo->ParityErrors,
2415                   PhysicalDeviceInfo->SoftErrors,
2416                   PhysicalDeviceInfo->HardErrors,
2417                   PhysicalDeviceInfo->MiscellaneousErrors);
2418       DAC960_Info("                  Timeouts: %d, Retries: %d, "
2419                   "Aborts: %d, Predicted: %d\n", Controller,
2420                   PhysicalDeviceInfo->CommandTimeouts,
2421                   PhysicalDeviceInfo->Retries,
2422                   PhysicalDeviceInfo->Aborts,
2423                   PhysicalDeviceInfo->PredictedFailuresDetected);
2424     }
2425   DAC960_Info("  Logical Drives:\n", Controller);
2426   for (LogicalDriveNumber = 0;
2427        LogicalDriveNumber < DAC960_MaxLogicalDrives;
2428        LogicalDriveNumber++)
2429     {
2430       DAC960_V2_LogicalDeviceInfo_T *LogicalDeviceInfo =
2431         Controller->V2.LogicalDeviceInformation[LogicalDriveNumber];
2432       unsigned char *ReadCacheStatus[] = { "Read Cache Disabled",
2433                                            "Read Cache Enabled",
2434                                            "Read Ahead Enabled",
2435                                            "Intelligent Read Ahead Enabled",
2436                                            "-", "-", "-", "-" };
2437       unsigned char *WriteCacheStatus[] = { "Write Cache Disabled",
2438                                             "Logical Device Read Only",
2439                                             "Write Cache Enabled",
2440                                             "Intelligent Write Cache Enabled",
2441                                             "-", "-", "-", "-" };
2442       unsigned char *GeometryTranslation;
2443       if (LogicalDeviceInfo == NULL) continue;
2444       switch (LogicalDeviceInfo->DriveGeometry)
2445         {
2446         case DAC960_V2_Geometry_128_32:
2447           GeometryTranslation = "128/32";
2448           break;
2449         case DAC960_V2_Geometry_255_63:
2450           GeometryTranslation = "255/63";
2451           break;
2452         default:
2453           GeometryTranslation = "Invalid";
2454           DAC960_Error("Illegal Logical Device Geometry %d\n",
2455                        Controller, LogicalDeviceInfo->DriveGeometry);
2456           break;
2457         }
2458       DAC960_Info("    /dev/rd/c%dd%d: RAID-%d, %s, %u blocks\n",
2459                   Controller, Controller->ControllerNumber, LogicalDriveNumber,
2460                   LogicalDeviceInfo->RAIDLevel,
2461                   (LogicalDeviceInfo->LogicalDeviceState
2462                    == DAC960_V2_LogicalDevice_Online
2463                    ? "Online"
2464                    : LogicalDeviceInfo->LogicalDeviceState
2465                      == DAC960_V2_LogicalDevice_Critical
2466                      ? "Critical" : "Offline"),
2467                   LogicalDeviceInfo->ConfigurableDeviceSize);
2468       DAC960_Info("                  Logical Device %s, BIOS Geometry: %s\n",
2469                   Controller,
2470                   (LogicalDeviceInfo->LogicalDeviceControl
2471                                      .LogicalDeviceInitialized
2472                    ? "Initialized" : "Uninitialized"),
2473                   GeometryTranslation);
2474       if (LogicalDeviceInfo->StripeSize == 0)
2475         {
2476           if (LogicalDeviceInfo->CacheLineSize == 0)
2477             DAC960_Info("                  Stripe Size: N/A, "
2478                         "Segment Size: N/A\n", Controller);
2479           else
2480             DAC960_Info("                  Stripe Size: N/A, "
2481                         "Segment Size: %dKB\n", Controller,
2482                         1 << (LogicalDeviceInfo->CacheLineSize - 2));
2483         }
2484       else
2485         {
2486           if (LogicalDeviceInfo->CacheLineSize == 0)
2487             DAC960_Info("                  Stripe Size: %dKB, "
2488                         "Segment Size: N/A\n", Controller,
2489                         1 << (LogicalDeviceInfo->StripeSize - 2));
2490           else
2491             DAC960_Info("                  Stripe Size: %dKB, "
2492                         "Segment Size: %dKB\n", Controller,
2493                         1 << (LogicalDeviceInfo->StripeSize - 2),
2494                         1 << (LogicalDeviceInfo->CacheLineSize - 2));
2495         }
2496       DAC960_Info("                  %s, %s\n", Controller,
2497                   ReadCacheStatus[
2498                     LogicalDeviceInfo->LogicalDeviceControl.ReadCache],
2499                   WriteCacheStatus[
2500                     LogicalDeviceInfo->LogicalDeviceControl.WriteCache]);
2501       if (LogicalDeviceInfo->SoftErrors > 0 ||
2502           LogicalDeviceInfo->CommandsFailed > 0 ||
2503           LogicalDeviceInfo->DeferredWriteErrors)
2504         DAC960_Info("                  Errors - Soft: %d, Failed: %d, "
2505                     "Deferred Write: %d\n", Controller,
2506                     LogicalDeviceInfo->SoftErrors,
2507                     LogicalDeviceInfo->CommandsFailed,
2508                     LogicalDeviceInfo->DeferredWriteErrors);
2509
2510     }
2511   return true;
2512 }
2513
2514 /*
2515   DAC960_RegisterBlockDevice registers the Block Device structures
2516   associated with Controller.
2517 */
2518
2519 static bool DAC960_RegisterBlockDevice(DAC960_Controller_T *Controller)
2520 {
2521   int MajorNumber = DAC960_MAJOR + Controller->ControllerNumber;
2522   int n;
2523
2524   /*
2525     Register the Block Device Major Number for this DAC960 Controller.
2526   */
2527   if (register_blkdev(MajorNumber, "dac960") < 0)
2528       return false;
2529
2530   for (n = 0; n < DAC960_MaxLogicalDrives; n++) {
2531         struct gendisk *disk = Controller->disks[n];
2532         struct request_queue *RequestQueue;
2533
2534         /* for now, let all request queues share controller's lock */
2535         RequestQueue = blk_init_queue(DAC960_RequestFunction,&Controller->queue_lock);
2536         if (!RequestQueue) {
2537                 printk("DAC960: failure to allocate request queue\n");
2538                 continue;
2539         }
2540         Controller->RequestQueue[n] = RequestQueue;
2541         blk_queue_bounce_limit(RequestQueue, Controller->BounceBufferLimit);
2542         RequestQueue->queuedata = Controller;
2543         blk_queue_max_segments(RequestQueue, Controller->DriverScatterGatherLimit);
2544         blk_queue_max_hw_sectors(RequestQueue, Controller->MaxBlocksPerCommand);
2545         disk->queue = RequestQueue;
2546         sprintf(disk->disk_name, "rd/c%dd%d", Controller->ControllerNumber, n);
2547         disk->major = MajorNumber;
2548         disk->first_minor = n << DAC960_MaxPartitionsBits;
2549         disk->fops = &DAC960_BlockDeviceOperations;
2550    }
2551   /*
2552     Indicate the Block Device Registration completed successfully,
2553   */
2554   return true;
2555 }
2556
2557
2558 /*
2559   DAC960_UnregisterBlockDevice unregisters the Block Device structures
2560   associated with Controller.
2561 */
2562
2563 static void DAC960_UnregisterBlockDevice(DAC960_Controller_T *Controller)
2564 {
2565   int MajorNumber = DAC960_MAJOR + Controller->ControllerNumber;
2566   int disk;
2567
2568   /* does order matter when deleting gendisk and cleanup in request queue? */
2569   for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++) {
2570         del_gendisk(Controller->disks[disk]);
2571         blk_cleanup_queue(Controller->RequestQueue[disk]);
2572         Controller->RequestQueue[disk] = NULL;
2573   }
2574
2575   /*
2576     Unregister the Block Device Major Number for this DAC960 Controller.
2577   */
2578   unregister_blkdev(MajorNumber, "dac960");
2579 }
2580
2581 /*
2582   DAC960_ComputeGenericDiskInfo computes the values for the Generic Disk
2583   Information Partition Sector Counts and Block Sizes.
2584 */
2585
2586 static void DAC960_ComputeGenericDiskInfo(DAC960_Controller_T *Controller)
2587 {
2588         int disk;
2589         for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++)
2590                 set_capacity(Controller->disks[disk], disk_size(Controller, disk));
2591 }
2592
2593 /*
2594   DAC960_ReportErrorStatus reports Controller BIOS Messages passed through
2595   the Error Status Register when the driver performs the BIOS handshaking.
2596   It returns true for fatal errors and false otherwise.
2597 */
2598
2599 static bool DAC960_ReportErrorStatus(DAC960_Controller_T *Controller,
2600                                         unsigned char ErrorStatus,
2601                                         unsigned char Parameter0,
2602                                         unsigned char Parameter1)
2603 {
2604   switch (ErrorStatus)
2605     {
2606     case 0x00:
2607       DAC960_Notice("Physical Device %d:%d Not Responding\n",
2608                     Controller, Parameter1, Parameter0);
2609       break;
2610     case 0x08:
2611       if (Controller->DriveSpinUpMessageDisplayed) break;
2612       DAC960_Notice("Spinning Up Drives\n", Controller);
2613       Controller->DriveSpinUpMessageDisplayed = true;
2614       break;
2615     case 0x30:
2616       DAC960_Notice("Configuration Checksum Error\n", Controller);
2617       break;
2618     case 0x60:
2619       DAC960_Notice("Mirror Race Recovery Failed\n", Controller);
2620       break;
2621     case 0x70:
2622       DAC960_Notice("Mirror Race Recovery In Progress\n", Controller);
2623       break;
2624     case 0x90:
2625       DAC960_Notice("Physical Device %d:%d COD Mismatch\n",
2626                     Controller, Parameter1, Parameter0);
2627       break;
2628     case 0xA0:
2629       DAC960_Notice("Logical Drive Installation Aborted\n", Controller);
2630       break;
2631     case 0xB0:
2632       DAC960_Notice("Mirror Race On A Critical Logical Drive\n", Controller);
2633       break;
2634     case 0xD0:
2635       DAC960_Notice("New Controller Configuration Found\n", Controller);
2636       break;
2637     case 0xF0:
2638       DAC960_Error("Fatal Memory Parity Error for Controller at\n", Controller);
2639       return true;
2640     default:
2641       DAC960_Error("Unknown Initialization Error %02X for Controller at\n",
2642                    Controller, ErrorStatus);
2643       return true;
2644     }
2645   return false;
2646 }
2647
2648
2649 /*
2650  * DAC960_DetectCleanup releases the resources that were allocated
2651  * during DAC960_DetectController().  DAC960_DetectController can
2652  * has several internal failure points, so not ALL resources may 
2653  * have been allocated.  It's important to free only
2654  * resources that HAVE been allocated.  The code below always
2655  * tests that the resource has been allocated before attempting to
2656  * free it.
2657  */
2658 static void DAC960_DetectCleanup(DAC960_Controller_T *Controller)
2659 {
2660   int i;
2661
2662   /* Free the memory mailbox, status, and related structures */
2663   free_dma_loaf(Controller->PCIDevice, &Controller->DmaPages);
2664   if (Controller->MemoryMappedAddress) {
2665         switch(Controller->HardwareType)
2666         {
2667                 case DAC960_GEM_Controller:
2668                         DAC960_GEM_DisableInterrupts(Controller->BaseAddress);
2669                         break;
2670                 case DAC960_BA_Controller:
2671                         DAC960_BA_DisableInterrupts(Controller->BaseAddress);
2672                         break;
2673                 case DAC960_LP_Controller:
2674                         DAC960_LP_DisableInterrupts(Controller->BaseAddress);
2675                         break;
2676                 case DAC960_LA_Controller:
2677                         DAC960_LA_DisableInterrupts(Controller->BaseAddress);
2678                         break;
2679                 case DAC960_PG_Controller:
2680                         DAC960_PG_DisableInterrupts(Controller->BaseAddress);
2681                         break;
2682                 case DAC960_PD_Controller:
2683                         DAC960_PD_DisableInterrupts(Controller->BaseAddress);
2684                         break;
2685                 case DAC960_P_Controller:
2686                         DAC960_PD_DisableInterrupts(Controller->BaseAddress);
2687                         break;
2688         }
2689         iounmap(Controller->MemoryMappedAddress);
2690   }
2691   if (Controller->IRQ_Channel)
2692         free_irq(Controller->IRQ_Channel, Controller);
2693   if (Controller->IO_Address)
2694         release_region(Controller->IO_Address, 0x80);
2695   pci_disable_device(Controller->PCIDevice);
2696   for (i = 0; (i < DAC960_MaxLogicalDrives) && Controller->disks[i]; i++)
2697        put_disk(Controller->disks[i]);
2698   DAC960_Controllers[Controller->ControllerNumber] = NULL;
2699   kfree(Controller);
2700 }
2701
2702
2703 /*
2704   DAC960_DetectController detects Mylex DAC960/AcceleRAID/eXtremeRAID
2705   PCI RAID Controllers by interrogating the PCI Configuration Space for
2706   Controller Type.
2707 */
2708
2709 static DAC960_Controller_T * 
2710 DAC960_DetectController(struct pci_dev *PCI_Device,
2711                         const struct pci_device_id *entry)
2712 {
2713   struct DAC960_privdata *privdata =
2714                 (struct DAC960_privdata *)entry->driver_data;
2715   irq_handler_t InterruptHandler = privdata->InterruptHandler;
2716   unsigned int MemoryWindowSize = privdata->MemoryWindowSize;
2717   DAC960_Controller_T *Controller = NULL;
2718   unsigned char DeviceFunction = PCI_Device->devfn;
2719   unsigned char ErrorStatus, Parameter0, Parameter1;
2720   unsigned int IRQ_Channel;
2721   void __iomem *BaseAddress;
2722   int i;
2723
2724   Controller = kzalloc(sizeof(DAC960_Controller_T), GFP_ATOMIC);
2725   if (Controller == NULL) {
2726         DAC960_Error("Unable to allocate Controller structure for "
2727                        "Controller at\n", NULL);
2728         return NULL;
2729   }
2730   Controller->ControllerNumber = DAC960_ControllerCount;
2731   DAC960_Controllers[DAC960_ControllerCount++] = Controller;
2732   Controller->Bus = PCI_Device->bus->number;
2733   Controller->FirmwareType = privdata->FirmwareType;
2734   Controller->HardwareType = privdata->HardwareType;
2735   Controller->Device = DeviceFunction >> 3;
2736   Controller->Function = DeviceFunction & 0x7;
2737   Controller->PCIDevice = PCI_Device;
2738   strcpy(Controller->FullModelName, "DAC960");
2739
2740   if (pci_enable_device(PCI_Device))
2741         goto Failure;
2742
2743   switch (Controller->HardwareType)
2744   {
2745         case DAC960_GEM_Controller:
2746           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2747           break;
2748         case DAC960_BA_Controller:
2749           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2750           break;
2751         case DAC960_LP_Controller:
2752           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2753           break;
2754         case DAC960_LA_Controller:
2755           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2756           break;
2757         case DAC960_PG_Controller:
2758           Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2759           break;
2760         case DAC960_PD_Controller:
2761           Controller->IO_Address = pci_resource_start(PCI_Device, 0);
2762           Controller->PCI_Address = pci_resource_start(PCI_Device, 1);
2763           break;
2764         case DAC960_P_Controller:
2765           Controller->IO_Address = pci_resource_start(PCI_Device, 0);
2766           Controller->PCI_Address = pci_resource_start(PCI_Device, 1);
2767           break;
2768   }
2769
2770   pci_set_drvdata(PCI_Device, (void *)((long)Controller->ControllerNumber));
2771   for (i = 0; i < DAC960_MaxLogicalDrives; i++) {
2772         Controller->disks[i] = alloc_disk(1<<DAC960_MaxPartitionsBits);
2773         if (!Controller->disks[i])
2774                 goto Failure;
2775         Controller->disks[i]->private_data = (void *)((long)i);
2776   }
2777   init_waitqueue_head(&Controller->CommandWaitQueue);
2778   init_waitqueue_head(&Controller->HealthStatusWaitQueue);
2779   spin_lock_init(&Controller->queue_lock);
2780   DAC960_AnnounceDriver(Controller);
2781   /*
2782     Map the Controller Register Window.
2783   */
2784  if (MemoryWindowSize < PAGE_SIZE)
2785         MemoryWindowSize = PAGE_SIZE;
2786   Controller->MemoryMappedAddress =
2787         ioremap_nocache(Controller->PCI_Address & PAGE_MASK, MemoryWindowSize);
2788   Controller->BaseAddress =
2789         Controller->MemoryMappedAddress + (Controller->PCI_Address & ~PAGE_MASK);
2790   if (Controller->MemoryMappedAddress == NULL)
2791   {
2792           DAC960_Error("Unable to map Controller Register Window for "
2793                        "Controller at\n", Controller);
2794           goto Failure;
2795   }
2796   BaseAddress = Controller->BaseAddress;
2797   switch (Controller->HardwareType)
2798   {
2799         case DAC960_GEM_Controller:
2800           DAC960_GEM_DisableInterrupts(BaseAddress);
2801           DAC960_GEM_AcknowledgeHardwareMailboxStatus(BaseAddress);
2802           udelay(1000);
2803           while (DAC960_GEM_InitializationInProgressP(BaseAddress))
2804             {
2805               if (DAC960_GEM_ReadErrorStatus(BaseAddress, &ErrorStatus,
2806                                             &Parameter0, &Parameter1) &&
2807                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2808                                            Parameter0, Parameter1))
2809                 goto Failure;
2810               udelay(10);
2811             }
2812           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2813             {
2814               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2815                            "for Controller at\n", Controller);
2816               goto Failure;
2817             }
2818           DAC960_GEM_EnableInterrupts(BaseAddress);
2819           Controller->QueueCommand = DAC960_GEM_QueueCommand;
2820           Controller->ReadControllerConfiguration =
2821             DAC960_V2_ReadControllerConfiguration;
2822           Controller->ReadDeviceConfiguration =
2823             DAC960_V2_ReadDeviceConfiguration;
2824           Controller->ReportDeviceConfiguration =
2825             DAC960_V2_ReportDeviceConfiguration;
2826           Controller->QueueReadWriteCommand =
2827             DAC960_V2_QueueReadWriteCommand;
2828           break;
2829         case DAC960_BA_Controller:
2830           DAC960_BA_DisableInterrupts(BaseAddress);
2831           DAC960_BA_AcknowledgeHardwareMailboxStatus(BaseAddress);
2832           udelay(1000);
2833           while (DAC960_BA_InitializationInProgressP(BaseAddress))
2834             {
2835               if (DAC960_BA_ReadErrorStatus(BaseAddress, &ErrorStatus,
2836                                             &Parameter0, &Parameter1) &&
2837                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2838                                            Parameter0, Parameter1))
2839                 goto Failure;
2840               udelay(10);
2841             }
2842           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2843             {
2844               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2845                            "for Controller at\n", Controller);
2846               goto Failure;
2847             }
2848           DAC960_BA_EnableInterrupts(BaseAddress);
2849           Controller->QueueCommand = DAC960_BA_QueueCommand;
2850           Controller->ReadControllerConfiguration =
2851             DAC960_V2_ReadControllerConfiguration;
2852           Controller->ReadDeviceConfiguration =
2853             DAC960_V2_ReadDeviceConfiguration;
2854           Controller->ReportDeviceConfiguration =
2855             DAC960_V2_ReportDeviceConfiguration;
2856           Controller->QueueReadWriteCommand =
2857             DAC960_V2_QueueReadWriteCommand;
2858           break;
2859         case DAC960_LP_Controller:
2860           DAC960_LP_DisableInterrupts(BaseAddress);
2861           DAC960_LP_AcknowledgeHardwareMailboxStatus(BaseAddress);
2862           udelay(1000);
2863           while (DAC960_LP_InitializationInProgressP(BaseAddress))
2864             {
2865               if (DAC960_LP_ReadErrorStatus(BaseAddress, &ErrorStatus,
2866                                             &Parameter0, &Parameter1) &&
2867                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2868                                            Parameter0, Parameter1))
2869                 goto Failure;
2870               udelay(10);
2871             }
2872           if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2873             {
2874               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2875                            "for Controller at\n", Controller);
2876               goto Failure;
2877             }
2878           DAC960_LP_EnableInterrupts(BaseAddress);
2879           Controller->QueueCommand = DAC960_LP_QueueCommand;
2880           Controller->ReadControllerConfiguration =
2881             DAC960_V2_ReadControllerConfiguration;
2882           Controller->ReadDeviceConfiguration =
2883             DAC960_V2_ReadDeviceConfiguration;
2884           Controller->ReportDeviceConfiguration =
2885             DAC960_V2_ReportDeviceConfiguration;
2886           Controller->QueueReadWriteCommand =
2887             DAC960_V2_QueueReadWriteCommand;
2888           break;
2889         case DAC960_LA_Controller:
2890           DAC960_LA_DisableInterrupts(BaseAddress);
2891           DAC960_LA_AcknowledgeHardwareMailboxStatus(BaseAddress);
2892           udelay(1000);
2893           while (DAC960_LA_InitializationInProgressP(BaseAddress))
2894             {
2895               if (DAC960_LA_ReadErrorStatus(BaseAddress, &ErrorStatus,
2896                                             &Parameter0, &Parameter1) &&
2897                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2898                                            Parameter0, Parameter1))
2899                 goto Failure;
2900               udelay(10);
2901             }
2902           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2903             {
2904               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2905                            "for Controller at\n", Controller);
2906               goto Failure;
2907             }
2908           DAC960_LA_EnableInterrupts(BaseAddress);
2909           if (Controller->V1.DualModeMemoryMailboxInterface)
2910             Controller->QueueCommand = DAC960_LA_QueueCommandDualMode;
2911           else Controller->QueueCommand = DAC960_LA_QueueCommandSingleMode;
2912           Controller->ReadControllerConfiguration =
2913             DAC960_V1_ReadControllerConfiguration;
2914           Controller->ReadDeviceConfiguration =
2915             DAC960_V1_ReadDeviceConfiguration;
2916           Controller->ReportDeviceConfiguration =
2917             DAC960_V1_ReportDeviceConfiguration;
2918           Controller->QueueReadWriteCommand =
2919             DAC960_V1_QueueReadWriteCommand;
2920           break;
2921         case DAC960_PG_Controller:
2922           DAC960_PG_DisableInterrupts(BaseAddress);
2923           DAC960_PG_AcknowledgeHardwareMailboxStatus(BaseAddress);
2924           udelay(1000);
2925           while (DAC960_PG_InitializationInProgressP(BaseAddress))
2926             {
2927               if (DAC960_PG_ReadErrorStatus(BaseAddress, &ErrorStatus,
2928                                             &Parameter0, &Parameter1) &&
2929                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2930                                            Parameter0, Parameter1))
2931                 goto Failure;
2932               udelay(10);
2933             }
2934           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2935             {
2936               DAC960_Error("Unable to Enable Memory Mailbox Interface "
2937                            "for Controller at\n", Controller);
2938               goto Failure;
2939             }
2940           DAC960_PG_EnableInterrupts(BaseAddress);
2941           if (Controller->V1.DualModeMemoryMailboxInterface)
2942             Controller->QueueCommand = DAC960_PG_QueueCommandDualMode;
2943           else Controller->QueueCommand = DAC960_PG_QueueCommandSingleMode;
2944           Controller->ReadControllerConfiguration =
2945             DAC960_V1_ReadControllerConfiguration;
2946           Controller->ReadDeviceConfiguration =
2947             DAC960_V1_ReadDeviceConfiguration;
2948           Controller->ReportDeviceConfiguration =
2949             DAC960_V1_ReportDeviceConfiguration;
2950           Controller->QueueReadWriteCommand =
2951             DAC960_V1_QueueReadWriteCommand;
2952           break;
2953         case DAC960_PD_Controller:
2954           if (!request_region(Controller->IO_Address, 0x80,
2955                               Controller->FullModelName)) {
2956                 DAC960_Error("IO port 0x%d busy for Controller at\n",
2957                              Controller, Controller->IO_Address);
2958                 goto Failure;
2959           }
2960           DAC960_PD_DisableInterrupts(BaseAddress);
2961           DAC960_PD_AcknowledgeStatus(BaseAddress);
2962           udelay(1000);
2963           while (DAC960_PD_InitializationInProgressP(BaseAddress))
2964             {
2965               if (DAC960_PD_ReadErrorStatus(BaseAddress, &ErrorStatus,
2966                                             &Parameter0, &Parameter1) &&
2967                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
2968                                            Parameter0, Parameter1))
2969                 goto Failure;
2970               udelay(10);
2971             }
2972           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
2973             {
2974               DAC960_Error("Unable to allocate DMA mapped memory "
2975                            "for Controller at\n", Controller);
2976               goto Failure;
2977             }
2978           DAC960_PD_EnableInterrupts(BaseAddress);
2979           Controller->QueueCommand = DAC960_PD_QueueCommand;
2980           Controller->ReadControllerConfiguration =
2981             DAC960_V1_ReadControllerConfiguration;
2982           Controller->ReadDeviceConfiguration =
2983             DAC960_V1_ReadDeviceConfiguration;
2984           Controller->ReportDeviceConfiguration =
2985             DAC960_V1_ReportDeviceConfiguration;
2986           Controller->QueueReadWriteCommand =
2987             DAC960_V1_QueueReadWriteCommand;
2988           break;
2989         case DAC960_P_Controller:
2990           if (!request_region(Controller->IO_Address, 0x80,
2991                               Controller->FullModelName)){
2992                 DAC960_Error("IO port 0x%d busy for Controller at\n",
2993                              Controller, Controller->IO_Address);
2994                 goto Failure;
2995           }
2996           DAC960_PD_DisableInterrupts(BaseAddress);
2997           DAC960_PD_AcknowledgeStatus(BaseAddress);
2998           udelay(1000);
2999           while (DAC960_PD_InitializationInProgressP(BaseAddress))
3000             {
3001               if (DAC960_PD_ReadErrorStatus(BaseAddress, &ErrorStatus,
3002                                             &Parameter0, &Parameter1) &&
3003                   DAC960_ReportErrorStatus(Controller, ErrorStatus,
3004                                            Parameter0, Parameter1))
3005                 goto Failure;
3006               udelay(10);
3007             }
3008           if (!DAC960_V1_EnableMemoryMailboxInterface(Controller))
3009             {
3010               DAC960_Error("Unable to allocate DMA mapped memory"
3011                            "for Controller at\n", Controller);
3012               goto Failure;
3013             }
3014           DAC960_PD_EnableInterrupts(BaseAddress);
3015           Controller->QueueCommand = DAC960_P_QueueCommand;
3016           Controller->ReadControllerConfiguration =
3017             DAC960_V1_ReadControllerConfiguration;
3018           Controller->ReadDeviceConfiguration =
3019             DAC960_V1_ReadDeviceConfiguration;
3020           Controller->ReportDeviceConfiguration =
3021             DAC960_V1_ReportDeviceConfiguration;
3022           Controller->QueueReadWriteCommand =
3023             DAC960_V1_QueueReadWriteCommand;
3024           break;
3025   }
3026   /*
3027      Acquire shared access to the IRQ Channel.
3028   */
3029   IRQ_Channel = PCI_Device->irq;
3030   if (request_irq(IRQ_Channel, InterruptHandler, IRQF_SHARED,
3031                       Controller->FullModelName, Controller) < 0)
3032   {
3033         DAC960_Error("Unable to acquire IRQ Channel %d for Controller at\n",
3034                        Controller, Controller->IRQ_Channel);
3035         goto Failure;
3036   }
3037   Controller->IRQ_Channel = IRQ_Channel;
3038   Controller->InitialCommand.CommandIdentifier = 1;
3039   Controller->InitialCommand.Controller = Controller;
3040   Controller->Commands[0] = &Controller->InitialCommand;
3041   Controller->FreeCommands = &Controller->InitialCommand;
3042   return Controller;
3043       
3044 Failure:
3045   if (Controller->IO_Address == 0)
3046         DAC960_Error("PCI Bus %d Device %d Function %d I/O Address N/A "
3047                      "PCI Address 0x%X\n", Controller,
3048                      Controller->Bus, Controller->Device,
3049                      Controller->Function, Controller->PCI_Address);
3050   else
3051         DAC960_Error("PCI Bus %d Device %d Function %d I/O Address "
3052                         "0x%X PCI Address 0x%X\n", Controller,
3053                         Controller->Bus, Controller->Device,
3054                         Controller->Function, Controller->IO_Address,
3055                         Controller->PCI_Address);
3056   DAC960_DetectCleanup(Controller);
3057   DAC960_ControllerCount--;
3058   return NULL;
3059 }
3060
3061 /*
3062   DAC960_InitializeController initializes Controller.
3063 */
3064
3065 static bool 
3066 DAC960_InitializeController(DAC960_Controller_T *Controller)
3067 {
3068   if (DAC960_ReadControllerConfiguration(Controller) &&
3069       DAC960_ReportControllerConfiguration(Controller) &&
3070       DAC960_CreateAuxiliaryStructures(Controller) &&
3071       DAC960_ReadDeviceConfiguration(Controller) &&
3072       DAC960_ReportDeviceConfiguration(Controller) &&
3073       DAC960_RegisterBlockDevice(Controller))
3074     {
3075       /*
3076         Initialize the Monitoring Timer.
3077       */
3078       init_timer(&Controller->MonitoringTimer);
3079       Controller->MonitoringTimer.expires =
3080         jiffies + DAC960_MonitoringTimerInterval;
3081       Controller->MonitoringTimer.data = (unsigned long) Controller;
3082       Controller->MonitoringTimer.function = DAC960_MonitoringTimerFunction;
3083       add_timer(&Controller->MonitoringTimer);
3084       Controller->ControllerInitialized = true;
3085       return true;
3086     }
3087   return false;
3088 }
3089
3090
3091 /*
3092   DAC960_FinalizeController finalizes Controller.
3093 */
3094
3095 static void DAC960_FinalizeController(DAC960_Controller_T *Controller)
3096 {
3097   if (Controller->ControllerInitialized)
3098     {
3099       unsigned long flags;
3100
3101       /*
3102        * Acquiring and releasing lock here eliminates
3103        * a very low probability race.
3104        *
3105        * The code below allocates controller command structures
3106        * from the free list without holding the controller lock.
3107        * This is safe assuming there is no other activity on
3108        * the controller at the time.
3109        * 
3110        * But, there might be a monitoring command still
3111        * in progress.  Setting the Shutdown flag while holding
3112        * the lock ensures that there is no monitoring command
3113        * in the interrupt handler currently, and any monitoring
3114        * commands that complete from this time on will NOT return
3115        * their command structure to the free list.
3116        */
3117
3118       spin_lock_irqsave(&Controller->queue_lock, flags);
3119       Controller->ShutdownMonitoringTimer = 1;
3120       spin_unlock_irqrestore(&Controller->queue_lock, flags);
3121
3122       del_timer_sync(&Controller->MonitoringTimer);
3123       if (Controller->FirmwareType == DAC960_V1_Controller)
3124         {
3125           DAC960_Notice("Flushing Cache...", Controller);
3126           DAC960_V1_ExecuteType3(Controller, DAC960_V1_Flush, 0);
3127           DAC960_Notice("done\n", Controller);
3128
3129           if (Controller->HardwareType == DAC960_PD_Controller)
3130               release_region(Controller->IO_Address, 0x80);
3131         }
3132       else
3133         {
3134           DAC960_Notice("Flushing Cache...", Controller);
3135           DAC960_V2_DeviceOperation(Controller, DAC960_V2_PauseDevice,
3136                                     DAC960_V2_RAID_Controller);
3137           DAC960_Notice("done\n", Controller);
3138         }
3139     }
3140   DAC960_UnregisterBlockDevice(Controller);
3141   DAC960_DestroyAuxiliaryStructures(Controller);
3142   DAC960_DestroyProcEntries(Controller);
3143   DAC960_DetectCleanup(Controller);
3144 }
3145
3146
3147 /*
3148   DAC960_Probe verifies controller's existence and
3149   initializes the DAC960 Driver for that controller.
3150 */
3151
3152 static int 
3153 DAC960_Probe(struct pci_dev *dev, const struct pci_device_id *entry)
3154 {
3155   int disk;
3156   DAC960_Controller_T *Controller;
3157
3158   if (DAC960_ControllerCount == DAC960_MaxControllers)
3159   {
3160         DAC960_Error("More than %d DAC960 Controllers detected - "
3161                        "ignoring from Controller at\n",
3162                        NULL, DAC960_MaxControllers);
3163         return -ENODEV;
3164   }
3165
3166   Controller = DAC960_DetectController(dev, entry);
3167   if (!Controller)
3168         return -ENODEV;
3169
3170   if (!DAC960_InitializeController(Controller)) {
3171         DAC960_FinalizeController(Controller);
3172         return -ENODEV;
3173   }
3174
3175   for (disk = 0; disk < DAC960_MaxLogicalDrives; disk++) {
3176         set_capacity(Controller->disks[disk], disk_size(Controller, disk));
3177         add_disk(Controller->disks[disk]);
3178   }
3179   DAC960_CreateProcEntries(Controller);
3180   return 0;
3181 }
3182
3183
3184 /*
3185   DAC960_Finalize finalizes the DAC960 Driver.
3186 */
3187
3188 static void DAC960_Remove(struct pci_dev *PCI_Device)
3189 {
3190   int Controller_Number = (long)pci_get_drvdata(PCI_Device);
3191   DAC960_Controller_T *Controller = DAC960_Controllers[Controller_Number];
3192   if (Controller != NULL)
3193       DAC960_FinalizeController(Controller);
3194 }
3195
3196
3197 /*
3198   DAC960_V1_QueueReadWriteCommand prepares and queues a Read/Write Command for
3199   DAC960 V1 Firmware Controllers.
3200 */
3201
3202 static void DAC960_V1_QueueReadWriteCommand(DAC960_Command_T *Command)
3203 {
3204   DAC960_Controller_T *Controller = Command->Controller;
3205   DAC960_V1_CommandMailbox_T *CommandMailbox = &Command->V1.CommandMailbox;
3206   DAC960_V1_ScatterGatherSegment_T *ScatterGatherList =
3207                                         Command->V1.ScatterGatherList;
3208   struct scatterlist *ScatterList = Command->V1.ScatterList;
3209
3210   DAC960_V1_ClearCommand(Command);
3211
3212   if (Command->SegmentCount == 1)
3213     {
3214       if (Command->DmaDirection == PCI_DMA_FROMDEVICE)
3215         CommandMailbox->Type5.CommandOpcode = DAC960_V1_Read;
3216       else 
3217         CommandMailbox->Type5.CommandOpcode = DAC960_V1_Write;
3218
3219       CommandMailbox->Type5.LD.TransferLength = Command->BlockCount;
3220       CommandMailbox->Type5.LD.LogicalDriveNumber = Command->LogicalDriveNumber;
3221       CommandMailbox->Type5.LogicalBlockAddress = Command->BlockNumber;
3222       CommandMailbox->Type5.BusAddress =
3223                         (DAC960_BusAddress32_T)sg_dma_address(ScatterList);     
3224     }
3225   else
3226     {
3227       int i;
3228
3229       if (Command->DmaDirection == PCI_DMA_FROMDEVICE)
3230         CommandMailbox->Type5.CommandOpcode = DAC960_V1_ReadWithScatterGather;
3231       else
3232         CommandMailbox->Type5.CommandOpcode = DAC960_V1_WriteWithScatterGather;
3233
3234       CommandMailbox->Type5.LD.TransferLength = Command->BlockCount;
3235       CommandMailbox->Type5.LD.LogicalDriveNumber = Command->LogicalDriveNumber;
3236       CommandMailbox->Type5.LogicalBlockAddress = Command->BlockNumber;
3237       CommandMailbox->Type5.BusAddress = Command->V1.ScatterGatherListDMA;
3238
3239       CommandMailbox->Type5.ScatterGatherCount = Command->SegmentCount;
3240
3241       for (i = 0; i < Command->SegmentCount; i++, ScatterList++, ScatterGatherList++) {
3242                 ScatterGatherList->SegmentDataPointer =
3243                         (DAC960_BusAddress32_T)sg_dma_address(ScatterList);
3244                 ScatterGatherList->SegmentByteCount =
3245                         (DAC960_ByteCount32_T)sg_dma_len(ScatterList);
3246       }
3247     }
3248   DAC960_QueueCommand(Command);
3249 }
3250
3251
3252 /*
3253   DAC960_V2_QueueReadWriteCommand prepares and queues a Read/Write Command for
3254   DAC960 V2 Firmware Controllers.
3255 */
3256
3257 static void DAC960_V2_QueueReadWriteCommand(DAC960_Command_T *Command)
3258 {
3259   DAC960_Controller_T *Controller = Command->Controller;
3260   DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
3261   struct scatterlist *ScatterList = Command->V2.ScatterList;
3262
3263   DAC960_V2_ClearCommand(Command);
3264
3265   CommandMailbox->SCSI_10.CommandOpcode = DAC960_V2_SCSI_10;
3266   CommandMailbox->SCSI_10.CommandControlBits.DataTransferControllerToHost =
3267     (Command->DmaDirection == PCI_DMA_FROMDEVICE);
3268   CommandMailbox->SCSI_10.DataTransferSize =
3269     Command->BlockCount << DAC960_BlockSizeBits;
3270   CommandMailbox->SCSI_10.RequestSenseBusAddress = Command->V2.RequestSenseDMA;
3271   CommandMailbox->SCSI_10.PhysicalDevice =
3272     Controller->V2.LogicalDriveToVirtualDevice[Command->LogicalDriveNumber];
3273   CommandMailbox->SCSI_10.RequestSenseSize = sizeof(DAC960_SCSI_RequestSense_T);
3274   CommandMailbox->SCSI_10.CDBLength = 10;
3275   CommandMailbox->SCSI_10.SCSI_CDB[0] =
3276     (Command->DmaDirection == PCI_DMA_FROMDEVICE ? 0x28 : 0x2A);
3277   CommandMailbox->SCSI_10.SCSI_CDB[2] = Command->BlockNumber >> 24;
3278   CommandMailbox->SCSI_10.SCSI_CDB[3] = Command->BlockNumber >> 16;
3279   CommandMailbox->SCSI_10.SCSI_CDB[4] = Command->BlockNumber >> 8;
3280   CommandMailbox->SCSI_10.SCSI_CDB[5] = Command->BlockNumber;
3281   CommandMailbox->SCSI_10.SCSI_CDB[7] = Command->BlockCount >> 8;
3282   CommandMailbox->SCSI_10.SCSI_CDB[8] = Command->BlockCount;
3283
3284   if (Command->SegmentCount == 1)
3285     {
3286       CommandMailbox->SCSI_10.DataTransferMemoryAddress
3287                              .ScatterGatherSegments[0]
3288                              .SegmentDataPointer =
3289         (DAC960_BusAddress64_T)sg_dma_address(ScatterList);
3290       CommandMailbox->SCSI_10.DataTransferMemoryAddress
3291                              .ScatterGatherSegments[0]
3292                              .SegmentByteCount =
3293         CommandMailbox->SCSI_10.DataTransferSize;
3294     }
3295   else
3296     {
3297       DAC960_V2_ScatterGatherSegment_T *ScatterGatherList;
3298       int i;
3299
3300       if (Command->SegmentCount > 2)
3301         {
3302           ScatterGatherList = Command->V2.ScatterGatherList;
3303           CommandMailbox->SCSI_10.CommandControlBits
3304                          .AdditionalScatterGatherListMemory = true;
3305           CommandMailbox->SCSI_10.DataTransferMemoryAddress
3306                 .ExtendedScatterGather.ScatterGatherList0Length = Command->SegmentCount;
3307           CommandMailbox->SCSI_10.DataTransferMemoryAddress
3308                          .ExtendedScatterGather.ScatterGatherList0Address =
3309             Command->V2.ScatterGatherListDMA;
3310         }
3311       else
3312         ScatterGatherList = CommandMailbox->SCSI_10.DataTransferMemoryAddress
3313                                  .ScatterGatherSegments;
3314
3315       for (i = 0; i < Command->SegmentCount; i++, ScatterList++, ScatterGatherList++) {
3316                 ScatterGatherList->SegmentDataPointer =
3317                         (DAC960_BusAddress64_T)sg_dma_address(ScatterList);
3318                 ScatterGatherList->SegmentByteCount =
3319                         (DAC960_ByteCount64_T)sg_dma_len(ScatterList);
3320       }
3321     }
3322   DAC960_QueueCommand(Command);
3323 }
3324
3325
3326 static int DAC960_process_queue(DAC960_Controller_T *Controller, struct request_queue *req_q)
3327 {
3328         struct request *Request;
3329         DAC960_Command_T *Command;
3330
3331    while(1) {
3332         Request = blk_peek_request(req_q);
3333         if (!Request)
3334                 return 1;
3335
3336         Command = DAC960_AllocateCommand(Controller);
3337         if (Command == NULL)
3338                 return 0;
3339
3340         if (rq_data_dir(Request) == READ) {
3341                 Command->DmaDirection = PCI_DMA_FROMDEVICE;
3342                 Command->CommandType = DAC960_ReadCommand;
3343         } else {
3344                 Command->DmaDirection = PCI_DMA_TODEVICE;
3345                 Command->CommandType = DAC960_WriteCommand;
3346         }
3347         Command->Completion = Request->end_io_data;
3348         Command->LogicalDriveNumber = (long)Request->rq_disk->private_data;
3349         Command->BlockNumber = blk_rq_pos(Request);
3350         Command->BlockCount = blk_rq_sectors(Request);
3351         Command->Request = Request;
3352         blk_start_request(Request);
3353         Command->SegmentCount = blk_rq_map_sg(req_q,
3354                   Command->Request, Command->cmd_sglist);
3355         /* pci_map_sg MAY change the value of SegCount */
3356         Command->SegmentCount = pci_map_sg(Controller->PCIDevice, Command->cmd_sglist,
3357                  Command->SegmentCount, Command->DmaDirection);
3358
3359         DAC960_QueueReadWriteCommand(Command);
3360   }
3361 }
3362
3363 /*
3364   DAC960_ProcessRequest attempts to remove one I/O Request from Controller's
3365   I/O Request Queue and queues it to the Controller.  WaitForCommand is true if
3366   this function should wait for a Command to become available if necessary.
3367   This function returns true if an I/O Request was queued and false otherwise.
3368 */
3369 static void DAC960_ProcessRequest(DAC960_Controller_T *controller)
3370 {
3371         int i;
3372
3373         if (!controller->ControllerInitialized)
3374                 return;
3375
3376         /* Do this better later! */
3377         for (i = controller->req_q_index; i < DAC960_MaxLogicalDrives; i++) {
3378                 struct request_queue *req_q = controller->RequestQueue[i];
3379
3380                 if (req_q == NULL)
3381                         continue;
3382
3383                 if (!DAC960_process_queue(controller, req_q)) {
3384                         controller->req_q_index = i;
3385                         return;
3386                 }
3387         }
3388
3389         if (controller->req_q_index == 0)
3390                 return;
3391
3392         for (i = 0; i < controller->req_q_index; i++) {
3393                 struct request_queue *req_q = controller->RequestQueue[i];
3394
3395                 if (req_q == NULL)
3396                         continue;
3397
3398                 if (!DAC960_process_queue(controller, req_q)) {
3399                         controller->req_q_index = i;
3400                         return;
3401                 }
3402       &nbs