Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma
[~shefty/rdma-dev.git] / drivers / dma / dw_dmac.c
1 /*
2  * Core driver for the Synopsys DesignWare DMA Controller
3  *
4  * Copyright (C) 2007-2008 Atmel Corporation
5  * Copyright (C) 2010-2011 ST Microelectronics
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 #include <linux/mm.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27
28 #include "dw_dmac_regs.h"
29 #include "dmaengine.h"
30
31 /*
32  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
33  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
34  * of which use ARM any more).  See the "Databook" from Synopsys for
35  * information beyond what licensees probably provide.
36  *
37  * The driver has currently been tested only with the Atmel AT32AP7000,
38  * which does not support descriptor writeback.
39  */
40
41 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
42 {
43         return slave ? slave->dst_master : 0;
44 }
45
46 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
47 {
48         return slave ? slave->src_master : 1;
49 }
50
51 #define SRC_MASTER      0
52 #define DST_MASTER      1
53
54 static inline unsigned int dwc_get_master(struct dma_chan *chan, int master)
55 {
56         struct dw_dma *dw = to_dw_dma(chan->device);
57         struct dw_dma_slave *dws = chan->private;
58         unsigned int m;
59
60         if (master == SRC_MASTER)
61                 m = dwc_get_sms(dws);
62         else
63                 m = dwc_get_dms(dws);
64
65         return min_t(unsigned int, dw->nr_masters - 1, m);
66 }
67
68 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
69                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
70                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
71                 bool _is_slave = is_slave_direction(_dwc->direction);   \
72                 int _dms = dwc_get_master(_chan, DST_MASTER);           \
73                 int _sms = dwc_get_master(_chan, SRC_MASTER);           \
74                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
75                         DW_DMA_MSIZE_16;                        \
76                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
77                         DW_DMA_MSIZE_16;                        \
78                                                                 \
79                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
80                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
81                  | DWC_CTLL_LLP_D_EN                            \
82                  | DWC_CTLL_LLP_S_EN                            \
83                  | DWC_CTLL_DMS(_dms)                           \
84                  | DWC_CTLL_SMS(_sms));                         \
85         })
86
87 /*
88  * Number of descriptors to allocate for each channel. This should be
89  * made configurable somehow; preferably, the clients (at least the
90  * ones using slave transfers) should be able to give us a hint.
91  */
92 #define NR_DESCS_PER_CHANNEL    64
93
94 static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master)
95 {
96         struct dw_dma *dw = to_dw_dma(chan->device);
97
98         return dw->data_width[dwc_get_master(chan, master)];
99 }
100
101 /*----------------------------------------------------------------------*/
102
103 static struct device *chan2dev(struct dma_chan *chan)
104 {
105         return &chan->dev->device;
106 }
107 static struct device *chan2parent(struct dma_chan *chan)
108 {
109         return chan->dev->device.parent;
110 }
111
112 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
113 {
114         return to_dw_desc(dwc->active_list.next);
115 }
116
117 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
118 {
119         struct dw_desc *desc, *_desc;
120         struct dw_desc *ret = NULL;
121         unsigned int i = 0;
122         unsigned long flags;
123
124         spin_lock_irqsave(&dwc->lock, flags);
125         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
126                 i++;
127                 if (async_tx_test_ack(&desc->txd)) {
128                         list_del(&desc->desc_node);
129                         ret = desc;
130                         break;
131                 }
132                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
133         }
134         spin_unlock_irqrestore(&dwc->lock, flags);
135
136         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
137
138         return ret;
139 }
140
141 /*
142  * Move a descriptor, including any children, to the free list.
143  * `desc' must not be on any lists.
144  */
145 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
146 {
147         unsigned long flags;
148
149         if (desc) {
150                 struct dw_desc *child;
151
152                 spin_lock_irqsave(&dwc->lock, flags);
153                 list_for_each_entry(child, &desc->tx_list, desc_node)
154                         dev_vdbg(chan2dev(&dwc->chan),
155                                         "moving child desc %p to freelist\n",
156                                         child);
157                 list_splice_init(&desc->tx_list, &dwc->free_list);
158                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
159                 list_add(&desc->desc_node, &dwc->free_list);
160                 spin_unlock_irqrestore(&dwc->lock, flags);
161         }
162 }
163
164 static void dwc_initialize(struct dw_dma_chan *dwc)
165 {
166         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
167         struct dw_dma_slave *dws = dwc->chan.private;
168         u32 cfghi = DWC_CFGH_FIFO_MODE;
169         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
170
171         if (dwc->initialized == true)
172                 return;
173
174         if (dws) {
175                 /*
176                  * We need controller-specific data to set up slave
177                  * transfers.
178                  */
179                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
180
181                 cfghi = dws->cfg_hi;
182                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
183         } else {
184                 if (dwc->direction == DMA_MEM_TO_DEV)
185                         cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
186                 else if (dwc->direction == DMA_DEV_TO_MEM)
187                         cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
188         }
189
190         channel_writel(dwc, CFG_LO, cfglo);
191         channel_writel(dwc, CFG_HI, cfghi);
192
193         /* Enable interrupts */
194         channel_set_bit(dw, MASK.XFER, dwc->mask);
195         channel_set_bit(dw, MASK.ERROR, dwc->mask);
196
197         dwc->initialized = true;
198 }
199
200 /*----------------------------------------------------------------------*/
201
202 static inline unsigned int dwc_fast_fls(unsigned long long v)
203 {
204         /*
205          * We can be a lot more clever here, but this should take care
206          * of the most common optimization.
207          */
208         if (!(v & 7))
209                 return 3;
210         else if (!(v & 3))
211                 return 2;
212         else if (!(v & 1))
213                 return 1;
214         return 0;
215 }
216
217 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
218 {
219         dev_err(chan2dev(&dwc->chan),
220                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
221                 channel_readl(dwc, SAR),
222                 channel_readl(dwc, DAR),
223                 channel_readl(dwc, LLP),
224                 channel_readl(dwc, CTL_HI),
225                 channel_readl(dwc, CTL_LO));
226 }
227
228 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
229 {
230         channel_clear_bit(dw, CH_EN, dwc->mask);
231         while (dma_readl(dw, CH_EN) & dwc->mask)
232                 cpu_relax();
233 }
234
235 /*----------------------------------------------------------------------*/
236
237 /* Perform single block transfer */
238 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
239                                        struct dw_desc *desc)
240 {
241         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
242         u32             ctllo;
243
244         /* Software emulation of LLP mode relies on interrupts to continue
245          * multi block transfer. */
246         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
247
248         channel_writel(dwc, SAR, desc->lli.sar);
249         channel_writel(dwc, DAR, desc->lli.dar);
250         channel_writel(dwc, CTL_LO, ctllo);
251         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
252         channel_set_bit(dw, CH_EN, dwc->mask);
253
254         /* Move pointer to next descriptor */
255         dwc->tx_node_active = dwc->tx_node_active->next;
256 }
257
258 /* Called with dwc->lock held and bh disabled */
259 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
260 {
261         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
262         unsigned long   was_soft_llp;
263
264         /* ASSERT:  channel is idle */
265         if (dma_readl(dw, CH_EN) & dwc->mask) {
266                 dev_err(chan2dev(&dwc->chan),
267                         "BUG: Attempted to start non-idle channel\n");
268                 dwc_dump_chan_regs(dwc);
269
270                 /* The tasklet will hopefully advance the queue... */
271                 return;
272         }
273
274         if (dwc->nollp) {
275                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
276                                                 &dwc->flags);
277                 if (was_soft_llp) {
278                         dev_err(chan2dev(&dwc->chan),
279                                 "BUG: Attempted to start new LLP transfer "
280                                 "inside ongoing one\n");
281                         return;
282                 }
283
284                 dwc_initialize(dwc);
285
286                 dwc->residue = first->total_len;
287                 dwc->tx_node_active = &first->tx_list;
288
289                 /* Submit first block */
290                 dwc_do_single_block(dwc, first);
291
292                 return;
293         }
294
295         dwc_initialize(dwc);
296
297         channel_writel(dwc, LLP, first->txd.phys);
298         channel_writel(dwc, CTL_LO,
299                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
300         channel_writel(dwc, CTL_HI, 0);
301         channel_set_bit(dw, CH_EN, dwc->mask);
302 }
303
304 /*----------------------------------------------------------------------*/
305
306 static void
307 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
308                 bool callback_required)
309 {
310         dma_async_tx_callback           callback = NULL;
311         void                            *param = NULL;
312         struct dma_async_tx_descriptor  *txd = &desc->txd;
313         struct dw_desc                  *child;
314         unsigned long                   flags;
315
316         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
317
318         spin_lock_irqsave(&dwc->lock, flags);
319         dma_cookie_complete(txd);
320         if (callback_required) {
321                 callback = txd->callback;
322                 param = txd->callback_param;
323         }
324
325         /* async_tx_ack */
326         list_for_each_entry(child, &desc->tx_list, desc_node)
327                 async_tx_ack(&child->txd);
328         async_tx_ack(&desc->txd);
329
330         list_splice_init(&desc->tx_list, &dwc->free_list);
331         list_move(&desc->desc_node, &dwc->free_list);
332
333         if (!is_slave_direction(dwc->direction)) {
334                 struct device *parent = chan2parent(&dwc->chan);
335                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
336                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
337                                 dma_unmap_single(parent, desc->lli.dar,
338                                         desc->total_len, DMA_FROM_DEVICE);
339                         else
340                                 dma_unmap_page(parent, desc->lli.dar,
341                                         desc->total_len, DMA_FROM_DEVICE);
342                 }
343                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
344                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
345                                 dma_unmap_single(parent, desc->lli.sar,
346                                         desc->total_len, DMA_TO_DEVICE);
347                         else
348                                 dma_unmap_page(parent, desc->lli.sar,
349                                         desc->total_len, DMA_TO_DEVICE);
350                 }
351         }
352
353         spin_unlock_irqrestore(&dwc->lock, flags);
354
355         if (callback)
356                 callback(param);
357 }
358
359 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
360 {
361         struct dw_desc *desc, *_desc;
362         LIST_HEAD(list);
363         unsigned long flags;
364
365         spin_lock_irqsave(&dwc->lock, flags);
366         if (dma_readl(dw, CH_EN) & dwc->mask) {
367                 dev_err(chan2dev(&dwc->chan),
368                         "BUG: XFER bit set, but channel not idle!\n");
369
370                 /* Try to continue after resetting the channel... */
371                 dwc_chan_disable(dw, dwc);
372         }
373
374         /*
375          * Submit queued descriptors ASAP, i.e. before we go through
376          * the completed ones.
377          */
378         list_splice_init(&dwc->active_list, &list);
379         if (!list_empty(&dwc->queue)) {
380                 list_move(dwc->queue.next, &dwc->active_list);
381                 dwc_dostart(dwc, dwc_first_active(dwc));
382         }
383
384         spin_unlock_irqrestore(&dwc->lock, flags);
385
386         list_for_each_entry_safe(desc, _desc, &list, desc_node)
387                 dwc_descriptor_complete(dwc, desc, true);
388 }
389
390 /* Returns how many bytes were already received from source */
391 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
392 {
393         u32 ctlhi = channel_readl(dwc, CTL_HI);
394         u32 ctllo = channel_readl(dwc, CTL_LO);
395
396         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
397 }
398
399 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
400 {
401         dma_addr_t llp;
402         struct dw_desc *desc, *_desc;
403         struct dw_desc *child;
404         u32 status_xfer;
405         unsigned long flags;
406
407         spin_lock_irqsave(&dwc->lock, flags);
408         llp = channel_readl(dwc, LLP);
409         status_xfer = dma_readl(dw, RAW.XFER);
410
411         if (status_xfer & dwc->mask) {
412                 /* Everything we've submitted is done */
413                 dma_writel(dw, CLEAR.XFER, dwc->mask);
414
415                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
416                         struct list_head *head, *active = dwc->tx_node_active;
417
418                         /*
419                          * We are inside first active descriptor.
420                          * Otherwise something is really wrong.
421                          */
422                         desc = dwc_first_active(dwc);
423
424                         head = &desc->tx_list;
425                         if (active != head) {
426                                 /* Update desc to reflect last sent one */
427                                 if (active != head->next)
428                                         desc = to_dw_desc(active->prev);
429
430                                 dwc->residue -= desc->len;
431
432                                 child = to_dw_desc(active);
433
434                                 /* Submit next block */
435                                 dwc_do_single_block(dwc, child);
436
437                                 spin_unlock_irqrestore(&dwc->lock, flags);
438                                 return;
439                         }
440
441                         /* We are done here */
442                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
443                 }
444
445                 dwc->residue = 0;
446
447                 spin_unlock_irqrestore(&dwc->lock, flags);
448
449                 dwc_complete_all(dw, dwc);
450                 return;
451         }
452
453         if (list_empty(&dwc->active_list)) {
454                 dwc->residue = 0;
455                 spin_unlock_irqrestore(&dwc->lock, flags);
456                 return;
457         }
458
459         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
460                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
461                 spin_unlock_irqrestore(&dwc->lock, flags);
462                 return;
463         }
464
465         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
466                         (unsigned long long)llp);
467
468         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
469                 /* initial residue value */
470                 dwc->residue = desc->total_len;
471
472                 /* check first descriptors addr */
473                 if (desc->txd.phys == llp) {
474                         spin_unlock_irqrestore(&dwc->lock, flags);
475                         return;
476                 }
477
478                 /* check first descriptors llp */
479                 if (desc->lli.llp == llp) {
480                         /* This one is currently in progress */
481                         dwc->residue -= dwc_get_sent(dwc);
482                         spin_unlock_irqrestore(&dwc->lock, flags);
483                         return;
484                 }
485
486                 dwc->residue -= desc->len;
487                 list_for_each_entry(child, &desc->tx_list, desc_node) {
488                         if (child->lli.llp == llp) {
489                                 /* Currently in progress */
490                                 dwc->residue -= dwc_get_sent(dwc);
491                                 spin_unlock_irqrestore(&dwc->lock, flags);
492                                 return;
493                         }
494                         dwc->residue -= child->len;
495                 }
496
497                 /*
498                  * No descriptors so far seem to be in progress, i.e.
499                  * this one must be done.
500                  */
501                 spin_unlock_irqrestore(&dwc->lock, flags);
502                 dwc_descriptor_complete(dwc, desc, true);
503                 spin_lock_irqsave(&dwc->lock, flags);
504         }
505
506         dev_err(chan2dev(&dwc->chan),
507                 "BUG: All descriptors done, but channel not idle!\n");
508
509         /* Try to continue after resetting the channel... */
510         dwc_chan_disable(dw, dwc);
511
512         if (!list_empty(&dwc->queue)) {
513                 list_move(dwc->queue.next, &dwc->active_list);
514                 dwc_dostart(dwc, dwc_first_active(dwc));
515         }
516         spin_unlock_irqrestore(&dwc->lock, flags);
517 }
518
519 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
520 {
521         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
522                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
523 }
524
525 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
526 {
527         struct dw_desc *bad_desc;
528         struct dw_desc *child;
529         unsigned long flags;
530
531         dwc_scan_descriptors(dw, dwc);
532
533         spin_lock_irqsave(&dwc->lock, flags);
534
535         /*
536          * The descriptor currently at the head of the active list is
537          * borked. Since we don't have any way to report errors, we'll
538          * just have to scream loudly and try to carry on.
539          */
540         bad_desc = dwc_first_active(dwc);
541         list_del_init(&bad_desc->desc_node);
542         list_move(dwc->queue.next, dwc->active_list.prev);
543
544         /* Clear the error flag and try to restart the controller */
545         dma_writel(dw, CLEAR.ERROR, dwc->mask);
546         if (!list_empty(&dwc->active_list))
547                 dwc_dostart(dwc, dwc_first_active(dwc));
548
549         /*
550          * WARN may seem harsh, but since this only happens
551          * when someone submits a bad physical address in a
552          * descriptor, we should consider ourselves lucky that the
553          * controller flagged an error instead of scribbling over
554          * random memory locations.
555          */
556         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
557                                        "  cookie: %d\n", bad_desc->txd.cookie);
558         dwc_dump_lli(dwc, &bad_desc->lli);
559         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
560                 dwc_dump_lli(dwc, &child->lli);
561
562         spin_unlock_irqrestore(&dwc->lock, flags);
563
564         /* Pretend the descriptor completed successfully */
565         dwc_descriptor_complete(dwc, bad_desc, true);
566 }
567
568 /* --------------------- Cyclic DMA API extensions -------------------- */
569
570 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
571 {
572         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
573         return channel_readl(dwc, SAR);
574 }
575 EXPORT_SYMBOL(dw_dma_get_src_addr);
576
577 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
578 {
579         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
580         return channel_readl(dwc, DAR);
581 }
582 EXPORT_SYMBOL(dw_dma_get_dst_addr);
583
584 /* called with dwc->lock held and all DMAC interrupts disabled */
585 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
586                 u32 status_err, u32 status_xfer)
587 {
588         unsigned long flags;
589
590         if (dwc->mask) {
591                 void (*callback)(void *param);
592                 void *callback_param;
593
594                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
595                                 channel_readl(dwc, LLP));
596
597                 callback = dwc->cdesc->period_callback;
598                 callback_param = dwc->cdesc->period_callback_param;
599
600                 if (callback)
601                         callback(callback_param);
602         }
603
604         /*
605          * Error and transfer complete are highly unlikely, and will most
606          * likely be due to a configuration error by the user.
607          */
608         if (unlikely(status_err & dwc->mask) ||
609                         unlikely(status_xfer & dwc->mask)) {
610                 int i;
611
612                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
613                                 "interrupt, stopping DMA transfer\n",
614                                 status_xfer ? "xfer" : "error");
615
616                 spin_lock_irqsave(&dwc->lock, flags);
617
618                 dwc_dump_chan_regs(dwc);
619
620                 dwc_chan_disable(dw, dwc);
621
622                 /* make sure DMA does not restart by loading a new list */
623                 channel_writel(dwc, LLP, 0);
624                 channel_writel(dwc, CTL_LO, 0);
625                 channel_writel(dwc, CTL_HI, 0);
626
627                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
628                 dma_writel(dw, CLEAR.XFER, dwc->mask);
629
630                 for (i = 0; i < dwc->cdesc->periods; i++)
631                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
632
633                 spin_unlock_irqrestore(&dwc->lock, flags);
634         }
635 }
636
637 /* ------------------------------------------------------------------------- */
638
639 static void dw_dma_tasklet(unsigned long data)
640 {
641         struct dw_dma *dw = (struct dw_dma *)data;
642         struct dw_dma_chan *dwc;
643         u32 status_xfer;
644         u32 status_err;
645         int i;
646
647         status_xfer = dma_readl(dw, RAW.XFER);
648         status_err = dma_readl(dw, RAW.ERROR);
649
650         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
651
652         for (i = 0; i < dw->dma.chancnt; i++) {
653                 dwc = &dw->chan[i];
654                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
655                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
656                 else if (status_err & (1 << i))
657                         dwc_handle_error(dw, dwc);
658                 else if (status_xfer & (1 << i))
659                         dwc_scan_descriptors(dw, dwc);
660         }
661
662         /*
663          * Re-enable interrupts.
664          */
665         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
666         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
667 }
668
669 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
670 {
671         struct dw_dma *dw = dev_id;
672         u32 status;
673
674         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
675                         dma_readl(dw, STATUS_INT));
676
677         /*
678          * Just disable the interrupts. We'll turn them back on in the
679          * softirq handler.
680          */
681         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
682         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
683
684         status = dma_readl(dw, STATUS_INT);
685         if (status) {
686                 dev_err(dw->dma.dev,
687                         "BUG: Unexpected interrupts pending: 0x%x\n",
688                         status);
689
690                 /* Try to recover */
691                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
692                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
693                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
694                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
695         }
696
697         tasklet_schedule(&dw->tasklet);
698
699         return IRQ_HANDLED;
700 }
701
702 /*----------------------------------------------------------------------*/
703
704 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
705 {
706         struct dw_desc          *desc = txd_to_dw_desc(tx);
707         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
708         dma_cookie_t            cookie;
709         unsigned long           flags;
710
711         spin_lock_irqsave(&dwc->lock, flags);
712         cookie = dma_cookie_assign(tx);
713
714         /*
715          * REVISIT: We should attempt to chain as many descriptors as
716          * possible, perhaps even appending to those already submitted
717          * for DMA. But this is hard to do in a race-free manner.
718          */
719         if (list_empty(&dwc->active_list)) {
720                 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
721                                 desc->txd.cookie);
722                 list_add_tail(&desc->desc_node, &dwc->active_list);
723                 dwc_dostart(dwc, dwc_first_active(dwc));
724         } else {
725                 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
726                                 desc->txd.cookie);
727
728                 list_add_tail(&desc->desc_node, &dwc->queue);
729         }
730
731         spin_unlock_irqrestore(&dwc->lock, flags);
732
733         return cookie;
734 }
735
736 static struct dma_async_tx_descriptor *
737 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
738                 size_t len, unsigned long flags)
739 {
740         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
741         struct dw_desc          *desc;
742         struct dw_desc          *first;
743         struct dw_desc          *prev;
744         size_t                  xfer_count;
745         size_t                  offset;
746         unsigned int            src_width;
747         unsigned int            dst_width;
748         unsigned int            data_width;
749         u32                     ctllo;
750
751         dev_vdbg(chan2dev(chan),
752                         "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
753                         (unsigned long long)dest, (unsigned long long)src,
754                         len, flags);
755
756         if (unlikely(!len)) {
757                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
758                 return NULL;
759         }
760
761         dwc->direction = DMA_MEM_TO_MEM;
762
763         data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER),
764                            dwc_get_data_width(chan, DST_MASTER));
765
766         src_width = dst_width = min_t(unsigned int, data_width,
767                                       dwc_fast_fls(src | dest | len));
768
769         ctllo = DWC_DEFAULT_CTLLO(chan)
770                         | DWC_CTLL_DST_WIDTH(dst_width)
771                         | DWC_CTLL_SRC_WIDTH(src_width)
772                         | DWC_CTLL_DST_INC
773                         | DWC_CTLL_SRC_INC
774                         | DWC_CTLL_FC_M2M;
775         prev = first = NULL;
776
777         for (offset = 0; offset < len; offset += xfer_count << src_width) {
778                 xfer_count = min_t(size_t, (len - offset) >> src_width,
779                                            dwc->block_size);
780
781                 desc = dwc_desc_get(dwc);
782                 if (!desc)
783                         goto err_desc_get;
784
785                 desc->lli.sar = src + offset;
786                 desc->lli.dar = dest + offset;
787                 desc->lli.ctllo = ctllo;
788                 desc->lli.ctlhi = xfer_count;
789                 desc->len = xfer_count << src_width;
790
791                 if (!first) {
792                         first = desc;
793                 } else {
794                         prev->lli.llp = desc->txd.phys;
795                         list_add_tail(&desc->desc_node,
796                                         &first->tx_list);
797                 }
798                 prev = desc;
799         }
800
801         if (flags & DMA_PREP_INTERRUPT)
802                 /* Trigger interrupt after last block */
803                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
804
805         prev->lli.llp = 0;
806         first->txd.flags = flags;
807         first->total_len = len;
808
809         return &first->txd;
810
811 err_desc_get:
812         dwc_desc_put(dwc, first);
813         return NULL;
814 }
815
816 static struct dma_async_tx_descriptor *
817 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
818                 unsigned int sg_len, enum dma_transfer_direction direction,
819                 unsigned long flags, void *context)
820 {
821         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
822         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
823         struct dw_desc          *prev;
824         struct dw_desc          *first;
825         u32                     ctllo;
826         dma_addr_t              reg;
827         unsigned int            reg_width;
828         unsigned int            mem_width;
829         unsigned int            data_width;
830         unsigned int            i;
831         struct scatterlist      *sg;
832         size_t                  total_len = 0;
833
834         dev_vdbg(chan2dev(chan), "%s\n", __func__);
835
836         if (unlikely(!is_slave_direction(direction) || !sg_len))
837                 return NULL;
838
839         dwc->direction = direction;
840
841         prev = first = NULL;
842
843         switch (direction) {
844         case DMA_MEM_TO_DEV:
845                 reg_width = __fls(sconfig->dst_addr_width);
846                 reg = sconfig->dst_addr;
847                 ctllo = (DWC_DEFAULT_CTLLO(chan)
848                                 | DWC_CTLL_DST_WIDTH(reg_width)
849                                 | DWC_CTLL_DST_FIX
850                                 | DWC_CTLL_SRC_INC);
851
852                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
853                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
854
855                 data_width = dwc_get_data_width(chan, SRC_MASTER);
856
857                 for_each_sg(sgl, sg, sg_len, i) {
858                         struct dw_desc  *desc;
859                         u32             len, dlen, mem;
860
861                         mem = sg_dma_address(sg);
862                         len = sg_dma_len(sg);
863
864                         mem_width = min_t(unsigned int,
865                                           data_width, dwc_fast_fls(mem | len));
866
867 slave_sg_todev_fill_desc:
868                         desc = dwc_desc_get(dwc);
869                         if (!desc) {
870                                 dev_err(chan2dev(chan),
871                                         "not enough descriptors available\n");
872                                 goto err_desc_get;
873                         }
874
875                         desc->lli.sar = mem;
876                         desc->lli.dar = reg;
877                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
878                         if ((len >> mem_width) > dwc->block_size) {
879                                 dlen = dwc->block_size << mem_width;
880                                 mem += dlen;
881                                 len -= dlen;
882                         } else {
883                                 dlen = len;
884                                 len = 0;
885                         }
886
887                         desc->lli.ctlhi = dlen >> mem_width;
888                         desc->len = dlen;
889
890                         if (!first) {
891                                 first = desc;
892                         } else {
893                                 prev->lli.llp = desc->txd.phys;
894                                 list_add_tail(&desc->desc_node,
895                                                 &first->tx_list);
896                         }
897                         prev = desc;
898                         total_len += dlen;
899
900                         if (len)
901                                 goto slave_sg_todev_fill_desc;
902                 }
903                 break;
904         case DMA_DEV_TO_MEM:
905                 reg_width = __fls(sconfig->src_addr_width);
906                 reg = sconfig->src_addr;
907                 ctllo = (DWC_DEFAULT_CTLLO(chan)
908                                 | DWC_CTLL_SRC_WIDTH(reg_width)
909                                 | DWC_CTLL_DST_INC
910                                 | DWC_CTLL_SRC_FIX);
911
912                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
913                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
914
915                 data_width = dwc_get_data_width(chan, DST_MASTER);
916
917                 for_each_sg(sgl, sg, sg_len, i) {
918                         struct dw_desc  *desc;
919                         u32             len, dlen, mem;
920
921                         mem = sg_dma_address(sg);
922                         len = sg_dma_len(sg);
923
924                         mem_width = min_t(unsigned int,
925                                           data_width, dwc_fast_fls(mem | len));
926
927 slave_sg_fromdev_fill_desc:
928                         desc = dwc_desc_get(dwc);
929                         if (!desc) {
930                                 dev_err(chan2dev(chan),
931                                                 "not enough descriptors available\n");
932                                 goto err_desc_get;
933                         }
934
935                         desc->lli.sar = reg;
936                         desc->lli.dar = mem;
937                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
938                         if ((len >> reg_width) > dwc->block_size) {
939                                 dlen = dwc->block_size << reg_width;
940                                 mem += dlen;
941                                 len -= dlen;
942                         } else {
943                                 dlen = len;
944                                 len = 0;
945                         }
946                         desc->lli.ctlhi = dlen >> reg_width;
947                         desc->len = dlen;
948
949                         if (!first) {
950                                 first = desc;
951                         } else {
952                                 prev->lli.llp = desc->txd.phys;
953                                 list_add_tail(&desc->desc_node,
954                                                 &first->tx_list);
955                         }
956                         prev = desc;
957                         total_len += dlen;
958
959                         if (len)
960                                 goto slave_sg_fromdev_fill_desc;
961                 }
962                 break;
963         default:
964                 return NULL;
965         }
966
967         if (flags & DMA_PREP_INTERRUPT)
968                 /* Trigger interrupt after last block */
969                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
970
971         prev->lli.llp = 0;
972         first->total_len = total_len;
973
974         return &first->txd;
975
976 err_desc_get:
977         dwc_desc_put(dwc, first);
978         return NULL;
979 }
980
981 /*
982  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
983  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
984  *
985  * NOTE: burst size 2 is not supported by controller.
986  *
987  * This can be done by finding least significant bit set: n & (n - 1)
988  */
989 static inline void convert_burst(u32 *maxburst)
990 {
991         if (*maxburst > 1)
992                 *maxburst = fls(*maxburst) - 2;
993         else
994                 *maxburst = 0;
995 }
996
997 static int
998 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
999 {
1000         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1001
1002         /* Check if chan will be configured for slave transfers */
1003         if (!is_slave_direction(sconfig->direction))
1004                 return -EINVAL;
1005
1006         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
1007         dwc->direction = sconfig->direction;
1008
1009         convert_burst(&dwc->dma_sconfig.src_maxburst);
1010         convert_burst(&dwc->dma_sconfig.dst_maxburst);
1011
1012         return 0;
1013 }
1014
1015 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
1016 {
1017         u32 cfglo = channel_readl(dwc, CFG_LO);
1018
1019         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1020         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
1021                 cpu_relax();
1022
1023         dwc->paused = true;
1024 }
1025
1026 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1027 {
1028         u32 cfglo = channel_readl(dwc, CFG_LO);
1029
1030         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1031
1032         dwc->paused = false;
1033 }
1034
1035 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1036                        unsigned long arg)
1037 {
1038         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1039         struct dw_dma           *dw = to_dw_dma(chan->device);
1040         struct dw_desc          *desc, *_desc;
1041         unsigned long           flags;
1042         LIST_HEAD(list);
1043
1044         if (cmd == DMA_PAUSE) {
1045                 spin_lock_irqsave(&dwc->lock, flags);
1046
1047                 dwc_chan_pause(dwc);
1048
1049                 spin_unlock_irqrestore(&dwc->lock, flags);
1050         } else if (cmd == DMA_RESUME) {
1051                 if (!dwc->paused)
1052                         return 0;
1053
1054                 spin_lock_irqsave(&dwc->lock, flags);
1055
1056                 dwc_chan_resume(dwc);
1057
1058                 spin_unlock_irqrestore(&dwc->lock, flags);
1059         } else if (cmd == DMA_TERMINATE_ALL) {
1060                 spin_lock_irqsave(&dwc->lock, flags);
1061
1062                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1063
1064                 dwc_chan_disable(dw, dwc);
1065
1066                 dwc_chan_resume(dwc);
1067
1068                 /* active_list entries will end up before queued entries */
1069                 list_splice_init(&dwc->queue, &list);
1070                 list_splice_init(&dwc->active_list, &list);
1071
1072                 spin_unlock_irqrestore(&dwc->lock, flags);
1073
1074                 /* Flush all pending and queued descriptors */
1075                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1076                         dwc_descriptor_complete(dwc, desc, false);
1077         } else if (cmd == DMA_SLAVE_CONFIG) {
1078                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1079         } else {
1080                 return -ENXIO;
1081         }
1082
1083         return 0;
1084 }
1085
1086 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1087 {
1088         unsigned long flags;
1089         u32 residue;
1090
1091         spin_lock_irqsave(&dwc->lock, flags);
1092
1093         residue = dwc->residue;
1094         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1095                 residue -= dwc_get_sent(dwc);
1096
1097         spin_unlock_irqrestore(&dwc->lock, flags);
1098         return residue;
1099 }
1100
1101 static enum dma_status
1102 dwc_tx_status(struct dma_chan *chan,
1103               dma_cookie_t cookie,
1104               struct dma_tx_state *txstate)
1105 {
1106         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1107         enum dma_status         ret;
1108
1109         ret = dma_cookie_status(chan, cookie, txstate);
1110         if (ret != DMA_SUCCESS) {
1111                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1112
1113                 ret = dma_cookie_status(chan, cookie, txstate);
1114         }
1115
1116         if (ret != DMA_SUCCESS)
1117                 dma_set_residue(txstate, dwc_get_residue(dwc));
1118
1119         if (dwc->paused)
1120                 return DMA_PAUSED;
1121
1122         return ret;
1123 }
1124
1125 static void dwc_issue_pending(struct dma_chan *chan)
1126 {
1127         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1128
1129         if (!list_empty(&dwc->queue))
1130                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1131 }
1132
1133 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1134 {
1135         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1136         struct dw_dma           *dw = to_dw_dma(chan->device);
1137         struct dw_desc          *desc;
1138         int                     i;
1139         unsigned long           flags;
1140
1141         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1142
1143         /* ASSERT:  channel is idle */
1144         if (dma_readl(dw, CH_EN) & dwc->mask) {
1145                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1146                 return -EIO;
1147         }
1148
1149         dma_cookie_init(chan);
1150
1151         /*
1152          * NOTE: some controllers may have additional features that we
1153          * need to initialize here, like "scatter-gather" (which
1154          * doesn't mean what you think it means), and status writeback.
1155          */
1156
1157         spin_lock_irqsave(&dwc->lock, flags);
1158         i = dwc->descs_allocated;
1159         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1160                 dma_addr_t phys;
1161
1162                 spin_unlock_irqrestore(&dwc->lock, flags);
1163
1164                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1165                 if (!desc)
1166                         goto err_desc_alloc;
1167
1168                 memset(desc, 0, sizeof(struct dw_desc));
1169
1170                 INIT_LIST_HEAD(&desc->tx_list);
1171                 dma_async_tx_descriptor_init(&desc->txd, chan);
1172                 desc->txd.tx_submit = dwc_tx_submit;
1173                 desc->txd.flags = DMA_CTRL_ACK;
1174                 desc->txd.phys = phys;
1175
1176                 dwc_desc_put(dwc, desc);
1177
1178                 spin_lock_irqsave(&dwc->lock, flags);
1179                 i = ++dwc->descs_allocated;
1180         }
1181
1182         spin_unlock_irqrestore(&dwc->lock, flags);
1183
1184         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1185
1186         return i;
1187
1188 err_desc_alloc:
1189         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1190
1191         return i;
1192 }
1193
1194 static void dwc_free_chan_resources(struct dma_chan *chan)
1195 {
1196         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1197         struct dw_dma           *dw = to_dw_dma(chan->device);
1198         struct dw_desc          *desc, *_desc;
1199         unsigned long           flags;
1200         LIST_HEAD(list);
1201
1202         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1203                         dwc->descs_allocated);
1204
1205         /* ASSERT:  channel is idle */
1206         BUG_ON(!list_empty(&dwc->active_list));
1207         BUG_ON(!list_empty(&dwc->queue));
1208         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1209
1210         spin_lock_irqsave(&dwc->lock, flags);
1211         list_splice_init(&dwc->free_list, &list);
1212         dwc->descs_allocated = 0;
1213         dwc->initialized = false;
1214
1215         /* Disable interrupts */
1216         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1217         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1218
1219         spin_unlock_irqrestore(&dwc->lock, flags);
1220
1221         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1222                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1223                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1224         }
1225
1226         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1227 }
1228
1229 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1230 {
1231         struct dw_dma *dw = to_dw_dma(chan->device);
1232         static struct dw_dma *last_dw;
1233         static char *last_bus_id;
1234         int i = -1;
1235
1236         /*
1237          * dmaengine framework calls this routine for all channels of all dma
1238          * controller, until true is returned. If 'param' bus_id is not
1239          * registered with a dma controller (dw), then there is no need of
1240          * running below function for all channels of dw.
1241          *
1242          * This block of code does this by saving the parameters of last
1243          * failure. If dw and param are same, i.e. trying on same dw with
1244          * different channel, return false.
1245          */
1246         if ((last_dw == dw) && (last_bus_id == param))
1247                 return false;
1248         /*
1249          * Return true:
1250          * - If dw_dma's platform data is not filled with slave info, then all
1251          *   dma controllers are fine for transfer.
1252          * - Or if param is NULL
1253          */
1254         if (!dw->sd || !param)
1255                 return true;
1256
1257         while (++i < dw->sd_count) {
1258                 if (!strcmp(dw->sd[i].bus_id, param)) {
1259                         chan->private = &dw->sd[i];
1260                         last_dw = NULL;
1261                         last_bus_id = NULL;
1262
1263                         return true;
1264                 }
1265         }
1266
1267         last_dw = dw;
1268         last_bus_id = param;
1269         return false;
1270 }
1271 EXPORT_SYMBOL(dw_dma_generic_filter);
1272
1273 /* --------------------- Cyclic DMA API extensions -------------------- */
1274
1275 /**
1276  * dw_dma_cyclic_start - start the cyclic DMA transfer
1277  * @chan: the DMA channel to start
1278  *
1279  * Must be called with soft interrupts disabled. Returns zero on success or
1280  * -errno on failure.
1281  */
1282 int dw_dma_cyclic_start(struct dma_chan *chan)
1283 {
1284         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1285         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1286         unsigned long           flags;
1287
1288         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1289                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1290                 return -ENODEV;
1291         }
1292
1293         spin_lock_irqsave(&dwc->lock, flags);
1294
1295         /* assert channel is idle */
1296         if (dma_readl(dw, CH_EN) & dwc->mask) {
1297                 dev_err(chan2dev(&dwc->chan),
1298                         "BUG: Attempted to start non-idle channel\n");
1299                 dwc_dump_chan_regs(dwc);
1300                 spin_unlock_irqrestore(&dwc->lock, flags);
1301                 return -EBUSY;
1302         }
1303
1304         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1305         dma_writel(dw, CLEAR.XFER, dwc->mask);
1306
1307         /* setup DMAC channel registers */
1308         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1309         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1310         channel_writel(dwc, CTL_HI, 0);
1311
1312         channel_set_bit(dw, CH_EN, dwc->mask);
1313
1314         spin_unlock_irqrestore(&dwc->lock, flags);
1315
1316         return 0;
1317 }
1318 EXPORT_SYMBOL(dw_dma_cyclic_start);
1319
1320 /**
1321  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1322  * @chan: the DMA channel to stop
1323  *
1324  * Must be called with soft interrupts disabled.
1325  */
1326 void dw_dma_cyclic_stop(struct dma_chan *chan)
1327 {
1328         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1329         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1330         unsigned long           flags;
1331
1332         spin_lock_irqsave(&dwc->lock, flags);
1333
1334         dwc_chan_disable(dw, dwc);
1335
1336         spin_unlock_irqrestore(&dwc->lock, flags);
1337 }
1338 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1339
1340 /**
1341  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1342  * @chan: the DMA channel to prepare
1343  * @buf_addr: physical DMA address where the buffer starts
1344  * @buf_len: total number of bytes for the entire buffer
1345  * @period_len: number of bytes for each period
1346  * @direction: transfer direction, to or from device
1347  *
1348  * Must be called before trying to start the transfer. Returns a valid struct
1349  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1350  */
1351 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1352                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1353                 enum dma_transfer_direction direction)
1354 {
1355         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1356         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1357         struct dw_cyclic_desc           *cdesc;
1358         struct dw_cyclic_desc           *retval = NULL;
1359         struct dw_desc                  *desc;
1360         struct dw_desc                  *last = NULL;
1361         unsigned long                   was_cyclic;
1362         unsigned int                    reg_width;
1363         unsigned int                    periods;
1364         unsigned int                    i;
1365         unsigned long                   flags;
1366
1367         spin_lock_irqsave(&dwc->lock, flags);
1368         if (dwc->nollp) {
1369                 spin_unlock_irqrestore(&dwc->lock, flags);
1370                 dev_dbg(chan2dev(&dwc->chan),
1371                                 "channel doesn't support LLP transfers\n");
1372                 return ERR_PTR(-EINVAL);
1373         }
1374
1375         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1376                 spin_unlock_irqrestore(&dwc->lock, flags);
1377                 dev_dbg(chan2dev(&dwc->chan),
1378                                 "queue and/or active list are not empty\n");
1379                 return ERR_PTR(-EBUSY);
1380         }
1381
1382         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1383         spin_unlock_irqrestore(&dwc->lock, flags);
1384         if (was_cyclic) {
1385                 dev_dbg(chan2dev(&dwc->chan),
1386                                 "channel already prepared for cyclic DMA\n");
1387                 return ERR_PTR(-EBUSY);
1388         }
1389
1390         retval = ERR_PTR(-EINVAL);
1391
1392         if (unlikely(!is_slave_direction(direction)))
1393                 goto out_err;
1394
1395         dwc->direction = direction;
1396
1397         if (direction == DMA_MEM_TO_DEV)
1398                 reg_width = __ffs(sconfig->dst_addr_width);
1399         else
1400                 reg_width = __ffs(sconfig->src_addr_width);
1401
1402         periods = buf_len / period_len;
1403
1404         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1405         if (period_len > (dwc->block_size << reg_width))
1406                 goto out_err;
1407         if (unlikely(period_len & ((1 << reg_width) - 1)))
1408                 goto out_err;
1409         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1410                 goto out_err;
1411
1412         retval = ERR_PTR(-ENOMEM);
1413
1414         if (periods > NR_DESCS_PER_CHANNEL)
1415                 goto out_err;
1416
1417         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1418         if (!cdesc)
1419                 goto out_err;
1420
1421         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1422         if (!cdesc->desc)
1423                 goto out_err_alloc;
1424
1425         for (i = 0; i < periods; i++) {
1426                 desc = dwc_desc_get(dwc);
1427                 if (!desc)
1428                         goto out_err_desc_get;
1429
1430                 switch (direction) {
1431                 case DMA_MEM_TO_DEV:
1432                         desc->lli.dar = sconfig->dst_addr;
1433                         desc->lli.sar = buf_addr + (period_len * i);
1434                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1435                                         | DWC_CTLL_DST_WIDTH(reg_width)
1436                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1437                                         | DWC_CTLL_DST_FIX
1438                                         | DWC_CTLL_SRC_INC
1439                                         | DWC_CTLL_INT_EN);
1440
1441                         desc->lli.ctllo |= sconfig->device_fc ?
1442                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1443                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1444
1445                         break;
1446                 case DMA_DEV_TO_MEM:
1447                         desc->lli.dar = buf_addr + (period_len * i);
1448                         desc->lli.sar = sconfig->src_addr;
1449                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1450                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1451                                         | DWC_CTLL_DST_WIDTH(reg_width)
1452                                         | DWC_CTLL_DST_INC
1453                                         | DWC_CTLL_SRC_FIX
1454                                         | DWC_CTLL_INT_EN);
1455
1456                         desc->lli.ctllo |= sconfig->device_fc ?
1457                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1458                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1459
1460                         break;
1461                 default:
1462                         break;
1463                 }
1464
1465                 desc->lli.ctlhi = (period_len >> reg_width);
1466                 cdesc->desc[i] = desc;
1467
1468                 if (last)
1469                         last->lli.llp = desc->txd.phys;
1470
1471                 last = desc;
1472         }
1473
1474         /* lets make a cyclic list */
1475         last->lli.llp = cdesc->desc[0]->txd.phys;
1476
1477         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1478                         "period %zu periods %d\n", (unsigned long long)buf_addr,
1479                         buf_len, period_len, periods);
1480
1481         cdesc->periods = periods;
1482         dwc->cdesc = cdesc;
1483
1484         return cdesc;
1485
1486 out_err_desc_get:
1487         while (i--)
1488                 dwc_desc_put(dwc, cdesc->desc[i]);
1489 out_err_alloc:
1490         kfree(cdesc);
1491 out_err:
1492         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1493         return (struct dw_cyclic_desc *)retval;
1494 }
1495 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1496
1497 /**
1498  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1499  * @chan: the DMA channel to free
1500  */
1501 void dw_dma_cyclic_free(struct dma_chan *chan)
1502 {
1503         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1504         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1505         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1506         int                     i;
1507         unsigned long           flags;
1508
1509         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1510
1511         if (!cdesc)
1512                 return;
1513
1514         spin_lock_irqsave(&dwc->lock, flags);
1515
1516         dwc_chan_disable(dw, dwc);
1517
1518         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1519         dma_writel(dw, CLEAR.XFER, dwc->mask);
1520
1521         spin_unlock_irqrestore(&dwc->lock, flags);
1522
1523         for (i = 0; i < cdesc->periods; i++)
1524                 dwc_desc_put(dwc, cdesc->desc[i]);
1525
1526         kfree(cdesc->desc);
1527         kfree(cdesc);
1528
1529         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1530 }
1531 EXPORT_SYMBOL(dw_dma_cyclic_free);
1532
1533 /*----------------------------------------------------------------------*/
1534
1535 static void dw_dma_off(struct dw_dma *dw)
1536 {
1537         int i;
1538
1539         dma_writel(dw, CFG, 0);
1540
1541         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1542         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1543         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1544         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1545
1546         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1547                 cpu_relax();
1548
1549         for (i = 0; i < dw->dma.chancnt; i++)
1550                 dw->chan[i].initialized = false;
1551 }
1552
1553 #ifdef CONFIG_OF
1554 static struct dw_dma_platform_data *
1555 dw_dma_parse_dt(struct platform_device *pdev)
1556 {
1557         struct device_node *sn, *cn, *np = pdev->dev.of_node;
1558         struct dw_dma_platform_data *pdata;
1559         struct dw_dma_slave *sd;
1560         u32 tmp, arr[4];
1561
1562         if (!np) {
1563                 dev_err(&pdev->dev, "Missing DT data\n");
1564                 return NULL;
1565         }
1566
1567         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1568         if (!pdata)
1569                 return NULL;
1570
1571         if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1572                 return NULL;
1573
1574         if (of_property_read_bool(np, "is_private"))
1575                 pdata->is_private = true;
1576
1577         if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1578                 pdata->chan_allocation_order = (unsigned char)tmp;
1579
1580         if (!of_property_read_u32(np, "chan_priority", &tmp))
1581                 pdata->chan_priority = tmp;
1582
1583         if (!of_property_read_u32(np, "block_size", &tmp))
1584                 pdata->block_size = tmp;
1585
1586         if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1587                 if (tmp > 4)
1588                         return NULL;
1589
1590                 pdata->nr_masters = tmp;
1591         }
1592
1593         if (!of_property_read_u32_array(np, "data_width", arr,
1594                                 pdata->nr_masters))
1595                 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1596                         pdata->data_width[tmp] = arr[tmp];
1597
1598         /* parse slave data */
1599         sn = of_find_node_by_name(np, "slave_info");
1600         if (!sn)
1601                 return pdata;
1602
1603         /* calculate number of slaves */
1604         tmp = of_get_child_count(sn);
1605         if (!tmp)
1606                 return NULL;
1607
1608         sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1609         if (!sd)
1610                 return NULL;
1611
1612         pdata->sd = sd;
1613         pdata->sd_count = tmp;
1614
1615         for_each_child_of_node(sn, cn) {
1616                 sd->dma_dev = &pdev->dev;
1617                 of_property_read_string(cn, "bus_id", &sd->bus_id);
1618                 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1619                 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1620                 if (!of_property_read_u32(cn, "src_master", &tmp))
1621                         sd->src_master = tmp;
1622
1623                 if (!of_property_read_u32(cn, "dst_master", &tmp))
1624                         sd->dst_master = tmp;
1625                 sd++;
1626         }
1627
1628         return pdata;
1629 }
1630 #else
1631 static inline struct dw_dma_platform_data *
1632 dw_dma_parse_dt(struct platform_device *pdev)
1633 {
1634         return NULL;
1635 }
1636 #endif
1637
1638 static int dw_probe(struct platform_device *pdev)
1639 {
1640         struct dw_dma_platform_data *pdata;
1641         struct resource         *io;
1642         struct dw_dma           *dw;
1643         size_t                  size;
1644         void __iomem            *regs;
1645         bool                    autocfg;
1646         unsigned int            dw_params;
1647         unsigned int            nr_channels;
1648         unsigned int            max_blk_size = 0;
1649         int                     irq;
1650         int                     err;
1651         int                     i;
1652
1653         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1654         if (!io)
1655                 return -EINVAL;
1656
1657         irq = platform_get_irq(pdev, 0);
1658         if (irq < 0)
1659                 return irq;
1660
1661         regs = devm_ioremap_resource(&pdev->dev, io);
1662         if (IS_ERR(regs))
1663                 return PTR_ERR(regs);
1664
1665         /* Apply default dma_mask if needed */
1666         if (!pdev->dev.dma_mask) {
1667                 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
1668                 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1669         }
1670
1671         dw_params = dma_read_byaddr(regs, DW_PARAMS);
1672         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1673
1674         dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1675
1676         pdata = dev_get_platdata(&pdev->dev);
1677         if (!pdata)
1678                 pdata = dw_dma_parse_dt(pdev);
1679
1680         if (!pdata && autocfg) {
1681                 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1682                 if (!pdata)
1683                         return -ENOMEM;
1684
1685                 /* Fill platform data with the default values */
1686                 pdata->is_private = true;
1687                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1688                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1689         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1690                 return -EINVAL;
1691
1692         if (autocfg)
1693                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1694         else
1695                 nr_channels = pdata->nr_channels;
1696
1697         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1698         dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1699         if (!dw)
1700                 return -ENOMEM;
1701
1702         dw->clk = devm_clk_get(&pdev->dev, "hclk");
1703         if (IS_ERR(dw->clk))
1704                 return PTR_ERR(dw->clk);
1705         clk_prepare_enable(dw->clk);
1706
1707         dw->regs = regs;
1708         dw->sd = pdata->sd;
1709         dw->sd_count = pdata->sd_count;
1710
1711         /* get hardware configuration parameters */
1712         if (autocfg) {
1713                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1714
1715                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1716                 for (i = 0; i < dw->nr_masters; i++) {
1717                         dw->data_width[i] =
1718                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1719                 }
1720         } else {
1721                 dw->nr_masters = pdata->nr_masters;
1722                 memcpy(dw->data_width, pdata->data_width, 4);
1723         }
1724
1725         /* Calculate all channel mask before DMA setup */
1726         dw->all_chan_mask = (1 << nr_channels) - 1;
1727
1728         /* force dma off, just in case */
1729         dw_dma_off(dw);
1730
1731         /* disable BLOCK interrupts as well */
1732         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1733
1734         err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1735                                "dw_dmac", dw);
1736         if (err)
1737                 return err;
1738
1739         platform_set_drvdata(pdev, dw);
1740
1741         /* create a pool of consistent memory blocks for hardware descriptors */
1742         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev,
1743                                          sizeof(struct dw_desc), 4, 0);
1744         if (!dw->desc_pool) {
1745                 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1746                 return -ENOMEM;
1747         }
1748
1749         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1750
1751         INIT_LIST_HEAD(&dw->dma.channels);
1752         for (i = 0; i < nr_channels; i++) {
1753                 struct dw_dma_chan      *dwc = &dw->chan[i];
1754                 int                     r = nr_channels - i - 1;
1755
1756                 dwc->chan.device = &dw->dma;
1757                 dma_cookie_init(&dwc->chan);
1758                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1759                         list_add_tail(&dwc->chan.device_node,
1760                                         &dw->dma.channels);
1761                 else
1762                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1763
1764                 /* 7 is highest priority & 0 is lowest. */
1765                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1766                         dwc->priority = r;
1767                 else
1768                         dwc->priority = i;
1769
1770                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1771                 spin_lock_init(&dwc->lock);
1772                 dwc->mask = 1 << i;
1773
1774                 INIT_LIST_HEAD(&dwc->active_list);
1775                 INIT_LIST_HEAD(&dwc->queue);
1776                 INIT_LIST_HEAD(&dwc->free_list);
1777
1778                 channel_clear_bit(dw, CH_EN, dwc->mask);
1779
1780                 dwc->direction = DMA_TRANS_NONE;
1781
1782                 /* hardware configuration */
1783                 if (autocfg) {
1784                         unsigned int dwc_params;
1785
1786                         dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1787                                                      DWC_PARAMS);
1788
1789                         dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1790                                             dwc_params);
1791
1792                         /* Decode maximum block size for given channel. The
1793                          * stored 4 bit value represents blocks from 0x00 for 3
1794                          * up to 0x0a for 4095. */
1795                         dwc->block_size =
1796                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1797                         dwc->nollp =
1798                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1799                 } else {
1800                         dwc->block_size = pdata->block_size;
1801
1802                         /* Check if channel supports multi block transfer */
1803                         channel_writel(dwc, LLP, 0xfffffffc);
1804                         dwc->nollp =
1805                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1806                         channel_writel(dwc, LLP, 0);
1807                 }
1808         }
1809
1810         /* Clear all interrupts on all channels. */
1811         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1812         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1813         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1814         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1815         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1816
1817         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1818         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1819         if (pdata->is_private)
1820                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1821         dw->dma.dev = &pdev->dev;
1822         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1823         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1824
1825         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1826
1827         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1828         dw->dma.device_control = dwc_control;
1829
1830         dw->dma.device_tx_status = dwc_tx_status;
1831         dw->dma.device_issue_pending = dwc_issue_pending;
1832
1833         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1834
1835         dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1836                  nr_channels);
1837
1838         dma_async_device_register(&dw->dma);
1839
1840         return 0;
1841 }
1842
1843 static int dw_remove(struct platform_device *pdev)
1844 {
1845         struct dw_dma           *dw = platform_get_drvdata(pdev);
1846         struct dw_dma_chan      *dwc, *_dwc;
1847
1848         dw_dma_off(dw);
1849         dma_async_device_unregister(&dw->dma);
1850
1851         tasklet_kill(&dw->tasklet);
1852
1853         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1854                         chan.device_node) {
1855                 list_del(&dwc->chan.device_node);
1856                 channel_clear_bit(dw, CH_EN, dwc->mask);
1857         }
1858
1859         return 0;
1860 }
1861
1862 static void dw_shutdown(struct platform_device *pdev)
1863 {
1864         struct dw_dma   *dw = platform_get_drvdata(pdev);
1865
1866         dw_dma_off(dw);
1867         clk_disable_unprepare(dw->clk);
1868 }
1869
1870 static int dw_suspend_noirq(struct device *dev)
1871 {
1872         struct platform_device *pdev = to_platform_device(dev);
1873         struct dw_dma   *dw = platform_get_drvdata(pdev);
1874
1875         dw_dma_off(dw);
1876         clk_disable_unprepare(dw->clk);
1877
1878         return 0;
1879 }
1880
1881 static int dw_resume_noirq(struct device *dev)
1882 {
1883         struct platform_device *pdev = to_platform_device(dev);
1884         struct dw_dma   *dw = platform_get_drvdata(pdev);
1885
1886         clk_prepare_enable(dw->clk);
1887         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1888
1889         return 0;
1890 }
1891
1892 static const struct dev_pm_ops dw_dev_pm_ops = {
1893         .suspend_noirq = dw_suspend_noirq,
1894         .resume_noirq = dw_resume_noirq,
1895         .freeze_noirq = dw_suspend_noirq,
1896         .thaw_noirq = dw_resume_noirq,
1897         .restore_noirq = dw_resume_noirq,
1898         .poweroff_noirq = dw_suspend_noirq,
1899 };
1900
1901 #ifdef CONFIG_OF
1902 static const struct of_device_id dw_dma_id_table[] = {
1903         { .compatible = "snps,dma-spear1340" },
1904         {}
1905 };
1906 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1907 #endif
1908
1909 static const struct platform_device_id dw_dma_ids[] = {
1910         { "INTL9C60", 0 },
1911         { }
1912 };
1913
1914 static struct platform_driver dw_driver = {
1915         .probe          = dw_probe,
1916         .remove         = dw_remove,
1917         .shutdown       = dw_shutdown,
1918         .driver = {
1919                 .name   = "dw_dmac",
1920                 .pm     = &dw_dev_pm_ops,
1921                 .of_match_table = of_match_ptr(dw_dma_id_table),
1922         },
1923         .id_table       = dw_dma_ids,
1924 };
1925
1926 static int __init dw_init(void)
1927 {
1928         return platform_driver_register(&dw_driver);
1929 }
1930 subsys_initcall(dw_init);
1931
1932 static void __exit dw_exit(void)
1933 {
1934         platform_driver_unregister(&dw_driver);
1935 }
1936 module_exit(dw_exit);
1937
1938 MODULE_LICENSE("GPL v2");
1939 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1940 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1941 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");