Merge tag 'pm+acpi-fixes-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[~shefty/rdma-dev.git] / drivers / dma / dw_dmac.c
1 /*
2  * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
3  * AVR32 systems.)
4  *
5  * Copyright (C) 2007-2008 Atmel Corporation
6  * Copyright (C) 2010-2011 ST Microelectronics
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/of.h>
22 #include <linux/mm.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26
27 #include "dw_dmac_regs.h"
28 #include "dmaengine.h"
29
30 /*
31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33  * of which use ARM any more).  See the "Databook" from Synopsys for
34  * information beyond what licensees probably provide.
35  *
36  * The driver has currently been tested only with the Atmel AT32AP7000,
37  * which does not support descriptor writeback.
38  */
39
40 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
41 {
42         return slave ? slave->dst_master : 0;
43 }
44
45 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
46 {
47         return slave ? slave->src_master : 1;
48 }
49
50 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
51                 struct dw_dma_slave *__slave = (_chan->private);        \
52                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
53                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
54                 int _dms = dwc_get_dms(__slave);                \
55                 int _sms = dwc_get_sms(__slave);                \
56                 u8 _smsize = __slave ? _sconfig->src_maxburst : \
57                         DW_DMA_MSIZE_16;                        \
58                 u8 _dmsize = __slave ? _sconfig->dst_maxburst : \
59                         DW_DMA_MSIZE_16;                        \
60                                                                 \
61                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
62                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
63                  | DWC_CTLL_LLP_D_EN                            \
64                  | DWC_CTLL_LLP_S_EN                            \
65                  | DWC_CTLL_DMS(_dms)                           \
66                  | DWC_CTLL_SMS(_sms));                         \
67         })
68
69 /*
70  * Number of descriptors to allocate for each channel. This should be
71  * made configurable somehow; preferably, the clients (at least the
72  * ones using slave transfers) should be able to give us a hint.
73  */
74 #define NR_DESCS_PER_CHANNEL    64
75
76 /*----------------------------------------------------------------------*/
77
78 /*
79  * Because we're not relying on writeback from the controller (it may not
80  * even be configured into the core!) we don't need to use dma_pool.  These
81  * descriptors -- and associated data -- are cacheable.  We do need to make
82  * sure their dcache entries are written back before handing them off to
83  * the controller, though.
84  */
85
86 static struct device *chan2dev(struct dma_chan *chan)
87 {
88         return &chan->dev->device;
89 }
90 static struct device *chan2parent(struct dma_chan *chan)
91 {
92         return chan->dev->device.parent;
93 }
94
95 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
96 {
97         return list_entry(dwc->active_list.next, struct dw_desc, desc_node);
98 }
99
100 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
101 {
102         struct dw_desc *desc, *_desc;
103         struct dw_desc *ret = NULL;
104         unsigned int i = 0;
105         unsigned long flags;
106
107         spin_lock_irqsave(&dwc->lock, flags);
108         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
109                 i++;
110                 if (async_tx_test_ack(&desc->txd)) {
111                         list_del(&desc->desc_node);
112                         ret = desc;
113                         break;
114                 }
115                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
116         }
117         spin_unlock_irqrestore(&dwc->lock, flags);
118
119         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
120
121         return ret;
122 }
123
124 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
125 {
126         struct dw_desc  *child;
127
128         list_for_each_entry(child, &desc->tx_list, desc_node)
129                 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
130                                 child->txd.phys, sizeof(child->lli),
131                                 DMA_TO_DEVICE);
132         dma_sync_single_for_cpu(chan2parent(&dwc->chan),
133                         desc->txd.phys, sizeof(desc->lli),
134                         DMA_TO_DEVICE);
135 }
136
137 /*
138  * Move a descriptor, including any children, to the free list.
139  * `desc' must not be on any lists.
140  */
141 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
142 {
143         unsigned long flags;
144
145         if (desc) {
146                 struct dw_desc *child;
147
148                 dwc_sync_desc_for_cpu(dwc, desc);
149
150                 spin_lock_irqsave(&dwc->lock, flags);
151                 list_for_each_entry(child, &desc->tx_list, desc_node)
152                         dev_vdbg(chan2dev(&dwc->chan),
153                                         "moving child desc %p to freelist\n",
154                                         child);
155                 list_splice_init(&desc->tx_list, &dwc->free_list);
156                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
157                 list_add(&desc->desc_node, &dwc->free_list);
158                 spin_unlock_irqrestore(&dwc->lock, flags);
159         }
160 }
161
162 static void dwc_initialize(struct dw_dma_chan *dwc)
163 {
164         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
165         struct dw_dma_slave *dws = dwc->chan.private;
166         u32 cfghi = DWC_CFGH_FIFO_MODE;
167         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
168
169         if (dwc->initialized == true)
170                 return;
171
172         if (dws) {
173                 /*
174                  * We need controller-specific data to set up slave
175                  * transfers.
176                  */
177                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
178
179                 cfghi = dws->cfg_hi;
180                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
181         } else {
182                 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
183                         cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
184                 else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
185                         cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
186         }
187
188         channel_writel(dwc, CFG_LO, cfglo);
189         channel_writel(dwc, CFG_HI, cfghi);
190
191         /* Enable interrupts */
192         channel_set_bit(dw, MASK.XFER, dwc->mask);
193         channel_set_bit(dw, MASK.ERROR, dwc->mask);
194
195         dwc->initialized = true;
196 }
197
198 /*----------------------------------------------------------------------*/
199
200 static inline unsigned int dwc_fast_fls(unsigned long long v)
201 {
202         /*
203          * We can be a lot more clever here, but this should take care
204          * of the most common optimization.
205          */
206         if (!(v & 7))
207                 return 3;
208         else if (!(v & 3))
209                 return 2;
210         else if (!(v & 1))
211                 return 1;
212         return 0;
213 }
214
215 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
216 {
217         dev_err(chan2dev(&dwc->chan),
218                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
219                 channel_readl(dwc, SAR),
220                 channel_readl(dwc, DAR),
221                 channel_readl(dwc, LLP),
222                 channel_readl(dwc, CTL_HI),
223                 channel_readl(dwc, CTL_LO));
224 }
225
226
227 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
228 {
229         channel_clear_bit(dw, CH_EN, dwc->mask);
230         while (dma_readl(dw, CH_EN) & dwc->mask)
231                 cpu_relax();
232 }
233
234 /*----------------------------------------------------------------------*/
235
236 /* Perform single block transfer */
237 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
238                                        struct dw_desc *desc)
239 {
240         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
241         u32             ctllo;
242
243         /* Software emulation of LLP mode relies on interrupts to continue
244          * multi block transfer. */
245         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
246
247         channel_writel(dwc, SAR, desc->lli.sar);
248         channel_writel(dwc, DAR, desc->lli.dar);
249         channel_writel(dwc, CTL_LO, ctllo);
250         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
251         channel_set_bit(dw, CH_EN, dwc->mask);
252 }
253
254 /* Called with dwc->lock held and bh disabled */
255 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
256 {
257         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
258         unsigned long   was_soft_llp;
259
260         /* ASSERT:  channel is idle */
261         if (dma_readl(dw, CH_EN) & dwc->mask) {
262                 dev_err(chan2dev(&dwc->chan),
263                         "BUG: Attempted to start non-idle channel\n");
264                 dwc_dump_chan_regs(dwc);
265
266                 /* The tasklet will hopefully advance the queue... */
267                 return;
268         }
269
270         if (dwc->nollp) {
271                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
272                                                 &dwc->flags);
273                 if (was_soft_llp) {
274                         dev_err(chan2dev(&dwc->chan),
275                                 "BUG: Attempted to start new LLP transfer "
276                                 "inside ongoing one\n");
277                         return;
278                 }
279
280                 dwc_initialize(dwc);
281
282                 dwc->tx_list = &first->tx_list;
283                 dwc->tx_node_active = first->tx_list.next;
284
285                 dwc_do_single_block(dwc, first);
286
287                 return;
288         }
289
290         dwc_initialize(dwc);
291
292         channel_writel(dwc, LLP, first->txd.phys);
293         channel_writel(dwc, CTL_LO,
294                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
295         channel_writel(dwc, CTL_HI, 0);
296         channel_set_bit(dw, CH_EN, dwc->mask);
297 }
298
299 /*----------------------------------------------------------------------*/
300
301 static void
302 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
303                 bool callback_required)
304 {
305         dma_async_tx_callback           callback = NULL;
306         void                            *param = NULL;
307         struct dma_async_tx_descriptor  *txd = &desc->txd;
308         struct dw_desc                  *child;
309         unsigned long                   flags;
310
311         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
312
313         spin_lock_irqsave(&dwc->lock, flags);
314         dma_cookie_complete(txd);
315         if (callback_required) {
316                 callback = txd->callback;
317                 param = txd->callback_param;
318         }
319
320         dwc_sync_desc_for_cpu(dwc, desc);
321
322         /* async_tx_ack */
323         list_for_each_entry(child, &desc->tx_list, desc_node)
324                 async_tx_ack(&child->txd);
325         async_tx_ack(&desc->txd);
326
327         list_splice_init(&desc->tx_list, &dwc->free_list);
328         list_move(&desc->desc_node, &dwc->free_list);
329
330         if (!dwc->chan.private) {
331                 struct device *parent = chan2parent(&dwc->chan);
332                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
333                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
334                                 dma_unmap_single(parent, desc->lli.dar,
335                                                 desc->len, DMA_FROM_DEVICE);
336                         else
337                                 dma_unmap_page(parent, desc->lli.dar,
338                                                 desc->len, DMA_FROM_DEVICE);
339                 }
340                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
341                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
342                                 dma_unmap_single(parent, desc->lli.sar,
343                                                 desc->len, DMA_TO_DEVICE);
344                         else
345                                 dma_unmap_page(parent, desc->lli.sar,
346                                                 desc->len, DMA_TO_DEVICE);
347                 }
348         }
349
350         spin_unlock_irqrestore(&dwc->lock, flags);
351
352         if (callback_required && callback)
353                 callback(param);
354 }
355
356 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
357 {
358         struct dw_desc *desc, *_desc;
359         LIST_HEAD(list);
360         unsigned long flags;
361
362         spin_lock_irqsave(&dwc->lock, flags);
363         if (dma_readl(dw, CH_EN) & dwc->mask) {
364                 dev_err(chan2dev(&dwc->chan),
365                         "BUG: XFER bit set, but channel not idle!\n");
366
367                 /* Try to continue after resetting the channel... */
368                 dwc_chan_disable(dw, dwc);
369         }
370
371         /*
372          * Submit queued descriptors ASAP, i.e. before we go through
373          * the completed ones.
374          */
375         list_splice_init(&dwc->active_list, &list);
376         if (!list_empty(&dwc->queue)) {
377                 list_move(dwc->queue.next, &dwc->active_list);
378                 dwc_dostart(dwc, dwc_first_active(dwc));
379         }
380
381         spin_unlock_irqrestore(&dwc->lock, flags);
382
383         list_for_each_entry_safe(desc, _desc, &list, desc_node)
384                 dwc_descriptor_complete(dwc, desc, true);
385 }
386
387 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
388 {
389         dma_addr_t llp;
390         struct dw_desc *desc, *_desc;
391         struct dw_desc *child;
392         u32 status_xfer;
393         unsigned long flags;
394
395         spin_lock_irqsave(&dwc->lock, flags);
396         llp = channel_readl(dwc, LLP);
397         status_xfer = dma_readl(dw, RAW.XFER);
398
399         if (status_xfer & dwc->mask) {
400                 /* Everything we've submitted is done */
401                 dma_writel(dw, CLEAR.XFER, dwc->mask);
402                 spin_unlock_irqrestore(&dwc->lock, flags);
403
404                 dwc_complete_all(dw, dwc);
405                 return;
406         }
407
408         if (list_empty(&dwc->active_list)) {
409                 spin_unlock_irqrestore(&dwc->lock, flags);
410                 return;
411         }
412
413         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
414                         (unsigned long long)llp);
415
416         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
417                 /* check first descriptors addr */
418                 if (desc->txd.phys == llp) {
419                         spin_unlock_irqrestore(&dwc->lock, flags);
420                         return;
421                 }
422
423                 /* check first descriptors llp */
424                 if (desc->lli.llp == llp) {
425                         /* This one is currently in progress */
426                         spin_unlock_irqrestore(&dwc->lock, flags);
427                         return;
428                 }
429
430                 list_for_each_entry(child, &desc->tx_list, desc_node)
431                         if (child->lli.llp == llp) {
432                                 /* Currently in progress */
433                                 spin_unlock_irqrestore(&dwc->lock, flags);
434                                 return;
435                         }
436
437                 /*
438                  * No descriptors so far seem to be in progress, i.e.
439                  * this one must be done.
440                  */
441                 spin_unlock_irqrestore(&dwc->lock, flags);
442                 dwc_descriptor_complete(dwc, desc, true);
443                 spin_lock_irqsave(&dwc->lock, flags);
444         }
445
446         dev_err(chan2dev(&dwc->chan),
447                 "BUG: All descriptors done, but channel not idle!\n");
448
449         /* Try to continue after resetting the channel... */
450         dwc_chan_disable(dw, dwc);
451
452         if (!list_empty(&dwc->queue)) {
453                 list_move(dwc->queue.next, &dwc->active_list);
454                 dwc_dostart(dwc, dwc_first_active(dwc));
455         }
456         spin_unlock_irqrestore(&dwc->lock, flags);
457 }
458
459 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
460 {
461         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
462                         "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
463                         lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
464 }
465
466 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
467 {
468         struct dw_desc *bad_desc;
469         struct dw_desc *child;
470         unsigned long flags;
471
472         dwc_scan_descriptors(dw, dwc);
473
474         spin_lock_irqsave(&dwc->lock, flags);
475
476         /*
477          * The descriptor currently at the head of the active list is
478          * borked. Since we don't have any way to report errors, we'll
479          * just have to scream loudly and try to carry on.
480          */
481         bad_desc = dwc_first_active(dwc);
482         list_del_init(&bad_desc->desc_node);
483         list_move(dwc->queue.next, dwc->active_list.prev);
484
485         /* Clear the error flag and try to restart the controller */
486         dma_writel(dw, CLEAR.ERROR, dwc->mask);
487         if (!list_empty(&dwc->active_list))
488                 dwc_dostart(dwc, dwc_first_active(dwc));
489
490         /*
491          * KERN_CRITICAL may seem harsh, but since this only happens
492          * when someone submits a bad physical address in a
493          * descriptor, we should consider ourselves lucky that the
494          * controller flagged an error instead of scribbling over
495          * random memory locations.
496          */
497         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
498                         "Bad descriptor submitted for DMA!\n");
499         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
500                         "  cookie: %d\n", bad_desc->txd.cookie);
501         dwc_dump_lli(dwc, &bad_desc->lli);
502         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
503                 dwc_dump_lli(dwc, &child->lli);
504
505         spin_unlock_irqrestore(&dwc->lock, flags);
506
507         /* Pretend the descriptor completed successfully */
508         dwc_descriptor_complete(dwc, bad_desc, true);
509 }
510
511 /* --------------------- Cyclic DMA API extensions -------------------- */
512
513 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
514 {
515         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
516         return channel_readl(dwc, SAR);
517 }
518 EXPORT_SYMBOL(dw_dma_get_src_addr);
519
520 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
521 {
522         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
523         return channel_readl(dwc, DAR);
524 }
525 EXPORT_SYMBOL(dw_dma_get_dst_addr);
526
527 /* called with dwc->lock held and all DMAC interrupts disabled */
528 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
529                 u32 status_err, u32 status_xfer)
530 {
531         unsigned long flags;
532
533         if (dwc->mask) {
534                 void (*callback)(void *param);
535                 void *callback_param;
536
537                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
538                                 channel_readl(dwc, LLP));
539
540                 callback = dwc->cdesc->period_callback;
541                 callback_param = dwc->cdesc->period_callback_param;
542
543                 if (callback)
544                         callback(callback_param);
545         }
546
547         /*
548          * Error and transfer complete are highly unlikely, and will most
549          * likely be due to a configuration error by the user.
550          */
551         if (unlikely(status_err & dwc->mask) ||
552                         unlikely(status_xfer & dwc->mask)) {
553                 int i;
554
555                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
556                                 "interrupt, stopping DMA transfer\n",
557                                 status_xfer ? "xfer" : "error");
558
559                 spin_lock_irqsave(&dwc->lock, flags);
560
561                 dwc_dump_chan_regs(dwc);
562
563                 dwc_chan_disable(dw, dwc);
564
565                 /* make sure DMA does not restart by loading a new list */
566                 channel_writel(dwc, LLP, 0);
567                 channel_writel(dwc, CTL_LO, 0);
568                 channel_writel(dwc, CTL_HI, 0);
569
570                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
571                 dma_writel(dw, CLEAR.XFER, dwc->mask);
572
573                 for (i = 0; i < dwc->cdesc->periods; i++)
574                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
575
576                 spin_unlock_irqrestore(&dwc->lock, flags);
577         }
578 }
579
580 /* ------------------------------------------------------------------------- */
581
582 static void dw_dma_tasklet(unsigned long data)
583 {
584         struct dw_dma *dw = (struct dw_dma *)data;
585         struct dw_dma_chan *dwc;
586         u32 status_xfer;
587         u32 status_err;
588         int i;
589
590         status_xfer = dma_readl(dw, RAW.XFER);
591         status_err = dma_readl(dw, RAW.ERROR);
592
593         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
594
595         for (i = 0; i < dw->dma.chancnt; i++) {
596                 dwc = &dw->chan[i];
597                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
598                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
599                 else if (status_err & (1 << i))
600                         dwc_handle_error(dw, dwc);
601                 else if (status_xfer & (1 << i)) {
602                         unsigned long flags;
603
604                         spin_lock_irqsave(&dwc->lock, flags);
605                         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
606                                 if (dwc->tx_node_active != dwc->tx_list) {
607                                         struct dw_desc *desc =
608                                                 list_entry(dwc->tx_node_active,
609                                                            struct dw_desc,
610                                                            desc_node);
611
612                                         dma_writel(dw, CLEAR.XFER, dwc->mask);
613
614                                         /* move pointer to next descriptor */
615                                         dwc->tx_node_active =
616                                                 dwc->tx_node_active->next;
617
618                                         dwc_do_single_block(dwc, desc);
619
620                                         spin_unlock_irqrestore(&dwc->lock, flags);
621                                         continue;
622                                 } else {
623                                         /* we are done here */
624                                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
625                                 }
626                         }
627                         spin_unlock_irqrestore(&dwc->lock, flags);
628
629                         dwc_scan_descriptors(dw, dwc);
630                 }
631         }
632
633         /*
634          * Re-enable interrupts.
635          */
636         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
637         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
638 }
639
640 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
641 {
642         struct dw_dma *dw = dev_id;
643         u32 status;
644
645         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
646                         dma_readl(dw, STATUS_INT));
647
648         /*
649          * Just disable the interrupts. We'll turn them back on in the
650          * softirq handler.
651          */
652         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
653         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
654
655         status = dma_readl(dw, STATUS_INT);
656         if (status) {
657                 dev_err(dw->dma.dev,
658                         "BUG: Unexpected interrupts pending: 0x%x\n",
659                         status);
660
661                 /* Try to recover */
662                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
663                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
664                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
665                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
666         }
667
668         tasklet_schedule(&dw->tasklet);
669
670         return IRQ_HANDLED;
671 }
672
673 /*----------------------------------------------------------------------*/
674
675 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
676 {
677         struct dw_desc          *desc = txd_to_dw_desc(tx);
678         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
679         dma_cookie_t            cookie;
680         unsigned long           flags;
681
682         spin_lock_irqsave(&dwc->lock, flags);
683         cookie = dma_cookie_assign(tx);
684
685         /*
686          * REVISIT: We should attempt to chain as many descriptors as
687          * possible, perhaps even appending to those already submitted
688          * for DMA. But this is hard to do in a race-free manner.
689          */
690         if (list_empty(&dwc->active_list)) {
691                 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
692                                 desc->txd.cookie);
693                 list_add_tail(&desc->desc_node, &dwc->active_list);
694                 dwc_dostart(dwc, dwc_first_active(dwc));
695         } else {
696                 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
697                                 desc->txd.cookie);
698
699                 list_add_tail(&desc->desc_node, &dwc->queue);
700         }
701
702         spin_unlock_irqrestore(&dwc->lock, flags);
703
704         return cookie;
705 }
706
707 static struct dma_async_tx_descriptor *
708 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
709                 size_t len, unsigned long flags)
710 {
711         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
712         struct dw_dma_slave     *dws = chan->private;
713         struct dw_desc          *desc;
714         struct dw_desc          *first;
715         struct dw_desc          *prev;
716         size_t                  xfer_count;
717         size_t                  offset;
718         unsigned int            src_width;
719         unsigned int            dst_width;
720         unsigned int            data_width;
721         u32                     ctllo;
722
723         dev_vdbg(chan2dev(chan),
724                         "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
725                         (unsigned long long)dest, (unsigned long long)src,
726                         len, flags);
727
728         if (unlikely(!len)) {
729                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
730                 return NULL;
731         }
732
733         data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)],
734                                          dwc->dw->data_width[dwc_get_dms(dws)]);
735
736         src_width = dst_width = min_t(unsigned int, data_width,
737                                       dwc_fast_fls(src | dest | len));
738
739         ctllo = DWC_DEFAULT_CTLLO(chan)
740                         | DWC_CTLL_DST_WIDTH(dst_width)
741                         | DWC_CTLL_SRC_WIDTH(src_width)
742                         | DWC_CTLL_DST_INC
743                         | DWC_CTLL_SRC_INC
744                         | DWC_CTLL_FC_M2M;
745         prev = first = NULL;
746
747         for (offset = 0; offset < len; offset += xfer_count << src_width) {
748                 xfer_count = min_t(size_t, (len - offset) >> src_width,
749                                            dwc->block_size);
750
751                 desc = dwc_desc_get(dwc);
752                 if (!desc)
753                         goto err_desc_get;
754
755                 desc->lli.sar = src + offset;
756                 desc->lli.dar = dest + offset;
757                 desc->lli.ctllo = ctllo;
758                 desc->lli.ctlhi = xfer_count;
759
760                 if (!first) {
761                         first = desc;
762                 } else {
763                         prev->lli.llp = desc->txd.phys;
764                         dma_sync_single_for_device(chan2parent(chan),
765                                         prev->txd.phys, sizeof(prev->lli),
766                                         DMA_TO_DEVICE);
767                         list_add_tail(&desc->desc_node,
768                                         &first->tx_list);
769                 }
770                 prev = desc;
771         }
772
773
774         if (flags & DMA_PREP_INTERRUPT)
775                 /* Trigger interrupt after last block */
776                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
777
778         prev->lli.llp = 0;
779         dma_sync_single_for_device(chan2parent(chan),
780                         prev->txd.phys, sizeof(prev->lli),
781                         DMA_TO_DEVICE);
782
783         first->txd.flags = flags;
784         first->len = len;
785
786         return &first->txd;
787
788 err_desc_get:
789         dwc_desc_put(dwc, first);
790         return NULL;
791 }
792
793 static struct dma_async_tx_descriptor *
794 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
795                 unsigned int sg_len, enum dma_transfer_direction direction,
796                 unsigned long flags, void *context)
797 {
798         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
799         struct dw_dma_slave     *dws = chan->private;
800         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
801         struct dw_desc          *prev;
802         struct dw_desc          *first;
803         u32                     ctllo;
804         dma_addr_t              reg;
805         unsigned int            reg_width;
806         unsigned int            mem_width;
807         unsigned int            data_width;
808         unsigned int            i;
809         struct scatterlist      *sg;
810         size_t                  total_len = 0;
811
812         dev_vdbg(chan2dev(chan), "%s\n", __func__);
813
814         if (unlikely(!dws || !sg_len))
815                 return NULL;
816
817         prev = first = NULL;
818
819         switch (direction) {
820         case DMA_MEM_TO_DEV:
821                 reg_width = __fls(sconfig->dst_addr_width);
822                 reg = sconfig->dst_addr;
823                 ctllo = (DWC_DEFAULT_CTLLO(chan)
824                                 | DWC_CTLL_DST_WIDTH(reg_width)
825                                 | DWC_CTLL_DST_FIX
826                                 | DWC_CTLL_SRC_INC);
827
828                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
829                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
830
831                 data_width = dwc->dw->data_width[dwc_get_sms(dws)];
832
833                 for_each_sg(sgl, sg, sg_len, i) {
834                         struct dw_desc  *desc;
835                         u32             len, dlen, mem;
836
837                         mem = sg_dma_address(sg);
838                         len = sg_dma_len(sg);
839
840                         mem_width = min_t(unsigned int,
841                                           data_width, dwc_fast_fls(mem | len));
842
843 slave_sg_todev_fill_desc:
844                         desc = dwc_desc_get(dwc);
845                         if (!desc) {
846                                 dev_err(chan2dev(chan),
847                                         "not enough descriptors available\n");
848                                 goto err_desc_get;
849                         }
850
851                         desc->lli.sar = mem;
852                         desc->lli.dar = reg;
853                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
854                         if ((len >> mem_width) > dwc->block_size) {
855                                 dlen = dwc->block_size << mem_width;
856                                 mem += dlen;
857                                 len -= dlen;
858                         } else {
859                                 dlen = len;
860                                 len = 0;
861                         }
862
863                         desc->lli.ctlhi = dlen >> mem_width;
864
865                         if (!first) {
866                                 first = desc;
867                         } else {
868                                 prev->lli.llp = desc->txd.phys;
869                                 dma_sync_single_for_device(chan2parent(chan),
870                                                 prev->txd.phys,
871                                                 sizeof(prev->lli),
872                                                 DMA_TO_DEVICE);
873                                 list_add_tail(&desc->desc_node,
874                                                 &first->tx_list);
875                         }
876                         prev = desc;
877                         total_len += dlen;
878
879                         if (len)
880                                 goto slave_sg_todev_fill_desc;
881                 }
882                 break;
883         case DMA_DEV_TO_MEM:
884                 reg_width = __fls(sconfig->src_addr_width);
885                 reg = sconfig->src_addr;
886                 ctllo = (DWC_DEFAULT_CTLLO(chan)
887                                 | DWC_CTLL_SRC_WIDTH(reg_width)
888                                 | DWC_CTLL_DST_INC
889                                 | DWC_CTLL_SRC_FIX);
890
891                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
892                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
893
894                 data_width = dwc->dw->data_width[dwc_get_dms(dws)];
895
896                 for_each_sg(sgl, sg, sg_len, i) {
897                         struct dw_desc  *desc;
898                         u32             len, dlen, mem;
899
900                         mem = sg_dma_address(sg);
901                         len = sg_dma_len(sg);
902
903                         mem_width = min_t(unsigned int,
904                                           data_width, dwc_fast_fls(mem | len));
905
906 slave_sg_fromdev_fill_desc:
907                         desc = dwc_desc_get(dwc);
908                         if (!desc) {
909                                 dev_err(chan2dev(chan),
910                                                 "not enough descriptors available\n");
911                                 goto err_desc_get;
912                         }
913
914                         desc->lli.sar = reg;
915                         desc->lli.dar = mem;
916                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
917                         if ((len >> reg_width) > dwc->block_size) {
918                                 dlen = dwc->block_size << reg_width;
919                                 mem += dlen;
920                                 len -= dlen;
921                         } else {
922                                 dlen = len;
923                                 len = 0;
924                         }
925                         desc->lli.ctlhi = dlen >> reg_width;
926
927                         if (!first) {
928                                 first = desc;
929                         } else {
930                                 prev->lli.llp = desc->txd.phys;
931                                 dma_sync_single_for_device(chan2parent(chan),
932                                                 prev->txd.phys,
933                                                 sizeof(prev->lli),
934                                                 DMA_TO_DEVICE);
935                                 list_add_tail(&desc->desc_node,
936                                                 &first->tx_list);
937                         }
938                         prev = desc;
939                         total_len += dlen;
940
941                         if (len)
942                                 goto slave_sg_fromdev_fill_desc;
943                 }
944                 break;
945         default:
946                 return NULL;
947         }
948
949         if (flags & DMA_PREP_INTERRUPT)
950                 /* Trigger interrupt after last block */
951                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
952
953         prev->lli.llp = 0;
954         dma_sync_single_for_device(chan2parent(chan),
955                         prev->txd.phys, sizeof(prev->lli),
956                         DMA_TO_DEVICE);
957
958         first->len = total_len;
959
960         return &first->txd;
961
962 err_desc_get:
963         dwc_desc_put(dwc, first);
964         return NULL;
965 }
966
967 /*
968  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
969  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
970  *
971  * NOTE: burst size 2 is not supported by controller.
972  *
973  * This can be done by finding least significant bit set: n & (n - 1)
974  */
975 static inline void convert_burst(u32 *maxburst)
976 {
977         if (*maxburst > 1)
978                 *maxburst = fls(*maxburst) - 2;
979         else
980                 *maxburst = 0;
981 }
982
983 static int
984 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
985 {
986         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
987
988         /* Check if it is chan is configured for slave transfers */
989         if (!chan->private)
990                 return -EINVAL;
991
992         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
993
994         convert_burst(&dwc->dma_sconfig.src_maxburst);
995         convert_burst(&dwc->dma_sconfig.dst_maxburst);
996
997         return 0;
998 }
999
1000 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1001                        unsigned long arg)
1002 {
1003         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1004         struct dw_dma           *dw = to_dw_dma(chan->device);
1005         struct dw_desc          *desc, *_desc;
1006         unsigned long           flags;
1007         u32                     cfglo;
1008         LIST_HEAD(list);
1009
1010         if (cmd == DMA_PAUSE) {
1011                 spin_lock_irqsave(&dwc->lock, flags);
1012
1013                 cfglo = channel_readl(dwc, CFG_LO);
1014                 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1015                 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
1016                         cpu_relax();
1017
1018                 dwc->paused = true;
1019                 spin_unlock_irqrestore(&dwc->lock, flags);
1020         } else if (cmd == DMA_RESUME) {
1021                 if (!dwc->paused)
1022                         return 0;
1023
1024                 spin_lock_irqsave(&dwc->lock, flags);
1025
1026                 cfglo = channel_readl(dwc, CFG_LO);
1027                 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1028                 dwc->paused = false;
1029
1030                 spin_unlock_irqrestore(&dwc->lock, flags);
1031         } else if (cmd == DMA_TERMINATE_ALL) {
1032                 spin_lock_irqsave(&dwc->lock, flags);
1033
1034                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1035
1036                 dwc_chan_disable(dw, dwc);
1037
1038                 dwc->paused = false;
1039
1040                 /* active_list entries will end up before queued entries */
1041                 list_splice_init(&dwc->queue, &list);
1042                 list_splice_init(&dwc->active_list, &list);
1043
1044                 spin_unlock_irqrestore(&dwc->lock, flags);
1045
1046                 /* Flush all pending and queued descriptors */
1047                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1048                         dwc_descriptor_complete(dwc, desc, false);
1049         } else if (cmd == DMA_SLAVE_CONFIG) {
1050                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1051         } else {
1052                 return -ENXIO;
1053         }
1054
1055         return 0;
1056 }
1057
1058 static enum dma_status
1059 dwc_tx_status(struct dma_chan *chan,
1060               dma_cookie_t cookie,
1061               struct dma_tx_state *txstate)
1062 {
1063         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1064         enum dma_status         ret;
1065
1066         ret = dma_cookie_status(chan, cookie, txstate);
1067         if (ret != DMA_SUCCESS) {
1068                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1069
1070                 ret = dma_cookie_status(chan, cookie, txstate);
1071         }
1072
1073         if (ret != DMA_SUCCESS)
1074                 dma_set_residue(txstate, dwc_first_active(dwc)->len);
1075
1076         if (dwc->paused)
1077                 return DMA_PAUSED;
1078
1079         return ret;
1080 }
1081
1082 static void dwc_issue_pending(struct dma_chan *chan)
1083 {
1084         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1085
1086         if (!list_empty(&dwc->queue))
1087                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1088 }
1089
1090 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1091 {
1092         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1093         struct dw_dma           *dw = to_dw_dma(chan->device);
1094         struct dw_desc          *desc;
1095         int                     i;
1096         unsigned long           flags;
1097
1098         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1099
1100         /* ASSERT:  channel is idle */
1101         if (dma_readl(dw, CH_EN) & dwc->mask) {
1102                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1103                 return -EIO;
1104         }
1105
1106         dma_cookie_init(chan);
1107
1108         /*
1109          * NOTE: some controllers may have additional features that we
1110          * need to initialize here, like "scatter-gather" (which
1111          * doesn't mean what you think it means), and status writeback.
1112          */
1113
1114         spin_lock_irqsave(&dwc->lock, flags);
1115         i = dwc->descs_allocated;
1116         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1117                 spin_unlock_irqrestore(&dwc->lock, flags);
1118
1119                 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
1120                 if (!desc) {
1121                         dev_info(chan2dev(chan),
1122                                 "only allocated %d descriptors\n", i);
1123                         spin_lock_irqsave(&dwc->lock, flags);
1124                         break;
1125                 }
1126
1127                 INIT_LIST_HEAD(&desc->tx_list);
1128                 dma_async_tx_descriptor_init(&desc->txd, chan);
1129                 desc->txd.tx_submit = dwc_tx_submit;
1130                 desc->txd.flags = DMA_CTRL_ACK;
1131                 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
1132                                 sizeof(desc->lli), DMA_TO_DEVICE);
1133                 dwc_desc_put(dwc, desc);
1134
1135                 spin_lock_irqsave(&dwc->lock, flags);
1136                 i = ++dwc->descs_allocated;
1137         }
1138
1139         spin_unlock_irqrestore(&dwc->lock, flags);
1140
1141         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1142
1143         return i;
1144 }
1145
1146 static void dwc_free_chan_resources(struct dma_chan *chan)
1147 {
1148         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1149         struct dw_dma           *dw = to_dw_dma(chan->device);
1150         struct dw_desc          *desc, *_desc;
1151         unsigned long           flags;
1152         LIST_HEAD(list);
1153
1154         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1155                         dwc->descs_allocated);
1156
1157         /* ASSERT:  channel is idle */
1158         BUG_ON(!list_empty(&dwc->active_list));
1159         BUG_ON(!list_empty(&dwc->queue));
1160         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1161
1162         spin_lock_irqsave(&dwc->lock, flags);
1163         list_splice_init(&dwc->free_list, &list);
1164         dwc->descs_allocated = 0;
1165         dwc->initialized = false;
1166
1167         /* Disable interrupts */
1168         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1169         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1170
1171         spin_unlock_irqrestore(&dwc->lock, flags);
1172
1173         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1174                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1175                 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1176                                 sizeof(desc->lli), DMA_TO_DEVICE);
1177                 kfree(desc);
1178         }
1179
1180         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1181 }
1182
1183 /* --------------------- Cyclic DMA API extensions -------------------- */
1184
1185 /**
1186  * dw_dma_cyclic_start - start the cyclic DMA transfer
1187  * @chan: the DMA channel to start
1188  *
1189  * Must be called with soft interrupts disabled. Returns zero on success or
1190  * -errno on failure.
1191  */
1192 int dw_dma_cyclic_start(struct dma_chan *chan)
1193 {
1194         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1195         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1196         unsigned long           flags;
1197
1198         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1199                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1200                 return -ENODEV;
1201         }
1202
1203         spin_lock_irqsave(&dwc->lock, flags);
1204
1205         /* assert channel is idle */
1206         if (dma_readl(dw, CH_EN) & dwc->mask) {
1207                 dev_err(chan2dev(&dwc->chan),
1208                         "BUG: Attempted to start non-idle channel\n");
1209                 dwc_dump_chan_regs(dwc);
1210                 spin_unlock_irqrestore(&dwc->lock, flags);
1211                 return -EBUSY;
1212         }
1213
1214         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1215         dma_writel(dw, CLEAR.XFER, dwc->mask);
1216
1217         /* setup DMAC channel registers */
1218         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1219         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1220         channel_writel(dwc, CTL_HI, 0);
1221
1222         channel_set_bit(dw, CH_EN, dwc->mask);
1223
1224         spin_unlock_irqrestore(&dwc->lock, flags);
1225
1226         return 0;
1227 }
1228 EXPORT_SYMBOL(dw_dma_cyclic_start);
1229
1230 /**
1231  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1232  * @chan: the DMA channel to stop
1233  *
1234  * Must be called with soft interrupts disabled.
1235  */
1236 void dw_dma_cyclic_stop(struct dma_chan *chan)
1237 {
1238         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1239         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1240         unsigned long           flags;
1241
1242         spin_lock_irqsave(&dwc->lock, flags);
1243
1244         dwc_chan_disable(dw, dwc);
1245
1246         spin_unlock_irqrestore(&dwc->lock, flags);
1247 }
1248 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1249
1250 /**
1251  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1252  * @chan: the DMA channel to prepare
1253  * @buf_addr: physical DMA address where the buffer starts
1254  * @buf_len: total number of bytes for the entire buffer
1255  * @period_len: number of bytes for each period
1256  * @direction: transfer direction, to or from device
1257  *
1258  * Must be called before trying to start the transfer. Returns a valid struct
1259  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1260  */
1261 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1262                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1263                 enum dma_transfer_direction direction)
1264 {
1265         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1266         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1267         struct dw_cyclic_desc           *cdesc;
1268         struct dw_cyclic_desc           *retval = NULL;
1269         struct dw_desc                  *desc;
1270         struct dw_desc                  *last = NULL;
1271         unsigned long                   was_cyclic;
1272         unsigned int                    reg_width;
1273         unsigned int                    periods;
1274         unsigned int                    i;
1275         unsigned long                   flags;
1276
1277         spin_lock_irqsave(&dwc->lock, flags);
1278         if (dwc->nollp) {
1279                 spin_unlock_irqrestore(&dwc->lock, flags);
1280                 dev_dbg(chan2dev(&dwc->chan),
1281                                 "channel doesn't support LLP transfers\n");
1282                 return ERR_PTR(-EINVAL);
1283         }
1284
1285         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1286                 spin_unlock_irqrestore(&dwc->lock, flags);
1287                 dev_dbg(chan2dev(&dwc->chan),
1288                                 "queue and/or active list are not empty\n");
1289                 return ERR_PTR(-EBUSY);
1290         }
1291
1292         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1293         spin_unlock_irqrestore(&dwc->lock, flags);
1294         if (was_cyclic) {
1295                 dev_dbg(chan2dev(&dwc->chan),
1296                                 "channel already prepared for cyclic DMA\n");
1297                 return ERR_PTR(-EBUSY);
1298         }
1299
1300         retval = ERR_PTR(-EINVAL);
1301
1302         if (direction == DMA_MEM_TO_DEV)
1303                 reg_width = __ffs(sconfig->dst_addr_width);
1304         else
1305                 reg_width = __ffs(sconfig->src_addr_width);
1306
1307         periods = buf_len / period_len;
1308
1309         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1310         if (period_len > (dwc->block_size << reg_width))
1311                 goto out_err;
1312         if (unlikely(period_len & ((1 << reg_width) - 1)))
1313                 goto out_err;
1314         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1315                 goto out_err;
1316         if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1317                 goto out_err;
1318
1319         retval = ERR_PTR(-ENOMEM);
1320
1321         if (periods > NR_DESCS_PER_CHANNEL)
1322                 goto out_err;
1323
1324         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1325         if (!cdesc)
1326                 goto out_err;
1327
1328         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1329         if (!cdesc->desc)
1330                 goto out_err_alloc;
1331
1332         for (i = 0; i < periods; i++) {
1333                 desc = dwc_desc_get(dwc);
1334                 if (!desc)
1335                         goto out_err_desc_get;
1336
1337                 switch (direction) {
1338                 case DMA_MEM_TO_DEV:
1339                         desc->lli.dar = sconfig->dst_addr;
1340                         desc->lli.sar = buf_addr + (period_len * i);
1341                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1342                                         | DWC_CTLL_DST_WIDTH(reg_width)
1343                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1344                                         | DWC_CTLL_DST_FIX
1345                                         | DWC_CTLL_SRC_INC
1346                                         | DWC_CTLL_INT_EN);
1347
1348                         desc->lli.ctllo |= sconfig->device_fc ?
1349                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1350                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1351
1352                         break;
1353                 case DMA_DEV_TO_MEM:
1354                         desc->lli.dar = buf_addr + (period_len * i);
1355                         desc->lli.sar = sconfig->src_addr;
1356                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1357                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1358                                         | DWC_CTLL_DST_WIDTH(reg_width)
1359                                         | DWC_CTLL_DST_INC
1360                                         | DWC_CTLL_SRC_FIX
1361                                         | DWC_CTLL_INT_EN);
1362
1363                         desc->lli.ctllo |= sconfig->device_fc ?
1364                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1365                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1366
1367                         break;
1368                 default:
1369                         break;
1370                 }
1371
1372                 desc->lli.ctlhi = (period_len >> reg_width);
1373                 cdesc->desc[i] = desc;
1374
1375                 if (last) {
1376                         last->lli.llp = desc->txd.phys;
1377                         dma_sync_single_for_device(chan2parent(chan),
1378                                         last->txd.phys, sizeof(last->lli),
1379                                         DMA_TO_DEVICE);
1380                 }
1381
1382                 last = desc;
1383         }
1384
1385         /* lets make a cyclic list */
1386         last->lli.llp = cdesc->desc[0]->txd.phys;
1387         dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1388                         sizeof(last->lli), DMA_TO_DEVICE);
1389
1390         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1391                         "period %zu periods %d\n", (unsigned long long)buf_addr,
1392                         buf_len, period_len, periods);
1393
1394         cdesc->periods = periods;
1395         dwc->cdesc = cdesc;
1396
1397         return cdesc;
1398
1399 out_err_desc_get:
1400         while (i--)
1401                 dwc_desc_put(dwc, cdesc->desc[i]);
1402 out_err_alloc:
1403         kfree(cdesc);
1404 out_err:
1405         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1406         return (struct dw_cyclic_desc *)retval;
1407 }
1408 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1409
1410 /**
1411  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1412  * @chan: the DMA channel to free
1413  */
1414 void dw_dma_cyclic_free(struct dma_chan *chan)
1415 {
1416         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1417         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1418         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1419         int                     i;
1420         unsigned long           flags;
1421
1422         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1423
1424         if (!cdesc)
1425                 return;
1426
1427         spin_lock_irqsave(&dwc->lock, flags);
1428
1429         dwc_chan_disable(dw, dwc);
1430
1431         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1432         dma_writel(dw, CLEAR.XFER, dwc->mask);
1433
1434         spin_unlock_irqrestore(&dwc->lock, flags);
1435
1436         for (i = 0; i < cdesc->periods; i++)
1437                 dwc_desc_put(dwc, cdesc->desc[i]);
1438
1439         kfree(cdesc->desc);
1440         kfree(cdesc);
1441
1442         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1443 }
1444 EXPORT_SYMBOL(dw_dma_cyclic_free);
1445
1446 /*----------------------------------------------------------------------*/
1447
1448 static void dw_dma_off(struct dw_dma *dw)
1449 {
1450         int i;
1451
1452         dma_writel(dw, CFG, 0);
1453
1454         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1455         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1456         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1457         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1458
1459         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1460                 cpu_relax();
1461
1462         for (i = 0; i < dw->dma.chancnt; i++)
1463                 dw->chan[i].initialized = false;
1464 }
1465
1466 static int dw_probe(struct platform_device *pdev)
1467 {
1468         struct dw_dma_platform_data *pdata;
1469         struct resource         *io;
1470         struct dw_dma           *dw;
1471         size_t                  size;
1472         void __iomem            *regs;
1473         bool                    autocfg;
1474         unsigned int            dw_params;
1475         unsigned int            nr_channels;
1476         unsigned int            max_blk_size = 0;
1477         int                     irq;
1478         int                     err;
1479         int                     i;
1480
1481         pdata = dev_get_platdata(&pdev->dev);
1482         if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1483                 return -EINVAL;
1484
1485         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1486         if (!io)
1487                 return -EINVAL;
1488
1489         irq = platform_get_irq(pdev, 0);
1490         if (irq < 0)
1491                 return irq;
1492
1493         regs = devm_ioremap_resource(&pdev->dev, io);
1494         if (IS_ERR(regs))
1495                 return PTR_ERR(regs);
1496
1497         dw_params = dma_read_byaddr(regs, DW_PARAMS);
1498         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1499
1500         if (autocfg)
1501                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1502         else
1503                 nr_channels = pdata->nr_channels;
1504
1505         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1506         dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1507         if (!dw)
1508                 return -ENOMEM;
1509
1510         dw->clk = devm_clk_get(&pdev->dev, "hclk");
1511         if (IS_ERR(dw->clk))
1512                 return PTR_ERR(dw->clk);
1513         clk_prepare_enable(dw->clk);
1514
1515         dw->regs = regs;
1516
1517         /* get hardware configuration parameters */
1518         if (autocfg) {
1519                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1520
1521                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1522                 for (i = 0; i < dw->nr_masters; i++) {
1523                         dw->data_width[i] =
1524                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1525                 }
1526         } else {
1527                 dw->nr_masters = pdata->nr_masters;
1528                 memcpy(dw->data_width, pdata->data_width, 4);
1529         }
1530
1531         /* Calculate all channel mask before DMA setup */
1532         dw->all_chan_mask = (1 << nr_channels) - 1;
1533
1534         /* force dma off, just in case */
1535         dw_dma_off(dw);
1536
1537         /* disable BLOCK interrupts as well */
1538         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1539
1540         err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1541                                "dw_dmac", dw);
1542         if (err)
1543                 return err;
1544
1545         platform_set_drvdata(pdev, dw);
1546
1547         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1548
1549         INIT_LIST_HEAD(&dw->dma.channels);
1550         for (i = 0; i < nr_channels; i++) {
1551                 struct dw_dma_chan      *dwc = &dw->chan[i];
1552                 int                     r = nr_channels - i - 1;
1553
1554                 dwc->chan.device = &dw->dma;
1555                 dma_cookie_init(&dwc->chan);
1556                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1557                         list_add_tail(&dwc->chan.device_node,
1558                                         &dw->dma.channels);
1559                 else
1560                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1561
1562                 /* 7 is highest priority & 0 is lowest. */
1563                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1564                         dwc->priority = r;
1565                 else
1566                         dwc->priority = i;
1567
1568                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1569                 spin_lock_init(&dwc->lock);
1570                 dwc->mask = 1 << i;
1571
1572                 INIT_LIST_HEAD(&dwc->active_list);
1573                 INIT_LIST_HEAD(&dwc->queue);
1574                 INIT_LIST_HEAD(&dwc->free_list);
1575
1576                 channel_clear_bit(dw, CH_EN, dwc->mask);
1577
1578                 dwc->dw = dw;
1579
1580                 /* hardware configuration */
1581                 if (autocfg) {
1582                         unsigned int dwc_params;
1583
1584                         dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1585                                                      DWC_PARAMS);
1586
1587                         /* Decode maximum block size for given channel. The
1588                          * stored 4 bit value represents blocks from 0x00 for 3
1589                          * up to 0x0a for 4095. */
1590                         dwc->block_size =
1591                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1592                         dwc->nollp =
1593                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1594                 } else {
1595                         dwc->block_size = pdata->block_size;
1596
1597                         /* Check if channel supports multi block transfer */
1598                         channel_writel(dwc, LLP, 0xfffffffc);
1599                         dwc->nollp =
1600                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1601                         channel_writel(dwc, LLP, 0);
1602                 }
1603         }
1604
1605         /* Clear all interrupts on all channels. */
1606         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1607         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1608         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1609         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1610         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1611
1612         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1613         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1614         if (pdata->is_private)
1615                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1616         dw->dma.dev = &pdev->dev;
1617         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1618         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1619
1620         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1621
1622         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1623         dw->dma.device_control = dwc_control;
1624
1625         dw->dma.device_tx_status = dwc_tx_status;
1626         dw->dma.device_issue_pending = dwc_issue_pending;
1627
1628         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1629
1630         printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n",
1631                         dev_name(&pdev->dev), nr_channels);
1632
1633         dma_async_device_register(&dw->dma);
1634
1635         return 0;
1636 }
1637
1638 static int dw_remove(struct platform_device *pdev)
1639 {
1640         struct dw_dma           *dw = platform_get_drvdata(pdev);
1641         struct dw_dma_chan      *dwc, *_dwc;
1642
1643         dw_dma_off(dw);
1644         dma_async_device_unregister(&dw->dma);
1645
1646         tasklet_kill(&dw->tasklet);
1647
1648         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1649                         chan.device_node) {
1650                 list_del(&dwc->chan.device_node);
1651                 channel_clear_bit(dw, CH_EN, dwc->mask);
1652         }
1653
1654         return 0;
1655 }
1656
1657 static void dw_shutdown(struct platform_device *pdev)
1658 {
1659         struct dw_dma   *dw = platform_get_drvdata(pdev);
1660
1661         dw_dma_off(platform_get_drvdata(pdev));
1662         clk_disable_unprepare(dw->clk);
1663 }
1664
1665 static int dw_suspend_noirq(struct device *dev)
1666 {
1667         struct platform_device *pdev = to_platform_device(dev);
1668         struct dw_dma   *dw = platform_get_drvdata(pdev);
1669
1670         dw_dma_off(platform_get_drvdata(pdev));
1671         clk_disable_unprepare(dw->clk);
1672
1673         return 0;
1674 }
1675
1676 static int dw_resume_noirq(struct device *dev)
1677 {
1678         struct platform_device *pdev = to_platform_device(dev);
1679         struct dw_dma   *dw = platform_get_drvdata(pdev);
1680
1681         clk_prepare_enable(dw->clk);
1682         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1683         return 0;
1684 }
1685
1686 static const struct dev_pm_ops dw_dev_pm_ops = {
1687         .suspend_noirq = dw_suspend_noirq,
1688         .resume_noirq = dw_resume_noirq,
1689         .freeze_noirq = dw_suspend_noirq,
1690         .thaw_noirq = dw_resume_noirq,
1691         .restore_noirq = dw_resume_noirq,
1692         .poweroff_noirq = dw_suspend_noirq,
1693 };
1694
1695 #ifdef CONFIG_OF
1696 static const struct of_device_id dw_dma_id_table[] = {
1697         { .compatible = "snps,dma-spear1340" },
1698         {}
1699 };
1700 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1701 #endif
1702
1703 static struct platform_driver dw_driver = {
1704         .remove         = dw_remove,
1705         .shutdown       = dw_shutdown,
1706         .driver = {
1707                 .name   = "dw_dmac",
1708                 .pm     = &dw_dev_pm_ops,
1709                 .of_match_table = of_match_ptr(dw_dma_id_table),
1710         },
1711 };
1712
1713 static int __init dw_init(void)
1714 {
1715         return platform_driver_probe(&dw_driver, dw_probe);
1716 }
1717 subsys_initcall(dw_init);
1718
1719 static void __exit dw_exit(void)
1720 {
1721         platform_driver_unregister(&dw_driver);
1722 }
1723 module_exit(dw_exit);
1724
1725 MODULE_LICENSE("GPL v2");
1726 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1727 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1728 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");