Merge tag 'firewire-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee139...
[~shefty/rdma-dev.git] / drivers / firewire / ohci.c
1 /*
2  * Driver for OHCI 1394 controllers
3  *
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45 #include <linux/workqueue.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/page.h>
49 #include <asm/system.h>
50
51 #ifdef CONFIG_PPC_PMAC
52 #include <asm/pmac_feature.h>
53 #endif
54
55 #include "core.h"
56 #include "ohci.h"
57
58 #define DESCRIPTOR_OUTPUT_MORE          0
59 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
60 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
61 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
62 #define DESCRIPTOR_STATUS               (1 << 11)
63 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
64 #define DESCRIPTOR_PING                 (1 << 7)
65 #define DESCRIPTOR_YY                   (1 << 6)
66 #define DESCRIPTOR_NO_IRQ               (0 << 4)
67 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
68 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
69 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
70 #define DESCRIPTOR_WAIT                 (3 << 0)
71
72 struct descriptor {
73         __le16 req_count;
74         __le16 control;
75         __le32 data_address;
76         __le32 branch_address;
77         __le16 res_count;
78         __le16 transfer_status;
79 } __attribute__((aligned(16)));
80
81 #define CONTROL_SET(regs)       (regs)
82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
83 #define COMMAND_PTR(regs)       ((regs) + 12)
84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
85
86 #define AR_BUFFER_SIZE  (32*1024)
87 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
88 /* we need at least two pages for proper list management */
89 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
90
91 #define MAX_ASYNC_PAYLOAD       4096
92 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
93 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
94
95 struct ar_context {
96         struct fw_ohci *ohci;
97         struct page *pages[AR_BUFFERS];
98         void *buffer;
99         struct descriptor *descriptors;
100         dma_addr_t descriptors_bus;
101         void *pointer;
102         unsigned int last_buffer_index;
103         u32 regs;
104         struct tasklet_struct tasklet;
105 };
106
107 struct context;
108
109 typedef int (*descriptor_callback_t)(struct context *ctx,
110                                      struct descriptor *d,
111                                      struct descriptor *last);
112
113 /*
114  * A buffer that contains a block of DMA-able coherent memory used for
115  * storing a portion of a DMA descriptor program.
116  */
117 struct descriptor_buffer {
118         struct list_head list;
119         dma_addr_t buffer_bus;
120         size_t buffer_size;
121         size_t used;
122         struct descriptor buffer[0];
123 };
124
125 struct context {
126         struct fw_ohci *ohci;
127         u32 regs;
128         int total_allocation;
129         u32 current_bus;
130         bool running;
131         bool flushing;
132
133         /*
134          * List of page-sized buffers for storing DMA descriptors.
135          * Head of list contains buffers in use and tail of list contains
136          * free buffers.
137          */
138         struct list_head buffer_list;
139
140         /*
141          * Pointer to a buffer inside buffer_list that contains the tail
142          * end of the current DMA program.
143          */
144         struct descriptor_buffer *buffer_tail;
145
146         /*
147          * The descriptor containing the branch address of the first
148          * descriptor that has not yet been filled by the device.
149          */
150         struct descriptor *last;
151
152         /*
153          * The last descriptor in the DMA program.  It contains the branch
154          * address that must be updated upon appending a new descriptor.
155          */
156         struct descriptor *prev;
157
158         descriptor_callback_t callback;
159
160         struct tasklet_struct tasklet;
161 };
162
163 #define IT_HEADER_SY(v)          ((v) <<  0)
164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
166 #define IT_HEADER_TAG(v)         ((v) << 14)
167 #define IT_HEADER_SPEED(v)       ((v) << 16)
168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
169
170 struct iso_context {
171         struct fw_iso_context base;
172         struct context context;
173         void *header;
174         size_t header_length;
175         unsigned long flushing_completions;
176         u32 mc_buffer_bus;
177         u16 mc_completed;
178         u16 last_timestamp;
179         u8 sync;
180         u8 tags;
181 };
182
183 #define CONFIG_ROM_SIZE 1024
184
185 struct fw_ohci {
186         struct fw_card card;
187
188         __iomem char *registers;
189         int node_id;
190         int generation;
191         int request_generation; /* for timestamping incoming requests */
192         unsigned quirks;
193         unsigned int pri_req_max;
194         u32 bus_time;
195         bool is_root;
196         bool csr_state_setclear_abdicate;
197         int n_ir;
198         int n_it;
199         /*
200          * Spinlock for accessing fw_ohci data.  Never call out of
201          * this driver with this lock held.
202          */
203         spinlock_t lock;
204
205         struct mutex phy_reg_mutex;
206
207         void *misc_buffer;
208         dma_addr_t misc_buffer_bus;
209
210         struct ar_context ar_request_ctx;
211         struct ar_context ar_response_ctx;
212         struct context at_request_ctx;
213         struct context at_response_ctx;
214
215         u32 it_context_support;
216         u32 it_context_mask;     /* unoccupied IT contexts */
217         struct iso_context *it_context_list;
218         u64 ir_context_channels; /* unoccupied channels */
219         u32 ir_context_support;
220         u32 ir_context_mask;     /* unoccupied IR contexts */
221         struct iso_context *ir_context_list;
222         u64 mc_channels; /* channels in use by the multichannel IR context */
223         bool mc_allocated;
224
225         __be32    *config_rom;
226         dma_addr_t config_rom_bus;
227         __be32    *next_config_rom;
228         dma_addr_t next_config_rom_bus;
229         __be32     next_header;
230
231         __le32    *self_id_cpu;
232         dma_addr_t self_id_bus;
233         struct work_struct bus_reset_work;
234
235         u32 self_id_buffer[512];
236 };
237
238 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
239 {
240         return container_of(card, struct fw_ohci, card);
241 }
242
243 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
244 #define IR_CONTEXT_BUFFER_FILL          0x80000000
245 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
246 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
247 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
248 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
249
250 #define CONTEXT_RUN     0x8000
251 #define CONTEXT_WAKE    0x1000
252 #define CONTEXT_DEAD    0x0800
253 #define CONTEXT_ACTIVE  0x0400
254
255 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
256 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
257 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
258
259 #define OHCI1394_REGISTER_SIZE          0x800
260 #define OHCI1394_PCI_HCI_Control        0x40
261 #define SELF_ID_BUF_SIZE                0x800
262 #define OHCI_TCODE_PHY_PACKET           0x0e
263 #define OHCI_VERSION_1_1                0x010010
264
265 static char ohci_driver_name[] = KBUILD_MODNAME;
266
267 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
268 #define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
269 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
270 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
271 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
272 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
273 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
274
275 #define QUIRK_CYCLE_TIMER               1
276 #define QUIRK_RESET_PACKET              2
277 #define QUIRK_BE_HEADERS                4
278 #define QUIRK_NO_1394A                  8
279 #define QUIRK_NO_MSI                    16
280 #define QUIRK_TI_SLLZ059                32
281
282 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
283 static const struct {
284         unsigned short vendor, device, revision, flags;
285 } ohci_quirks[] = {
286         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
287                 QUIRK_CYCLE_TIMER},
288
289         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
290                 QUIRK_BE_HEADERS},
291
292         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
293                 QUIRK_NO_MSI},
294
295         {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
296                 QUIRK_RESET_PACKET},
297
298         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
299                 QUIRK_NO_MSI},
300
301         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
302                 QUIRK_CYCLE_TIMER},
303
304         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
305                 QUIRK_NO_MSI},
306
307         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
308                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
309
310         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
311                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
312
313         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
314                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
315
316         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
317                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
318
319         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
320                 QUIRK_RESET_PACKET},
321
322         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
323                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
324 };
325
326 /* This overrides anything that was found in ohci_quirks[]. */
327 static int param_quirks;
328 module_param_named(quirks, param_quirks, int, 0644);
329 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
330         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
331         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
332         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
333         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
334         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
335         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
336         ")");
337
338 #define OHCI_PARAM_DEBUG_AT_AR          1
339 #define OHCI_PARAM_DEBUG_SELFIDS        2
340 #define OHCI_PARAM_DEBUG_IRQS           4
341 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
342
343 static int param_debug;
344 module_param_named(debug, param_debug, int, 0644);
345 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
346         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
347         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
348         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
349         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
350         ", or a combination, or all = -1)");
351
352 static void log_irqs(struct fw_ohci *ohci, u32 evt)
353 {
354         if (likely(!(param_debug &
355                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
356                 return;
357
358         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
359             !(evt & OHCI1394_busReset))
360                 return;
361
362         dev_notice(ohci->card.device,
363             "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
364             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
365             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
366             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
367             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
368             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
369             evt & OHCI1394_isochRx              ? " IR"                 : "",
370             evt & OHCI1394_isochTx              ? " IT"                 : "",
371             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
372             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
373             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
374             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
375             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
376             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
377             evt & OHCI1394_busReset             ? " busReset"           : "",
378             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
379                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
380                     OHCI1394_respTxComplete | OHCI1394_isochRx |
381                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
382                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
383                     OHCI1394_cycleInconsistent |
384                     OHCI1394_regAccessFail | OHCI1394_busReset)
385                                                 ? " ?"                  : "");
386 }
387
388 static const char *speed[] = {
389         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
390 };
391 static const char *power[] = {
392         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
393         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
394 };
395 static const char port[] = { '.', '-', 'p', 'c', };
396
397 static char _p(u32 *s, int shift)
398 {
399         return port[*s >> shift & 3];
400 }
401
402 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
403 {
404         u32 *s;
405
406         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
407                 return;
408
409         dev_notice(ohci->card.device,
410                    "%d selfIDs, generation %d, local node ID %04x\n",
411                    self_id_count, generation, ohci->node_id);
412
413         for (s = ohci->self_id_buffer; self_id_count--; ++s)
414                 if ((*s & 1 << 23) == 0)
415                         dev_notice(ohci->card.device,
416                             "selfID 0: %08x, phy %d [%c%c%c] "
417                             "%s gc=%d %s %s%s%s\n",
418                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
419                             speed[*s >> 14 & 3], *s >> 16 & 63,
420                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
421                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
422                 else
423                         dev_notice(ohci->card.device,
424                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
425                             *s, *s >> 24 & 63,
426                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
427                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
428 }
429
430 static const char *evts[] = {
431         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
432         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
433         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
434         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
435         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
436         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
437         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
438         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
439         [0x10] = "-reserved-",          [0x11] = "ack_complete",
440         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
441         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
442         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
443         [0x18] = "-reserved-",          [0x19] = "-reserved-",
444         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
445         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
446         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
447         [0x20] = "pending/cancelled",
448 };
449 static const char *tcodes[] = {
450         [0x0] = "QW req",               [0x1] = "BW req",
451         [0x2] = "W resp",               [0x3] = "-reserved-",
452         [0x4] = "QR req",               [0x5] = "BR req",
453         [0x6] = "QR resp",              [0x7] = "BR resp",
454         [0x8] = "cycle start",          [0x9] = "Lk req",
455         [0xa] = "async stream packet",  [0xb] = "Lk resp",
456         [0xc] = "-reserved-",           [0xd] = "-reserved-",
457         [0xe] = "link internal",        [0xf] = "-reserved-",
458 };
459
460 static void log_ar_at_event(struct fw_ohci *ohci,
461                             char dir, int speed, u32 *header, int evt)
462 {
463         int tcode = header[0] >> 4 & 0xf;
464         char specific[12];
465
466         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
467                 return;
468
469         if (unlikely(evt >= ARRAY_SIZE(evts)))
470                         evt = 0x1f;
471
472         if (evt == OHCI1394_evt_bus_reset) {
473                 dev_notice(ohci->card.device,
474                            "A%c evt_bus_reset, generation %d\n",
475                            dir, (header[2] >> 16) & 0xff);
476                 return;
477         }
478
479         switch (tcode) {
480         case 0x0: case 0x6: case 0x8:
481                 snprintf(specific, sizeof(specific), " = %08x",
482                          be32_to_cpu((__force __be32)header[3]));
483                 break;
484         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
485                 snprintf(specific, sizeof(specific), " %x,%x",
486                          header[3] >> 16, header[3] & 0xffff);
487                 break;
488         default:
489                 specific[0] = '\0';
490         }
491
492         switch (tcode) {
493         case 0xa:
494                 dev_notice(ohci->card.device,
495                            "A%c %s, %s\n",
496                            dir, evts[evt], tcodes[tcode]);
497                 break;
498         case 0xe:
499                 dev_notice(ohci->card.device,
500                            "A%c %s, PHY %08x %08x\n",
501                            dir, evts[evt], header[1], header[2]);
502                 break;
503         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
504                 dev_notice(ohci->card.device,
505                            "A%c spd %x tl %02x, "
506                            "%04x -> %04x, %s, "
507                            "%s, %04x%08x%s\n",
508                            dir, speed, header[0] >> 10 & 0x3f,
509                            header[1] >> 16, header[0] >> 16, evts[evt],
510                            tcodes[tcode], header[1] & 0xffff, header[2], specific);
511                 break;
512         default:
513                 dev_notice(ohci->card.device,
514                            "A%c spd %x tl %02x, "
515                            "%04x -> %04x, %s, "
516                            "%s%s\n",
517                            dir, speed, header[0] >> 10 & 0x3f,
518                            header[1] >> 16, header[0] >> 16, evts[evt],
519                            tcodes[tcode], specific);
520         }
521 }
522
523 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
524 {
525         writel(data, ohci->registers + offset);
526 }
527
528 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
529 {
530         return readl(ohci->registers + offset);
531 }
532
533 static inline void flush_writes(const struct fw_ohci *ohci)
534 {
535         /* Do a dummy read to flush writes. */
536         reg_read(ohci, OHCI1394_Version);
537 }
538
539 /*
540  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
541  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
542  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
543  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
544  */
545 static int read_phy_reg(struct fw_ohci *ohci, int addr)
546 {
547         u32 val;
548         int i;
549
550         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
551         for (i = 0; i < 3 + 100; i++) {
552                 val = reg_read(ohci, OHCI1394_PhyControl);
553                 if (!~val)
554                         return -ENODEV; /* Card was ejected. */
555
556                 if (val & OHCI1394_PhyControl_ReadDone)
557                         return OHCI1394_PhyControl_ReadData(val);
558
559                 /*
560                  * Try a few times without waiting.  Sleeping is necessary
561                  * only when the link/PHY interface is busy.
562                  */
563                 if (i >= 3)
564                         msleep(1);
565         }
566         dev_err(ohci->card.device, "failed to read phy reg\n");
567
568         return -EBUSY;
569 }
570
571 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
572 {
573         int i;
574
575         reg_write(ohci, OHCI1394_PhyControl,
576                   OHCI1394_PhyControl_Write(addr, val));
577         for (i = 0; i < 3 + 100; i++) {
578                 val = reg_read(ohci, OHCI1394_PhyControl);
579                 if (!~val)
580                         return -ENODEV; /* Card was ejected. */
581
582                 if (!(val & OHCI1394_PhyControl_WritePending))
583                         return 0;
584
585                 if (i >= 3)
586                         msleep(1);
587         }
588         dev_err(ohci->card.device, "failed to write phy reg\n");
589
590         return -EBUSY;
591 }
592
593 static int update_phy_reg(struct fw_ohci *ohci, int addr,
594                           int clear_bits, int set_bits)
595 {
596         int ret = read_phy_reg(ohci, addr);
597         if (ret < 0)
598                 return ret;
599
600         /*
601          * The interrupt status bits are cleared by writing a one bit.
602          * Avoid clearing them unless explicitly requested in set_bits.
603          */
604         if (addr == 5)
605                 clear_bits |= PHY_INT_STATUS_BITS;
606
607         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
608 }
609
610 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
611 {
612         int ret;
613
614         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
615         if (ret < 0)
616                 return ret;
617
618         return read_phy_reg(ohci, addr);
619 }
620
621 static int ohci_read_phy_reg(struct fw_card *card, int addr)
622 {
623         struct fw_ohci *ohci = fw_ohci(card);
624         int ret;
625
626         mutex_lock(&ohci->phy_reg_mutex);
627         ret = read_phy_reg(ohci, addr);
628         mutex_unlock(&ohci->phy_reg_mutex);
629
630         return ret;
631 }
632
633 static int ohci_update_phy_reg(struct fw_card *card, int addr,
634                                int clear_bits, int set_bits)
635 {
636         struct fw_ohci *ohci = fw_ohci(card);
637         int ret;
638
639         mutex_lock(&ohci->phy_reg_mutex);
640         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
641         mutex_unlock(&ohci->phy_reg_mutex);
642
643         return ret;
644 }
645
646 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
647 {
648         return page_private(ctx->pages[i]);
649 }
650
651 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
652 {
653         struct descriptor *d;
654
655         d = &ctx->descriptors[index];
656         d->branch_address  &= cpu_to_le32(~0xf);
657         d->res_count       =  cpu_to_le16(PAGE_SIZE);
658         d->transfer_status =  0;
659
660         wmb(); /* finish init of new descriptors before branch_address update */
661         d = &ctx->descriptors[ctx->last_buffer_index];
662         d->branch_address  |= cpu_to_le32(1);
663
664         ctx->last_buffer_index = index;
665
666         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
667 }
668
669 static void ar_context_release(struct ar_context *ctx)
670 {
671         unsigned int i;
672
673         if (ctx->buffer)
674                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
675
676         for (i = 0; i < AR_BUFFERS; i++)
677                 if (ctx->pages[i]) {
678                         dma_unmap_page(ctx->ohci->card.device,
679                                        ar_buffer_bus(ctx, i),
680                                        PAGE_SIZE, DMA_FROM_DEVICE);
681                         __free_page(ctx->pages[i]);
682                 }
683 }
684
685 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
686 {
687         struct fw_ohci *ohci = ctx->ohci;
688
689         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
690                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
691                 flush_writes(ohci);
692
693                 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
694                         error_msg);
695         }
696         /* FIXME: restart? */
697 }
698
699 static inline unsigned int ar_next_buffer_index(unsigned int index)
700 {
701         return (index + 1) % AR_BUFFERS;
702 }
703
704 static inline unsigned int ar_prev_buffer_index(unsigned int index)
705 {
706         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
707 }
708
709 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
710 {
711         return ar_next_buffer_index(ctx->last_buffer_index);
712 }
713
714 /*
715  * We search for the buffer that contains the last AR packet DMA data written
716  * by the controller.
717  */
718 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
719                                                  unsigned int *buffer_offset)
720 {
721         unsigned int i, next_i, last = ctx->last_buffer_index;
722         __le16 res_count, next_res_count;
723
724         i = ar_first_buffer_index(ctx);
725         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
726
727         /* A buffer that is not yet completely filled must be the last one. */
728         while (i != last && res_count == 0) {
729
730                 /* Peek at the next descriptor. */
731                 next_i = ar_next_buffer_index(i);
732                 rmb(); /* read descriptors in order */
733                 next_res_count = ACCESS_ONCE(
734                                 ctx->descriptors[next_i].res_count);
735                 /*
736                  * If the next descriptor is still empty, we must stop at this
737                  * descriptor.
738                  */
739                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
740                         /*
741                          * The exception is when the DMA data for one packet is
742                          * split over three buffers; in this case, the middle
743                          * buffer's descriptor might be never updated by the
744                          * controller and look still empty, and we have to peek
745                          * at the third one.
746                          */
747                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
748                                 next_i = ar_next_buffer_index(next_i);
749                                 rmb();
750                                 next_res_count = ACCESS_ONCE(
751                                         ctx->descriptors[next_i].res_count);
752                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
753                                         goto next_buffer_is_active;
754                         }
755
756                         break;
757                 }
758
759 next_buffer_is_active:
760                 i = next_i;
761                 res_count = next_res_count;
762         }
763
764         rmb(); /* read res_count before the DMA data */
765
766         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
767         if (*buffer_offset > PAGE_SIZE) {
768                 *buffer_offset = 0;
769                 ar_context_abort(ctx, "corrupted descriptor");
770         }
771
772         return i;
773 }
774
775 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
776                                     unsigned int end_buffer_index,
777                                     unsigned int end_buffer_offset)
778 {
779         unsigned int i;
780
781         i = ar_first_buffer_index(ctx);
782         while (i != end_buffer_index) {
783                 dma_sync_single_for_cpu(ctx->ohci->card.device,
784                                         ar_buffer_bus(ctx, i),
785                                         PAGE_SIZE, DMA_FROM_DEVICE);
786                 i = ar_next_buffer_index(i);
787         }
788         if (end_buffer_offset > 0)
789                 dma_sync_single_for_cpu(ctx->ohci->card.device,
790                                         ar_buffer_bus(ctx, i),
791                                         end_buffer_offset, DMA_FROM_DEVICE);
792 }
793
794 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
795 #define cond_le32_to_cpu(v) \
796         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
797 #else
798 #define cond_le32_to_cpu(v) le32_to_cpu(v)
799 #endif
800
801 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
802 {
803         struct fw_ohci *ohci = ctx->ohci;
804         struct fw_packet p;
805         u32 status, length, tcode;
806         int evt;
807
808         p.header[0] = cond_le32_to_cpu(buffer[0]);
809         p.header[1] = cond_le32_to_cpu(buffer[1]);
810         p.header[2] = cond_le32_to_cpu(buffer[2]);
811
812         tcode = (p.header[0] >> 4) & 0x0f;
813         switch (tcode) {
814         case TCODE_WRITE_QUADLET_REQUEST:
815         case TCODE_READ_QUADLET_RESPONSE:
816                 p.header[3] = (__force __u32) buffer[3];
817                 p.header_length = 16;
818                 p.payload_length = 0;
819                 break;
820
821         case TCODE_READ_BLOCK_REQUEST :
822                 p.header[3] = cond_le32_to_cpu(buffer[3]);
823                 p.header_length = 16;
824                 p.payload_length = 0;
825                 break;
826
827         case TCODE_WRITE_BLOCK_REQUEST:
828         case TCODE_READ_BLOCK_RESPONSE:
829         case TCODE_LOCK_REQUEST:
830         case TCODE_LOCK_RESPONSE:
831                 p.header[3] = cond_le32_to_cpu(buffer[3]);
832                 p.header_length = 16;
833                 p.payload_length = p.header[3] >> 16;
834                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
835                         ar_context_abort(ctx, "invalid packet length");
836                         return NULL;
837                 }
838                 break;
839
840         case TCODE_WRITE_RESPONSE:
841         case TCODE_READ_QUADLET_REQUEST:
842         case OHCI_TCODE_PHY_PACKET:
843                 p.header_length = 12;
844                 p.payload_length = 0;
845                 break;
846
847         default:
848                 ar_context_abort(ctx, "invalid tcode");
849                 return NULL;
850         }
851
852         p.payload = (void *) buffer + p.header_length;
853
854         /* FIXME: What to do about evt_* errors? */
855         length = (p.header_length + p.payload_length + 3) / 4;
856         status = cond_le32_to_cpu(buffer[length]);
857         evt    = (status >> 16) & 0x1f;
858
859         p.ack        = evt - 16;
860         p.speed      = (status >> 21) & 0x7;
861         p.timestamp  = status & 0xffff;
862         p.generation = ohci->request_generation;
863
864         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
865
866         /*
867          * Several controllers, notably from NEC and VIA, forget to
868          * write ack_complete status at PHY packet reception.
869          */
870         if (evt == OHCI1394_evt_no_status &&
871             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
872                 p.ack = ACK_COMPLETE;
873
874         /*
875          * The OHCI bus reset handler synthesizes a PHY packet with
876          * the new generation number when a bus reset happens (see
877          * section 8.4.2.3).  This helps us determine when a request
878          * was received and make sure we send the response in the same
879          * generation.  We only need this for requests; for responses
880          * we use the unique tlabel for finding the matching
881          * request.
882          *
883          * Alas some chips sometimes emit bus reset packets with a
884          * wrong generation.  We set the correct generation for these
885          * at a slightly incorrect time (in bus_reset_work).
886          */
887         if (evt == OHCI1394_evt_bus_reset) {
888                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
889                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
890         } else if (ctx == &ohci->ar_request_ctx) {
891                 fw_core_handle_request(&ohci->card, &p);
892         } else {
893                 fw_core_handle_response(&ohci->card, &p);
894         }
895
896         return buffer + length + 1;
897 }
898
899 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
900 {
901         void *next;
902
903         while (p < end) {
904                 next = handle_ar_packet(ctx, p);
905                 if (!next)
906                         return p;
907                 p = next;
908         }
909
910         return p;
911 }
912
913 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
914 {
915         unsigned int i;
916
917         i = ar_first_buffer_index(ctx);
918         while (i != end_buffer) {
919                 dma_sync_single_for_device(ctx->ohci->card.device,
920                                            ar_buffer_bus(ctx, i),
921                                            PAGE_SIZE, DMA_FROM_DEVICE);
922                 ar_context_link_page(ctx, i);
923                 i = ar_next_buffer_index(i);
924         }
925 }
926
927 static void ar_context_tasklet(unsigned long data)
928 {
929         struct ar_context *ctx = (struct ar_context *)data;
930         unsigned int end_buffer_index, end_buffer_offset;
931         void *p, *end;
932
933         p = ctx->pointer;
934         if (!p)
935                 return;
936
937         end_buffer_index = ar_search_last_active_buffer(ctx,
938                                                         &end_buffer_offset);
939         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
940         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
941
942         if (end_buffer_index < ar_first_buffer_index(ctx)) {
943                 /*
944                  * The filled part of the overall buffer wraps around; handle
945                  * all packets up to the buffer end here.  If the last packet
946                  * wraps around, its tail will be visible after the buffer end
947                  * because the buffer start pages are mapped there again.
948                  */
949                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
950                 p = handle_ar_packets(ctx, p, buffer_end);
951                 if (p < buffer_end)
952                         goto error;
953                 /* adjust p to point back into the actual buffer */
954                 p -= AR_BUFFERS * PAGE_SIZE;
955         }
956
957         p = handle_ar_packets(ctx, p, end);
958         if (p != end) {
959                 if (p > end)
960                         ar_context_abort(ctx, "inconsistent descriptor");
961                 goto error;
962         }
963
964         ctx->pointer = p;
965         ar_recycle_buffers(ctx, end_buffer_index);
966
967         return;
968
969 error:
970         ctx->pointer = NULL;
971 }
972
973 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
974                            unsigned int descriptors_offset, u32 regs)
975 {
976         unsigned int i;
977         dma_addr_t dma_addr;
978         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
979         struct descriptor *d;
980
981         ctx->regs        = regs;
982         ctx->ohci        = ohci;
983         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
984
985         for (i = 0; i < AR_BUFFERS; i++) {
986                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
987                 if (!ctx->pages[i])
988                         goto out_of_memory;
989                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
990                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
991                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
992                         __free_page(ctx->pages[i]);
993                         ctx->pages[i] = NULL;
994                         goto out_of_memory;
995                 }
996                 set_page_private(ctx->pages[i], dma_addr);
997         }
998
999         for (i = 0; i < AR_BUFFERS; i++)
1000                 pages[i]              = ctx->pages[i];
1001         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1002                 pages[AR_BUFFERS + i] = ctx->pages[i];
1003         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1004                                  -1, PAGE_KERNEL);
1005         if (!ctx->buffer)
1006                 goto out_of_memory;
1007
1008         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1009         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1010
1011         for (i = 0; i < AR_BUFFERS; i++) {
1012                 d = &ctx->descriptors[i];
1013                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1014                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1015                                                 DESCRIPTOR_STATUS |
1016                                                 DESCRIPTOR_BRANCH_ALWAYS);
1017                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1018                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1019                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1020         }
1021
1022         return 0;
1023
1024 out_of_memory:
1025         ar_context_release(ctx);
1026
1027         return -ENOMEM;
1028 }
1029
1030 static void ar_context_run(struct ar_context *ctx)
1031 {
1032         unsigned int i;
1033
1034         for (i = 0; i < AR_BUFFERS; i++)
1035                 ar_context_link_page(ctx, i);
1036
1037         ctx->pointer = ctx->buffer;
1038
1039         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1040         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1041 }
1042
1043 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1044 {
1045         __le16 branch;
1046
1047         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1048
1049         /* figure out which descriptor the branch address goes in */
1050         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1051                 return d;
1052         else
1053                 return d + z - 1;
1054 }
1055
1056 static void context_tasklet(unsigned long data)
1057 {
1058         struct context *ctx = (struct context *) data;
1059         struct descriptor *d, *last;
1060         u32 address;
1061         int z;
1062         struct descriptor_buffer *desc;
1063
1064         desc = list_entry(ctx->buffer_list.next,
1065                         struct descriptor_buffer, list);
1066         last = ctx->last;
1067         while (last->branch_address != 0) {
1068                 struct descriptor_buffer *old_desc = desc;
1069                 address = le32_to_cpu(last->branch_address);
1070                 z = address & 0xf;
1071                 address &= ~0xf;
1072                 ctx->current_bus = address;
1073
1074                 /* If the branch address points to a buffer outside of the
1075                  * current buffer, advance to the next buffer. */
1076                 if (address < desc->buffer_bus ||
1077                                 address >= desc->buffer_bus + desc->used)
1078                         desc = list_entry(desc->list.next,
1079                                         struct descriptor_buffer, list);
1080                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1081                 last = find_branch_descriptor(d, z);
1082
1083                 if (!ctx->callback(ctx, d, last))
1084                         break;
1085
1086                 if (old_desc != desc) {
1087                         /* If we've advanced to the next buffer, move the
1088                          * previous buffer to the free list. */
1089                         unsigned long flags;
1090                         old_desc->used = 0;
1091                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1092                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1093                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1094                 }
1095                 ctx->last = last;
1096         }
1097 }
1098
1099 /*
1100  * Allocate a new buffer and add it to the list of free buffers for this
1101  * context.  Must be called with ohci->lock held.
1102  */
1103 static int context_add_buffer(struct context *ctx)
1104 {
1105         struct descriptor_buffer *desc;
1106         dma_addr_t uninitialized_var(bus_addr);
1107         int offset;
1108
1109         /*
1110          * 16MB of descriptors should be far more than enough for any DMA
1111          * program.  This will catch run-away userspace or DoS attacks.
1112          */
1113         if (ctx->total_allocation >= 16*1024*1024)
1114                 return -ENOMEM;
1115
1116         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1117                         &bus_addr, GFP_ATOMIC);
1118         if (!desc)
1119                 return -ENOMEM;
1120
1121         offset = (void *)&desc->buffer - (void *)desc;
1122         desc->buffer_size = PAGE_SIZE - offset;
1123         desc->buffer_bus = bus_addr + offset;
1124         desc->used = 0;
1125
1126         list_add_tail(&desc->list, &ctx->buffer_list);
1127         ctx->total_allocation += PAGE_SIZE;
1128
1129         return 0;
1130 }
1131
1132 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1133                         u32 regs, descriptor_callback_t callback)
1134 {
1135         ctx->ohci = ohci;
1136         ctx->regs = regs;
1137         ctx->total_allocation = 0;
1138
1139         INIT_LIST_HEAD(&ctx->buffer_list);
1140         if (context_add_buffer(ctx) < 0)
1141                 return -ENOMEM;
1142
1143         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1144                         struct descriptor_buffer, list);
1145
1146         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1147         ctx->callback = callback;
1148
1149         /*
1150          * We put a dummy descriptor in the buffer that has a NULL
1151          * branch address and looks like it's been sent.  That way we
1152          * have a descriptor to append DMA programs to.
1153          */
1154         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1155         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1156         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1157         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1158         ctx->last = ctx->buffer_tail->buffer;
1159         ctx->prev = ctx->buffer_tail->buffer;
1160
1161         return 0;
1162 }
1163
1164 static void context_release(struct context *ctx)
1165 {
1166         struct fw_card *card = &ctx->ohci->card;
1167         struct descriptor_buffer *desc, *tmp;
1168
1169         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1170                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1171                         desc->buffer_bus -
1172                         ((void *)&desc->buffer - (void *)desc));
1173 }
1174
1175 /* Must be called with ohci->lock held */
1176 static struct descriptor *context_get_descriptors(struct context *ctx,
1177                                                   int z, dma_addr_t *d_bus)
1178 {
1179         struct descriptor *d = NULL;
1180         struct descriptor_buffer *desc = ctx->buffer_tail;
1181
1182         if (z * sizeof(*d) > desc->buffer_size)
1183                 return NULL;
1184
1185         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1186                 /* No room for the descriptor in this buffer, so advance to the
1187                  * next one. */
1188
1189                 if (desc->list.next == &ctx->buffer_list) {
1190                         /* If there is no free buffer next in the list,
1191                          * allocate one. */
1192                         if (context_add_buffer(ctx) < 0)
1193                                 return NULL;
1194                 }
1195                 desc = list_entry(desc->list.next,
1196                                 struct descriptor_buffer, list);
1197                 ctx->buffer_tail = desc;
1198         }
1199
1200         d = desc->buffer + desc->used / sizeof(*d);
1201         memset(d, 0, z * sizeof(*d));
1202         *d_bus = desc->buffer_bus + desc->used;
1203
1204         return d;
1205 }
1206
1207 static void context_run(struct context *ctx, u32 extra)
1208 {
1209         struct fw_ohci *ohci = ctx->ohci;
1210
1211         reg_write(ohci, COMMAND_PTR(ctx->regs),
1212                   le32_to_cpu(ctx->last->branch_address));
1213         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1214         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1215         ctx->running = true;
1216         flush_writes(ohci);
1217 }
1218
1219 static void context_append(struct context *ctx,
1220                            struct descriptor *d, int z, int extra)
1221 {
1222         dma_addr_t d_bus;
1223         struct descriptor_buffer *desc = ctx->buffer_tail;
1224
1225         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1226
1227         desc->used += (z + extra) * sizeof(*d);
1228
1229         wmb(); /* finish init of new descriptors before branch_address update */
1230         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1231         ctx->prev = find_branch_descriptor(d, z);
1232 }
1233
1234 static void context_stop(struct context *ctx)
1235 {
1236         struct fw_ohci *ohci = ctx->ohci;
1237         u32 reg;
1238         int i;
1239
1240         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1241         ctx->running = false;
1242
1243         for (i = 0; i < 1000; i++) {
1244                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1245                 if ((reg & CONTEXT_ACTIVE) == 0)
1246                         return;
1247
1248                 if (i)
1249                         udelay(10);
1250         }
1251         dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
1252 }
1253
1254 struct driver_data {
1255         u8 inline_data[8];
1256         struct fw_packet *packet;
1257 };
1258
1259 /*
1260  * This function apppends a packet to the DMA queue for transmission.
1261  * Must always be called with the ochi->lock held to ensure proper
1262  * generation handling and locking around packet queue manipulation.
1263  */
1264 static int at_context_queue_packet(struct context *ctx,
1265                                    struct fw_packet *packet)
1266 {
1267         struct fw_ohci *ohci = ctx->ohci;
1268         dma_addr_t d_bus, uninitialized_var(payload_bus);
1269         struct driver_data *driver_data;
1270         struct descriptor *d, *last;
1271         __le32 *header;
1272         int z, tcode;
1273
1274         d = context_get_descriptors(ctx, 4, &d_bus);
1275         if (d == NULL) {
1276                 packet->ack = RCODE_SEND_ERROR;
1277                 return -1;
1278         }
1279
1280         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1281         d[0].res_count = cpu_to_le16(packet->timestamp);
1282
1283         /*
1284          * The DMA format for asyncronous link packets is different
1285          * from the IEEE1394 layout, so shift the fields around
1286          * accordingly.
1287          */
1288
1289         tcode = (packet->header[0] >> 4) & 0x0f;
1290         header = (__le32 *) &d[1];
1291         switch (tcode) {
1292         case TCODE_WRITE_QUADLET_REQUEST:
1293         case TCODE_WRITE_BLOCK_REQUEST:
1294         case TCODE_WRITE_RESPONSE:
1295         case TCODE_READ_QUADLET_REQUEST:
1296         case TCODE_READ_BLOCK_REQUEST:
1297         case TCODE_READ_QUADLET_RESPONSE:
1298         case TCODE_READ_BLOCK_RESPONSE:
1299         case TCODE_LOCK_REQUEST:
1300         case TCODE_LOCK_RESPONSE:
1301                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1302                                         (packet->speed << 16));
1303                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1304                                         (packet->header[0] & 0xffff0000));
1305                 header[2] = cpu_to_le32(packet->header[2]);
1306
1307                 if (TCODE_IS_BLOCK_PACKET(tcode))
1308                         header[3] = cpu_to_le32(packet->header[3]);
1309                 else
1310                         header[3] = (__force __le32) packet->header[3];
1311
1312                 d[0].req_count = cpu_to_le16(packet->header_length);
1313                 break;
1314
1315         case TCODE_LINK_INTERNAL:
1316                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1317                                         (packet->speed << 16));
1318                 header[1] = cpu_to_le32(packet->header[1]);
1319                 header[2] = cpu_to_le32(packet->header[2]);
1320                 d[0].req_count = cpu_to_le16(12);
1321
1322                 if (is_ping_packet(&packet->header[1]))
1323                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1324                 break;
1325
1326         case TCODE_STREAM_DATA:
1327                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1328                                         (packet->speed << 16));
1329                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1330                 d[0].req_count = cpu_to_le16(8);
1331                 break;
1332
1333         default:
1334                 /* BUG(); */
1335                 packet->ack = RCODE_SEND_ERROR;
1336                 return -1;
1337         }
1338
1339         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1340         driver_data = (struct driver_data *) &d[3];
1341         driver_data->packet = packet;
1342         packet->driver_data = driver_data;
1343
1344         if (packet->payload_length > 0) {
1345                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1346                         payload_bus = dma_map_single(ohci->card.device,
1347                                                      packet->payload,
1348                                                      packet->payload_length,
1349                                                      DMA_TO_DEVICE);
1350                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1351                                 packet->ack = RCODE_SEND_ERROR;
1352                                 return -1;
1353                         }
1354                         packet->payload_bus     = payload_bus;
1355                         packet->payload_mapped  = true;
1356                 } else {
1357                         memcpy(driver_data->inline_data, packet->payload,
1358                                packet->payload_length);
1359                         payload_bus = d_bus + 3 * sizeof(*d);
1360                 }
1361
1362                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1363                 d[2].data_address = cpu_to_le32(payload_bus);
1364                 last = &d[2];
1365                 z = 3;
1366         } else {
1367                 last = &d[0];
1368                 z = 2;
1369         }
1370
1371         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1372                                      DESCRIPTOR_IRQ_ALWAYS |
1373                                      DESCRIPTOR_BRANCH_ALWAYS);
1374
1375         /* FIXME: Document how the locking works. */
1376         if (ohci->generation != packet->generation) {
1377                 if (packet->payload_mapped)
1378                         dma_unmap_single(ohci->card.device, payload_bus,
1379                                          packet->payload_length, DMA_TO_DEVICE);
1380                 packet->ack = RCODE_GENERATION;
1381                 return -1;
1382         }
1383
1384         context_append(ctx, d, z, 4 - z);
1385
1386         if (ctx->running)
1387                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1388         else
1389                 context_run(ctx, 0);
1390
1391         return 0;
1392 }
1393
1394 static void at_context_flush(struct context *ctx)
1395 {
1396         tasklet_disable(&ctx->tasklet);
1397
1398         ctx->flushing = true;
1399         context_tasklet((unsigned long)ctx);
1400         ctx->flushing = false;
1401
1402         tasklet_enable(&ctx->tasklet);
1403 }
1404
1405 static int handle_at_packet(struct context *context,
1406                             struct descriptor *d,
1407                             struct descriptor *last)
1408 {
1409         struct driver_data *driver_data;
1410         struct fw_packet *packet;
1411         struct fw_ohci *ohci = context->ohci;
1412         int evt;
1413
1414         if (last->transfer_status == 0 && !context->flushing)
1415                 /* This descriptor isn't done yet, stop iteration. */
1416                 return 0;
1417
1418         driver_data = (struct driver_data *) &d[3];
1419         packet = driver_data->packet;
1420         if (packet == NULL)
1421                 /* This packet was cancelled, just continue. */
1422                 return 1;
1423
1424         if (packet->payload_mapped)
1425                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1426                                  packet->payload_length, DMA_TO_DEVICE);
1427
1428         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1429         packet->timestamp = le16_to_cpu(last->res_count);
1430
1431         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1432
1433         switch (evt) {
1434         case OHCI1394_evt_timeout:
1435                 /* Async response transmit timed out. */
1436                 packet->ack = RCODE_CANCELLED;
1437                 break;
1438
1439         case OHCI1394_evt_flushed:
1440                 /*
1441                  * The packet was flushed should give same error as
1442                  * when we try to use a stale generation count.
1443                  */
1444                 packet->ack = RCODE_GENERATION;
1445                 break;
1446
1447         case OHCI1394_evt_missing_ack:
1448                 if (context->flushing)
1449                         packet->ack = RCODE_GENERATION;
1450                 else {
1451                         /*
1452                          * Using a valid (current) generation count, but the
1453                          * node is not on the bus or not sending acks.
1454                          */
1455                         packet->ack = RCODE_NO_ACK;
1456                 }
1457                 break;
1458
1459         case ACK_COMPLETE + 0x10:
1460         case ACK_PENDING + 0x10:
1461         case ACK_BUSY_X + 0x10:
1462         case ACK_BUSY_A + 0x10:
1463         case ACK_BUSY_B + 0x10:
1464         case ACK_DATA_ERROR + 0x10:
1465         case ACK_TYPE_ERROR + 0x10:
1466                 packet->ack = evt - 0x10;
1467                 break;
1468
1469         case OHCI1394_evt_no_status:
1470                 if (context->flushing) {
1471                         packet->ack = RCODE_GENERATION;
1472                         break;
1473                 }
1474                 /* fall through */
1475
1476         default:
1477                 packet->ack = RCODE_SEND_ERROR;
1478                 break;
1479         }
1480
1481         packet->callback(packet, &ohci->card, packet->ack);
1482
1483         return 1;
1484 }
1485
1486 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1487 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1488 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1489 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1490 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1491
1492 static void handle_local_rom(struct fw_ohci *ohci,
1493                              struct fw_packet *packet, u32 csr)
1494 {
1495         struct fw_packet response;
1496         int tcode, length, i;
1497
1498         tcode = HEADER_GET_TCODE(packet->header[0]);
1499         if (TCODE_IS_BLOCK_PACKET(tcode))
1500                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1501         else
1502                 length = 4;
1503
1504         i = csr - CSR_CONFIG_ROM;
1505         if (i + length > CONFIG_ROM_SIZE) {
1506                 fw_fill_response(&response, packet->header,
1507                                  RCODE_ADDRESS_ERROR, NULL, 0);
1508         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1509                 fw_fill_response(&response, packet->header,
1510                                  RCODE_TYPE_ERROR, NULL, 0);
1511         } else {
1512                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1513                                  (void *) ohci->config_rom + i, length);
1514         }
1515
1516         fw_core_handle_response(&ohci->card, &response);
1517 }
1518
1519 static void handle_local_lock(struct fw_ohci *ohci,
1520                               struct fw_packet *packet, u32 csr)
1521 {
1522         struct fw_packet response;
1523         int tcode, length, ext_tcode, sel, try;
1524         __be32 *payload, lock_old;
1525         u32 lock_arg, lock_data;
1526
1527         tcode = HEADER_GET_TCODE(packet->header[0]);
1528         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1529         payload = packet->payload;
1530         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1531
1532         if (tcode == TCODE_LOCK_REQUEST &&
1533             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1534                 lock_arg = be32_to_cpu(payload[0]);
1535                 lock_data = be32_to_cpu(payload[1]);
1536         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1537                 lock_arg = 0;
1538                 lock_data = 0;
1539         } else {
1540                 fw_fill_response(&response, packet->header,
1541                                  RCODE_TYPE_ERROR, NULL, 0);
1542                 goto out;
1543         }
1544
1545         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1546         reg_write(ohci, OHCI1394_CSRData, lock_data);
1547         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1548         reg_write(ohci, OHCI1394_CSRControl, sel);
1549
1550         for (try = 0; try < 20; try++)
1551                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1552                         lock_old = cpu_to_be32(reg_read(ohci,
1553                                                         OHCI1394_CSRData));
1554                         fw_fill_response(&response, packet->header,
1555                                          RCODE_COMPLETE,
1556                                          &lock_old, sizeof(lock_old));
1557                         goto out;
1558                 }
1559
1560         dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
1561         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1562
1563  out:
1564         fw_core_handle_response(&ohci->card, &response);
1565 }
1566
1567 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1568 {
1569         u64 offset, csr;
1570
1571         if (ctx == &ctx->ohci->at_request_ctx) {
1572                 packet->ack = ACK_PENDING;
1573                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1574         }
1575
1576         offset =
1577                 ((unsigned long long)
1578                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1579                 packet->header[2];
1580         csr = offset - CSR_REGISTER_BASE;
1581
1582         /* Handle config rom reads. */
1583         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1584                 handle_local_rom(ctx->ohci, packet, csr);
1585         else switch (csr) {
1586         case CSR_BUS_MANAGER_ID:
1587         case CSR_BANDWIDTH_AVAILABLE:
1588         case CSR_CHANNELS_AVAILABLE_HI:
1589         case CSR_CHANNELS_AVAILABLE_LO:
1590                 handle_local_lock(ctx->ohci, packet, csr);
1591                 break;
1592         default:
1593                 if (ctx == &ctx->ohci->at_request_ctx)
1594                         fw_core_handle_request(&ctx->ohci->card, packet);
1595                 else
1596                         fw_core_handle_response(&ctx->ohci->card, packet);
1597                 break;
1598         }
1599
1600         if (ctx == &ctx->ohci->at_response_ctx) {
1601                 packet->ack = ACK_COMPLETE;
1602                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1603         }
1604 }
1605
1606 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1607 {
1608         unsigned long flags;
1609         int ret;
1610
1611         spin_lock_irqsave(&ctx->ohci->lock, flags);
1612
1613         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1614             ctx->ohci->generation == packet->generation) {
1615                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1616                 handle_local_request(ctx, packet);
1617                 return;
1618         }
1619
1620         ret = at_context_queue_packet(ctx, packet);
1621         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1622
1623         if (ret < 0)
1624                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1625
1626 }
1627
1628 static void detect_dead_context(struct fw_ohci *ohci,
1629                                 const char *name, unsigned int regs)
1630 {
1631         u32 ctl;
1632
1633         ctl = reg_read(ohci, CONTROL_SET(regs));
1634         if (ctl & CONTEXT_DEAD)
1635                 dev_err(ohci->card.device,
1636                         "DMA context %s has stopped, error code: %s\n",
1637                         name, evts[ctl & 0x1f]);
1638 }
1639
1640 static void handle_dead_contexts(struct fw_ohci *ohci)
1641 {
1642         unsigned int i;
1643         char name[8];
1644
1645         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1646         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1647         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1648         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1649         for (i = 0; i < 32; ++i) {
1650                 if (!(ohci->it_context_support & (1 << i)))
1651                         continue;
1652                 sprintf(name, "IT%u", i);
1653                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1654         }
1655         for (i = 0; i < 32; ++i) {
1656                 if (!(ohci->ir_context_support & (1 << i)))
1657                         continue;
1658                 sprintf(name, "IR%u", i);
1659                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1660         }
1661         /* TODO: maybe try to flush and restart the dead contexts */
1662 }
1663
1664 static u32 cycle_timer_ticks(u32 cycle_timer)
1665 {
1666         u32 ticks;
1667
1668         ticks = cycle_timer & 0xfff;
1669         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1670         ticks += (3072 * 8000) * (cycle_timer >> 25);
1671
1672         return ticks;
1673 }
1674
1675 /*
1676  * Some controllers exhibit one or more of the following bugs when updating the
1677  * iso cycle timer register:
1678  *  - When the lowest six bits are wrapping around to zero, a read that happens
1679  *    at the same time will return garbage in the lowest ten bits.
1680  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1681  *    not incremented for about 60 ns.
1682  *  - Occasionally, the entire register reads zero.
1683  *
1684  * To catch these, we read the register three times and ensure that the
1685  * difference between each two consecutive reads is approximately the same, i.e.
1686  * less than twice the other.  Furthermore, any negative difference indicates an
1687  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1688  * execute, so we have enough precision to compute the ratio of the differences.)
1689  */
1690 static u32 get_cycle_time(struct fw_ohci *ohci)
1691 {
1692         u32 c0, c1, c2;
1693         u32 t0, t1, t2;
1694         s32 diff01, diff12;
1695         int i;
1696
1697         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1698
1699         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1700                 i = 0;
1701                 c1 = c2;
1702                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1703                 do {
1704                         c0 = c1;
1705                         c1 = c2;
1706                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1707                         t0 = cycle_timer_ticks(c0);
1708                         t1 = cycle_timer_ticks(c1);
1709                         t2 = cycle_timer_ticks(c2);
1710                         diff01 = t1 - t0;
1711                         diff12 = t2 - t1;
1712                 } while ((diff01 <= 0 || diff12 <= 0 ||
1713                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1714                          && i++ < 20);
1715         }
1716
1717         return c2;
1718 }
1719
1720 /*
1721  * This function has to be called at least every 64 seconds.  The bus_time
1722  * field stores not only the upper 25 bits of the BUS_TIME register but also
1723  * the most significant bit of the cycle timer in bit 6 so that we can detect
1724  * changes in this bit.
1725  */
1726 static u32 update_bus_time(struct fw_ohci *ohci)
1727 {
1728         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1729
1730         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1731                 ohci->bus_time += 0x40;
1732
1733         return ohci->bus_time | cycle_time_seconds;
1734 }
1735
1736 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1737 {
1738         int reg;
1739
1740         mutex_lock(&ohci->phy_reg_mutex);
1741         reg = write_phy_reg(ohci, 7, port_index);
1742         if (reg >= 0)
1743                 reg = read_phy_reg(ohci, 8);
1744         mutex_unlock(&ohci->phy_reg_mutex);
1745         if (reg < 0)
1746                 return reg;
1747
1748         switch (reg & 0x0f) {
1749         case 0x06:
1750                 return 2;       /* is child node (connected to parent node) */
1751         case 0x0e:
1752                 return 3;       /* is parent node (connected to child node) */
1753         }
1754         return 1;               /* not connected */
1755 }
1756
1757 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1758         int self_id_count)
1759 {
1760         int i;
1761         u32 entry;
1762
1763         for (i = 0; i < self_id_count; i++) {
1764                 entry = ohci->self_id_buffer[i];
1765                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1766                         return -1;
1767                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1768                         return i;
1769         }
1770         return i;
1771 }
1772
1773 /*
1774  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1775  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1776  * Construct the selfID from phy register contents.
1777  * FIXME:  How to determine the selfID.i flag?
1778  */
1779 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1780 {
1781         int reg, i, pos, status;
1782         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1783         u32 self_id = 0x8040c800;
1784
1785         reg = reg_read(ohci, OHCI1394_NodeID);
1786         if (!(reg & OHCI1394_NodeID_idValid)) {
1787                 dev_notice(ohci->card.device,
1788                            "node ID not valid, new bus reset in progress\n");
1789                 return -EBUSY;
1790         }
1791         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1792
1793         reg = ohci_read_phy_reg(&ohci->card, 4);
1794         if (reg < 0)
1795                 return reg;
1796         self_id |= ((reg & 0x07) << 8); /* power class */
1797
1798         reg = ohci_read_phy_reg(&ohci->card, 1);
1799         if (reg < 0)
1800                 return reg;
1801         self_id |= ((reg & 0x3f) << 16); /* gap count */
1802
1803         for (i = 0; i < 3; i++) {
1804                 status = get_status_for_port(ohci, i);
1805                 if (status < 0)
1806                         return status;
1807                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1808         }
1809
1810         pos = get_self_id_pos(ohci, self_id, self_id_count);
1811         if (pos >= 0) {
1812                 memmove(&(ohci->self_id_buffer[pos+1]),
1813                         &(ohci->self_id_buffer[pos]),
1814                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1815                 ohci->self_id_buffer[pos] = self_id;
1816                 self_id_count++;
1817         }
1818         return self_id_count;
1819 }
1820
1821 static void bus_reset_work(struct work_struct *work)
1822 {
1823         struct fw_ohci *ohci =
1824                 container_of(work, struct fw_ohci, bus_reset_work);
1825         int self_id_count, i, j, reg;
1826         int generation, new_generation;
1827         unsigned long flags;
1828         void *free_rom = NULL;
1829         dma_addr_t free_rom_bus = 0;
1830         bool is_new_root;
1831
1832         reg = reg_read(ohci, OHCI1394_NodeID);
1833         if (!(reg & OHCI1394_NodeID_idValid)) {
1834                 dev_notice(ohci->card.device,
1835                            "node ID not valid, new bus reset in progress\n");
1836                 return;
1837         }
1838         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1839                 dev_notice(ohci->card.device, "malconfigured bus\n");
1840                 return;
1841         }
1842         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1843                                OHCI1394_NodeID_nodeNumber);
1844
1845         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1846         if (!(ohci->is_root && is_new_root))
1847                 reg_write(ohci, OHCI1394_LinkControlSet,
1848                           OHCI1394_LinkControl_cycleMaster);
1849         ohci->is_root = is_new_root;
1850
1851         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1852         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1853                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1854                 return;
1855         }
1856         /*
1857          * The count in the SelfIDCount register is the number of
1858          * bytes in the self ID receive buffer.  Since we also receive
1859          * the inverted quadlets and a header quadlet, we shift one
1860          * bit extra to get the actual number of self IDs.
1861          */
1862         self_id_count = (reg >> 3) & 0xff;
1863
1864         if (self_id_count > 252) {
1865                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1866                 return;
1867         }
1868
1869         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1870         rmb();
1871
1872         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1873                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1874                         /*
1875                          * If the invalid data looks like a cycle start packet,
1876                          * it's likely to be the result of the cycle master
1877                          * having a wrong gap count.  In this case, the self IDs
1878                          * so far are valid and should be processed so that the
1879                          * bus manager can then correct the gap count.
1880                          */
1881                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1882                                                         == 0xffff008f) {
1883                                 dev_notice(ohci->card.device,
1884                                            "ignoring spurious self IDs\n");
1885                                 self_id_count = j;
1886                                 break;
1887                         } else {
1888                                 dev_notice(ohci->card.device,
1889                                            "inconsistent self IDs\n");
1890                                 return;
1891                         }
1892                 }
1893                 ohci->self_id_buffer[j] =
1894                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1895         }
1896
1897         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1898                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1899                 if (self_id_count < 0) {
1900                         dev_notice(ohci->card.device,
1901                                    "could not construct local self ID\n");
1902                         return;
1903                 }
1904         }
1905
1906         if (self_id_count == 0) {
1907                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1908                 return;
1909         }
1910         rmb();
1911
1912         /*
1913          * Check the consistency of the self IDs we just read.  The
1914          * problem we face is that a new bus reset can start while we
1915          * read out the self IDs from the DMA buffer. If this happens,
1916          * the DMA buffer will be overwritten with new self IDs and we
1917          * will read out inconsistent data.  The OHCI specification
1918          * (section 11.2) recommends a technique similar to
1919          * linux/seqlock.h, where we remember the generation of the
1920          * self IDs in the buffer before reading them out and compare
1921          * it to the current generation after reading them out.  If
1922          * the two generations match we know we have a consistent set
1923          * of self IDs.
1924          */
1925
1926         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1927         if (new_generation != generation) {
1928                 dev_notice(ohci->card.device,
1929                            "new bus reset, discarding self ids\n");
1930                 return;
1931         }
1932
1933         /* FIXME: Document how the locking works. */
1934         spin_lock_irqsave(&ohci->lock, flags);
1935
1936         ohci->generation = -1; /* prevent AT packet queueing */
1937         context_stop(&ohci->at_request_ctx);
1938         context_stop(&ohci->at_response_ctx);
1939
1940         spin_unlock_irqrestore(&ohci->lock, flags);
1941
1942         /*
1943          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1944          * packets in the AT queues and software needs to drain them.
1945          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1946          */
1947         at_context_flush(&ohci->at_request_ctx);
1948         at_context_flush(&ohci->at_response_ctx);
1949
1950         spin_lock_irqsave(&ohci->lock, flags);
1951
1952         ohci->generation = generation;
1953         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1954
1955         if (ohci->quirks & QUIRK_RESET_PACKET)
1956                 ohci->request_generation = generation;
1957
1958         /*
1959          * This next bit is unrelated to the AT context stuff but we
1960          * have to do it under the spinlock also.  If a new config rom
1961          * was set up before this reset, the old one is now no longer
1962          * in use and we can free it. Update the config rom pointers
1963          * to point to the current config rom and clear the
1964          * next_config_rom pointer so a new update can take place.
1965          */
1966
1967         if (ohci->next_config_rom != NULL) {
1968                 if (ohci->next_config_rom != ohci->config_rom) {
1969                         free_rom      = ohci->config_rom;
1970                         free_rom_bus  = ohci->config_rom_bus;
1971                 }
1972                 ohci->config_rom      = ohci->next_config_rom;
1973                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1974                 ohci->next_config_rom = NULL;
1975
1976                 /*
1977                  * Restore config_rom image and manually update
1978                  * config_rom registers.  Writing the header quadlet
1979                  * will indicate that the config rom is ready, so we
1980                  * do that last.
1981                  */
1982                 reg_write(ohci, OHCI1394_BusOptions,
1983                           be32_to_cpu(ohci->config_rom[2]));
1984                 ohci->config_rom[0] = ohci->next_header;
1985                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1986                           be32_to_cpu(ohci->next_header));
1987         }
1988
1989 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1990         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1991         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1992 #endif
1993
1994         spin_unlock_irqrestore(&ohci->lock, flags);
1995
1996         if (free_rom)
1997                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1998                                   free_rom, free_rom_bus);
1999
2000         log_selfids(ohci, generation, self_id_count);
2001
2002         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2003                                  self_id_count, ohci->self_id_buffer,
2004                                  ohci->csr_state_setclear_abdicate);
2005         ohci->csr_state_setclear_abdicate = false;
2006 }
2007
2008 static irqreturn_t irq_handler(int irq, void *data)
2009 {
2010         struct fw_ohci *ohci = data;
2011         u32 event, iso_event;
2012         int i;
2013
2014         event = reg_read(ohci, OHCI1394_IntEventClear);
2015
2016         if (!event || !~event)
2017                 return IRQ_NONE;
2018
2019         /*
2020          * busReset and postedWriteErr must not be cleared yet
2021          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2022          */
2023         reg_write(ohci, OHCI1394_IntEventClear,
2024                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2025         log_irqs(ohci, event);
2026
2027         if (event & OHCI1394_selfIDComplete)
2028                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2029
2030         if (event & OHCI1394_RQPkt)
2031                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2032
2033         if (event & OHCI1394_RSPkt)
2034                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2035
2036         if (event & OHCI1394_reqTxComplete)
2037                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2038
2039         if (event & OHCI1394_respTxComplete)
2040                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2041
2042         if (event & OHCI1394_isochRx) {
2043                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2044                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2045
2046                 while (iso_event) {
2047                         i = ffs(iso_event) - 1;
2048                         tasklet_schedule(
2049                                 &ohci->ir_context_list[i].context.tasklet);
2050                         iso_event &= ~(1 << i);
2051                 }
2052         }
2053
2054         if (event & OHCI1394_isochTx) {
2055                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2056                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2057
2058                 while (iso_event) {
2059                         i = ffs(iso_event) - 1;
2060                         tasklet_schedule(
2061                                 &ohci->it_context_list[i].context.tasklet);
2062                         iso_event &= ~(1 << i);
2063                 }
2064         }
2065
2066         if (unlikely(event & OHCI1394_regAccessFail))
2067                 dev_err(ohci->card.device, "register access failure\n");
2068
2069         if (unlikely(event & OHCI1394_postedWriteErr)) {
2070                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2071                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2072                 reg_write(ohci, OHCI1394_IntEventClear,
2073                           OHCI1394_postedWriteErr);
2074                 if (printk_ratelimit())
2075                         dev_err(ohci->card.device, "PCI posted write error\n");
2076         }
2077
2078         if (unlikely(event & OHCI1394_cycleTooLong)) {
2079                 if (printk_ratelimit())
2080                         dev_notice(ohci->card.device,
2081                                    "isochronous cycle too long\n");
2082                 reg_write(ohci, OHCI1394_LinkControlSet,
2083                           OHCI1394_LinkControl_cycleMaster);
2084         }
2085
2086         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2087                 /*
2088                  * We need to clear this event bit in order to make
2089                  * cycleMatch isochronous I/O work.  In theory we should
2090                  * stop active cycleMatch iso contexts now and restart
2091                  * them at least two cycles later.  (FIXME?)
2092                  */
2093                 if (printk_ratelimit())
2094                         dev_notice(ohci->card.device,
2095                                    "isochronous cycle inconsistent\n");
2096         }
2097
2098         if (unlikely(event & OHCI1394_unrecoverableError))
2099                 handle_dead_contexts(ohci);
2100
2101         if (event & OHCI1394_cycle64Seconds) {
2102                 spin_lock(&ohci->lock);
2103                 update_bus_time(ohci);
2104                 spin_unlock(&ohci->lock);
2105         } else
2106                 flush_writes(ohci);
2107
2108         return IRQ_HANDLED;
2109 }
2110
2111 static int software_reset(struct fw_ohci *ohci)
2112 {
2113         u32 val;
2114         int i;
2115
2116         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2117         for (i = 0; i < 500; i++) {
2118                 val = reg_read(ohci, OHCI1394_HCControlSet);
2119                 if (!~val)
2120                         return -ENODEV; /* Card was ejected. */
2121
2122                 if (!(val & OHCI1394_HCControl_softReset))
2123                         return 0;
2124
2125                 msleep(1);
2126         }
2127
2128         return -EBUSY;
2129 }
2130
2131 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2132 {
2133         size_t size = length * 4;
2134
2135         memcpy(dest, src, size);
2136         if (size < CONFIG_ROM_SIZE)
2137                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2138 }
2139
2140 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2141 {
2142         bool enable_1394a;
2143         int ret, clear, set, offset;
2144
2145         /* Check if the driver should configure link and PHY. */
2146         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2147               OHCI1394_HCControl_programPhyEnable))
2148                 return 0;
2149
2150         /* Paranoia: check whether the PHY supports 1394a, too. */
2151         enable_1394a = false;
2152         ret = read_phy_reg(ohci, 2);
2153         if (ret < 0)
2154                 return ret;
2155         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2156                 ret = read_paged_phy_reg(ohci, 1, 8);
2157                 if (ret < 0)
2158                         return ret;
2159                 if (ret >= 1)
2160                         enable_1394a = true;
2161         }
2162
2163         if (ohci->quirks & QUIRK_NO_1394A)
2164                 enable_1394a = false;
2165
2166         /* Configure PHY and link consistently. */
2167         if (enable_1394a) {
2168                 clear = 0;
2169                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2170         } else {
2171                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2172                 set = 0;
2173         }
2174         ret = update_phy_reg(ohci, 5, clear, set);
2175         if (ret < 0)
2176                 return ret;
2177
2178         if (enable_1394a)
2179                 offset = OHCI1394_HCControlSet;
2180         else
2181                 offset = OHCI1394_HCControlClear;
2182         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2183
2184         /* Clean up: configuration has been taken care of. */
2185         reg_write(ohci, OHCI1394_HCControlClear,
2186                   OHCI1394_HCControl_programPhyEnable);
2187
2188         return 0;
2189 }
2190
2191 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2192 {
2193         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2194         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2195         int reg, i;
2196
2197         reg = read_phy_reg(ohci, 2);
2198         if (reg < 0)
2199                 return reg;
2200         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2201                 return 0;
2202
2203         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2204                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2205                 if (reg < 0)
2206                         return reg;
2207                 if (reg != id[i])
2208                         return 0;
2209         }
2210         return 1;
2211 }
2212
2213 static int ohci_enable(struct fw_card *card,
2214                        const __be32 *config_rom, size_t length)
2215 {
2216         struct fw_ohci *ohci = fw_ohci(card);
2217         struct pci_dev *dev = to_pci_dev(card->device);
2218         u32 lps, seconds, version, irqs;
2219         int i, ret;
2220
2221         if (software_reset(ohci)) {
2222                 dev_err(card->device, "failed to reset ohci card\n");
2223                 return -EBUSY;
2224         }
2225
2226         /*
2227          * Now enable LPS, which we need in order to start accessing
2228          * most of the registers.  In fact, on some cards (ALI M5251),
2229          * accessing registers in the SClk domain without LPS enabled
2230          * will lock up the machine.  Wait 50msec to make sure we have
2231          * full link enabled.  However, with some cards (well, at least
2232          * a JMicron PCIe card), we have to try again sometimes.
2233          */
2234         reg_write(ohci, OHCI1394_HCControlSet,
2235                   OHCI1394_HCControl_LPS |
2236                   OHCI1394_HCControl_postedWriteEnable);
2237         flush_writes(ohci);
2238
2239         for (lps = 0, i = 0; !lps && i < 3; i++) {
2240                 msleep(50);
2241                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2242                       OHCI1394_HCControl_LPS;
2243         }
2244
2245         if (!lps) {
2246                 dev_err(card->device, "failed to set Link Power Status\n");
2247                 return -EIO;
2248         }
2249
2250         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2251                 ret = probe_tsb41ba3d(ohci);
2252                 if (ret < 0)
2253                         return ret;
2254                 if (ret)
2255                         dev_notice(card->device, "local TSB41BA3D phy\n");
2256                 else
2257                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2258         }
2259
2260         reg_write(ohci, OHCI1394_HCControlClear,
2261                   OHCI1394_HCControl_noByteSwapData);
2262
2263         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2264         reg_write(ohci, OHCI1394_LinkControlSet,
2265                   OHCI1394_LinkControl_cycleTimerEnable |
2266                   OHCI1394_LinkControl_cycleMaster);
2267
2268         reg_write(ohci, OHCI1394_ATRetries,
2269                   OHCI1394_MAX_AT_REQ_RETRIES |
2270                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2271                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2272                   (200 << 16));
2273
2274         seconds = lower_32_bits(get_seconds());
2275         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2276         ohci->bus_time = seconds & ~0x3f;
2277
2278         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2279         if (version >= OHCI_VERSION_1_1) {
2280                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2281                           0xfffffffe);
2282                 card->broadcast_channel_auto_allocated = true;
2283         }
2284
2285         /* Get implemented bits of the priority arbitration request counter. */
2286         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2287         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2288         reg_write(ohci, OHCI1394_FairnessControl, 0);
2289         card->priority_budget_implemented = ohci->pri_req_max != 0;
2290
2291         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2292         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2293         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2294
2295         ret = configure_1394a_enhancements(ohci);
2296         if (ret < 0)
2297                 return ret;
2298
2299         /* Activate link_on bit and contender bit in our self ID packets.*/
2300         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2301         if (ret < 0)
2302                 return ret;
2303
2304         /*
2305          * When the link is not yet enabled, the atomic config rom
2306          * update mechanism described below in ohci_set_config_rom()
2307          * is not active.  We have to update ConfigRomHeader and
2308          * BusOptions manually, and the write to ConfigROMmap takes
2309          * effect immediately.  We tie this to the enabling of the
2310          * link, so we have a valid config rom before enabling - the
2311          * OHCI requires that ConfigROMhdr and BusOptions have valid
2312          * values before enabling.
2313          *
2314          * However, when the ConfigROMmap is written, some controllers
2315          * always read back quadlets 0 and 2 from the config rom to
2316          * the ConfigRomHeader and BusOptions registers on bus reset.
2317          * They shouldn't do that in this initial case where the link
2318          * isn't enabled.  This means we have to use the same
2319          * workaround here, setting the bus header to 0 and then write
2320          * the right values in the bus reset tasklet.
2321          */
2322
2323         if (config_rom) {
2324                 ohci->next_config_rom =
2325                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2326                                            &ohci->next_config_rom_bus,
2327                                            GFP_KERNEL);
2328                 if (ohci->next_config_rom == NULL)
2329                         return -ENOMEM;
2330
2331                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2332         } else {
2333                 /*
2334                  * In the suspend case, config_rom is NULL, which
2335                  * means that we just reuse the old config rom.
2336                  */
2337                 ohci->next_config_rom = ohci->config_rom;
2338                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2339         }
2340
2341         ohci->next_header = ohci->next_config_rom[0];
2342         ohci->next_config_rom[0] = 0;
2343         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2344         reg_write(ohci, OHCI1394_BusOptions,
2345                   be32_to_cpu(ohci->next_config_rom[2]));
2346         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2347
2348         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2349
2350         if (!(ohci->quirks & QUIRK_NO_MSI))
2351                 pci_enable_msi(dev);
2352         if (request_irq(dev->irq, irq_handler,
2353                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2354                         ohci_driver_name, ohci)) {
2355                 dev_err(card->device, "failed to allocate interrupt %d\n",
2356                         dev->irq);
2357                 pci_disable_msi(dev);
2358
2359                 if (config_rom) {
2360                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2361                                           ohci->next_config_rom,
2362                                           ohci->next_config_rom_bus);
2363                         ohci->next_config_rom = NULL;
2364                 }
2365                 return -EIO;
2366         }
2367
2368         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2369                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2370                 OHCI1394_isochTx | OHCI1394_isochRx |
2371                 OHCI1394_postedWriteErr |
2372                 OHCI1394_selfIDComplete |
2373                 OHCI1394_regAccessFail |
2374                 OHCI1394_cycle64Seconds |
2375                 OHCI1394_cycleInconsistent |
2376                 OHCI1394_unrecoverableError |
2377                 OHCI1394_cycleTooLong |
2378                 OHCI1394_masterIntEnable;
2379         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2380                 irqs |= OHCI1394_busReset;
2381         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2382
2383         reg_write(ohci, OHCI1394_HCControlSet,
2384                   OHCI1394_HCControl_linkEnable |
2385                   OHCI1394_HCControl_BIBimageValid);
2386
2387         reg_write(ohci, OHCI1394_LinkControlSet,
2388                   OHCI1394_LinkControl_rcvSelfID |
2389                   OHCI1394_LinkControl_rcvPhyPkt);
2390
2391         ar_context_run(&ohci->ar_request_ctx);
2392         ar_context_run(&ohci->ar_response_ctx);
2393
2394         flush_writes(ohci);
2395
2396         /* We are ready to go, reset bus to finish initialization. */
2397         fw_schedule_bus_reset(&ohci->card, false, true);
2398
2399         return 0;
2400 }
2401
2402 static int ohci_set_config_rom(struct fw_card *card,
2403                                const __be32 *config_rom, size_t length)
2404 {
2405         struct fw_ohci *ohci;
2406         unsigned long flags;
2407         __be32 *next_config_rom;
2408         dma_addr_t uninitialized_var(next_config_rom_bus);
2409
2410         ohci = fw_ohci(card);
2411
2412         /*
2413          * When the OHCI controller is enabled, the config rom update
2414          * mechanism is a bit tricky, but easy enough to use.  See
2415          * section 5.5.6 in the OHCI specification.
2416          *
2417          * The OHCI controller caches the new config rom address in a
2418          * shadow register (ConfigROMmapNext) and needs a bus reset
2419          * for the changes to take place.  When the bus reset is
2420          * detected, the controller loads the new values for the
2421          * ConfigRomHeader and BusOptions registers from the specified
2422          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2423          * shadow register. All automatically and atomically.
2424          *
2425          * Now, there's a twist to this story.  The automatic load of
2426          * ConfigRomHeader and BusOptions doesn't honor the
2427          * noByteSwapData bit, so with a be32 config rom, the
2428          * controller will load be32 values in to these registers
2429          * during the atomic update, even on litte endian
2430          * architectures.  The workaround we use is to put a 0 in the
2431          * header quadlet; 0 is endian agnostic and means that the
2432          * config rom isn't ready yet.  In the bus reset tasklet we
2433          * then set up the real values for the two registers.
2434          *
2435          * We use ohci->lock to avoid racing with the code that sets
2436          * ohci->next_config_rom to NULL (see bus_reset_work).
2437          */
2438
2439         next_config_rom =
2440                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2441                                    &next_config_rom_bus, GFP_KERNEL);
2442         if (next_config_rom == NULL)
2443                 return -ENOMEM;
2444
2445         spin_lock_irqsave(&ohci->lock, flags);
2446
2447         /*
2448          * If there is not an already pending config_rom update,
2449          * push our new allocation into the ohci->next_config_rom
2450          * and then mark the local variable as null so that we
2451          * won't deallocate the new buffer.
2452          *
2453          * OTOH, if there is a pending config_rom update, just
2454          * use that buffer with the new config_rom data, and
2455          * let this routine free the unused DMA allocation.
2456          */
2457
2458         if (ohci->next_config_rom == NULL) {
2459                 ohci->next_config_rom = next_config_rom;
2460                 ohci->next_config_rom_bus = next_config_rom_bus;
2461                 next_config_rom = NULL;
2462         }
2463
2464         copy_config_rom(ohci->next_config_rom, config_rom, length);
2465
2466         ohci->next_header = config_rom[0];
2467         ohci->next_config_rom[0] = 0;
2468
2469         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2470
2471         spin_unlock_irqrestore(&ohci->lock, flags);
2472
2473         /* If we didn't use the DMA allocation, delete it. */
2474         if (next_config_rom != NULL)
2475                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2476                                   next_config_rom, next_config_rom_bus);
2477
2478         /*
2479          * Now initiate a bus reset to have the changes take
2480          * effect. We clean up the old config rom memory and DMA
2481          * mappings in the bus reset tasklet, since the OHCI
2482          * controller could need to access it before the bus reset
2483          * takes effect.
2484          */
2485
2486         fw_schedule_bus_reset(&ohci->card, true, true);
2487
2488         return 0;
2489 }
2490
2491 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2492 {
2493         struct fw_ohci *ohci = fw_ohci(card);
2494
2495         at_context_transmit(&ohci->at_request_ctx, packet);
2496 }
2497
2498 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2499 {
2500         struct fw_ohci *ohci = fw_ohci(card);
2501
2502         at_context_transmit(&ohci->at_response_ctx, packet);
2503 }
2504
2505 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2506 {
2507         struct fw_ohci *ohci = fw_ohci(card);
2508         struct context *ctx = &ohci->at_request_ctx;
2509         struct driver_data *driver_data = packet->driver_data;
2510         int ret = -ENOENT;
2511
2512         tasklet_disable(&ctx->tasklet);
2513
2514         if (packet->ack != 0)
2515                 goto out;
2516
2517         if (packet->payload_mapped)
2518                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2519                                  packet->payload_length, DMA_TO_DEVICE);
2520
2521         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2522         driver_data->packet = NULL;
2523         packet->ack = RCODE_CANCELLED;
2524         packet->callback(packet, &ohci->card, packet->ack);
2525         ret = 0;
2526  out:
2527         tasklet_enable(&ctx->tasklet);
2528
2529         return ret;
2530 }
2531
2532 static int ohci_enable_phys_dma(struct fw_card *card,
2533                                 int node_id, int generation)
2534 {
2535 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2536         return 0;
2537 #else
2538         struct fw_ohci *ohci = fw_ohci(card);
2539         unsigned long flags;
2540         int n, ret = 0;
2541
2542         /*
2543          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2544          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2545          */
2546
2547         spin_lock_irqsave(&ohci->lock, flags);
2548
2549         if (ohci->generation != generation) {
2550                 ret = -ESTALE;
2551                 goto out;
2552         }
2553
2554         /*
2555          * Note, if the node ID contains a non-local bus ID, physical DMA is
2556          * enabled for _all_ nodes on remote buses.
2557          */
2558
2559         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2560         if (n < 32)
2561                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2562         else
2563                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2564
2565         flush_writes(ohci);
2566  out:
2567         spin_unlock_irqrestore(&ohci->lock, flags);
2568
2569         return ret;
2570 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2571 }
2572
2573 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2574 {
2575         struct fw_ohci *ohci = fw_ohci(card);
2576         unsigned long flags;
2577         u32 value;
2578
2579         switch (csr_offset) {
2580         case CSR_STATE_CLEAR:
2581         case CSR_STATE_SET:
2582                 if (ohci->is_root &&
2583                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2584                      OHCI1394_LinkControl_cycleMaster))
2585                         value = CSR_STATE_BIT_CMSTR;
2586                 else
2587                         value = 0;
2588                 if (ohci->csr_state_setclear_abdicate)
2589                         value |= CSR_STATE_BIT_ABDICATE;
2590
2591                 return value;
2592
2593         case CSR_NODE_IDS:
2594                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2595
2596         case CSR_CYCLE_TIME:
2597                 return get_cycle_time(ohci);
2598
2599         case CSR_BUS_TIME:
2600                 /*
2601                  * We might be called just after the cycle timer has wrapped
2602                  * around but just before the cycle64Seconds handler, so we
2603                  * better check here, too, if the bus time needs to be updated.
2604                  */
2605                 spin_lock_irqsave(&ohci->lock, flags);
2606                 value = update_bus_time(ohci);
2607                 spin_unlock_irqrestore(&ohci->lock, flags);
2608                 return value;
2609
2610         case CSR_BUSY_TIMEOUT:
2611                 value = reg_read(ohci, OHCI1394_ATRetries);
2612                 return (value >> 4) & 0x0ffff00f;
2613
2614         case CSR_PRIORITY_BUDGET:
2615                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2616                         (ohci->pri_req_max << 8);
2617
2618         default:
2619                 WARN_ON(1);
2620                 return 0;
2621         }
2622 }
2623
2624 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2625 {
2626         struct fw_ohci *ohci = fw_ohci(card);
2627         unsigned long flags;
2628
2629         switch (csr_offset) {
2630         case CSR_STATE_CLEAR:
2631                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2632                         reg_write(ohci, OHCI1394_LinkControlClear,
2633                                   OHCI1394_LinkControl_cycleMaster);
2634                         flush_writes(ohci);
2635                 }
2636                 if (value & CSR_STATE_BIT_ABDICATE)
2637                         ohci->csr_state_setclear_abdicate = false;
2638                 break;
2639
2640         case CSR_STATE_SET:
2641                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2642                         reg_write(ohci, OHCI1394_LinkControlSet,
2643                                   OHCI1394_LinkControl_cycleMaster);
2644                         flush_writes(ohci);
2645                 }
2646                 if (value & CSR_STATE_BIT_ABDICATE)
2647                         ohci->csr_state_setclear_abdicate = true;
2648                 break;
2649
2650         case CSR_NODE_IDS:
2651                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2652                 flush_writes(ohci);
2653                 break;
2654
2655         case CSR_CYCLE_TIME:
2656                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2657                 reg_write(ohci, OHCI1394_IntEventSet,
2658                           OHCI1394_cycleInconsistent);
2659                 flush_writes(ohci);
2660                 break;
2661
2662         case CSR_BUS_TIME:
2663                 spin_lock_irqsave(&ohci->lock, flags);
2664                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2665                 spin_unlock_irqrestore(&ohci->lock, flags);
2666                 break;
2667
2668         case CSR_BUSY_TIMEOUT:
2669                 value = (value & 0xf) | ((value & 0xf) << 4) |
2670                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2671                 reg_write(ohci, OHCI1394_ATRetries, value);
2672                 flush_writes(ohci);
2673                 break;
2674
2675         case CSR_PRIORITY_BUDGET:
2676                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2677                 flush_writes(ohci);
2678                 break;
2679
2680         default:
2681                 WARN_ON(1);
2682                 break;
2683         }
2684 }
2685
2686 static void flush_iso_completions(struct iso_context *ctx)
2687 {
2688         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2689                               ctx->header_length, ctx->header,
2690                               ctx->base.callback_data);
2691         ctx->header_length = 0;
2692 }
2693
2694 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2695 {
2696         u32 *ctx_hdr;
2697
2698         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE)
2699                 flush_iso_completions(ctx);
2700
2701         ctx_hdr = ctx->header + ctx->header_length;
2702         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2703
2704         /*
2705          * The two iso header quadlets are byteswapped to little
2706          * endian by the controller, but we want to present them
2707          * as big endian for consistency with the bus endianness.
2708          */
2709         if (ctx->base.header_size > 0)
2710                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2711         if (ctx->base.header_size > 4)
2712                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2713         if (ctx->base.header_size > 8)
2714                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2715         ctx->header_length += ctx->base.header_size;
2716 }
2717
2718 static int handle_ir_packet_per_buffer(struct context *context,
2719                                        struct descriptor *d,
2720                                        struct descriptor *last)
2721 {
2722         struct iso_context *ctx =
2723                 container_of(context, struct iso_context, context);
2724         struct descriptor *pd;
2725         u32 buffer_dma;
2726
2727         for (pd = d; pd <= last; pd++)
2728                 if (pd->transfer_status)
2729                         break;
2730         if (pd > last)
2731                 /* Descriptor(s) not done yet, stop iteration */
2732                 return 0;
2733
2734         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2735                 d++;
2736                 buffer_dma = le32_to_cpu(d->data_address);
2737                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2738                                               buffer_dma & PAGE_MASK,
2739                                               buffer_dma & ~PAGE_MASK,
2740                                               le16_to_cpu(d->req_count),
2741                                               DMA_FROM_DEVICE);
2742         }
2743
2744         copy_iso_headers(ctx, (u32 *) (last + 1));
2745
2746         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2747                 flush_iso_completions(ctx);
2748
2749         return 1;
2750 }
2751
2752 /* d == last because each descriptor block is only a single descriptor. */
2753 static int handle_ir_buffer_fill(struct context *context,
2754                                  struct descriptor *d,
2755                                  struct descriptor *last)
2756 {
2757         struct iso_context *ctx =
2758                 container_of(context, struct iso_context, context);
2759         unsigned int req_count, res_count, completed;
2760         u32 buffer_dma;
2761
2762         req_count = le16_to_cpu(last->req_count);
2763         res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2764         completed = req_count - res_count;
2765         buffer_dma = le32_to_cpu(last->data_address);
2766
2767         if (completed > 0) {
2768                 ctx->mc_buffer_bus = buffer_dma;
2769                 ctx->mc_completed = completed;
2770         }
2771
2772         if (res_count != 0)
2773                 /* Descriptor(s) not done yet, stop iteration */
2774                 return 0;
2775
2776         dma_sync_single_range_for_cpu(context->ohci->card.device,
2777                                       buffer_dma & PAGE_MASK,
2778                                       buffer_dma & ~PAGE_MASK,
2779                                       completed, DMA_FROM_DEVICE);
2780
2781         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2782                 ctx->base.callback.mc(&ctx->base,
2783                                       buffer_dma + completed,
2784                                       ctx->base.callback_data);
2785                 ctx->mc_completed = 0;
2786         }
2787
2788         return 1;
2789 }
2790
2791 static void flush_ir_buffer_fill(struct iso_context *ctx)
2792 {
2793         dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2794                                       ctx->mc_buffer_bus & PAGE_MASK,
2795                                       ctx->mc_buffer_bus & ~PAGE_MASK,
2796                                       ctx->mc_completed, DMA_FROM_DEVICE);
2797
2798         ctx->base.callback.mc(&ctx->base,
2799                               ctx->mc_buffer_bus + ctx->mc_completed,
2800                               ctx->base.callback_data);
2801         ctx->mc_completed = 0;
2802 }
2803
2804 static inline void sync_it_packet_for_cpu(struct context *context,
2805                                           struct descriptor *pd)
2806 {
2807         __le16 control;
2808         u32 buffer_dma;
2809
2810         /* only packets beginning with OUTPUT_MORE* have data buffers */
2811         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2812                 return;
2813
2814         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2815         pd += 2;
2816
2817         /*
2818          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2819          * data buffer is in the context program's coherent page and must not
2820          * be synced.
2821          */
2822         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2823             (context->current_bus          & PAGE_MASK)) {
2824                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2825                         return;
2826                 pd++;
2827         }
2828
2829         do {
2830                 buffer_dma = le32_to_cpu(pd->data_address);
2831                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2832                                               buffer_dma & PAGE_MASK,
2833                                               buffer_dma & ~PAGE_MASK,
2834                                               le16_to_cpu(pd->req_count),
2835                                               DMA_TO_DEVICE);
2836                 control = pd->control;
2837                 pd++;
2838         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2839 }
2840
2841 static int handle_it_packet(struct context *context,
2842                             struct descriptor *d,
2843                             struct descriptor *last)
2844 {
2845         struct iso_context *ctx =
2846                 container_of(context, struct iso_context, context);
2847         struct descriptor *pd;
2848         __be32 *ctx_hdr;
2849
2850         for (pd = d; pd <= last; pd++)
2851                 if (pd->transfer_status)
2852                         break;
2853         if (pd > last)
2854                 /* Descriptor(s) not done yet, stop iteration */
2855                 return 0;
2856
2857         sync_it_packet_for_cpu(context, d);
2858
2859         if (ctx->header_length + 4 > PAGE_SIZE)
2860                 flush_iso_completions(ctx);
2861
2862         ctx_hdr = ctx->header + ctx->header_length;
2863         ctx->last_timestamp = le16_to_cpu(last->res_count);
2864         /* Present this value as big-endian to match the receive code */
2865         *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2866                                le16_to_cpu(pd->res_count));
2867         ctx->header_length += 4;
2868
2869         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2870                 flush_iso_completions(ctx);
2871
2872         return 1;
2873 }
2874
2875 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2876 {
2877         u32 hi = channels >> 32, lo = channels;
2878
2879         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2880         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2881         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2882         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2883         mmiowb();
2884         ohci->mc_channels = channels;
2885 }
2886
2887 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2888                                 int type, int channel, size_t header_size)
2889 {
2890         struct fw_ohci *ohci = fw_ohci(card);
2891         struct iso_context *uninitialized_var(ctx);
2892         descriptor_callback_t uninitialized_var(callback);
2893         u64 *uninitialized_var(channels);
2894         u32 *uninitialized_var(mask), uninitialized_var(regs);
2895         unsigned long flags;
2896         int index, ret = -EBUSY;
2897
2898         spin_lock_irqsave(&ohci->lock, flags);
2899
2900         switch (type) {
2901         case FW_ISO_CONTEXT_TRANSMIT:
2902                 mask     = &ohci->it_context_mask;
2903                 callback = handle_it_packet;
2904                 index    = ffs(*mask) - 1;
2905                 if (index >= 0) {
2906                         *mask &= ~(1 << index);
2907                         regs = OHCI1394_IsoXmitContextBase(index);
2908                         ctx  = &ohci->it_context_list[index];
2909                 }
2910                 break;
2911
2912         case FW_ISO_CONTEXT_RECEIVE:
2913                 channels = &ohci->ir_context_channels;
2914                 mask     = &ohci->ir_context_mask;
2915                 callback = handle_ir_packet_per_buffer;
2916                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2917                 if (index >= 0) {
2918                         *channels &= ~(1ULL << channel);
2919                         *mask     &= ~(1 << index);
2920                         regs = OHCI1394_IsoRcvContextBase(index);
2921                         ctx  = &ohci->ir_context_list[index];
2922                 }
2923                 break;
2924
2925         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2926                 mask     = &ohci->ir_context_mask;
2927                 callback = handle_ir_buffer_fill;
2928                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2929                 if (index >= 0) {
2930                         ohci->mc_allocated = true;
2931                         *mask &= ~(1 << index);
2932                         regs = OHCI1394_IsoRcvContextBase(index);
2933                         ctx  = &ohci->ir_context_list[index];
2934                 }
2935                 break;
2936
2937         default:
2938                 index = -1;
2939                 ret = -ENOSYS;
2940         }
2941
2942         spin_unlock_irqrestore(&ohci->lock, flags);
2943
2944         if (index < 0)
2945                 return ERR_PTR(ret);
2946
2947         memset(ctx, 0, sizeof(*ctx));
2948         ctx->header_length = 0;
2949         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2950         if (ctx->header == NULL) {
2951                 ret = -ENOMEM;
2952                 goto out;
2953         }
2954         ret = context_init(&ctx->context, ohci, regs, callback);
2955         if (ret < 0)
2956                 goto out_with_header;
2957
2958         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
2959                 set_multichannel_mask(ohci, 0);
2960                 ctx->mc_completed = 0;
2961         }
2962
2963         return &ctx->base;
2964
2965  out_with_header:
2966         free_page((unsigned long)ctx->header);
2967  out:
2968         spin_lock_irqsave(&ohci->lock, flags);
2969
2970         switch (type) {
2971         case FW_ISO_CONTEXT_RECEIVE:
2972                 *channels |= 1ULL << channel;
2973                 break;
2974
2975         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2976                 ohci->mc_allocated = false;
2977                 break;
2978         }
2979         *mask |= 1 << index;
2980
2981         spin_unlock_irqrestore(&ohci->lock, flags);
2982
2983         return ERR_PTR(ret);
2984 }
2985
2986 static int ohci_start_iso(struct fw_iso_context *base,
2987                           s32 cycle, u32 sync, u32 tags)
2988 {
2989         struct iso_context *ctx = container_of(base, struct iso_context, base);
2990         struct fw_ohci *ohci = ctx->context.ohci;
2991         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2992         int index;
2993
2994         /* the controller cannot start without any queued packets */
2995         if (ctx->context.last->branch_address == 0)
2996                 return -ENODATA;
2997
2998         switch (ctx->base.type) {
2999         case FW_ISO_CONTEXT_TRANSMIT:
3000                 index = ctx - ohci->it_context_list;
3001                 match = 0;
3002                 if (cycle >= 0)
3003                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3004                                 (cycle & 0x7fff) << 16;
3005
3006                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3007                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3008                 context_run(&ctx->context, match);
3009                 break;
3010
3011         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3012                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3013                 /* fall through */
3014         case FW_ISO_CONTEXT_RECEIVE:
3015                 index = ctx - ohci->ir_context_list;
3016                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3017                 if (cycle >= 0) {
3018                         match |= (cycle & 0x07fff) << 12;
3019                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3020                 }
3021
3022                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3023                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3024                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3025                 context_run(&ctx->context, control);
3026
3027                 ctx->sync = sync;
3028                 ctx->tags = tags;
3029
3030                 break;
3031         }
3032
3033         return 0;
3034 }
3035
3036 static int ohci_stop_iso(struct fw_iso_context *base)
3037 {
3038         struct fw_ohci *ohci = fw_ohci(base->card);
3039         struct iso_context *ctx = container_of(base, struct iso_context, base);
3040         int index;
3041
3042         switch (ctx->base.type) {
3043         case FW_ISO_CONTEXT_TRANSMIT:
3044                 index = ctx - ohci->it_context_list;
3045                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3046                 break;
3047
3048         case FW_ISO_CONTEXT_RECEIVE:
3049         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3050                 index = ctx - ohci->ir_context_list;
3051                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3052                 break;
3053         }
3054         flush_writes(ohci);
3055         context_stop(&ctx->context);
3056         tasklet_kill(&ctx->context.tasklet);
3057
3058         return 0;
3059 }
3060
3061 static void ohci_free_iso_context(struct fw_iso_context *base)
3062 {
3063         struct fw_ohci *ohci = fw_ohci(base->card);
3064         struct iso_context *ctx = container_of(base, struct iso_context, base);
3065         unsigned long flags;
3066         int index;
3067
3068         ohci_stop_iso(base);
3069         context_release(&ctx->context);
3070         free_page((unsigned long)ctx->header);
3071
3072         spin_lock_irqsave(&ohci->lock, flags);
3073
3074         switch (base->type) {
3075         case FW_ISO_CONTEXT_TRANSMIT:
3076                 index = ctx - ohci->it_context_list;
3077                 ohci->it_context_mask |= 1 << index;
3078                 break;
3079
3080         case FW_ISO_CONTEXT_RECEIVE:
3081                 index = ctx - ohci->ir_context_list;
3082                 ohci->ir_context_mask |= 1 << index;
3083                 ohci->ir_context_channels |= 1ULL << base->channel;
3084                 break;
3085
3086         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3087                 index = ctx - ohci->ir_context_list;
3088                 ohci->ir_context_mask |= 1 << index;
3089                 ohci->ir_context_channels |= ohci->mc_channels;
3090                 ohci->mc_channels = 0;
3091                 ohci->mc_allocated = false;
3092                 break;
3093         }
3094
3095         spin_unlock_irqrestore(&ohci->lock, flags);
3096 }
3097
3098 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3099 {
3100         struct fw_ohci *ohci = fw_ohci(base->card);
3101         unsigned long flags;
3102         int ret;
3103
3104         switch (base->type) {
3105         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3106
3107                 spin_lock_irqsave(&ohci->lock, flags);
3108
3109                 /* Don't allow multichannel to grab other contexts' channels. */
3110                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3111                         *channels = ohci->ir_context_channels;
3112                         ret = -EBUSY;
3113                 } else {
3114                         set_multichannel_mask(ohci, *channels);
3115                         ret = 0;
3116                 }
3117
3118                 spin_unlock_irqrestore(&ohci->lock, flags);
3119
3120                 break;
3121         default:
3122                 ret = -EINVAL;
3123         }
3124
3125         return ret;
3126 }
3127
3128 #ifdef CONFIG_PM
3129 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3130 {
3131         int i;
3132         struct iso_context *ctx;
3133
3134         for (i = 0 ; i < ohci->n_ir ; i++) {
3135                 ctx = &ohci->ir_context_list[i];
3136                 if (ctx->context.running)
3137                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3138         }
3139
3140         for (i = 0 ; i < ohci->n_it ; i++) {
3141                 ctx = &ohci->it_context_list[i];
3142                 if (ctx->context.running)
3143                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3144         }
3145 }
3146 #endif
3147
3148 static int queue_iso_transmit(struct iso_context *ctx,
3149                               struct fw_iso_packet *packet,
3150                               struct fw_iso_buffer *buffer,
3151                               unsigned long payload)
3152 {
3153         struct descriptor *d, *last, *pd;
3154         struct fw_iso_packet *p;
3155         __le32 *header;
3156         dma_addr_t d_bus, page_bus;
3157         u32 z, header_z, payload_z, irq;
3158         u32 payload_index, payload_end_index, next_page_index;
3159         int page, end_page, i, length, offset;
3160
3161         p = packet;
3162         payload_index = payload;
3163
3164         if (p->skip)
3165                 z = 1;
3166         else
3167                 z = 2;
3168         if (p->header_length > 0)
3169                 z++;
3170
3171         /* Determine the first page the payload isn't contained in. */
3172         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3173         if (p->payload_length > 0)
3174                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3175         else
3176                 payload_z = 0;
3177
3178         z += payload_z;
3179
3180         /* Get header size in number of descriptors. */
3181         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3182
3183         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3184         if (d == NULL)
3185                 return -ENOMEM;
3186
3187         if (!p->skip) {
3188                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3189                 d[0].req_count = cpu_to_le16(8);
3190                 /*
3191                  * Link the skip address to this descriptor itself.  This causes
3192                  * a context to skip a cycle whenever lost cycles or FIFO
3193                  * overruns occur, without dropping the data.  The application
3194                  * should then decide whether this is an error condition or not.
3195                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3196                  */
3197                 d[0].branch_address = cpu_to_le32(d_bus | z);
3198
3199                 header = (__le32 *) &d[1];
3200                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3201                                         IT_HEADER_TAG(p->tag) |
3202                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3203                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3204                                         IT_HEADER_SPEED(ctx->base.speed));
3205                 header[1] =
3206                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3207                                                           p->payload_length));
3208         }
3209
3210         if (p->header_length > 0) {
3211                 d[2].req_count    = cpu_to_le16(p->header_length);
3212                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3213                 memcpy(&d[z], p->header, p->header_length);
3214         }
3215
3216         pd = d + z - payload_z;
3217         payload_end_index = payload_index + p->payload_length;
3218         for (i = 0; i < payload_z; i++) {
3219                 page               = payload_index >> PAGE_SHIFT;
3220                 offset             = payload_index & ~PAGE_MASK;
3221                 next_page_index    = (page + 1) << PAGE_SHIFT;
3222                 length             =
3223                         min(next_page_index, payload_end_index) - payload_index;
3224                 pd[i].req_count    = cpu_to_le16(length);
3225
3226                 page_bus = page_private(buffer->pages[page]);
3227                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3228
3229                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3230                                                  page_bus, offset, length,
3231                                                  DMA_TO_DEVICE);
3232
3233                 payload_index += length;
3234         }
3235
3236         if (p->interrupt)
3237                 irq = DESCRIPTOR_IRQ_ALWAYS;
3238         else
3239                 irq = DESCRIPTOR_NO_IRQ;
3240
3241         last = z == 2 ? d : d + z - 1;
3242         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3243                                      DESCRIPTOR_STATUS |
3244                                      DESCRIPTOR_BRANCH_ALWAYS |
3245                                      irq);
3246
3247         context_append(&ctx->context, d, z, header_z);
3248
3249         return 0;
3250 }
3251
3252 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3253                                        struct fw_iso_packet *packet,
3254                                        struct fw_iso_buffer *buffer,
3255                                        unsigned long payload)
3256 {
3257         struct device *device = ctx->context.ohci->card.device;
3258         struct descriptor *d, *pd;
3259         dma_addr_t d_bus, page_bus;
3260         u32 z, header_z, rest;
3261         int i, j, length;
3262         int page, offset, packet_count, header_size, payload_per_buffer;
3263
3264         /*
3265          * The OHCI controller puts the isochronous header and trailer in the
3266          * buffer, so we need at least 8 bytes.
3267          */
3268         packet_count = packet->header_length / ctx->base.header_size;
3269         header_size  = max(ctx->base.header_size, (size_t)8);
3270
3271         /* Get header size in number of descriptors. */
3272         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3273         page     = payload >> PAGE_SHIFT;
3274         offset   = payload & ~PAGE_MASK;
3275         payload_per_buffer = packet->payload_length / packet_count;
3276
3277         for (i = 0; i < packet_count; i++) {
3278                 /* d points to the header descriptor */
3279                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3280                 d = context_get_descriptors(&ctx->context,