]> git.openfabrics.org - ~shefty/rdma-dev.git/blob - drivers/firewire/ohci.c
ded0c9bf96f44cf62216d4ef4e76c06ac15e24f5
[~shefty/rdma-dev.git] / drivers / firewire / ohci.c
1 /*
2  * Driver for OHCI 1394 controllers
3  *
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45
46 #include <asm/byteorder.h>
47 #include <asm/page.h>
48 #include <asm/system.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define DESCRIPTOR_OUTPUT_MORE          0
58 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
59 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
60 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
61 #define DESCRIPTOR_STATUS               (1 << 11)
62 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
63 #define DESCRIPTOR_PING                 (1 << 7)
64 #define DESCRIPTOR_YY                   (1 << 6)
65 #define DESCRIPTOR_NO_IRQ               (0 << 4)
66 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
67 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
68 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
69 #define DESCRIPTOR_WAIT                 (3 << 0)
70
71 struct descriptor {
72         __le16 req_count;
73         __le16 control;
74         __le32 data_address;
75         __le32 branch_address;
76         __le16 res_count;
77         __le16 transfer_status;
78 } __attribute__((aligned(16)));
79
80 #define CONTROL_SET(regs)       (regs)
81 #define CONTROL_CLEAR(regs)     ((regs) + 4)
82 #define COMMAND_PTR(regs)       ((regs) + 12)
83 #define CONTEXT_MATCH(regs)     ((regs) + 16)
84
85 #define AR_BUFFER_SIZE  (32*1024)
86 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87 /* we need at least two pages for proper list management */
88 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90 #define MAX_ASYNC_PAYLOAD       4096
91 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
92 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
93
94 struct ar_context {
95         struct fw_ohci *ohci;
96         struct page *pages[AR_BUFFERS];
97         void *buffer;
98         struct descriptor *descriptors;
99         dma_addr_t descriptors_bus;
100         void *pointer;
101         unsigned int last_buffer_index;
102         u32 regs;
103         struct tasklet_struct tasklet;
104 };
105
106 struct context;
107
108 typedef int (*descriptor_callback_t)(struct context *ctx,
109                                      struct descriptor *d,
110                                      struct descriptor *last);
111
112 /*
113  * A buffer that contains a block of DMA-able coherent memory used for
114  * storing a portion of a DMA descriptor program.
115  */
116 struct descriptor_buffer {
117         struct list_head list;
118         dma_addr_t buffer_bus;
119         size_t buffer_size;
120         size_t used;
121         struct descriptor buffer[0];
122 };
123
124 struct context {
125         struct fw_ohci *ohci;
126         u32 regs;
127         int total_allocation;
128         bool running;
129         bool flushing;
130
131         /*
132          * List of page-sized buffers for storing DMA descriptors.
133          * Head of list contains buffers in use and tail of list contains
134          * free buffers.
135          */
136         struct list_head buffer_list;
137
138         /*
139          * Pointer to a buffer inside buffer_list that contains the tail
140          * end of the current DMA program.
141          */
142         struct descriptor_buffer *buffer_tail;
143
144         /*
145          * The descriptor containing the branch address of the first
146          * descriptor that has not yet been filled by the device.
147          */
148         struct descriptor *last;
149
150         /*
151          * The last descriptor in the DMA program.  It contains the branch
152          * address that must be updated upon appending a new descriptor.
153          */
154         struct descriptor *prev;
155
156         descriptor_callback_t callback;
157
158         struct tasklet_struct tasklet;
159 };
160
161 #define IT_HEADER_SY(v)          ((v) <<  0)
162 #define IT_HEADER_TCODE(v)       ((v) <<  4)
163 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
164 #define IT_HEADER_TAG(v)         ((v) << 14)
165 #define IT_HEADER_SPEED(v)       ((v) << 16)
166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
167
168 struct iso_context {
169         struct fw_iso_context base;
170         struct context context;
171         int excess_bytes;
172         void *header;
173         size_t header_length;
174
175         u8 sync;
176         u8 tags;
177 };
178
179 #define CONFIG_ROM_SIZE 1024
180
181 struct fw_ohci {
182         struct fw_card card;
183
184         __iomem char *registers;
185         int node_id;
186         int generation;
187         int request_generation; /* for timestamping incoming requests */
188         unsigned quirks;
189         unsigned int pri_req_max;
190         u32 bus_time;
191         bool is_root;
192         bool csr_state_setclear_abdicate;
193         int n_ir;
194         int n_it;
195         /*
196          * Spinlock for accessing fw_ohci data.  Never call out of
197          * this driver with this lock held.
198          */
199         spinlock_t lock;
200
201         struct mutex phy_reg_mutex;
202
203         void *misc_buffer;
204         dma_addr_t misc_buffer_bus;
205
206         struct ar_context ar_request_ctx;
207         struct ar_context ar_response_ctx;
208         struct context at_request_ctx;
209         struct context at_response_ctx;
210
211         u32 it_context_support;
212         u32 it_context_mask;     /* unoccupied IT contexts */
213         struct iso_context *it_context_list;
214         u64 ir_context_channels; /* unoccupied channels */
215         u32 ir_context_support;
216         u32 ir_context_mask;     /* unoccupied IR contexts */
217         struct iso_context *ir_context_list;
218         u64 mc_channels; /* channels in use by the multichannel IR context */
219         bool mc_allocated;
220
221         __be32    *config_rom;
222         dma_addr_t config_rom_bus;
223         __be32    *next_config_rom;
224         dma_addr_t next_config_rom_bus;
225         __be32     next_header;
226
227         __le32    *self_id_cpu;
228         dma_addr_t self_id_bus;
229         struct tasklet_struct bus_reset_tasklet;
230
231         u32 self_id_buffer[512];
232 };
233
234 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
235 {
236         return container_of(card, struct fw_ohci, card);
237 }
238
239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
240 #define IR_CONTEXT_BUFFER_FILL          0x80000000
241 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
243 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
244 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
245
246 #define CONTEXT_RUN     0x8000
247 #define CONTEXT_WAKE    0x1000
248 #define CONTEXT_DEAD    0x0800
249 #define CONTEXT_ACTIVE  0x0400
250
251 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
252 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
253 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
254
255 #define OHCI1394_REGISTER_SIZE          0x800
256 #define OHCI1394_PCI_HCI_Control        0x40
257 #define SELF_ID_BUF_SIZE                0x800
258 #define OHCI_TCODE_PHY_PACKET           0x0e
259 #define OHCI_VERSION_1_1                0x010010
260
261 static char ohci_driver_name[] = KBUILD_MODNAME;
262
263 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
264 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
265 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
266
267 #define QUIRK_CYCLE_TIMER               1
268 #define QUIRK_RESET_PACKET              2
269 #define QUIRK_BE_HEADERS                4
270 #define QUIRK_NO_1394A                  8
271 #define QUIRK_NO_MSI                    16
272
273 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
274 static const struct {
275         unsigned short vendor, device, revision, flags;
276 } ohci_quirks[] = {
277         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
278                 QUIRK_CYCLE_TIMER},
279
280         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
281                 QUIRK_BE_HEADERS},
282
283         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
284                 QUIRK_NO_MSI},
285
286         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
287                 QUIRK_NO_MSI},
288
289         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
290                 QUIRK_CYCLE_TIMER},
291
292         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
293                 QUIRK_CYCLE_TIMER},
294
295         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
296                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
297
298         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
299                 QUIRK_RESET_PACKET},
300
301         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
302                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
303 };
304
305 /* This overrides anything that was found in ohci_quirks[]. */
306 static int param_quirks;
307 module_param_named(quirks, param_quirks, int, 0644);
308 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
309         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
310         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
311         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
312         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
313         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
314         ")");
315
316 #define OHCI_PARAM_DEBUG_AT_AR          1
317 #define OHCI_PARAM_DEBUG_SELFIDS        2
318 #define OHCI_PARAM_DEBUG_IRQS           4
319 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
320
321 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
322
323 static int param_debug;
324 module_param_named(debug, param_debug, int, 0644);
325 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
326         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
327         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
328         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
329         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
330         ", or a combination, or all = -1)");
331
332 static void log_irqs(u32 evt)
333 {
334         if (likely(!(param_debug &
335                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
336                 return;
337
338         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
339             !(evt & OHCI1394_busReset))
340                 return;
341
342         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
343             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
344             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
345             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
346             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
347             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
348             evt & OHCI1394_isochRx              ? " IR"                 : "",
349             evt & OHCI1394_isochTx              ? " IT"                 : "",
350             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
351             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
352             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
353             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
354             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
355             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
356             evt & OHCI1394_busReset             ? " busReset"           : "",
357             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
358                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
359                     OHCI1394_respTxComplete | OHCI1394_isochRx |
360                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
361                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
362                     OHCI1394_cycleInconsistent |
363                     OHCI1394_regAccessFail | OHCI1394_busReset)
364                                                 ? " ?"                  : "");
365 }
366
367 static const char *speed[] = {
368         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
369 };
370 static const char *power[] = {
371         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
372         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
373 };
374 static const char port[] = { '.', '-', 'p', 'c', };
375
376 static char _p(u32 *s, int shift)
377 {
378         return port[*s >> shift & 3];
379 }
380
381 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
382 {
383         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
384                 return;
385
386         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
387                   self_id_count, generation, node_id);
388
389         for (; self_id_count--; ++s)
390                 if ((*s & 1 << 23) == 0)
391                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
392                             "%s gc=%d %s %s%s%s\n",
393                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
394                             speed[*s >> 14 & 3], *s >> 16 & 63,
395                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
396                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
397                 else
398                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
399                             *s, *s >> 24 & 63,
400                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
401                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
402 }
403
404 static const char *evts[] = {
405         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
406         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
407         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
408         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
409         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
410         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
411         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
412         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
413         [0x10] = "-reserved-",          [0x11] = "ack_complete",
414         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
415         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
416         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
417         [0x18] = "-reserved-",          [0x19] = "-reserved-",
418         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
419         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
420         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
421         [0x20] = "pending/cancelled",
422 };
423 static const char *tcodes[] = {
424         [0x0] = "QW req",               [0x1] = "BW req",
425         [0x2] = "W resp",               [0x3] = "-reserved-",
426         [0x4] = "QR req",               [0x5] = "BR req",
427         [0x6] = "QR resp",              [0x7] = "BR resp",
428         [0x8] = "cycle start",          [0x9] = "Lk req",
429         [0xa] = "async stream packet",  [0xb] = "Lk resp",
430         [0xc] = "-reserved-",           [0xd] = "-reserved-",
431         [0xe] = "link internal",        [0xf] = "-reserved-",
432 };
433
434 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
435 {
436         int tcode = header[0] >> 4 & 0xf;
437         char specific[12];
438
439         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
440                 return;
441
442         if (unlikely(evt >= ARRAY_SIZE(evts)))
443                         evt = 0x1f;
444
445         if (evt == OHCI1394_evt_bus_reset) {
446                 fw_notify("A%c evt_bus_reset, generation %d\n",
447                     dir, (header[2] >> 16) & 0xff);
448                 return;
449         }
450
451         switch (tcode) {
452         case 0x0: case 0x6: case 0x8:
453                 snprintf(specific, sizeof(specific), " = %08x",
454                          be32_to_cpu((__force __be32)header[3]));
455                 break;
456         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
457                 snprintf(specific, sizeof(specific), " %x,%x",
458                          header[3] >> 16, header[3] & 0xffff);
459                 break;
460         default:
461                 specific[0] = '\0';
462         }
463
464         switch (tcode) {
465         case 0xa:
466                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
467                 break;
468         case 0xe:
469                 fw_notify("A%c %s, PHY %08x %08x\n",
470                           dir, evts[evt], header[1], header[2]);
471                 break;
472         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
473                 fw_notify("A%c spd %x tl %02x, "
474                     "%04x -> %04x, %s, "
475                     "%s, %04x%08x%s\n",
476                     dir, speed, header[0] >> 10 & 0x3f,
477                     header[1] >> 16, header[0] >> 16, evts[evt],
478                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
479                 break;
480         default:
481                 fw_notify("A%c spd %x tl %02x, "
482                     "%04x -> %04x, %s, "
483                     "%s%s\n",
484                     dir, speed, header[0] >> 10 & 0x3f,
485                     header[1] >> 16, header[0] >> 16, evts[evt],
486                     tcodes[tcode], specific);
487         }
488 }
489
490 #else
491
492 #define param_debug 0
493 static inline void log_irqs(u32 evt) {}
494 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
495 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
496
497 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
498
499 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
500 {
501         writel(data, ohci->registers + offset);
502 }
503
504 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
505 {
506         return readl(ohci->registers + offset);
507 }
508
509 static inline void flush_writes(const struct fw_ohci *ohci)
510 {
511         /* Do a dummy read to flush writes. */
512         reg_read(ohci, OHCI1394_Version);
513 }
514
515 /*
516  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
517  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
518  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
519  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
520  */
521 static int read_phy_reg(struct fw_ohci *ohci, int addr)
522 {
523         u32 val;
524         int i;
525
526         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
527         for (i = 0; i < 3 + 100; i++) {
528                 val = reg_read(ohci, OHCI1394_PhyControl);
529                 if (!~val)
530                         return -ENODEV; /* Card was ejected. */
531
532                 if (val & OHCI1394_PhyControl_ReadDone)
533                         return OHCI1394_PhyControl_ReadData(val);
534
535                 /*
536                  * Try a few times without waiting.  Sleeping is necessary
537                  * only when the link/PHY interface is busy.
538                  */
539                 if (i >= 3)
540                         msleep(1);
541         }
542         fw_error("failed to read phy reg\n");
543
544         return -EBUSY;
545 }
546
547 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
548 {
549         int i;
550
551         reg_write(ohci, OHCI1394_PhyControl,
552                   OHCI1394_PhyControl_Write(addr, val));
553         for (i = 0; i < 3 + 100; i++) {
554                 val = reg_read(ohci, OHCI1394_PhyControl);
555                 if (!~val)
556                         return -ENODEV; /* Card was ejected. */
557
558                 if (!(val & OHCI1394_PhyControl_WritePending))
559                         return 0;
560
561                 if (i >= 3)
562                         msleep(1);
563         }
564         fw_error("failed to write phy reg\n");
565
566         return -EBUSY;
567 }
568
569 static int update_phy_reg(struct fw_ohci *ohci, int addr,
570                           int clear_bits, int set_bits)
571 {
572         int ret = read_phy_reg(ohci, addr);
573         if (ret < 0)
574                 return ret;
575
576         /*
577          * The interrupt status bits are cleared by writing a one bit.
578          * Avoid clearing them unless explicitly requested in set_bits.
579          */
580         if (addr == 5)
581                 clear_bits |= PHY_INT_STATUS_BITS;
582
583         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
584 }
585
586 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
587 {
588         int ret;
589
590         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
591         if (ret < 0)
592                 return ret;
593
594         return read_phy_reg(ohci, addr);
595 }
596
597 static int ohci_read_phy_reg(struct fw_card *card, int addr)
598 {
599         struct fw_ohci *ohci = fw_ohci(card);
600         int ret;
601
602         mutex_lock(&ohci->phy_reg_mutex);
603         ret = read_phy_reg(ohci, addr);
604         mutex_unlock(&ohci->phy_reg_mutex);
605
606         return ret;
607 }
608
609 static int ohci_update_phy_reg(struct fw_card *card, int addr,
610                                int clear_bits, int set_bits)
611 {
612         struct fw_ohci *ohci = fw_ohci(card);
613         int ret;
614
615         mutex_lock(&ohci->phy_reg_mutex);
616         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
617         mutex_unlock(&ohci->phy_reg_mutex);
618
619         return ret;
620 }
621
622 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
623 {
624         return page_private(ctx->pages[i]);
625 }
626
627 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
628 {
629         struct descriptor *d;
630
631         d = &ctx->descriptors[index];
632         d->branch_address  &= cpu_to_le32(~0xf);
633         d->res_count       =  cpu_to_le16(PAGE_SIZE);
634         d->transfer_status =  0;
635
636         wmb(); /* finish init of new descriptors before branch_address update */
637         d = &ctx->descriptors[ctx->last_buffer_index];
638         d->branch_address  |= cpu_to_le32(1);
639
640         ctx->last_buffer_index = index;
641
642         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
643 }
644
645 static void ar_context_release(struct ar_context *ctx)
646 {
647         unsigned int i;
648
649         if (ctx->buffer)
650                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
651
652         for (i = 0; i < AR_BUFFERS; i++)
653                 if (ctx->pages[i]) {
654                         dma_unmap_page(ctx->ohci->card.device,
655                                        ar_buffer_bus(ctx, i),
656                                        PAGE_SIZE, DMA_FROM_DEVICE);
657                         __free_page(ctx->pages[i]);
658                 }
659 }
660
661 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
662 {
663         if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
664                 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
665                 flush_writes(ctx->ohci);
666
667                 fw_error("AR error: %s; DMA stopped\n", error_msg);
668         }
669         /* FIXME: restart? */
670 }
671
672 static inline unsigned int ar_next_buffer_index(unsigned int index)
673 {
674         return (index + 1) % AR_BUFFERS;
675 }
676
677 static inline unsigned int ar_prev_buffer_index(unsigned int index)
678 {
679         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
680 }
681
682 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
683 {
684         return ar_next_buffer_index(ctx->last_buffer_index);
685 }
686
687 /*
688  * We search for the buffer that contains the last AR packet DMA data written
689  * by the controller.
690  */
691 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
692                                                  unsigned int *buffer_offset)
693 {
694         unsigned int i, next_i, last = ctx->last_buffer_index;
695         __le16 res_count, next_res_count;
696
697         i = ar_first_buffer_index(ctx);
698         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
699
700         /* A buffer that is not yet completely filled must be the last one. */
701         while (i != last && res_count == 0) {
702
703                 /* Peek at the next descriptor. */
704                 next_i = ar_next_buffer_index(i);
705                 rmb(); /* read descriptors in order */
706                 next_res_count = ACCESS_ONCE(
707                                 ctx->descriptors[next_i].res_count);
708                 /*
709                  * If the next descriptor is still empty, we must stop at this
710                  * descriptor.
711                  */
712                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
713                         /*
714                          * The exception is when the DMA data for one packet is
715                          * split over three buffers; in this case, the middle
716                          * buffer's descriptor might be never updated by the
717                          * controller and look still empty, and we have to peek
718                          * at the third one.
719                          */
720                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
721                                 next_i = ar_next_buffer_index(next_i);
722                                 rmb();
723                                 next_res_count = ACCESS_ONCE(
724                                         ctx->descriptors[next_i].res_count);
725                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
726                                         goto next_buffer_is_active;
727                         }
728
729                         break;
730                 }
731
732 next_buffer_is_active:
733                 i = next_i;
734                 res_count = next_res_count;
735         }
736
737         rmb(); /* read res_count before the DMA data */
738
739         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
740         if (*buffer_offset > PAGE_SIZE) {
741                 *buffer_offset = 0;
742                 ar_context_abort(ctx, "corrupted descriptor");
743         }
744
745         return i;
746 }
747
748 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
749                                     unsigned int end_buffer_index,
750                                     unsigned int end_buffer_offset)
751 {
752         unsigned int i;
753
754         i = ar_first_buffer_index(ctx);
755         while (i != end_buffer_index) {
756                 dma_sync_single_for_cpu(ctx->ohci->card.device,
757                                         ar_buffer_bus(ctx, i),
758                                         PAGE_SIZE, DMA_FROM_DEVICE);
759                 i = ar_next_buffer_index(i);
760         }
761         if (end_buffer_offset > 0)
762                 dma_sync_single_for_cpu(ctx->ohci->card.device,
763                                         ar_buffer_bus(ctx, i),
764                                         end_buffer_offset, DMA_FROM_DEVICE);
765 }
766
767 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
768 #define cond_le32_to_cpu(v) \
769         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
770 #else
771 #define cond_le32_to_cpu(v) le32_to_cpu(v)
772 #endif
773
774 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
775 {
776         struct fw_ohci *ohci = ctx->ohci;
777         struct fw_packet p;
778         u32 status, length, tcode;
779         int evt;
780
781         p.header[0] = cond_le32_to_cpu(buffer[0]);
782         p.header[1] = cond_le32_to_cpu(buffer[1]);
783         p.header[2] = cond_le32_to_cpu(buffer[2]);
784
785         tcode = (p.header[0] >> 4) & 0x0f;
786         switch (tcode) {
787         case TCODE_WRITE_QUADLET_REQUEST:
788         case TCODE_READ_QUADLET_RESPONSE:
789                 p.header[3] = (__force __u32) buffer[3];
790                 p.header_length = 16;
791                 p.payload_length = 0;
792                 break;
793
794         case TCODE_READ_BLOCK_REQUEST :
795                 p.header[3] = cond_le32_to_cpu(buffer[3]);
796                 p.header_length = 16;
797                 p.payload_length = 0;
798                 break;
799
800         case TCODE_WRITE_BLOCK_REQUEST:
801         case TCODE_READ_BLOCK_RESPONSE:
802         case TCODE_LOCK_REQUEST:
803         case TCODE_LOCK_RESPONSE:
804                 p.header[3] = cond_le32_to_cpu(buffer[3]);
805                 p.header_length = 16;
806                 p.payload_length = p.header[3] >> 16;
807                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
808                         ar_context_abort(ctx, "invalid packet length");
809                         return NULL;
810                 }
811                 break;
812
813         case TCODE_WRITE_RESPONSE:
814         case TCODE_READ_QUADLET_REQUEST:
815         case OHCI_TCODE_PHY_PACKET:
816                 p.header_length = 12;
817                 p.payload_length = 0;
818                 break;
819
820         default:
821                 ar_context_abort(ctx, "invalid tcode");
822                 return NULL;
823         }
824
825         p.payload = (void *) buffer + p.header_length;
826
827         /* FIXME: What to do about evt_* errors? */
828         length = (p.header_length + p.payload_length + 3) / 4;
829         status = cond_le32_to_cpu(buffer[length]);
830         evt    = (status >> 16) & 0x1f;
831
832         p.ack        = evt - 16;
833         p.speed      = (status >> 21) & 0x7;
834         p.timestamp  = status & 0xffff;
835         p.generation = ohci->request_generation;
836
837         log_ar_at_event('R', p.speed, p.header, evt);
838
839         /*
840          * Several controllers, notably from NEC and VIA, forget to
841          * write ack_complete status at PHY packet reception.
842          */
843         if (evt == OHCI1394_evt_no_status &&
844             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
845                 p.ack = ACK_COMPLETE;
846
847         /*
848          * The OHCI bus reset handler synthesizes a PHY packet with
849          * the new generation number when a bus reset happens (see
850          * section 8.4.2.3).  This helps us determine when a request
851          * was received and make sure we send the response in the same
852          * generation.  We only need this for requests; for responses
853          * we use the unique tlabel for finding the matching
854          * request.
855          *
856          * Alas some chips sometimes emit bus reset packets with a
857          * wrong generation.  We set the correct generation for these
858          * at a slightly incorrect time (in bus_reset_tasklet).
859          */
860         if (evt == OHCI1394_evt_bus_reset) {
861                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
862                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
863         } else if (ctx == &ohci->ar_request_ctx) {
864                 fw_core_handle_request(&ohci->card, &p);
865         } else {
866                 fw_core_handle_response(&ohci->card, &p);
867         }
868
869         return buffer + length + 1;
870 }
871
872 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
873 {
874         void *next;
875
876         while (p < end) {
877                 next = handle_ar_packet(ctx, p);
878                 if (!next)
879                         return p;
880                 p = next;
881         }
882
883         return p;
884 }
885
886 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
887 {
888         unsigned int i;
889
890         i = ar_first_buffer_index(ctx);
891         while (i != end_buffer) {
892                 dma_sync_single_for_device(ctx->ohci->card.device,
893                                            ar_buffer_bus(ctx, i),
894                                            PAGE_SIZE, DMA_FROM_DEVICE);
895                 ar_context_link_page(ctx, i);
896                 i = ar_next_buffer_index(i);
897         }
898 }
899
900 static void ar_context_tasklet(unsigned long data)
901 {
902         struct ar_context *ctx = (struct ar_context *)data;
903         unsigned int end_buffer_index, end_buffer_offset;
904         void *p, *end;
905
906         p = ctx->pointer;
907         if (!p)
908                 return;
909
910         end_buffer_index = ar_search_last_active_buffer(ctx,
911                                                         &end_buffer_offset);
912         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
913         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
914
915         if (end_buffer_index < ar_first_buffer_index(ctx)) {
916                 /*
917                  * The filled part of the overall buffer wraps around; handle
918                  * all packets up to the buffer end here.  If the last packet
919                  * wraps around, its tail will be visible after the buffer end
920                  * because the buffer start pages are mapped there again.
921                  */
922                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
923                 p = handle_ar_packets(ctx, p, buffer_end);
924                 if (p < buffer_end)
925                         goto error;
926                 /* adjust p to point back into the actual buffer */
927                 p -= AR_BUFFERS * PAGE_SIZE;
928         }
929
930         p = handle_ar_packets(ctx, p, end);
931         if (p != end) {
932                 if (p > end)
933                         ar_context_abort(ctx, "inconsistent descriptor");
934                 goto error;
935         }
936
937         ctx->pointer = p;
938         ar_recycle_buffers(ctx, end_buffer_index);
939
940         return;
941
942 error:
943         ctx->pointer = NULL;
944 }
945
946 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
947                            unsigned int descriptors_offset, u32 regs)
948 {
949         unsigned int i;
950         dma_addr_t dma_addr;
951         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
952         struct descriptor *d;
953
954         ctx->regs        = regs;
955         ctx->ohci        = ohci;
956         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
957
958         for (i = 0; i < AR_BUFFERS; i++) {
959                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
960                 if (!ctx->pages[i])
961                         goto out_of_memory;
962                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
963                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
964                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
965                         __free_page(ctx->pages[i]);
966                         ctx->pages[i] = NULL;
967                         goto out_of_memory;
968                 }
969                 set_page_private(ctx->pages[i], dma_addr);
970         }
971
972         for (i = 0; i < AR_BUFFERS; i++)
973                 pages[i]              = ctx->pages[i];
974         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
975                 pages[AR_BUFFERS + i] = ctx->pages[i];
976         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
977                                  -1, PAGE_KERNEL);
978         if (!ctx->buffer)
979                 goto out_of_memory;
980
981         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
982         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
983
984         for (i = 0; i < AR_BUFFERS; i++) {
985                 d = &ctx->descriptors[i];
986                 d->req_count      = cpu_to_le16(PAGE_SIZE);
987                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
988                                                 DESCRIPTOR_STATUS |
989                                                 DESCRIPTOR_BRANCH_ALWAYS);
990                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
991                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
992                         ar_next_buffer_index(i) * sizeof(struct descriptor));
993         }
994
995         return 0;
996
997 out_of_memory:
998         ar_context_release(ctx);
999
1000         return -ENOMEM;
1001 }
1002
1003 static void ar_context_run(struct ar_context *ctx)
1004 {
1005         unsigned int i;
1006
1007         for (i = 0; i < AR_BUFFERS; i++)
1008                 ar_context_link_page(ctx, i);
1009
1010         ctx->pointer = ctx->buffer;
1011
1012         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1013         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1014 }
1015
1016 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1017 {
1018         __le16 branch;
1019
1020         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1021
1022         /* figure out which descriptor the branch address goes in */
1023         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1024                 return d;
1025         else
1026                 return d + z - 1;
1027 }
1028
1029 static void context_tasklet(unsigned long data)
1030 {
1031         struct context *ctx = (struct context *) data;
1032         struct descriptor *d, *last;
1033         u32 address;
1034         int z;
1035         struct descriptor_buffer *desc;
1036
1037         desc = list_entry(ctx->buffer_list.next,
1038                         struct descriptor_buffer, list);
1039         last = ctx->last;
1040         while (last->branch_address != 0) {
1041                 struct descriptor_buffer *old_desc = desc;
1042                 address = le32_to_cpu(last->branch_address);
1043                 z = address & 0xf;
1044                 address &= ~0xf;
1045
1046                 /* If the branch address points to a buffer outside of the
1047                  * current buffer, advance to the next buffer. */
1048                 if (address < desc->buffer_bus ||
1049                                 address >= desc->buffer_bus + desc->used)
1050                         desc = list_entry(desc->list.next,
1051                                         struct descriptor_buffer, list);
1052                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1053                 last = find_branch_descriptor(d, z);
1054
1055                 if (!ctx->callback(ctx, d, last))
1056                         break;
1057
1058                 if (old_desc != desc) {
1059                         /* If we've advanced to the next buffer, move the
1060                          * previous buffer to the free list. */
1061                         unsigned long flags;
1062                         old_desc->used = 0;
1063                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1064                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1065                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1066                 }
1067                 ctx->last = last;
1068         }
1069 }
1070
1071 /*
1072  * Allocate a new buffer and add it to the list of free buffers for this
1073  * context.  Must be called with ohci->lock held.
1074  */
1075 static int context_add_buffer(struct context *ctx)
1076 {
1077         struct descriptor_buffer *desc;
1078         dma_addr_t uninitialized_var(bus_addr);
1079         int offset;
1080
1081         /*
1082          * 16MB of descriptors should be far more than enough for any DMA
1083          * program.  This will catch run-away userspace or DoS attacks.
1084          */
1085         if (ctx->total_allocation >= 16*1024*1024)
1086                 return -ENOMEM;
1087
1088         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1089                         &bus_addr, GFP_ATOMIC);
1090         if (!desc)
1091                 return -ENOMEM;
1092
1093         offset = (void *)&desc->buffer - (void *)desc;
1094         desc->buffer_size = PAGE_SIZE - offset;
1095         desc->buffer_bus = bus_addr + offset;
1096         desc->used = 0;
1097
1098         list_add_tail(&desc->list, &ctx->buffer_list);
1099         ctx->total_allocation += PAGE_SIZE;
1100
1101         return 0;
1102 }
1103
1104 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1105                         u32 regs, descriptor_callback_t callback)
1106 {
1107         ctx->ohci = ohci;
1108         ctx->regs = regs;
1109         ctx->total_allocation = 0;
1110
1111         INIT_LIST_HEAD(&ctx->buffer_list);
1112         if (context_add_buffer(ctx) < 0)
1113                 return -ENOMEM;
1114
1115         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1116                         struct descriptor_buffer, list);
1117
1118         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1119         ctx->callback = callback;
1120
1121         /*
1122          * We put a dummy descriptor in the buffer that has a NULL
1123          * branch address and looks like it's been sent.  That way we
1124          * have a descriptor to append DMA programs to.
1125          */
1126         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1127         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1128         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1129         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1130         ctx->last = ctx->buffer_tail->buffer;
1131         ctx->prev = ctx->buffer_tail->buffer;
1132
1133         return 0;
1134 }
1135
1136 static void context_release(struct context *ctx)
1137 {
1138         struct fw_card *card = &ctx->ohci->card;
1139         struct descriptor_buffer *desc, *tmp;
1140
1141         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1142                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1143                         desc->buffer_bus -
1144                         ((void *)&desc->buffer - (void *)desc));
1145 }
1146
1147 /* Must be called with ohci->lock held */
1148 static struct descriptor *context_get_descriptors(struct context *ctx,
1149                                                   int z, dma_addr_t *d_bus)
1150 {
1151         struct descriptor *d = NULL;
1152         struct descriptor_buffer *desc = ctx->buffer_tail;
1153
1154         if (z * sizeof(*d) > desc->buffer_size)
1155                 return NULL;
1156
1157         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1158                 /* No room for the descriptor in this buffer, so advance to the
1159                  * next one. */
1160
1161                 if (desc->list.next == &ctx->buffer_list) {
1162                         /* If there is no free buffer next in the list,
1163                          * allocate one. */
1164                         if (context_add_buffer(ctx) < 0)
1165                                 return NULL;
1166                 }
1167                 desc = list_entry(desc->list.next,
1168                                 struct descriptor_buffer, list);
1169                 ctx->buffer_tail = desc;
1170         }
1171
1172         d = desc->buffer + desc->used / sizeof(*d);
1173         memset(d, 0, z * sizeof(*d));
1174         *d_bus = desc->buffer_bus + desc->used;
1175
1176         return d;
1177 }
1178
1179 static void context_run(struct context *ctx, u32 extra)
1180 {
1181         struct fw_ohci *ohci = ctx->ohci;
1182
1183         reg_write(ohci, COMMAND_PTR(ctx->regs),
1184                   le32_to_cpu(ctx->last->branch_address));
1185         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1186         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1187         ctx->running = true;
1188         flush_writes(ohci);
1189 }
1190
1191 static void context_append(struct context *ctx,
1192                            struct descriptor *d, int z, int extra)
1193 {
1194         dma_addr_t d_bus;
1195         struct descriptor_buffer *desc = ctx->buffer_tail;
1196
1197         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1198
1199         desc->used += (z + extra) * sizeof(*d);
1200
1201         wmb(); /* finish init of new descriptors before branch_address update */
1202         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1203         ctx->prev = find_branch_descriptor(d, z);
1204 }
1205
1206 static void context_stop(struct context *ctx)
1207 {
1208         u32 reg;
1209         int i;
1210
1211         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1212         ctx->running = false;
1213
1214         for (i = 0; i < 1000; i++) {
1215                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1216                 if ((reg & CONTEXT_ACTIVE) == 0)
1217                         return;
1218
1219                 if (i)
1220                         udelay(10);
1221         }
1222         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1223 }
1224
1225 struct driver_data {
1226         u8 inline_data[8];
1227         struct fw_packet *packet;
1228 };
1229
1230 /*
1231  * This function apppends a packet to the DMA queue for transmission.
1232  * Must always be called with the ochi->lock held to ensure proper
1233  * generation handling and locking around packet queue manipulation.
1234  */
1235 static int at_context_queue_packet(struct context *ctx,
1236                                    struct fw_packet *packet)
1237 {
1238         struct fw_ohci *ohci = ctx->ohci;
1239         dma_addr_t d_bus, uninitialized_var(payload_bus);
1240         struct driver_data *driver_data;
1241         struct descriptor *d, *last;
1242         __le32 *header;
1243         int z, tcode;
1244
1245         d = context_get_descriptors(ctx, 4, &d_bus);
1246         if (d == NULL) {
1247                 packet->ack = RCODE_SEND_ERROR;
1248                 return -1;
1249         }
1250
1251         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1252         d[0].res_count = cpu_to_le16(packet->timestamp);
1253
1254         /*
1255          * The DMA format for asyncronous link packets is different
1256          * from the IEEE1394 layout, so shift the fields around
1257          * accordingly.
1258          */
1259
1260         tcode = (packet->header[0] >> 4) & 0x0f;
1261         header = (__le32 *) &d[1];
1262         switch (tcode) {
1263         case TCODE_WRITE_QUADLET_REQUEST:
1264         case TCODE_WRITE_BLOCK_REQUEST:
1265         case TCODE_WRITE_RESPONSE:
1266         case TCODE_READ_QUADLET_REQUEST:
1267         case TCODE_READ_BLOCK_REQUEST:
1268         case TCODE_READ_QUADLET_RESPONSE:
1269         case TCODE_READ_BLOCK_RESPONSE:
1270         case TCODE_LOCK_REQUEST:
1271         case TCODE_LOCK_RESPONSE:
1272                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1273                                         (packet->speed << 16));
1274                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1275                                         (packet->header[0] & 0xffff0000));
1276                 header[2] = cpu_to_le32(packet->header[2]);
1277
1278                 if (TCODE_IS_BLOCK_PACKET(tcode))
1279                         header[3] = cpu_to_le32(packet->header[3]);
1280                 else
1281                         header[3] = (__force __le32) packet->header[3];
1282
1283                 d[0].req_count = cpu_to_le16(packet->header_length);
1284                 break;
1285
1286         case TCODE_LINK_INTERNAL:
1287                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1288                                         (packet->speed << 16));
1289                 header[1] = cpu_to_le32(packet->header[1]);
1290                 header[2] = cpu_to_le32(packet->header[2]);
1291                 d[0].req_count = cpu_to_le16(12);
1292
1293                 if (is_ping_packet(&packet->header[1]))
1294                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1295                 break;
1296
1297         case TCODE_STREAM_DATA:
1298                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1299                                         (packet->speed << 16));
1300                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1301                 d[0].req_count = cpu_to_le16(8);
1302                 break;
1303
1304         default:
1305                 /* BUG(); */
1306                 packet->ack = RCODE_SEND_ERROR;
1307                 return -1;
1308         }
1309
1310         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1311         driver_data = (struct driver_data *) &d[3];
1312         driver_data->packet = packet;
1313         packet->driver_data = driver_data;
1314
1315         if (packet->payload_length > 0) {
1316                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1317                         payload_bus = dma_map_single(ohci->card.device,
1318                                                      packet->payload,
1319                                                      packet->payload_length,
1320                                                      DMA_TO_DEVICE);
1321                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1322                                 packet->ack = RCODE_SEND_ERROR;
1323                                 return -1;
1324                         }
1325                         packet->payload_bus     = payload_bus;
1326                         packet->payload_mapped  = true;
1327                 } else {
1328                         memcpy(driver_data->inline_data, packet->payload,
1329                                packet->payload_length);
1330                         payload_bus = d_bus + 3 * sizeof(*d);
1331                 }
1332
1333                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1334                 d[2].data_address = cpu_to_le32(payload_bus);
1335                 last = &d[2];
1336                 z = 3;
1337         } else {
1338                 last = &d[0];
1339                 z = 2;
1340         }
1341
1342         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1343                                      DESCRIPTOR_IRQ_ALWAYS |
1344                                      DESCRIPTOR_BRANCH_ALWAYS);
1345
1346         /* FIXME: Document how the locking works. */
1347         if (ohci->generation != packet->generation) {
1348                 if (packet->payload_mapped)
1349                         dma_unmap_single(ohci->card.device, payload_bus,
1350                                          packet->payload_length, DMA_TO_DEVICE);
1351                 packet->ack = RCODE_GENERATION;
1352                 return -1;
1353         }
1354
1355         context_append(ctx, d, z, 4 - z);
1356
1357         if (ctx->running)
1358                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1359         else
1360                 context_run(ctx, 0);
1361
1362         return 0;
1363 }
1364
1365 static void at_context_flush(struct context *ctx)
1366 {
1367         tasklet_disable(&ctx->tasklet);
1368
1369         ctx->flushing = true;
1370         context_tasklet((unsigned long)ctx);
1371         ctx->flushing = false;
1372
1373         tasklet_enable(&ctx->tasklet);
1374 }
1375
1376 static int handle_at_packet(struct context *context,
1377                             struct descriptor *d,
1378                             struct descriptor *last)
1379 {
1380         struct driver_data *driver_data;
1381         struct fw_packet *packet;
1382         struct fw_ohci *ohci = context->ohci;
1383         int evt;
1384
1385         if (last->transfer_status == 0 && !context->flushing)
1386                 /* This descriptor isn't done yet, stop iteration. */
1387                 return 0;
1388
1389         driver_data = (struct driver_data *) &d[3];
1390         packet = driver_data->packet;
1391         if (packet == NULL)
1392                 /* This packet was cancelled, just continue. */
1393                 return 1;
1394
1395         if (packet->payload_mapped)
1396                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1397                                  packet->payload_length, DMA_TO_DEVICE);
1398
1399         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1400         packet->timestamp = le16_to_cpu(last->res_count);
1401
1402         log_ar_at_event('T', packet->speed, packet->header, evt);
1403
1404         switch (evt) {
1405         case OHCI1394_evt_timeout:
1406                 /* Async response transmit timed out. */
1407                 packet->ack = RCODE_CANCELLED;
1408                 break;
1409
1410         case OHCI1394_evt_flushed:
1411                 /*
1412                  * The packet was flushed should give same error as
1413                  * when we try to use a stale generation count.
1414                  */
1415                 packet->ack = RCODE_GENERATION;
1416                 break;
1417
1418         case OHCI1394_evt_missing_ack:
1419                 if (context->flushing)
1420                         packet->ack = RCODE_GENERATION;
1421                 else {
1422                         /*
1423                          * Using a valid (current) generation count, but the
1424                          * node is not on the bus or not sending acks.
1425                          */
1426                         packet->ack = RCODE_NO_ACK;
1427                 }
1428                 break;
1429
1430         case ACK_COMPLETE + 0x10:
1431         case ACK_PENDING + 0x10:
1432         case ACK_BUSY_X + 0x10:
1433         case ACK_BUSY_A + 0x10:
1434         case ACK_BUSY_B + 0x10:
1435         case ACK_DATA_ERROR + 0x10:
1436         case ACK_TYPE_ERROR + 0x10:
1437                 packet->ack = evt - 0x10;
1438                 break;
1439
1440         case OHCI1394_evt_no_status:
1441                 if (context->flushing) {
1442                         packet->ack = RCODE_GENERATION;
1443                         break;
1444                 }
1445                 /* fall through */
1446
1447         default:
1448                 packet->ack = RCODE_SEND_ERROR;
1449                 break;
1450         }
1451
1452         packet->callback(packet, &ohci->card, packet->ack);
1453
1454         return 1;
1455 }
1456
1457 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1458 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1459 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1460 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1461 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1462
1463 static void handle_local_rom(struct fw_ohci *ohci,
1464                              struct fw_packet *packet, u32 csr)
1465 {
1466         struct fw_packet response;
1467         int tcode, length, i;
1468
1469         tcode = HEADER_GET_TCODE(packet->header[0]);
1470         if (TCODE_IS_BLOCK_PACKET(tcode))
1471                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1472         else
1473                 length = 4;
1474
1475         i = csr - CSR_CONFIG_ROM;
1476         if (i + length > CONFIG_ROM_SIZE) {
1477                 fw_fill_response(&response, packet->header,
1478                                  RCODE_ADDRESS_ERROR, NULL, 0);
1479         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1480                 fw_fill_response(&response, packet->header,
1481                                  RCODE_TYPE_ERROR, NULL, 0);
1482         } else {
1483                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1484                                  (void *) ohci->config_rom + i, length);
1485         }
1486
1487         fw_core_handle_response(&ohci->card, &response);
1488 }
1489
1490 static void handle_local_lock(struct fw_ohci *ohci,
1491                               struct fw_packet *packet, u32 csr)
1492 {
1493         struct fw_packet response;
1494         int tcode, length, ext_tcode, sel, try;
1495         __be32 *payload, lock_old;
1496         u32 lock_arg, lock_data;
1497
1498         tcode = HEADER_GET_TCODE(packet->header[0]);
1499         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1500         payload = packet->payload;
1501         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1502
1503         if (tcode == TCODE_LOCK_REQUEST &&
1504             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1505                 lock_arg = be32_to_cpu(payload[0]);
1506                 lock_data = be32_to_cpu(payload[1]);
1507         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1508                 lock_arg = 0;
1509                 lock_data = 0;
1510         } else {
1511                 fw_fill_response(&response, packet->header,
1512                                  RCODE_TYPE_ERROR, NULL, 0);
1513                 goto out;
1514         }
1515
1516         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1517         reg_write(ohci, OHCI1394_CSRData, lock_data);
1518         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1519         reg_write(ohci, OHCI1394_CSRControl, sel);
1520
1521         for (try = 0; try < 20; try++)
1522                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1523                         lock_old = cpu_to_be32(reg_read(ohci,
1524                                                         OHCI1394_CSRData));
1525                         fw_fill_response(&response, packet->header,
1526                                          RCODE_COMPLETE,
1527                                          &lock_old, sizeof(lock_old));
1528                         goto out;
1529                 }
1530
1531         fw_error("swap not done (CSR lock timeout)\n");
1532         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1533
1534  out:
1535         fw_core_handle_response(&ohci->card, &response);
1536 }
1537
1538 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1539 {
1540         u64 offset, csr;
1541
1542         if (ctx == &ctx->ohci->at_request_ctx) {
1543                 packet->ack = ACK_PENDING;
1544                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1545         }
1546
1547         offset =
1548                 ((unsigned long long)
1549                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1550                 packet->header[2];
1551         csr = offset - CSR_REGISTER_BASE;
1552
1553         /* Handle config rom reads. */
1554         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1555                 handle_local_rom(ctx->ohci, packet, csr);
1556         else switch (csr) {
1557         case CSR_BUS_MANAGER_ID:
1558         case CSR_BANDWIDTH_AVAILABLE:
1559         case CSR_CHANNELS_AVAILABLE_HI:
1560         case CSR_CHANNELS_AVAILABLE_LO:
1561                 handle_local_lock(ctx->ohci, packet, csr);
1562                 break;
1563         default:
1564                 if (ctx == &ctx->ohci->at_request_ctx)
1565                         fw_core_handle_request(&ctx->ohci->card, packet);
1566                 else
1567                         fw_core_handle_response(&ctx->ohci->card, packet);
1568                 break;
1569         }
1570
1571         if (ctx == &ctx->ohci->at_response_ctx) {
1572                 packet->ack = ACK_COMPLETE;
1573                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1574         }
1575 }
1576
1577 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1578 {
1579         unsigned long flags;
1580         int ret;
1581
1582         spin_lock_irqsave(&ctx->ohci->lock, flags);
1583
1584         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1585             ctx->ohci->generation == packet->generation) {
1586                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1587                 handle_local_request(ctx, packet);
1588                 return;
1589         }
1590
1591         ret = at_context_queue_packet(ctx, packet);
1592         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1593
1594         if (ret < 0)
1595                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1596
1597 }
1598
1599 static void detect_dead_context(struct fw_ohci *ohci,
1600                                 const char *name, unsigned int regs)
1601 {
1602         u32 ctl;
1603
1604         ctl = reg_read(ohci, CONTROL_SET(regs));
1605         if (ctl & CONTEXT_DEAD) {
1606 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1607                 fw_error("DMA context %s has stopped, error code: %s\n",
1608                          name, evts[ctl & 0x1f]);
1609 #else
1610                 fw_error("DMA context %s has stopped, error code: %#x\n",
1611                          name, ctl & 0x1f);
1612 #endif
1613         }
1614 }
1615
1616 static void handle_dead_contexts(struct fw_ohci *ohci)
1617 {
1618         unsigned int i;
1619         char name[8];
1620
1621         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1622         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1623         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1624         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1625         for (i = 0; i < 32; ++i) {
1626                 if (!(ohci->it_context_support & (1 << i)))
1627                         continue;
1628                 sprintf(name, "IT%u", i);
1629                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1630         }
1631         for (i = 0; i < 32; ++i) {
1632                 if (!(ohci->ir_context_support & (1 << i)))
1633                         continue;
1634                 sprintf(name, "IR%u", i);
1635                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1636         }
1637         /* TODO: maybe try to flush and restart the dead contexts */
1638 }
1639
1640 static u32 cycle_timer_ticks(u32 cycle_timer)
1641 {
1642         u32 ticks;
1643
1644         ticks = cycle_timer & 0xfff;
1645         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1646         ticks += (3072 * 8000) * (cycle_timer >> 25);
1647
1648         return ticks;
1649 }
1650
1651 /*
1652  * Some controllers exhibit one or more of the following bugs when updating the
1653  * iso cycle timer register:
1654  *  - When the lowest six bits are wrapping around to zero, a read that happens
1655  *    at the same time will return garbage in the lowest ten bits.
1656  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1657  *    not incremented for about 60 ns.
1658  *  - Occasionally, the entire register reads zero.
1659  *
1660  * To catch these, we read the register three times and ensure that the
1661  * difference between each two consecutive reads is approximately the same, i.e.
1662  * less than twice the other.  Furthermore, any negative difference indicates an
1663  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1664  * execute, so we have enough precision to compute the ratio of the differences.)
1665  */
1666 static u32 get_cycle_time(struct fw_ohci *ohci)
1667 {
1668         u32 c0, c1, c2;
1669         u32 t0, t1, t2;
1670         s32 diff01, diff12;
1671         int i;
1672
1673         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1674
1675         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1676                 i = 0;
1677                 c1 = c2;
1678                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1679                 do {
1680                         c0 = c1;
1681                         c1 = c2;
1682                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1683                         t0 = cycle_timer_ticks(c0);
1684                         t1 = cycle_timer_ticks(c1);
1685                         t2 = cycle_timer_ticks(c2);
1686                         diff01 = t1 - t0;
1687                         diff12 = t2 - t1;
1688                 } while ((diff01 <= 0 || diff12 <= 0 ||
1689                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1690                          && i++ < 20);
1691         }
1692
1693         return c2;
1694 }
1695
1696 /*
1697  * This function has to be called at least every 64 seconds.  The bus_time
1698  * field stores not only the upper 25 bits of the BUS_TIME register but also
1699  * the most significant bit of the cycle timer in bit 6 so that we can detect
1700  * changes in this bit.
1701  */
1702 static u32 update_bus_time(struct fw_ohci *ohci)
1703 {
1704         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1705
1706         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1707                 ohci->bus_time += 0x40;
1708
1709         return ohci->bus_time | cycle_time_seconds;
1710 }
1711
1712 static void bus_reset_tasklet(unsigned long data)
1713 {
1714         struct fw_ohci *ohci = (struct fw_ohci *)data;
1715         int self_id_count, i, j, reg;
1716         int generation, new_generation;
1717         unsigned long flags;
1718         void *free_rom = NULL;
1719         dma_addr_t free_rom_bus = 0;
1720         bool is_new_root;
1721
1722         reg = reg_read(ohci, OHCI1394_NodeID);
1723         if (!(reg & OHCI1394_NodeID_idValid)) {
1724                 fw_notify("node ID not valid, new bus reset in progress\n");
1725                 return;
1726         }
1727         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1728                 fw_notify("malconfigured bus\n");
1729                 return;
1730         }
1731         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1732                                OHCI1394_NodeID_nodeNumber);
1733
1734         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1735         if (!(ohci->is_root && is_new_root))
1736                 reg_write(ohci, OHCI1394_LinkControlSet,
1737                           OHCI1394_LinkControl_cycleMaster);
1738         ohci->is_root = is_new_root;
1739
1740         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1741         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1742                 fw_notify("inconsistent self IDs\n");
1743                 return;
1744         }
1745         /*
1746          * The count in the SelfIDCount register is the number of
1747          * bytes in the self ID receive buffer.  Since we also receive
1748          * the inverted quadlets and a header quadlet, we shift one
1749          * bit extra to get the actual number of self IDs.
1750          */
1751         self_id_count = (reg >> 3) & 0xff;
1752         if (self_id_count == 0 || self_id_count > 252) {
1753                 fw_notify("inconsistent self IDs\n");
1754                 return;
1755         }
1756         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1757         rmb();
1758
1759         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1760                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1761                         fw_notify("inconsistent self IDs\n");
1762                         return;
1763                 }
1764                 ohci->self_id_buffer[j] =
1765                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1766         }
1767         rmb();
1768
1769         /*
1770          * Check the consistency of the self IDs we just read.  The
1771          * problem we face is that a new bus reset can start while we
1772          * read out the self IDs from the DMA buffer. If this happens,
1773          * the DMA buffer will be overwritten with new self IDs and we
1774          * will read out inconsistent data.  The OHCI specification
1775          * (section 11.2) recommends a technique similar to
1776          * linux/seqlock.h, where we remember the generation of the
1777          * self IDs in the buffer before reading them out and compare
1778          * it to the current generation after reading them out.  If
1779          * the two generations match we know we have a consistent set
1780          * of self IDs.
1781          */
1782
1783         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1784         if (new_generation != generation) {
1785                 fw_notify("recursive bus reset detected, "
1786                           "discarding self ids\n");
1787                 return;
1788         }
1789
1790         /* FIXME: Document how the locking works. */
1791         spin_lock_irqsave(&ohci->lock, flags);
1792
1793         ohci->generation = -1; /* prevent AT packet queueing */
1794         context_stop(&ohci->at_request_ctx);
1795         context_stop(&ohci->at_response_ctx);
1796
1797         spin_unlock_irqrestore(&ohci->lock, flags);
1798
1799         /*
1800          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1801          * packets in the AT queues and software needs to drain them.
1802          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1803          */
1804         at_context_flush(&ohci->at_request_ctx);
1805         at_context_flush(&ohci->at_response_ctx);
1806
1807         spin_lock_irqsave(&ohci->lock, flags);
1808
1809         ohci->generation = generation;
1810         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1811
1812         if (ohci->quirks & QUIRK_RESET_PACKET)
1813                 ohci->request_generation = generation;
1814
1815         /*
1816          * This next bit is unrelated to the AT context stuff but we
1817          * have to do it under the spinlock also.  If a new config rom
1818          * was set up before this reset, the old one is now no longer
1819          * in use and we can free it. Update the config rom pointers
1820          * to point to the current config rom and clear the
1821          * next_config_rom pointer so a new update can take place.
1822          */
1823
1824         if (ohci->next_config_rom != NULL) {
1825                 if (ohci->next_config_rom != ohci->config_rom) {
1826                         free_rom      = ohci->config_rom;
1827                         free_rom_bus  = ohci->config_rom_bus;
1828                 }
1829                 ohci->config_rom      = ohci->next_config_rom;
1830                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1831                 ohci->next_config_rom = NULL;
1832
1833                 /*
1834                  * Restore config_rom image and manually update
1835                  * config_rom registers.  Writing the header quadlet
1836                  * will indicate that the config rom is ready, so we
1837                  * do that last.
1838                  */
1839                 reg_write(ohci, OHCI1394_BusOptions,
1840                           be32_to_cpu(ohci->config_rom[2]));
1841                 ohci->config_rom[0] = ohci->next_header;
1842                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1843                           be32_to_cpu(ohci->next_header));
1844         }
1845
1846 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1847         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1848         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1849 #endif
1850
1851         spin_unlock_irqrestore(&ohci->lock, flags);
1852
1853         if (free_rom)
1854                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1855                                   free_rom, free_rom_bus);
1856
1857         log_selfids(ohci->node_id, generation,
1858                     self_id_count, ohci->self_id_buffer);
1859
1860         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1861                                  self_id_count, ohci->self_id_buffer,
1862                                  ohci->csr_state_setclear_abdicate);
1863         ohci->csr_state_setclear_abdicate = false;
1864 }
1865
1866 static irqreturn_t irq_handler(int irq, void *data)
1867 {
1868         struct fw_ohci *ohci = data;
1869         u32 event, iso_event;
1870         int i;
1871
1872         event = reg_read(ohci, OHCI1394_IntEventClear);
1873
1874         if (!event || !~event)
1875                 return IRQ_NONE;
1876
1877         /*
1878          * busReset and postedWriteErr must not be cleared yet
1879          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1880          */
1881         reg_write(ohci, OHCI1394_IntEventClear,
1882                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
1883         log_irqs(event);
1884
1885         if (event & OHCI1394_selfIDComplete)
1886                 tasklet_schedule(&ohci->bus_reset_tasklet);
1887
1888         if (event & OHCI1394_RQPkt)
1889                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1890
1891         if (event & OHCI1394_RSPkt)
1892                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1893
1894         if (event & OHCI1394_reqTxComplete)
1895                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1896
1897         if (event & OHCI1394_respTxComplete)
1898                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1899
1900         if (event & OHCI1394_isochRx) {
1901                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1902                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1903
1904                 while (iso_event) {
1905                         i = ffs(iso_event) - 1;
1906                         tasklet_schedule(
1907                                 &ohci->ir_context_list[i].context.tasklet);
1908                         iso_event &= ~(1 << i);
1909                 }
1910         }
1911
1912         if (event & OHCI1394_isochTx) {
1913                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1914                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1915
1916                 while (iso_event) {
1917                         i = ffs(iso_event) - 1;
1918                         tasklet_schedule(
1919                                 &ohci->it_context_list[i].context.tasklet);
1920                         iso_event &= ~(1 << i);
1921                 }
1922         }
1923
1924         if (unlikely(event & OHCI1394_regAccessFail))
1925                 fw_error("Register access failure - "
1926                          "please notify linux1394-devel@lists.sf.net\n");
1927
1928         if (unlikely(event & OHCI1394_postedWriteErr)) {
1929                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1930                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1931                 reg_write(ohci, OHCI1394_IntEventClear,
1932                           OHCI1394_postedWriteErr);
1933                 fw_error("PCI posted write error\n");
1934         }
1935
1936         if (unlikely(event & OHCI1394_cycleTooLong)) {
1937                 if (printk_ratelimit())
1938                         fw_notify("isochronous cycle too long\n");
1939                 reg_write(ohci, OHCI1394_LinkControlSet,
1940                           OHCI1394_LinkControl_cycleMaster);
1941         }
1942
1943         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1944                 /*
1945                  * We need to clear this event bit in order to make
1946                  * cycleMatch isochronous I/O work.  In theory we should
1947                  * stop active cycleMatch iso contexts now and restart
1948                  * them at least two cycles later.  (FIXME?)
1949                  */
1950                 if (printk_ratelimit())
1951                         fw_notify("isochronous cycle inconsistent\n");
1952         }
1953
1954         if (unlikely(event & OHCI1394_unrecoverableError))
1955                 handle_dead_contexts(ohci);
1956
1957         if (event & OHCI1394_cycle64Seconds) {
1958                 spin_lock(&ohci->lock);
1959                 update_bus_time(ohci);
1960                 spin_unlock(&ohci->lock);
1961         } else
1962                 flush_writes(ohci);
1963
1964         return IRQ_HANDLED;
1965 }
1966
1967 static int software_reset(struct fw_ohci *ohci)
1968 {
1969         u32 val;
1970         int i;
1971
1972         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1973         for (i = 0; i < 500; i++) {
1974                 val = reg_read(ohci, OHCI1394_HCControlSet);
1975                 if (!~val)
1976                         return -ENODEV; /* Card was ejected. */
1977
1978                 if (!(val & OHCI1394_HCControl_softReset))
1979                         return 0;
1980
1981                 msleep(1);
1982         }
1983
1984         return -EBUSY;
1985 }
1986
1987 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1988 {
1989         size_t size = length * 4;
1990
1991         memcpy(dest, src, size);
1992         if (size < CONFIG_ROM_SIZE)
1993                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1994 }
1995
1996 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1997 {
1998         bool enable_1394a;
1999         int ret, clear, set, offset;
2000
2001         /* Check if the driver should configure link and PHY. */
2002         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2003               OHCI1394_HCControl_programPhyEnable))
2004                 return 0;
2005
2006         /* Paranoia: check whether the PHY supports 1394a, too. */
2007         enable_1394a = false;
2008         ret = read_phy_reg(ohci, 2);
2009         if (ret < 0)
2010                 return ret;
2011         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2012                 ret = read_paged_phy_reg(ohci, 1, 8);
2013                 if (ret < 0)
2014                         return ret;
2015                 if (ret >= 1)
2016                         enable_1394a = true;
2017         }
2018
2019         if (ohci->quirks & QUIRK_NO_1394A)
2020                 enable_1394a = false;
2021
2022         /* Configure PHY and link consistently. */
2023         if (enable_1394a) {
2024                 clear = 0;
2025                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2026         } else {
2027                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2028                 set = 0;
2029         }
2030         ret = update_phy_reg(ohci, 5, clear, set);
2031         if (ret < 0)
2032                 return ret;
2033
2034         if (enable_1394a)
2035                 offset = OHCI1394_HCControlSet;
2036         else
2037                 offset = OHCI1394_HCControlClear;
2038         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2039
2040         /* Clean up: configuration has been taken care of. */
2041         reg_write(ohci, OHCI1394_HCControlClear,
2042                   OHCI1394_HCControl_programPhyEnable);
2043
2044         return 0;
2045 }
2046
2047 static int ohci_enable(struct fw_card *card,
2048                        const __be32 *config_rom, size_t length)
2049 {
2050         struct fw_ohci *ohci = fw_ohci(card);
2051         struct pci_dev *dev = to_pci_dev(card->device);
2052         u32 lps, seconds, version, irqs;
2053         int i, ret;
2054
2055         if (software_reset(ohci)) {
2056                 fw_error("Failed to reset ohci card.\n");
2057                 return -EBUSY;
2058         }
2059
2060         /*
2061          * Now enable LPS, which we need in order to start accessing
2062          * most of the registers.  In fact, on some cards (ALI M5251),
2063          * accessing registers in the SClk domain without LPS enabled
2064          * will lock up the machine.  Wait 50msec to make sure we have
2065          * full link enabled.  However, with some cards (well, at least
2066          * a JMicron PCIe card), we have to try again sometimes.
2067          */
2068         reg_write(ohci, OHCI1394_HCControlSet,
2069                   OHCI1394_HCControl_LPS |
2070                   OHCI1394_HCControl_postedWriteEnable);
2071         flush_writes(ohci);
2072
2073         for (lps = 0, i = 0; !lps && i < 3; i++) {
2074                 msleep(50);
2075                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2076                       OHCI1394_HCControl_LPS;
2077         }
2078
2079         if (!lps) {
2080                 fw_error("Failed to set Link Power Status\n");
2081                 return -EIO;
2082         }
2083
2084         reg_write(ohci, OHCI1394_HCControlClear,
2085                   OHCI1394_HCControl_noByteSwapData);
2086
2087         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2088         reg_write(ohci, OHCI1394_LinkControlSet,
2089                   OHCI1394_LinkControl_cycleTimerEnable |
2090                   OHCI1394_LinkControl_cycleMaster);
2091
2092         reg_write(ohci, OHCI1394_ATRetries,
2093                   OHCI1394_MAX_AT_REQ_RETRIES |
2094                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2095                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2096                   (200 << 16));
2097
2098         seconds = lower_32_bits(get_seconds());
2099         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2100         ohci->bus_time = seconds & ~0x3f;
2101
2102         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2103         if (version >= OHCI_VERSION_1_1) {
2104                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2105                           0xfffffffe);
2106                 card->broadcast_channel_auto_allocated = true;
2107         }
2108
2109         /* Get implemented bits of the priority arbitration request counter. */
2110         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2111         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2112         reg_write(ohci, OHCI1394_FairnessControl, 0);
2113         card->priority_budget_implemented = ohci->pri_req_max != 0;
2114
2115         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2116         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2117         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2118
2119         ret = configure_1394a_enhancements(ohci);
2120         if (ret < 0)
2121                 return ret;
2122
2123         /* Activate link_on bit and contender bit in our self ID packets.*/
2124         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2125         if (ret < 0)
2126                 return ret;
2127
2128         /*
2129          * When the link is not yet enabled, the atomic config rom
2130          * update mechanism described below in ohci_set_config_rom()
2131          * is not active.  We have to update ConfigRomHeader and
2132          * BusOptions manually, and the write to ConfigROMmap takes
2133          * effect immediately.  We tie this to the enabling of the
2134          * link, so we have a valid config rom before enabling - the
2135          * OHCI requires that ConfigROMhdr and BusOptions have valid
2136          * values before enabling.
2137          *
2138          * However, when the ConfigROMmap is written, some controllers
2139          * always read back quadlets 0 and 2 from the config rom to
2140          * the ConfigRomHeader and BusOptions registers on bus reset.
2141          * They shouldn't do that in this initial case where the link
2142          * isn't enabled.  This means we have to use the same
2143          * workaround here, setting the bus header to 0 and then write
2144          * the right values in the bus reset tasklet.
2145          */
2146
2147         if (config_rom) {
2148                 ohci->next_config_rom =
2149                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2150                                            &ohci->next_config_rom_bus,
2151                                            GFP_KERNEL);
2152                 if (ohci->next_config_rom == NULL)
2153                         return -ENOMEM;
2154
2155                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2156         } else {
2157                 /*
2158                  * In the suspend case, config_rom is NULL, which
2159                  * means that we just reuse the old config rom.
2160                  */
2161                 ohci->next_config_rom = ohci->config_rom;
2162                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2163         }
2164
2165         ohci->next_header = ohci->next_config_rom[0];
2166         ohci->next_config_rom[0] = 0;
2167         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2168         reg_write(ohci, OHCI1394_BusOptions,
2169                   be32_to_cpu(ohci->next_config_rom[2]));
2170         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2171
2172         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2173
2174         if (!(ohci->quirks & QUIRK_NO_MSI))
2175                 pci_enable_msi(dev);
2176         if (request_irq(dev->irq, irq_handler,
2177                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2178                         ohci_driver_name, ohci)) {
2179                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2180                 pci_disable_msi(dev);
2181
2182                 if (config_rom) {
2183                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2184                                           ohci->next_config_rom,
2185                                           ohci->next_config_rom_bus);
2186                         ohci->next_config_rom = NULL;
2187                 }
2188                 return -EIO;
2189         }
2190
2191         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2192                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2193                 OHCI1394_isochTx | OHCI1394_isochRx |
2194                 OHCI1394_postedWriteErr |
2195                 OHCI1394_selfIDComplete |
2196                 OHCI1394_regAccessFail |
2197                 OHCI1394_cycle64Seconds |
2198                 OHCI1394_cycleInconsistent |
2199                 OHCI1394_unrecoverableError |
2200                 OHCI1394_cycleTooLong |
2201                 OHCI1394_masterIntEnable;
2202         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2203                 irqs |= OHCI1394_busReset;
2204         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2205
2206         reg_write(ohci, OHCI1394_HCControlSet,
2207                   OHCI1394_HCControl_linkEnable |
2208                   OHCI1394_HCControl_BIBimageValid);
2209
2210         reg_write(ohci, OHCI1394_LinkControlSet,
2211                   OHCI1394_LinkControl_rcvSelfID |
2212                   OHCI1394_LinkControl_rcvPhyPkt);
2213
2214         ar_context_run(&ohci->ar_request_ctx);
2215         ar_context_run(&ohci->ar_response_ctx);
2216
2217         flush_writes(ohci);
2218
2219         /* We are ready to go, reset bus to finish initialization. */
2220         fw_schedule_bus_reset(&ohci->card, false, true);
2221
2222         return 0;
2223 }
2224
2225 static int ohci_set_config_rom(struct fw_card *card,
2226                                const __be32 *config_rom, size_t length)
2227 {
2228         struct fw_ohci *ohci;
2229         unsigned long flags;
2230         __be32 *next_config_rom;
2231         dma_addr_t uninitialized_var(next_config_rom_bus);
2232
2233         ohci = fw_ohci(card);
2234
2235         /*
2236          * When the OHCI controller is enabled, the config rom update
2237          * mechanism is a bit tricky, but easy enough to use.  See
2238          * section 5.5.6 in the OHCI specification.
2239          *
2240          * The OHCI controller caches the new config rom address in a
2241          * shadow register (ConfigROMmapNext) and needs a bus reset
2242          * for the changes to take place.  When the bus reset is
2243          * detected, the controller loads the new values for the
2244          * ConfigRomHeader and BusOptions registers from the specified
2245          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2246          * shadow register. All automatically and atomically.
2247          *
2248          * Now, there's a twist to this story.  The automatic load of
2249          * ConfigRomHeader and BusOptions doesn't honor the
2250          * noByteSwapData bit, so with a be32 config rom, the
2251          * controller will load be32 values in to these registers
2252          * during the atomic update, even on litte endian
2253          * architectures.  The workaround we use is to put a 0 in the
2254          * header quadlet; 0 is endian agnostic and means that the
2255          * config rom isn't ready yet.  In the bus reset tasklet we
2256          * then set up the real values for the two registers.
2257          *
2258          * We use ohci->lock to avoid racing with the code that sets
2259          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2260          */
2261
2262         next_config_rom =
2263                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2264                                    &next_config_rom_bus, GFP_KERNEL);
2265         if (next_config_rom == NULL)
2266                 return -ENOMEM;
2267
2268         spin_lock_irqsave(&ohci->lock, flags);
2269
2270         /*
2271          * If there is not an already pending config_rom update,
2272          * push our new allocation into the ohci->next_config_rom
2273          * and then mark the local variable as null so that we
2274          * won't deallocate the new buffer.
2275          *
2276          * OTOH, if there is a pending config_rom update, just
2277          * use that buffer with the new config_rom data, and
2278          * let this routine free the unused DMA allocation.
2279          */
2280
2281         if (ohci->next_config_rom == NULL) {
2282                 ohci->next_config_rom = next_config_rom;
2283                 ohci->next_config_rom_bus = next_config_rom_bus;
2284                 next_config_rom = NULL;
2285         }
2286
2287         copy_config_rom(ohci->next_config_rom, config_rom, length);
2288
2289         ohci->next_header = config_rom[0];
2290         ohci->next_config_rom[0] = 0;
2291
2292         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2293
2294         spin_unlock_irqrestore(&ohci->lock, flags);
2295
2296         /* If we didn't use the DMA allocation, delete it. */
2297         if (next_config_rom != NULL)
2298                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2299                                   next_config_rom, next_config_rom_bus);
2300
2301         /*
2302          * Now initiate a bus reset to have the changes take
2303          * effect. We clean up the old config rom memory and DMA
2304          * mappings in the bus reset tasklet, since the OHCI
2305          * controller could need to access it before the bus reset
2306          * takes effect.
2307          */
2308
2309         fw_schedule_bus_reset(&ohci->card, true, true);
2310
2311         return 0;
2312 }
2313
2314 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2315 {
2316         struct fw_ohci *ohci = fw_ohci(card);
2317
2318         at_context_transmit(&ohci->at_request_ctx, packet);
2319 }
2320
2321 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2322 {
2323         struct fw_ohci *ohci = fw_ohci(card);
2324
2325         at_context_transmit(&ohci->at_response_ctx, packet);
2326 }
2327
2328 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2329 {
2330         struct fw_ohci *ohci = fw_ohci(card);
2331         struct context *ctx = &ohci->at_request_ctx;
2332         struct driver_data *driver_data = packet->driver_data;
2333         int ret = -ENOENT;
2334
2335         tasklet_disable(&ctx->tasklet);
2336
2337         if (packet->ack != 0)
2338                 goto out;
2339
2340         if (packet->payload_mapped)
2341                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2342                                  packet->payload_length, DMA_TO_DEVICE);
2343
2344         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2345         driver_data->packet = NULL;
2346         packet->ack = RCODE_CANCELLED;
2347         packet->callback(packet, &ohci->card, packet->ack);
2348         ret = 0;
2349  out:
2350         tasklet_enable(&ctx->tasklet);
2351
2352         return ret;
2353 }
2354
2355 static int ohci_enable_phys_dma(struct fw_card *card,
2356                                 int node_id, int generation)
2357 {
2358 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2359         return 0;
2360 #else
2361         struct fw_ohci *ohci = fw_ohci(card);
2362         unsigned long flags;
2363         int n, ret = 0;
2364
2365         /*
2366          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2367          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2368          */
2369
2370         spin_lock_irqsave(&ohci->lock, flags);
2371
2372         if (ohci->generation != generation) {
2373                 ret = -ESTALE;
2374                 goto out;
2375         }
2376
2377         /*
2378          * Note, if the node ID contains a non-local bus ID, physical DMA is
2379          * enabled for _all_ nodes on remote buses.
2380          */
2381
2382         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2383         if (n < 32)
2384                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2385         else
2386                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2387
2388         flush_writes(ohci);
2389  out:
2390         spin_unlock_irqrestore(&ohci->lock, flags);
2391
2392         return ret;
2393 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2394 }
2395
2396 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2397 {
2398         struct fw_ohci *ohci = fw_ohci(card);
2399         unsigned long flags;
2400         u32 value;
2401
2402         switch (csr_offset) {
2403         case CSR_STATE_CLEAR:
2404         case CSR_STATE_SET:
2405                 if (ohci->is_root &&
2406                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2407                      OHCI1394_LinkControl_cycleMaster))
2408                         value = CSR_STATE_BIT_CMSTR;
2409                 else
2410                         value = 0;
2411                 if (ohci->csr_state_setclear_abdicate)
2412                         value |= CSR_STATE_BIT_ABDICATE;
2413
2414                 return value;
2415
2416         case CSR_NODE_IDS:
2417                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2418
2419         case CSR_CYCLE_TIME:
2420                 return get_cycle_time(ohci);
2421
2422         case CSR_BUS_TIME:
2423                 /*
2424                  * We might be called just after the cycle timer has wrapped
2425                  * around but just before the cycle64Seconds handler, so we
2426                  * better check here, too, if the bus time needs to be updated.
2427                  */
2428                 spin_lock_irqsave(&ohci->lock, flags);
2429                 value = update_bus_time(ohci);
2430                 spin_unlock_irqrestore(&ohci->lock, flags);
2431                 return value;
2432
2433         case CSR_BUSY_TIMEOUT:
2434                 value = reg_read(ohci, OHCI1394_ATRetries);
2435                 return (value >> 4) & 0x0ffff00f;
2436
2437         case CSR_PRIORITY_BUDGET:
2438                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2439                         (ohci->pri_req_max << 8);
2440
2441         default:
2442                 WARN_ON(1);
2443                 return 0;
2444         }
2445 }
2446
2447 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2448 {
2449         struct fw_ohci *ohci = fw_ohci(card);
2450         unsigned long flags;
2451
2452         switch (csr_offset) {
2453         case CSR_STATE_CLEAR:
2454                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2455                         reg_write(ohci, OHCI1394_LinkControlClear,
2456                                   OHCI1394_LinkControl_cycleMaster);
2457                         flush_writes(ohci);
2458                 }
2459                 if (value & CSR_STATE_BIT_ABDICATE)
2460                         ohci->csr_state_setclear_abdicate = false;
2461                 break;
2462
2463         case CSR_STATE_SET:
2464                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2465                         reg_write(ohci, OHCI1394_LinkControlSet,
2466                                   OHCI1394_LinkControl_cycleMaster);
2467                         flush_writes(ohci);
2468                 }
2469                 if (value & CSR_STATE_BIT_ABDICATE)
2470                         ohci->csr_state_setclear_abdicate = true;
2471                 break;
2472
2473         case CSR_NODE_IDS:
2474                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2475                 flush_writes(ohci);
2476                 break;
2477
2478         case CSR_CYCLE_TIME:
2479                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2480                 reg_write(ohci, OHCI1394_IntEventSet,
2481                           OHCI1394_cycleInconsistent);
2482                 flush_writes(ohci);
2483                 break;
2484
2485         case CSR_BUS_TIME:
2486                 spin_lock_irqsave(&ohci->lock, flags);
2487                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2488                 spin_unlock_irqrestore(&ohci->lock, flags);
2489                 break;
2490
2491         case CSR_BUSY_TIMEOUT:
2492                 value = (value & 0xf) | ((value & 0xf) << 4) |
2493                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2494                 reg_write(ohci, OHCI1394_ATRetries, value);
2495                 flush_writes(ohci);
2496                 break;
2497
2498         case CSR_PRIORITY_BUDGET:
2499                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2500                 flush_writes(ohci);
2501                 break;
2502
2503         default:
2504                 WARN_ON(1);
2505                 break;
2506         }
2507 }
2508
2509 static void copy_iso_headers(struct iso_context *ctx, void *p)
2510 {
2511         int i = ctx->header_length;
2512
2513         if (i + ctx->base.header_size > PAGE_SIZE)
2514                 return;
2515
2516         /*
2517          * The iso header is byteswapped to little endian by
2518          * the controller, but the remaining header quadlets
2519          * are big endian.  We want to present all the headers
2520          * as big endian, so we have to swap the first quadlet.
2521          */
2522         if (ctx->base.header_size > 0)
2523                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2524         if (ctx->base.header_size > 4)
2525                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2526         if (ctx->base.header_size > 8)
2527                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2528         ctx->header_length += ctx->base.header_size;
2529 }
2530
2531 static int handle_ir_packet_per_buffer(struct context *context,
2532                                        struct descriptor *d,
2533                                        struct descriptor *last)
2534 {
2535         struct iso_context *ctx =
2536                 container_of(context, struct iso_context, context);
2537         struct descriptor *pd;
2538         __le32 *ir_header;
2539         void *p;
2540
2541         for (pd = d; pd <= last; pd++)
2542                 if (pd->transfer_status)
2543                         break;
2544         if (pd > last)
2545                 /* Descriptor(s) not done yet, stop iteration */
2546                 return 0;
2547
2548         p = last + 1;
2549         copy_iso_headers(ctx, p);
2550
2551         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2552                 ir_header = (__le32 *) p;
2553                 ctx->base.callback.sc(&ctx->base,
2554                                       le32_to_cpu(ir_header[0]) & 0xffff,
2555                                       ctx->header_length, ctx->header,
2556                                       ctx->base.callback_data);
2557                 ctx->header_length = 0;
2558         }
2559
2560         return 1;
2561 }
2562
2563 /* d == last because each descriptor block is only a single descriptor. */
2564 static int handle_ir_buffer_fill(struct context *context,
2565                                  struct descriptor *d,
2566                                  struct descriptor *last)
2567 {
2568         struct iso_context *ctx =
2569                 container_of(context, struct iso_context, context);
2570
2571         if (!last->transfer_status)
2572                 /* Descriptor(s) not done yet, stop iteration */
2573                 return 0;
2574
2575         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2576                 ctx->base.callback.mc(&ctx->base,
2577                                       le32_to_cpu(last->data_address) +
2578                                       le16_to_cpu(last->req_count) -
2579                                       le16_to_cpu(last->res_count),
2580                                       ctx->base.callback_data);
2581
2582         return 1;
2583 }
2584
2585 static int handle_it_packet(struct context *context,
2586                             struct descriptor *d,
2587                             struct descriptor *last)
2588 {
2589         struct iso_context *ctx =
2590                 container_of(context, struct iso_context, context);
2591         int i;
2592         struct descriptor *pd;
2593
2594         for (pd = d; pd <= last; pd++)
2595                 if (pd->transfer_status)
2596                         break;
2597         if (pd > last)
2598                 /* Descriptor(s) not done yet, stop iteration */
2599                 return 0;
2600
2601         i = ctx->header_length;
2602         if (i + 4 < PAGE_SIZE) {
2603                 /* Present this value as big-endian to match the receive code */
2604                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2605                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2606                                 le16_to_cpu(pd->res_count));
2607                 ctx->header_length += 4;
2608         }
2609         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2610                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2611                                       ctx->header_length, ctx->header,
2612                                       ctx->base.callback_data);
2613                 ctx->header_length = 0;
2614         }
2615         return 1;
2616 }
2617
2618 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2619 {
2620         u32 hi = channels >> 32, lo = channels;
2621
2622         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2623         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2624         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2625         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2626         mmiowb();
2627         ohci->mc_channels = channels;
2628 }
2629
2630 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2631                                 int type, int channel, size_t header_size)
2632 {
2633         struct fw_ohci *ohci = fw_ohci(card);
2634         struct iso_context *uninitialized_var(ctx);
2635         descriptor_callback_t uninitialized_var(callback);
2636         u64 *uninitialized_var(channels);
2637         u32 *uninitialized_var(mask), uninitialized_var(regs);
2638         unsigned long flags;
2639         int index, ret = -EBUSY;
2640
2641         spin_lock_irqsave(&ohci->lock, flags);
2642
2643         switch (type) {
2644         case FW_ISO_CONTEXT_TRANSMIT:
2645                 mask     = &ohci->it_context_mask;
2646                 callback = handle_it_packet;
2647                 index    = ffs(*mask) - 1;
2648                 if (index >= 0) {
2649                         *mask &= ~(1 << index);
2650                         regs = OHCI1394_IsoXmitContextBase(index);
2651                         ctx  = &ohci->it_context_list[index];
2652                 }
2653                 break;
2654
2655         case FW_ISO_CONTEXT_RECEIVE:
2656                 channels = &ohci->ir_context_channels;
2657                 mask     = &ohci->ir_context_mask;
2658                 callback = handle_ir_packet_per_buffer;
2659                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2660                 if (index >= 0) {
2661                         *channels &= ~(1ULL << channel);
2662                         *mask     &= ~(1 << index);
2663                         regs = OHCI1394_IsoRcvContextBase(index);
2664                         ctx  = &ohci->ir_context_list[index];
2665                 }
2666                 break;
2667
2668         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2669                 mask     = &ohci->ir_context_mask;
2670                 callback = handle_ir_buffer_fill;
2671                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2672                 if (index >= 0) {
2673                         ohci->mc_allocated = true;
2674                         *mask &= ~(1 << index);
2675                         regs = OHCI1394_IsoRcvContextBase(index);
2676                         ctx  = &ohci->ir_context_list[index];
2677                 }
2678                 break;
2679
2680         default:
2681                 index = -1;
2682                 ret = -ENOSYS;
2683         }
2684
2685         spin_unlock_irqrestore(&ohci->lock, flags);
2686
2687         if (index < 0)
2688                 return ERR_PTR(ret);
2689
2690         memset(ctx, 0, sizeof(*ctx));
2691         ctx->header_length = 0;
2692         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2693         if (ctx->header == NULL) {
2694                 ret = -ENOMEM;
2695                 goto out;
2696         }
2697         ret = context_init(&ctx->context, ohci, regs, callback);
2698         if (ret < 0)
2699                 goto out_with_header;
2700
2701         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2702                 set_multichannel_mask(ohci, 0);
2703
2704         return &ctx->base;
2705
2706  out_with_header:
2707         free_page((unsigned long)ctx->header);
2708  out:
2709         spin_lock_irqsave(&ohci->lock, flags);
2710
2711         switch (type) {
2712         case FW_ISO_CONTEXT_RECEIVE:
2713                 *channels |= 1ULL << channel;
2714                 break;
2715
2716         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2717                 ohci->mc_allocated = false;
2718                 break;
2719         }
2720         *mask |= 1 << index;
2721
2722         spin_unlock_irqrestore(&ohci->lock, flags);
2723
2724         return ERR_PTR(ret);
2725 }
2726
2727 static int ohci_start_iso(struct fw_iso_context *base,
2728                           s32 cycle, u32 sync, u32 tags)
2729 {
2730         struct iso_context *ctx = container_of(base, struct iso_context, base);
2731         struct fw_ohci *ohci = ctx->context.ohci;
2732         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2733         int index;
2734
2735         /* the controller cannot start without any queued packets */
2736         if (ctx->context.last->branch_address == 0)
2737                 return -ENODATA;
2738
2739         switch (ctx->base.type) {
2740         case FW_ISO_CONTEXT_TRANSMIT:
2741                 index = ctx - ohci->it_context_list;
2742                 match = 0;
2743                 if (cycle >= 0)
2744                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2745                                 (cycle & 0x7fff) << 16;
2746
2747                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2748                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2749                 context_run(&ctx->context, match);
2750                 break;
2751
2752         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2753                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2754                 /* fall through */
2755         case FW_ISO_CONTEXT_RECEIVE:
2756                 index = ctx - ohci->ir_context_list;
2757                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2758                 if (cycle >= 0) {
2759                         match |= (cycle & 0x07fff) << 12;
2760                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2761                 }
2762
2763                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2764                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2765                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2766                 context_run(&ctx->context, control);
2767
2768                 ctx->sync = sync;
2769                 ctx->tags = tags;
2770
2771                 break;
2772         }
2773
2774         return 0;
2775 }
2776
2777 static int ohci_stop_iso(struct fw_iso_context *base)
2778 {
2779         struct fw_ohci *ohci = fw_ohci(base->card);
2780         struct iso_context *ctx = container_of(base, struct iso_context, base);
2781         int index;
2782
2783         switch (ctx->base.type) {
2784         case FW_ISO_CONTEXT_TRANSMIT:
2785                 index = ctx - ohci->it_context_list;
2786                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2787                 break;
2788
2789         case FW_ISO_CONTEXT_RECEIVE:
2790         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2791                 index = ctx - ohci->ir_context_list;
2792                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2793                 break;
2794         }
2795         flush_writes(ohci);
2796         context_stop(&ctx->context);
2797         tasklet_kill(&ctx->context.tasklet);
2798
2799         return 0;
2800 }
2801
2802 static void ohci_free_iso_context(struct fw_iso_context *base)
2803 {
2804         struct fw_ohci *ohci = fw_ohci(base->card);
2805         struct iso_context *ctx = container_of(base, struct iso_context, base);
2806         unsigned long flags;
2807         int index;
2808
2809         ohci_stop_iso(base);
2810         context_release(&ctx->context);
2811         free_page((unsigned long)ctx->header);
2812
2813         spin_lock_irqsave(&ohci->lock, flags);
2814
2815         switch (base->type) {
2816         case FW_ISO_CONTEXT_TRANSMIT:
2817                 index = ctx - ohci->it_context_list;
2818                 ohci->it_context_mask |= 1 << index;
2819                 break;
2820
2821         case FW_ISO_CONTEXT_RECEIVE:
2822                 index = ctx - ohci->ir_context_list;
2823                 ohci->ir_context_mask |= 1 << index;
2824                 ohci->ir_context_channels |= 1ULL << base->channel;
2825                 break;
2826
2827         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2828                 index = ctx - ohci->ir_context_list;
2829                 ohci->ir_context_mask |= 1 << index;
2830                 ohci->ir_context_channels |= ohci->mc_channels;
2831                 ohci->mc_channels = 0;
2832                 ohci->mc_allocated = false;
2833                 break;
2834         }
2835
2836         spin_unlock_irqrestore(&ohci->lock, flags);
2837 }
2838
2839 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2840 {
2841         struct fw_ohci *ohci = fw_ohci(base->card);
2842         unsigned long flags;
2843         int ret;
2844
2845         switch (base->type) {
2846         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2847
2848                 spin_lock_irqsave(&ohci->lock, flags);
2849
2850                 /* Don't allow multichannel to grab other contexts' channels. */
2851                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2852                         *channels = ohci->ir_context_channels;
2853                         ret = -EBUSY;
2854                 } else {
2855                         set_multichannel_mask(ohci, *channels);
2856                         ret = 0;
2857                 }
2858
2859                 spin_unlock_irqrestore(&ohci->lock, flags);
2860
2861                 break;
2862         default:
2863                 ret = -EINVAL;
2864         }
2865
2866         return ret;
2867 }
2868
2869 #ifdef CONFIG_PM
2870 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2871 {
2872         int i;
2873         struct iso_context *ctx;
2874
2875         for (i = 0 ; i < ohci->n_ir ; i++) {
2876                 ctx = &ohci->ir_context_list[i];
2877                 if (ctx->context.running)
2878                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2879         }
2880
2881         for (i = 0 ; i < ohci->n_it ; i++) {
2882                 ctx = &ohci->it_context_list[i];
2883                 if (ctx->context.running)
2884                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2885         }
2886 }
2887 #endif
2888
2889 static int queue_iso_transmit(struct iso_context *ctx,
2890                               struct fw_iso_packet *packet,
2891                               struct fw_iso_buffer *buffer,
2892                               unsigned long payload)
2893 {
2894         struct descriptor *d, *last, *pd;
2895         struct fw_iso_packet *p;
2896         __le32 *header;
2897         dma_addr_t d_bus, page_bus;
2898         u32 z, header_z, payload_z, irq;
2899         u32 payload_index, payload_end_index, next_page_index;
2900         int page, end_page, i, length, offset;
2901
2902         p = packet;
2903         payload_index = payload;
2904
2905         if (p->skip)
2906                 z = 1;
2907         else
2908                 z = 2;
2909         if (p->header_length > 0)
2910                 z++;
2911
2912         /* Determine the first page the payload isn't contained in. */
2913         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2914         if (p->payload_length > 0)
2915                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2916         else
2917                 payload_z = 0;
2918
2919         z += payload_z;
2920
2921         /* Get header size in number of descriptors. */
2922         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2923
2924         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2925         if (d == NULL)
2926                 return -ENOMEM;
2927
2928         if (!p->skip) {
2929                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2930                 d[0].req_count = cpu_to_le16(8);
2931                 /*
2932                  * Link the skip address to this descriptor itself.  This causes
2933                  * a context to skip a cycle whenever lost cycles or FIFO
2934                  * overruns occur, without dropping the data.  The application
2935                  * should then decide whether this is an error condition or not.
2936                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2937                  */
2938                 d[0].branch_address = cpu_to_le32(d_bus | z);
2939
2940                 header = (__le32 *) &d[1];
2941                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2942                                         IT_HEADER_TAG(p->tag) |
2943                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2944                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2945                                         IT_HEADER_SPEED(ctx->base.speed));
2946                 header[1] =
2947                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2948                                                           p->payload_length));
2949         }
2950
2951         if (p->header_length > 0) {
2952                 d[2].req_count    = cpu_to_le16(p->header_length);
2953                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2954                 memcpy(&d[z], p->header, p->header_length);
2955         }
2956
2957         pd = d + z - payload_z;
2958         payload_end_index = payload_index + p->payload_length;
2959         for (i = 0; i < payload_z; i++) {
2960                 page               = payload_index >> PAGE_SHIFT;
2961                 offset             = payload_index & ~PAGE_MASK;
2962                 next_page_index    = (page + 1) << PAGE_SHIFT;
2963                 length             =
2964                         min(next_page_index, payload_end_index) - payload_index;
2965                 pd[i].req_count    = cpu_to_le16(length);
2966
2967                 page_bus = page_private(buffer->pages[page]);
2968                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2969
2970                 payload_index += length;
2971         }
2972
2973         if (p->interrupt)
2974                 irq = DESCRIPTOR_IRQ_ALWAYS;
2975         else
2976                 irq = DESCRIPTOR_NO_IRQ;
2977
2978         last = z == 2 ? d : d + z - 1;
2979         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2980                                      DESCRIPTOR_STATUS |
2981                                      DESCRIPTOR_BRANCH_ALWAYS |
2982                                      irq);
2983
2984         context_append(&ctx->context, d, z, header_z);
2985
2986         return 0;
2987 }
2988
2989 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2990                                        struct fw_iso_packet *packet,
2991                                        struct fw_iso_buffer *buffer,
2992                                        unsigned long payload)
2993 {
2994         struct descriptor *d, *pd;
2995         dma_addr_t d_bus, page_bus;
2996         u32 z, header_z, rest;
2997         int i, j, length;
2998         int page, offset, packet_count, header_size, payload_per_buffer;
2999
3000         /*
3001          * The OHCI controller puts the isochronous header and trailer in the
3002          * buffer, so we need at least 8 bytes.
3003          */
3004         packet_count = packet->header_length / ctx->base.header_size;
3005         header_size  = max(ctx->base.header_size, (size_t)8);
3006
3007         /* Get header size in number of descriptors. */
3008         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3009         page     = payload >> PAGE_SHIFT;
3010         offset   = payload & ~PAGE_MASK;
3011         payload_per_buffer = packet->payload_length / packet_count;
3012
3013         for (i = 0; i < packet_count; i++) {
3014                 /* d points to the header descriptor */
3015                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3016                 d = context_get_descriptors(&ctx->context,
3017                                 z + header_z, &d_bus);
3018                 if (d == NULL)
3019                         return -ENOMEM;
3020
3021                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3022                                               DESCRIPTOR_INPUT_MORE);
3023                 if (packet->skip && i == 0)
3024                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3025                 d->req_count    = cpu_to_le16(header_size);
3026                 d->res_count    = d->req_count;
3027                 d->transfer_status = 0;
3028                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3029
3030                 rest = payload_per_buffer;
3031                 pd = d;
3032                 for (j = 1; j < z; j++) {
3033                         pd++;
3034                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3035                                                   DESCRIPTOR_INPUT_MORE);
3036
3037                         if (offset + rest < PAGE_SIZE)
3038                                 length = rest;
3039                         else
3040                                 length = PAGE_SIZE - offset;
3041                         pd->req_count = cpu_to_le16(length);
3042                         pd->res_count = pd->req_count;
3043                         pd->transfer_status = 0;
3044
3045                         page_bus = page_private(buffer->pages[page]);
3046                         pd->data_address = cpu_to_le32(page_bus + offset);
3047
3048                         offset = (offset + length) & ~PAGE_MASK;
3049                         rest -= length;
3050                         if (offset == 0)
3051                                 page++;
3052                 }
3053                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3054                                           DESCRIPTOR_INPUT_LAST |
3055                                           DESCRIPTOR_BRANCH_ALWAYS);
3056                 if (packet->interrupt && i == packet_count - 1)
3057                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3058
3059                 context_append(&ctx->context, d, z, header_z);
3060         }
3061
3062         return 0;
3063 }
3064
3065 static int queue_iso_buffer_fill(struct iso_context *ctx,
3066                                  struct fw_iso_packet *packet,
3067                                  struct fw_iso_buffer *buffer,
3068                                  unsigned long payload)
3069 {
3070         struct descriptor *d;
3071         dma_addr_t d_bus, page_bus;
3072         int page, offset, rest, z, i, length;
3073
3074         page   = payload >> PAGE_SHIFT;
3075         offset = payload & ~PAGE_MASK;
3076         rest   = packet->payload_length;
3077
3078         /* We need one descriptor for each page in the buffer. */
3079         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3080
3081         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3082                 return -EFAULT;
3083
3084         for (i = 0; i < z; i++) {
3085                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3086                 if (d == NULL)
3087                         return -ENOMEM;
3088
3089                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3090                                          DESCRIPTOR_BRANCH_ALWAYS);
3091                 if (packet->skip && i == 0)
3092                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3093                 if (packet->interrupt && i == z - 1)
3094                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3095
3096                 if (offset + rest < PAGE_SIZE)
3097                         length = rest;
3098                 else
3099                         length = PAGE_SIZE - offset;
3100                 d->req_count = cpu_to_le16(length);
3101                 d->res_count = d->req_count;
3102                 d->transfer_status = 0;
3103
3104                 page_bus = page_private(buffer->pages[page]);
3105                 d->data_address = cpu_to_le32(page_bus + offset);
3106
3107                 rest -= length;
3108                 offset = 0;
3109                 page++;
3110
3111                 context_append(&ctx->context, d, 1, 0);
3112         }
3113
3114         return 0;
3115 }
3116
3117 static int ohci_queue_iso(struct fw_iso_context *base,
3118                           struct fw_iso_packet *packet,
3119                           struct fw_iso_buffer *buffer,
3120                           unsigned long payload)
3121 {
3122         struct iso_context *ctx = container_of(base, struct iso_context, base);
3123         unsigned long flags;
3124         int ret = -ENOSYS;
3125
3126         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3127         switch (base->type) {
3128         case FW_ISO_CONTEXT_TRANSMIT:
3129                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3130                 break;
3131         case FW_ISO_CONTEXT_RECEIVE:
3132                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3133                 break;
3134         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3135                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3136                 break;
3137         }
3138         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3139
3140         return ret;
3141 }
3142
3143 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3144 {
3145         struct context *ctx =
3146                         &container_of(base, struct iso_context, base)->context;
3147
3148         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3149 }
3150
3151 static const struct fw_card_driver ohci_driver = {
3152         .enable                 = ohci_enable,
3153         .read_phy_reg           = ohci_read_phy_reg,
3154         .update_phy_reg         = ohci_update_phy_reg,
3155         .set_config_rom         = ohci_set_config_rom,
3156         .send_request           = ohci_send_request,
3157         .send_response          = ohci_send_response,
3158         .cancel_packet          = ohci_cancel_packet,
3159         .enable_phys_dma        = ohci_enable_phys_dma,
3160         .read_csr               = ohci_read_csr,
3161         .write_csr              = ohci_write_csr,
3162
3163         .allocate_iso_context   = ohci_allocate_iso_context,
3164         .free_iso_context       = ohci_free_iso_context,
3165         .set_iso_channels       = ohci_set_iso_channels,
3166         .queue_iso              = ohci_queue_iso,
3167         .flush_queue_iso        = ohci_flush_queue_iso,
3168         .start_iso              = ohci_start_iso,
3169         .stop_iso               = ohci_stop_iso,
3170 };
3171
3172 #ifdef CONFIG_PPC_PMAC
3173 static void pmac_ohci_on(struct pci_dev *dev)
3174 {
3175         if (machine_is(powermac)) {
3176                 struct device_node *ofn = pci_device_to_OF_node(dev);
3177
3178                 if (ofn) {
3179                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3180                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3181                 }
3182         }
3183 }
3184
3185 static void pmac_ohci_off(struct pci_dev *dev)
3186 {
3187         if (machine_is(powermac)) {
3188                 struct device_node *ofn = pci_device_to_OF_node(dev);
3189
3190                 if (ofn) {
3191                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3192                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3193                 }
3194         }
3195 }
3196 #else
3197 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3198 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3199 #endif /* CONFIG_PPC_PMAC */
3200
3201 static int __devinit pci_probe(struct pci_dev *dev,
3202                                const struct pci_device_id *ent)
3203 {
3204         struct fw_ohci *ohci;
3205         u32 bus_options, max_receive, link_speed, version;
3206         u64 guid;
3207         int i, err;
3208         size_t size;
3209
3210         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3211         if (ohci == NULL) {
3212                 err = -ENOMEM;
3213                 goto fail;
3214         }
3215
3216         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3217
3218         pmac_ohci_on(dev);
3219
3220         err = pci_enable_device(dev);
3221         if (err) {
3222                 fw_error("Failed to enable OHCI hardware\n");
3223                 goto fail_free;
3224         }
3225
3226         pci_set_master(dev);
3227         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3228         pci_set_drvdata(dev, ohci);
3229
3230         spin_lock_init(&ohci->lock);
3231         mutex_init(&ohci->phy_reg_mutex);
3232
3233         tasklet_init(&ohci->bus_reset_tasklet,
3234                      bus_reset_tasklet, (unsigned long)ohci);
3235
3236         err = pci_request_region(dev, 0, ohci_driver_name);
3237         if (err) {
3238                 fw_error("MMIO resource unavailable\n");
3239                 goto fail_disable;
3240         }
3241
3242         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3243         if (ohci->registers == NULL) {
3244                 fw_error("Failed to remap registers\n");
3245                 err = -ENXIO;
3246                 goto fail_iomem;
3247         }
3248
3249         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3250                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3251                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3252                      ohci_quirks[i].device == dev->device) &&
3253                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3254                      ohci_quirks[i].revision >= dev->revision)) {
3255                         ohci->quirks = ohci_quirks[i].flags;
3256                         break;
3257                 }
3258         if (param_quirks)
3259                 ohci->quirks = param_quirks;
3260
3261         /*
3262          * Because dma_alloc_coherent() allocates at least one page,
3263          * we save space by using a common buffer for the AR request/
3264          * response descriptors and the self IDs buffer.
3265          */
3266         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3267         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3268         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3269                                                PAGE_SIZE,
3270                                                &ohci->misc_buffer_bus,
3271                                                GFP_KERNEL);
3272         if (!ohci->misc_buffer) {
3273                 err = -ENOMEM;
3274                 goto fail_iounmap;
3275         }
3276
3277         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3278                               OHCI1394_AsReqRcvContextControlSet);
3279         if (err < 0)
3280                 goto fail_misc_buf;
3281
3282         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3283                               OHCI1394_AsRspRcvContextControlSet);
3284         if (err < 0)
3285                 goto fail_arreq_ctx;
3286
3287         err = context_init(&ohci->at_request_ctx, ohci,
3288                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3289         if (err < 0)