drm: ati_pcigart: Fix limit check in drm_ati_pcigart_init().
[~shefty/rdma-dev.git] / drivers / gpu / drm / ati_pcigart.c
1 /**
2  * \file ati_pcigart.c
3  * ATI PCI GART support
4  *
5  * \author Gareth Hughes <gareth@valinux.com>
6  */
7
8 /*
9  * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
10  *
11  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
12  * All Rights Reserved.
13  *
14  * Permission is hereby granted, free of charge, to any person obtaining a
15  * copy of this software and associated documentation files (the "Software"),
16  * to deal in the Software without restriction, including without limitation
17  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18  * and/or sell copies of the Software, and to permit persons to whom the
19  * Software is furnished to do so, subject to the following conditions:
20  *
21  * The above copyright notice and this permission notice (including the next
22  * paragraph) shall be included in all copies or substantial portions of the
23  * Software.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
28  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
30  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
31  * DEALINGS IN THE SOFTWARE.
32  */
33
34 #include "drmP.h"
35
36 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
37
38 static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
39                                        struct drm_ati_pcigart_info *gart_info)
40 {
41         gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
42                                                 PAGE_SIZE,
43                                                 gart_info->table_mask);
44         if (gart_info->table_handle == NULL)
45                 return -ENOMEM;
46
47         return 0;
48 }
49
50 static void drm_ati_free_pcigart_table(struct drm_device *dev,
51                                        struct drm_ati_pcigart_info *gart_info)
52 {
53         drm_pci_free(dev, gart_info->table_handle);
54         gart_info->table_handle = NULL;
55 }
56
57 int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
58 {
59         struct drm_sg_mem *entry = dev->sg;
60         unsigned long pages;
61         int i;
62         int max_pages;
63
64         /* we need to support large memory configurations */
65         if (!entry) {
66                 DRM_ERROR("no scatter/gather memory!\n");
67                 return 0;
68         }
69
70         if (gart_info->bus_addr) {
71
72                 max_pages = (gart_info->table_size / sizeof(u32));
73                 pages = (entry->pages <= max_pages)
74                   ? entry->pages : max_pages;
75
76                 for (i = 0; i < pages; i++) {
77                         if (!entry->busaddr[i])
78                                 break;
79                         pci_unmap_page(dev->pdev, entry->busaddr[i],
80                                          PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
81                 }
82
83                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
84                         gart_info->bus_addr = 0;
85         }
86
87         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
88             gart_info->table_handle) {
89                 drm_ati_free_pcigart_table(dev, gart_info);
90         }
91
92         return 1;
93 }
94 EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
95
96 int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
97 {
98         struct drm_local_map *map = &gart_info->mapping;
99         struct drm_sg_mem *entry = dev->sg;
100         void *address = NULL;
101         unsigned long pages;
102         u32 *pci_gart, page_base, gart_idx;
103         dma_addr_t bus_address = 0;
104         int i, j, ret = 0;
105         int max_ati_pages, max_real_pages;
106
107         if (!entry) {
108                 DRM_ERROR("no scatter/gather memory!\n");
109                 goto done;
110         }
111
112         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
113                 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
114
115                 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
116                 if (ret) {
117                         DRM_ERROR("cannot allocate PCI GART page!\n");
118                         goto done;
119                 }
120
121                 address = gart_info->table_handle->vaddr;
122                 bus_address = gart_info->table_handle->busaddr;
123         } else {
124                 address = gart_info->addr;
125                 bus_address = gart_info->bus_addr;
126                 DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
127                           (unsigned long long)bus_address,
128                           (unsigned long)address);
129         }
130
131         pci_gart = (u32 *) address;
132
133         max_ati_pages = (gart_info->table_size / sizeof(u32));
134         max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
135         pages = (entry->pages <= max_real_pages)
136             ? entry->pages : max_real_pages;
137
138         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
139                 memset(pci_gart, 0, max_ati_pages * sizeof(u32));
140         } else {
141                 for (gart_idx = 0; gart_idx < max_ati_pages; gart_idx++)
142                         DRM_WRITE32(map, gart_idx * sizeof(u32), 0);
143         }
144
145         gart_idx = 0;
146         for (i = 0; i < pages; i++) {
147                 /* we need to support large memory configurations */
148                 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
149                                                  0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
150                 if (entry->busaddr[i] == 0) {
151                         DRM_ERROR("unable to map PCIGART pages!\n");
152                         drm_ati_pcigart_cleanup(dev, gart_info);
153                         address = NULL;
154                         bus_address = 0;
155                         goto done;
156                 }
157                 page_base = (u32) entry->busaddr[i];
158
159                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
160                         u32 val;
161
162                         switch(gart_info->gart_reg_if) {
163                         case DRM_ATI_GART_IGP:
164                                 val = page_base | 0xc;
165                                 break;
166                         case DRM_ATI_GART_PCIE:
167                                 val = (page_base >> 8) | 0xc;
168                                 break;
169                         default:
170                         case DRM_ATI_GART_PCI:
171                                 val = page_base;
172                                 break;
173                         }
174                         if (gart_info->gart_table_location ==
175                             DRM_ATI_GART_MAIN)
176                                 pci_gart[gart_idx] = cpu_to_le32(val);
177                         else
178                                 DRM_WRITE32(map, gart_idx * sizeof(u32), val);
179                         gart_idx++;
180                         page_base += ATI_PCIGART_PAGE_SIZE;
181                 }
182         }
183         ret = 1;
184
185 #if defined(__i386__) || defined(__x86_64__)
186         wbinvd();
187 #else
188         mb();
189 #endif
190
191       done:
192         gart_info->addr = address;
193         gart_info->bus_addr = bus_address;
194         return ret;
195 }
196 EXPORT_SYMBOL(drm_ati_pcigart_init);