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1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
38
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
40
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
44 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
45                                              int write);
46 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47                                                      uint64_t offset,
48                                                      uint64_t size);
49 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
50 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
51                                           bool interruptible);
52 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
53                                            unsigned alignment);
54 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
55 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
56                                 struct drm_i915_gem_pwrite *args,
57                                 struct drm_file *file_priv);
58 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
59
60 static int
61 i915_gem_object_get_pages(struct drm_gem_object *obj,
62                           gfp_t gfpmask);
63
64 static void
65 i915_gem_object_put_pages(struct drm_gem_object *obj);
66
67 static LIST_HEAD(shrink_list);
68 static DEFINE_SPINLOCK(shrink_list_lock);
69
70 /* some bookkeeping */
71 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
72                                   size_t size)
73 {
74         dev_priv->mm.object_count++;
75         dev_priv->mm.object_memory += size;
76 }
77
78 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
79                                      size_t size)
80 {
81         dev_priv->mm.object_count--;
82         dev_priv->mm.object_memory -= size;
83 }
84
85 static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
86                                   size_t size)
87 {
88         dev_priv->mm.gtt_count++;
89         dev_priv->mm.gtt_memory += size;
90 }
91
92 static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
93                                      size_t size)
94 {
95         dev_priv->mm.gtt_count--;
96         dev_priv->mm.gtt_memory -= size;
97 }
98
99 static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
100                                   size_t size)
101 {
102         dev_priv->mm.pin_count++;
103         dev_priv->mm.pin_memory += size;
104 }
105
106 static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
107                                      size_t size)
108 {
109         dev_priv->mm.pin_count--;
110         dev_priv->mm.pin_memory -= size;
111 }
112
113 int
114 i915_gem_check_is_wedged(struct drm_device *dev)
115 {
116         struct drm_i915_private *dev_priv = dev->dev_private;
117         struct completion *x = &dev_priv->error_completion;
118         unsigned long flags;
119         int ret;
120
121         if (!atomic_read(&dev_priv->mm.wedged))
122                 return 0;
123
124         ret = wait_for_completion_interruptible(x);
125         if (ret)
126                 return ret;
127
128         /* Success, we reset the GPU! */
129         if (!atomic_read(&dev_priv->mm.wedged))
130                 return 0;
131
132         /* GPU is hung, bump the completion count to account for
133          * the token we just consumed so that we never hit zero and
134          * end up waiting upon a subsequent completion event that
135          * will never happen.
136          */
137         spin_lock_irqsave(&x->wait.lock, flags);
138         x->done++;
139         spin_unlock_irqrestore(&x->wait.lock, flags);
140         return -EIO;
141 }
142
143 static int i915_mutex_lock_interruptible(struct drm_device *dev)
144 {
145         struct drm_i915_private *dev_priv = dev->dev_private;
146         int ret;
147
148         ret = i915_gem_check_is_wedged(dev);
149         if (ret)
150                 return ret;
151
152         ret = mutex_lock_interruptible(&dev->struct_mutex);
153         if (ret)
154                 return ret;
155
156         if (atomic_read(&dev_priv->mm.wedged)) {
157                 mutex_unlock(&dev->struct_mutex);
158                 return -EAGAIN;
159         }
160
161         WARN_ON(i915_verify_lists(dev));
162         return 0;
163 }
164
165 static inline bool
166 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
167 {
168         return obj_priv->gtt_space &&
169                 !obj_priv->active &&
170                 obj_priv->pin_count == 0;
171 }
172
173 int i915_gem_do_init(struct drm_device *dev,
174                      unsigned long start,
175                      unsigned long end)
176 {
177         drm_i915_private_t *dev_priv = dev->dev_private;
178
179         if (start >= end ||
180             (start & (PAGE_SIZE - 1)) != 0 ||
181             (end & (PAGE_SIZE - 1)) != 0) {
182                 return -EINVAL;
183         }
184
185         drm_mm_init(&dev_priv->mm.gtt_space, start,
186                     end - start);
187
188         dev_priv->mm.gtt_total = end - start;
189
190         return 0;
191 }
192
193 int
194 i915_gem_init_ioctl(struct drm_device *dev, void *data,
195                     struct drm_file *file_priv)
196 {
197         struct drm_i915_gem_init *args = data;
198         int ret;
199
200         mutex_lock(&dev->struct_mutex);
201         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
202         mutex_unlock(&dev->struct_mutex);
203
204         return ret;
205 }
206
207 int
208 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
209                             struct drm_file *file_priv)
210 {
211         struct drm_i915_private *dev_priv = dev->dev_private;
212         struct drm_i915_gem_get_aperture *args = data;
213
214         if (!(dev->driver->driver_features & DRIVER_GEM))
215                 return -ENODEV;
216
217         mutex_lock(&dev->struct_mutex);
218         args->aper_size = dev_priv->mm.gtt_total;
219         args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
220         mutex_unlock(&dev->struct_mutex);
221
222         return 0;
223 }
224
225
226 /**
227  * Creates a new mm object and returns a handle to it.
228  */
229 int
230 i915_gem_create_ioctl(struct drm_device *dev, void *data,
231                       struct drm_file *file_priv)
232 {
233         struct drm_i915_gem_create *args = data;
234         struct drm_gem_object *obj;
235         int ret;
236         u32 handle;
237
238         args->size = roundup(args->size, PAGE_SIZE);
239
240         /* Allocate the new object */
241         obj = i915_gem_alloc_object(dev, args->size);
242         if (obj == NULL)
243                 return -ENOMEM;
244
245         ret = drm_gem_handle_create(file_priv, obj, &handle);
246         if (ret) {
247                 drm_gem_object_release(obj);
248                 i915_gem_info_remove_obj(dev->dev_private, obj->size);
249                 kfree(obj);
250                 return ret;
251         }
252
253         /* drop reference from allocate - handle holds it now */
254         drm_gem_object_unreference(obj);
255         trace_i915_gem_object_create(obj);
256
257         args->handle = handle;
258         return 0;
259 }
260
261 static inline int
262 fast_shmem_read(struct page **pages,
263                 loff_t page_base, int page_offset,
264                 char __user *data,
265                 int length)
266 {
267         char *vaddr;
268         int ret;
269
270         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]);
271         ret = __copy_to_user_inatomic(data, vaddr + page_offset, length);
272         kunmap_atomic(vaddr);
273
274         return ret;
275 }
276
277 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
278 {
279         drm_i915_private_t *dev_priv = obj->dev->dev_private;
280         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
281
282         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
283                 obj_priv->tiling_mode != I915_TILING_NONE;
284 }
285
286 static inline void
287 slow_shmem_copy(struct page *dst_page,
288                 int dst_offset,
289                 struct page *src_page,
290                 int src_offset,
291                 int length)
292 {
293         char *dst_vaddr, *src_vaddr;
294
295         dst_vaddr = kmap(dst_page);
296         src_vaddr = kmap(src_page);
297
298         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
299
300         kunmap(src_page);
301         kunmap(dst_page);
302 }
303
304 static inline void
305 slow_shmem_bit17_copy(struct page *gpu_page,
306                       int gpu_offset,
307                       struct page *cpu_page,
308                       int cpu_offset,
309                       int length,
310                       int is_read)
311 {
312         char *gpu_vaddr, *cpu_vaddr;
313
314         /* Use the unswizzled path if this page isn't affected. */
315         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
316                 if (is_read)
317                         return slow_shmem_copy(cpu_page, cpu_offset,
318                                                gpu_page, gpu_offset, length);
319                 else
320                         return slow_shmem_copy(gpu_page, gpu_offset,
321                                                cpu_page, cpu_offset, length);
322         }
323
324         gpu_vaddr = kmap(gpu_page);
325         cpu_vaddr = kmap(cpu_page);
326
327         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
328          * XORing with the other bits (A9 for Y, A9 and A10 for X)
329          */
330         while (length > 0) {
331                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
332                 int this_length = min(cacheline_end - gpu_offset, length);
333                 int swizzled_gpu_offset = gpu_offset ^ 64;
334
335                 if (is_read) {
336                         memcpy(cpu_vaddr + cpu_offset,
337                                gpu_vaddr + swizzled_gpu_offset,
338                                this_length);
339                 } else {
340                         memcpy(gpu_vaddr + swizzled_gpu_offset,
341                                cpu_vaddr + cpu_offset,
342                                this_length);
343                 }
344                 cpu_offset += this_length;
345                 gpu_offset += this_length;
346                 length -= this_length;
347         }
348
349         kunmap(cpu_page);
350         kunmap(gpu_page);
351 }
352
353 /**
354  * This is the fast shmem pread path, which attempts to copy_from_user directly
355  * from the backing pages of the object to the user's address space.  On a
356  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
357  */
358 static int
359 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
360                           struct drm_i915_gem_pread *args,
361                           struct drm_file *file_priv)
362 {
363         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
364         ssize_t remain;
365         loff_t offset, page_base;
366         char __user *user_data;
367         int page_offset, page_length;
368
369         user_data = (char __user *) (uintptr_t) args->data_ptr;
370         remain = args->size;
371
372         obj_priv = to_intel_bo(obj);
373         offset = args->offset;
374
375         while (remain > 0) {
376                 /* Operation in this page
377                  *
378                  * page_base = page offset within aperture
379                  * page_offset = offset within page
380                  * page_length = bytes to copy for this page
381                  */
382                 page_base = (offset & ~(PAGE_SIZE-1));
383                 page_offset = offset & (PAGE_SIZE-1);
384                 page_length = remain;
385                 if ((page_offset + remain) > PAGE_SIZE)
386                         page_length = PAGE_SIZE - page_offset;
387
388                 if (fast_shmem_read(obj_priv->pages,
389                                     page_base, page_offset,
390                                     user_data, page_length))
391                         return -EFAULT;
392
393                 remain -= page_length;
394                 user_data += page_length;
395                 offset += page_length;
396         }
397
398         return 0;
399 }
400
401 static int
402 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
403 {
404         int ret;
405
406         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
407
408         /* If we've insufficient memory to map in the pages, attempt
409          * to make some space by throwing out some old buffers.
410          */
411         if (ret == -ENOMEM) {
412                 struct drm_device *dev = obj->dev;
413
414                 ret = i915_gem_evict_something(dev, obj->size,
415                                                i915_gem_get_gtt_alignment(obj));
416                 if (ret)
417                         return ret;
418
419                 ret = i915_gem_object_get_pages(obj, 0);
420         }
421
422         return ret;
423 }
424
425 /**
426  * This is the fallback shmem pread path, which allocates temporary storage
427  * in kernel space to copy_to_user into outside of the struct_mutex, so we
428  * can copy out of the object's backing pages while holding the struct mutex
429  * and not take page faults.
430  */
431 static int
432 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
433                           struct drm_i915_gem_pread *args,
434                           struct drm_file *file_priv)
435 {
436         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
437         struct mm_struct *mm = current->mm;
438         struct page **user_pages;
439         ssize_t remain;
440         loff_t offset, pinned_pages, i;
441         loff_t first_data_page, last_data_page, num_pages;
442         int shmem_page_index, shmem_page_offset;
443         int data_page_index,  data_page_offset;
444         int page_length;
445         int ret;
446         uint64_t data_ptr = args->data_ptr;
447         int do_bit17_swizzling;
448
449         remain = args->size;
450
451         /* Pin the user pages containing the data.  We can't fault while
452          * holding the struct mutex, yet we want to hold it while
453          * dereferencing the user data.
454          */
455         first_data_page = data_ptr / PAGE_SIZE;
456         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
457         num_pages = last_data_page - first_data_page + 1;
458
459         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
460         if (user_pages == NULL)
461                 return -ENOMEM;
462
463         mutex_unlock(&dev->struct_mutex);
464         down_read(&mm->mmap_sem);
465         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
466                                       num_pages, 1, 0, user_pages, NULL);
467         up_read(&mm->mmap_sem);
468         mutex_lock(&dev->struct_mutex);
469         if (pinned_pages < num_pages) {
470                 ret = -EFAULT;
471                 goto out;
472         }
473
474         ret = i915_gem_object_set_cpu_read_domain_range(obj,
475                                                         args->offset,
476                                                         args->size);
477         if (ret)
478                 goto out;
479
480         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
481
482         obj_priv = to_intel_bo(obj);
483         offset = args->offset;
484
485         while (remain > 0) {
486                 /* Operation in this page
487                  *
488                  * shmem_page_index = page number within shmem file
489                  * shmem_page_offset = offset within page in shmem file
490                  * data_page_index = page number in get_user_pages return
491                  * data_page_offset = offset with data_page_index page.
492                  * page_length = bytes to copy for this page
493                  */
494                 shmem_page_index = offset / PAGE_SIZE;
495                 shmem_page_offset = offset & ~PAGE_MASK;
496                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
497                 data_page_offset = data_ptr & ~PAGE_MASK;
498
499                 page_length = remain;
500                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
501                         page_length = PAGE_SIZE - shmem_page_offset;
502                 if ((data_page_offset + page_length) > PAGE_SIZE)
503                         page_length = PAGE_SIZE - data_page_offset;
504
505                 if (do_bit17_swizzling) {
506                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
507                                               shmem_page_offset,
508                                               user_pages[data_page_index],
509                                               data_page_offset,
510                                               page_length,
511                                               1);
512                 } else {
513                         slow_shmem_copy(user_pages[data_page_index],
514                                         data_page_offset,
515                                         obj_priv->pages[shmem_page_index],
516                                         shmem_page_offset,
517                                         page_length);
518                 }
519
520                 remain -= page_length;
521                 data_ptr += page_length;
522                 offset += page_length;
523         }
524
525 out:
526         for (i = 0; i < pinned_pages; i++) {
527                 SetPageDirty(user_pages[i]);
528                 page_cache_release(user_pages[i]);
529         }
530         drm_free_large(user_pages);
531
532         return ret;
533 }
534
535 /**
536  * Reads data from the object referenced by handle.
537  *
538  * On error, the contents of *data are undefined.
539  */
540 int
541 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
542                      struct drm_file *file_priv)
543 {
544         struct drm_i915_gem_pread *args = data;
545         struct drm_gem_object *obj;
546         struct drm_i915_gem_object *obj_priv;
547         int ret = 0;
548
549         if (args->size == 0)
550                 return 0;
551
552         if (!access_ok(VERIFY_WRITE,
553                        (char __user *)(uintptr_t)args->data_ptr,
554                        args->size))
555                 return -EFAULT;
556
557         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
558                                        args->size);
559         if (ret)
560                 return -EFAULT;
561
562         ret = i915_mutex_lock_interruptible(dev);
563         if (ret)
564                 return ret;
565
566         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
567         if (obj == NULL) {
568                 ret = -ENOENT;
569                 goto unlock;
570         }
571         obj_priv = to_intel_bo(obj);
572
573         /* Bounds check source.  */
574         if (args->offset > obj->size || args->size > obj->size - args->offset) {
575                 ret = -EINVAL;
576                 goto out;
577         }
578
579         ret = i915_gem_object_get_pages_or_evict(obj);
580         if (ret)
581                 goto out;
582
583         ret = i915_gem_object_set_cpu_read_domain_range(obj,
584                                                         args->offset,
585                                                         args->size);
586         if (ret)
587                 goto out_put;
588
589         ret = -EFAULT;
590         if (!i915_gem_object_needs_bit17_swizzle(obj))
591                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
592         if (ret == -EFAULT)
593                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
594
595 out_put:
596         i915_gem_object_put_pages(obj);
597 out:
598         drm_gem_object_unreference(obj);
599 unlock:
600         mutex_unlock(&dev->struct_mutex);
601         return ret;
602 }
603
604 /* This is the fast write path which cannot handle
605  * page faults in the source data
606  */
607
608 static inline int
609 fast_user_write(struct io_mapping *mapping,
610                 loff_t page_base, int page_offset,
611                 char __user *user_data,
612                 int length)
613 {
614         char *vaddr_atomic;
615         unsigned long unwritten;
616
617         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
618         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
619                                                       user_data, length);
620         io_mapping_unmap_atomic(vaddr_atomic);
621         return unwritten;
622 }
623
624 /* Here's the write path which can sleep for
625  * page faults
626  */
627
628 static inline void
629 slow_kernel_write(struct io_mapping *mapping,
630                   loff_t gtt_base, int gtt_offset,
631                   struct page *user_page, int user_offset,
632                   int length)
633 {
634         char __iomem *dst_vaddr;
635         char *src_vaddr;
636
637         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
638         src_vaddr = kmap(user_page);
639
640         memcpy_toio(dst_vaddr + gtt_offset,
641                     src_vaddr + user_offset,
642                     length);
643
644         kunmap(user_page);
645         io_mapping_unmap(dst_vaddr);
646 }
647
648 static inline int
649 fast_shmem_write(struct page **pages,
650                  loff_t page_base, int page_offset,
651                  char __user *data,
652                  int length)
653 {
654         char *vaddr;
655         int ret;
656
657         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]);
658         ret = __copy_from_user_inatomic(vaddr + page_offset, data, length);
659         kunmap_atomic(vaddr);
660
661         return ret;
662 }
663
664 /**
665  * This is the fast pwrite path, where we copy the data directly from the
666  * user into the GTT, uncached.
667  */
668 static int
669 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
670                          struct drm_i915_gem_pwrite *args,
671                          struct drm_file *file_priv)
672 {
673         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
674         drm_i915_private_t *dev_priv = dev->dev_private;
675         ssize_t remain;
676         loff_t offset, page_base;
677         char __user *user_data;
678         int page_offset, page_length;
679
680         user_data = (char __user *) (uintptr_t) args->data_ptr;
681         remain = args->size;
682
683         obj_priv = to_intel_bo(obj);
684         offset = obj_priv->gtt_offset + args->offset;
685
686         while (remain > 0) {
687                 /* Operation in this page
688                  *
689                  * page_base = page offset within aperture
690                  * page_offset = offset within page
691                  * page_length = bytes to copy for this page
692                  */
693                 page_base = (offset & ~(PAGE_SIZE-1));
694                 page_offset = offset & (PAGE_SIZE-1);
695                 page_length = remain;
696                 if ((page_offset + remain) > PAGE_SIZE)
697                         page_length = PAGE_SIZE - page_offset;
698
699                 /* If we get a fault while copying data, then (presumably) our
700                  * source page isn't available.  Return the error and we'll
701                  * retry in the slow path.
702                  */
703                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
704                                     page_offset, user_data, page_length))
705
706                         return -EFAULT;
707
708                 remain -= page_length;
709                 user_data += page_length;
710                 offset += page_length;
711         }
712
713         return 0;
714 }
715
716 /**
717  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
718  * the memory and maps it using kmap_atomic for copying.
719  *
720  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
721  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
722  */
723 static int
724 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
725                          struct drm_i915_gem_pwrite *args,
726                          struct drm_file *file_priv)
727 {
728         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
729         drm_i915_private_t *dev_priv = dev->dev_private;
730         ssize_t remain;
731         loff_t gtt_page_base, offset;
732         loff_t first_data_page, last_data_page, num_pages;
733         loff_t pinned_pages, i;
734         struct page **user_pages;
735         struct mm_struct *mm = current->mm;
736         int gtt_page_offset, data_page_offset, data_page_index, page_length;
737         int ret;
738         uint64_t data_ptr = args->data_ptr;
739
740         remain = args->size;
741
742         /* Pin the user pages containing the data.  We can't fault while
743          * holding the struct mutex, and all of the pwrite implementations
744          * want to hold it while dereferencing the user data.
745          */
746         first_data_page = data_ptr / PAGE_SIZE;
747         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
748         num_pages = last_data_page - first_data_page + 1;
749
750         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
751         if (user_pages == NULL)
752                 return -ENOMEM;
753
754         mutex_unlock(&dev->struct_mutex);
755         down_read(&mm->mmap_sem);
756         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
757                                       num_pages, 0, 0, user_pages, NULL);
758         up_read(&mm->mmap_sem);
759         mutex_lock(&dev->struct_mutex);
760         if (pinned_pages < num_pages) {
761                 ret = -EFAULT;
762                 goto out_unpin_pages;
763         }
764
765         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
766         if (ret)
767                 goto out_unpin_pages;
768
769         obj_priv = to_intel_bo(obj);
770         offset = obj_priv->gtt_offset + args->offset;
771
772         while (remain > 0) {
773                 /* Operation in this page
774                  *
775                  * gtt_page_base = page offset within aperture
776                  * gtt_page_offset = offset within page in aperture
777                  * data_page_index = page number in get_user_pages return
778                  * data_page_offset = offset with data_page_index page.
779                  * page_length = bytes to copy for this page
780                  */
781                 gtt_page_base = offset & PAGE_MASK;
782                 gtt_page_offset = offset & ~PAGE_MASK;
783                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
784                 data_page_offset = data_ptr & ~PAGE_MASK;
785
786                 page_length = remain;
787                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
788                         page_length = PAGE_SIZE - gtt_page_offset;
789                 if ((data_page_offset + page_length) > PAGE_SIZE)
790                         page_length = PAGE_SIZE - data_page_offset;
791
792                 slow_kernel_write(dev_priv->mm.gtt_mapping,
793                                   gtt_page_base, gtt_page_offset,
794                                   user_pages[data_page_index],
795                                   data_page_offset,
796                                   page_length);
797
798                 remain -= page_length;
799                 offset += page_length;
800                 data_ptr += page_length;
801         }
802
803 out_unpin_pages:
804         for (i = 0; i < pinned_pages; i++)
805                 page_cache_release(user_pages[i]);
806         drm_free_large(user_pages);
807
808         return ret;
809 }
810
811 /**
812  * This is the fast shmem pwrite path, which attempts to directly
813  * copy_from_user into the kmapped pages backing the object.
814  */
815 static int
816 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
817                            struct drm_i915_gem_pwrite *args,
818                            struct drm_file *file_priv)
819 {
820         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
821         ssize_t remain;
822         loff_t offset, page_base;
823         char __user *user_data;
824         int page_offset, page_length;
825
826         user_data = (char __user *) (uintptr_t) args->data_ptr;
827         remain = args->size;
828
829         obj_priv = to_intel_bo(obj);
830         offset = args->offset;
831         obj_priv->dirty = 1;
832
833         while (remain > 0) {
834                 /* Operation in this page
835                  *
836                  * page_base = page offset within aperture
837                  * page_offset = offset within page
838                  * page_length = bytes to copy for this page
839                  */
840                 page_base = (offset & ~(PAGE_SIZE-1));
841                 page_offset = offset & (PAGE_SIZE-1);
842                 page_length = remain;
843                 if ((page_offset + remain) > PAGE_SIZE)
844                         page_length = PAGE_SIZE - page_offset;
845
846                 if (fast_shmem_write(obj_priv->pages,
847                                        page_base, page_offset,
848                                        user_data, page_length))
849                         return -EFAULT;
850
851                 remain -= page_length;
852                 user_data += page_length;
853                 offset += page_length;
854         }
855
856         return 0;
857 }
858
859 /**
860  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
861  * the memory and maps it using kmap_atomic for copying.
862  *
863  * This avoids taking mmap_sem for faulting on the user's address while the
864  * struct_mutex is held.
865  */
866 static int
867 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
868                            struct drm_i915_gem_pwrite *args,
869                            struct drm_file *file_priv)
870 {
871         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
872         struct mm_struct *mm = current->mm;
873         struct page **user_pages;
874         ssize_t remain;
875         loff_t offset, pinned_pages, i;
876         loff_t first_data_page, last_data_page, num_pages;
877         int shmem_page_index, shmem_page_offset;
878         int data_page_index,  data_page_offset;
879         int page_length;
880         int ret;
881         uint64_t data_ptr = args->data_ptr;
882         int do_bit17_swizzling;
883
884         remain = args->size;
885
886         /* Pin the user pages containing the data.  We can't fault while
887          * holding the struct mutex, and all of the pwrite implementations
888          * want to hold it while dereferencing the user data.
889          */
890         first_data_page = data_ptr / PAGE_SIZE;
891         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
892         num_pages = last_data_page - first_data_page + 1;
893
894         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
895         if (user_pages == NULL)
896                 return -ENOMEM;
897
898         mutex_unlock(&dev->struct_mutex);
899         down_read(&mm->mmap_sem);
900         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
901                                       num_pages, 0, 0, user_pages, NULL);
902         up_read(&mm->mmap_sem);
903         mutex_lock(&dev->struct_mutex);
904         if (pinned_pages < num_pages) {
905                 ret = -EFAULT;
906                 goto out;
907         }
908
909         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
910         if (ret)
911                 goto out;
912
913         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
914
915         obj_priv = to_intel_bo(obj);
916         offset = args->offset;
917         obj_priv->dirty = 1;
918
919         while (remain > 0) {
920                 /* Operation in this page
921                  *
922                  * shmem_page_index = page number within shmem file
923                  * shmem_page_offset = offset within page in shmem file
924                  * data_page_index = page number in get_user_pages return
925                  * data_page_offset = offset with data_page_index page.
926                  * page_length = bytes to copy for this page
927                  */
928                 shmem_page_index = offset / PAGE_SIZE;
929                 shmem_page_offset = offset & ~PAGE_MASK;
930                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
931                 data_page_offset = data_ptr & ~PAGE_MASK;
932
933                 page_length = remain;
934                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
935                         page_length = PAGE_SIZE - shmem_page_offset;
936                 if ((data_page_offset + page_length) > PAGE_SIZE)
937                         page_length = PAGE_SIZE - data_page_offset;
938
939                 if (do_bit17_swizzling) {
940                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
941                                               shmem_page_offset,
942                                               user_pages[data_page_index],
943                                               data_page_offset,
944                                               page_length,
945                                               0);
946                 } else {
947                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
948                                         shmem_page_offset,
949                                         user_pages[data_page_index],
950                                         data_page_offset,
951                                         page_length);
952                 }
953
954                 remain -= page_length;
955                 data_ptr += page_length;
956                 offset += page_length;
957         }
958
959 out:
960         for (i = 0; i < pinned_pages; i++)
961                 page_cache_release(user_pages[i]);
962         drm_free_large(user_pages);
963
964         return ret;
965 }
966
967 /**
968  * Writes data to the object referenced by handle.
969  *
970  * On error, the contents of the buffer that were to be modified are undefined.
971  */
972 int
973 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
974                       struct drm_file *file)
975 {
976         struct drm_i915_gem_pwrite *args = data;
977         struct drm_gem_object *obj;
978         struct drm_i915_gem_object *obj_priv;
979         int ret;
980
981         if (args->size == 0)
982                 return 0;
983
984         if (!access_ok(VERIFY_READ,
985                        (char __user *)(uintptr_t)args->data_ptr,
986                        args->size))
987                 return -EFAULT;
988
989         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
990                                       args->size);
991         if (ret)
992                 return -EFAULT;
993
994         ret = i915_mutex_lock_interruptible(dev);
995         if (ret)
996                 return ret;
997
998         obj = drm_gem_object_lookup(dev, file, args->handle);
999         if (obj == NULL) {
1000                 ret = -ENOENT;
1001                 goto unlock;
1002         }
1003         obj_priv = to_intel_bo(obj);
1004
1005         /* Bounds check destination. */
1006         if (args->offset > obj->size || args->size > obj->size - args->offset) {
1007                 ret = -EINVAL;
1008                 goto out;
1009         }
1010
1011         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1012          * it would end up going through the fenced access, and we'll get
1013          * different detiling behavior between reading and writing.
1014          * pread/pwrite currently are reading and writing from the CPU
1015          * perspective, requiring manual detiling by the client.
1016          */
1017         if (obj_priv->phys_obj)
1018                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1019         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
1020                  obj_priv->gtt_space &&
1021                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
1022                 ret = i915_gem_object_pin(obj, 0);
1023                 if (ret)
1024                         goto out;
1025
1026                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1027                 if (ret)
1028                         goto out_unpin;
1029
1030                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1031                 if (ret == -EFAULT)
1032                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1033
1034 out_unpin:
1035                 i915_gem_object_unpin(obj);
1036         } else {
1037                 ret = i915_gem_object_get_pages_or_evict(obj);
1038                 if (ret)
1039                         goto out;
1040
1041                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1042                 if (ret)
1043                         goto out_put;
1044
1045                 ret = -EFAULT;
1046                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1047                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1048                 if (ret == -EFAULT)
1049                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1050
1051 out_put:
1052                 i915_gem_object_put_pages(obj);
1053         }
1054
1055 out:
1056         drm_gem_object_unreference(obj);
1057 unlock:
1058         mutex_unlock(&dev->struct_mutex);
1059         return ret;
1060 }
1061
1062 /**
1063  * Called when user space prepares to use an object with the CPU, either
1064  * through the mmap ioctl's mapping or a GTT mapping.
1065  */
1066 int
1067 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1068                           struct drm_file *file_priv)
1069 {
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         struct drm_i915_gem_set_domain *args = data;
1072         struct drm_gem_object *obj;
1073         struct drm_i915_gem_object *obj_priv;
1074         uint32_t read_domains = args->read_domains;
1075         uint32_t write_domain = args->write_domain;
1076         int ret;
1077
1078         if (!(dev->driver->driver_features & DRIVER_GEM))
1079                 return -ENODEV;
1080
1081         /* Only handle setting domains to types used by the CPU. */
1082         if (write_domain & I915_GEM_GPU_DOMAINS)
1083                 return -EINVAL;
1084
1085         if (read_domains & I915_GEM_GPU_DOMAINS)
1086                 return -EINVAL;
1087
1088         /* Having something in the write domain implies it's in the read
1089          * domain, and only that read domain.  Enforce that in the request.
1090          */
1091         if (write_domain != 0 && read_domains != write_domain)
1092                 return -EINVAL;
1093
1094         ret = i915_mutex_lock_interruptible(dev);
1095         if (ret)
1096                 return ret;
1097
1098         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1099         if (obj == NULL) {
1100                 ret = -ENOENT;
1101                 goto unlock;
1102         }
1103         obj_priv = to_intel_bo(obj);
1104
1105         intel_mark_busy(dev, obj);
1106
1107         if (read_domains & I915_GEM_DOMAIN_GTT) {
1108                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1109
1110                 /* Update the LRU on the fence for the CPU access that's
1111                  * about to occur.
1112                  */
1113                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1114                         struct drm_i915_fence_reg *reg =
1115                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1116                         list_move_tail(&reg->lru_list,
1117                                        &dev_priv->mm.fence_list);
1118                 }
1119
1120                 /* Silently promote "you're not bound, there was nothing to do"
1121                  * to success, since the client was just asking us to
1122                  * make sure everything was done.
1123                  */
1124                 if (ret == -EINVAL)
1125                         ret = 0;
1126         } else {
1127                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1128         }
1129
1130         /* Maintain LRU order of "inactive" objects */
1131         if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1132                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1133
1134         drm_gem_object_unreference(obj);
1135 unlock:
1136         mutex_unlock(&dev->struct_mutex);
1137         return ret;
1138 }
1139
1140 /**
1141  * Called when user space has done writes to this buffer
1142  */
1143 int
1144 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1145                       struct drm_file *file_priv)
1146 {
1147         struct drm_i915_gem_sw_finish *args = data;
1148         struct drm_gem_object *obj;
1149         int ret = 0;
1150
1151         if (!(dev->driver->driver_features & DRIVER_GEM))
1152                 return -ENODEV;
1153
1154         ret = i915_mutex_lock_interruptible(dev);
1155         if (ret)
1156                 return ret;
1157
1158         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1159         if (obj == NULL) {
1160                 ret = -ENOENT;
1161                 goto unlock;
1162         }
1163
1164         /* Pinned buffers may be scanout, so flush the cache */
1165         if (to_intel_bo(obj)->pin_count)
1166                 i915_gem_object_flush_cpu_write_domain(obj);
1167
1168         drm_gem_object_unreference(obj);
1169 unlock:
1170         mutex_unlock(&dev->struct_mutex);
1171         return ret;
1172 }
1173
1174 /**
1175  * Maps the contents of an object, returning the address it is mapped
1176  * into.
1177  *
1178  * While the mapping holds a reference on the contents of the object, it doesn't
1179  * imply a ref on the object itself.
1180  */
1181 int
1182 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1183                    struct drm_file *file_priv)
1184 {
1185         struct drm_i915_gem_mmap *args = data;
1186         struct drm_gem_object *obj;
1187         loff_t offset;
1188         unsigned long addr;
1189
1190         if (!(dev->driver->driver_features & DRIVER_GEM))
1191                 return -ENODEV;
1192
1193         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1194         if (obj == NULL)
1195                 return -ENOENT;
1196
1197         offset = args->offset;
1198
1199         down_write(&current->mm->mmap_sem);
1200         addr = do_mmap(obj->filp, 0, args->size,
1201                        PROT_READ | PROT_WRITE, MAP_SHARED,
1202                        args->offset);
1203         up_write(&current->mm->mmap_sem);
1204         drm_gem_object_unreference_unlocked(obj);
1205         if (IS_ERR((void *)addr))
1206                 return addr;
1207
1208         args->addr_ptr = (uint64_t) addr;
1209
1210         return 0;
1211 }
1212
1213 /**
1214  * i915_gem_fault - fault a page into the GTT
1215  * vma: VMA in question
1216  * vmf: fault info
1217  *
1218  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1219  * from userspace.  The fault handler takes care of binding the object to
1220  * the GTT (if needed), allocating and programming a fence register (again,
1221  * only if needed based on whether the old reg is still valid or the object
1222  * is tiled) and inserting a new PTE into the faulting process.
1223  *
1224  * Note that the faulting process may involve evicting existing objects
1225  * from the GTT and/or fence registers to make room.  So performance may
1226  * suffer if the GTT working set is large or there are few fence registers
1227  * left.
1228  */
1229 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1230 {
1231         struct drm_gem_object *obj = vma->vm_private_data;
1232         struct drm_device *dev = obj->dev;
1233         drm_i915_private_t *dev_priv = dev->dev_private;
1234         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1235         pgoff_t page_offset;
1236         unsigned long pfn;
1237         int ret = 0;
1238         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1239
1240         /* We don't use vmf->pgoff since that has the fake offset */
1241         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1242                 PAGE_SHIFT;
1243
1244         /* Now bind it into the GTT if needed */
1245         mutex_lock(&dev->struct_mutex);
1246         if (!obj_priv->gtt_space) {
1247                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1248                 if (ret)
1249                         goto unlock;
1250
1251                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1252                 if (ret)
1253                         goto unlock;
1254         }
1255
1256         /* Need a new fence register? */
1257         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1258                 ret = i915_gem_object_get_fence_reg(obj, true);
1259                 if (ret)
1260                         goto unlock;
1261         }
1262
1263         if (i915_gem_object_is_inactive(obj_priv))
1264                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1265
1266         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1267                 page_offset;
1268
1269         /* Finally, remap it using the new GTT offset */
1270         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1271 unlock:
1272         mutex_unlock(&dev->struct_mutex);
1273
1274         switch (ret) {
1275         case 0:
1276         case -ERESTARTSYS:
1277                 return VM_FAULT_NOPAGE;
1278         case -ENOMEM:
1279         case -EAGAIN:
1280                 return VM_FAULT_OOM;
1281         default:
1282                 return VM_FAULT_SIGBUS;
1283         }
1284 }
1285
1286 /**
1287  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1288  * @obj: obj in question
1289  *
1290  * GEM memory mapping works by handing back to userspace a fake mmap offset
1291  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1292  * up the object based on the offset and sets up the various memory mapping
1293  * structures.
1294  *
1295  * This routine allocates and attaches a fake offset for @obj.
1296  */
1297 static int
1298 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1299 {
1300         struct drm_device *dev = obj->dev;
1301         struct drm_gem_mm *mm = dev->mm_private;
1302         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1303         struct drm_map_list *list;
1304         struct drm_local_map *map;
1305         int ret = 0;
1306
1307         /* Set the object up for mmap'ing */
1308         list = &obj->map_list;
1309         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1310         if (!list->map)
1311                 return -ENOMEM;
1312
1313         map = list->map;
1314         map->type = _DRM_GEM;
1315         map->size = obj->size;
1316         map->handle = obj;
1317
1318         /* Get a DRM GEM mmap offset allocated... */
1319         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1320                                                     obj->size / PAGE_SIZE, 0, 0);
1321         if (!list->file_offset_node) {
1322                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1323                 ret = -ENOSPC;
1324                 goto out_free_list;
1325         }
1326
1327         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1328                                                   obj->size / PAGE_SIZE, 0);
1329         if (!list->file_offset_node) {
1330                 ret = -ENOMEM;
1331                 goto out_free_list;
1332         }
1333
1334         list->hash.key = list->file_offset_node->start;
1335         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1336         if (ret) {
1337                 DRM_ERROR("failed to add to map hash\n");
1338                 goto out_free_mm;
1339         }
1340
1341         /* By now we should be all set, any drm_mmap request on the offset
1342          * below will get to our mmap & fault handler */
1343         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1344
1345         return 0;
1346
1347 out_free_mm:
1348         drm_mm_put_block(list->file_offset_node);
1349 out_free_list:
1350         kfree(list->map);
1351
1352         return ret;
1353 }
1354
1355 /**
1356  * i915_gem_release_mmap - remove physical page mappings
1357  * @obj: obj in question
1358  *
1359  * Preserve the reservation of the mmapping with the DRM core code, but
1360  * relinquish ownership of the pages back to the system.
1361  *
1362  * It is vital that we remove the page mapping if we have mapped a tiled
1363  * object through the GTT and then lose the fence register due to
1364  * resource pressure. Similarly if the object has been moved out of the
1365  * aperture, than pages mapped into userspace must be revoked. Removing the
1366  * mapping will then trigger a page fault on the next user access, allowing
1367  * fixup by i915_gem_fault().
1368  */
1369 void
1370 i915_gem_release_mmap(struct drm_gem_object *obj)
1371 {
1372         struct drm_device *dev = obj->dev;
1373         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1374
1375         if (dev->dev_mapping)
1376                 unmap_mapping_range(dev->dev_mapping,
1377                                     obj_priv->mmap_offset, obj->size, 1);
1378 }
1379
1380 static void
1381 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1382 {
1383         struct drm_device *dev = obj->dev;
1384         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1385         struct drm_gem_mm *mm = dev->mm_private;
1386         struct drm_map_list *list;
1387
1388         list = &obj->map_list;
1389         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1390
1391         if (list->file_offset_node) {
1392                 drm_mm_put_block(list->file_offset_node);
1393                 list->file_offset_node = NULL;
1394         }
1395
1396         if (list->map) {
1397                 kfree(list->map);
1398                 list->map = NULL;
1399         }
1400
1401         obj_priv->mmap_offset = 0;
1402 }
1403
1404 /**
1405  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1406  * @obj: object to check
1407  *
1408  * Return the required GTT alignment for an object, taking into account
1409  * potential fence register mapping if needed.
1410  */
1411 static uint32_t
1412 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1413 {
1414         struct drm_device *dev = obj->dev;
1415         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1416         int start, i;
1417
1418         /*
1419          * Minimum alignment is 4k (GTT page size), but might be greater
1420          * if a fence register is needed for the object.
1421          */
1422         if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
1423                 return 4096;
1424
1425         /*
1426          * Previous chips need to be aligned to the size of the smallest
1427          * fence register that can contain the object.
1428          */
1429         if (INTEL_INFO(dev)->gen == 3)
1430                 start = 1024*1024;
1431         else
1432                 start = 512*1024;
1433
1434         for (i = start; i < obj->size; i <<= 1)
1435                 ;
1436
1437         return i;
1438 }
1439
1440 /**
1441  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1442  * @dev: DRM device
1443  * @data: GTT mapping ioctl data
1444  * @file_priv: GEM object info
1445  *
1446  * Simply returns the fake offset to userspace so it can mmap it.
1447  * The mmap call will end up in drm_gem_mmap(), which will set things
1448  * up so we can get faults in the handler above.
1449  *
1450  * The fault handler will take care of binding the object into the GTT
1451  * (since it may have been evicted to make room for something), allocating
1452  * a fence register, and mapping the appropriate aperture address into
1453  * userspace.
1454  */
1455 int
1456 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1457                         struct drm_file *file_priv)
1458 {
1459         struct drm_i915_gem_mmap_gtt *args = data;
1460         struct drm_gem_object *obj;
1461         struct drm_i915_gem_object *obj_priv;
1462         int ret;
1463
1464         if (!(dev->driver->driver_features & DRIVER_GEM))
1465                 return -ENODEV;
1466
1467         ret = i915_mutex_lock_interruptible(dev);
1468         if (ret)
1469                 return ret;
1470
1471         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1472         if (obj == NULL) {
1473                 ret = -ENOENT;
1474                 goto unlock;
1475         }
1476         obj_priv = to_intel_bo(obj);
1477
1478         if (obj_priv->madv != I915_MADV_WILLNEED) {
1479                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1480                 ret = -EINVAL;
1481                 goto out;
1482         }
1483
1484         if (!obj_priv->mmap_offset) {
1485                 ret = i915_gem_create_mmap_offset(obj);
1486                 if (ret)
1487                         goto out;
1488         }
1489
1490         args->offset = obj_priv->mmap_offset;
1491
1492         /*
1493          * Pull it into the GTT so that we have a page list (makes the
1494          * initial fault faster and any subsequent flushing possible).
1495          */
1496         if (!obj_priv->agp_mem) {
1497                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1498                 if (ret)
1499                         goto out;
1500         }
1501
1502 out:
1503         drm_gem_object_unreference(obj);
1504 unlock:
1505         mutex_unlock(&dev->struct_mutex);
1506         return ret;
1507 }
1508
1509 static void
1510 i915_gem_object_put_pages(struct drm_gem_object *obj)
1511 {
1512         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1513         int page_count = obj->size / PAGE_SIZE;
1514         int i;
1515
1516         BUG_ON(obj_priv->pages_refcount == 0);
1517         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1518
1519         if (--obj_priv->pages_refcount != 0)
1520                 return;
1521
1522         if (obj_priv->tiling_mode != I915_TILING_NONE)
1523                 i915_gem_object_save_bit_17_swizzle(obj);
1524
1525         if (obj_priv->madv == I915_MADV_DONTNEED)
1526                 obj_priv->dirty = 0;
1527
1528         for (i = 0; i < page_count; i++) {
1529                 if (obj_priv->dirty)
1530                         set_page_dirty(obj_priv->pages[i]);
1531
1532                 if (obj_priv->madv == I915_MADV_WILLNEED)
1533                         mark_page_accessed(obj_priv->pages[i]);
1534
1535                 page_cache_release(obj_priv->pages[i]);
1536         }
1537         obj_priv->dirty = 0;
1538
1539         drm_free_large(obj_priv->pages);
1540         obj_priv->pages = NULL;
1541 }
1542
1543 static uint32_t
1544 i915_gem_next_request_seqno(struct drm_device *dev,
1545                             struct intel_ring_buffer *ring)
1546 {
1547         drm_i915_private_t *dev_priv = dev->dev_private;
1548
1549         ring->outstanding_lazy_request = true;
1550         return dev_priv->next_seqno;
1551 }
1552
1553 static void
1554 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1555                                struct intel_ring_buffer *ring)
1556 {
1557         struct drm_device *dev = obj->dev;
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1560         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1561
1562         BUG_ON(ring == NULL);
1563         obj_priv->ring = ring;
1564
1565         /* Add a reference if we're newly entering the active list. */
1566         if (!obj_priv->active) {
1567                 drm_gem_object_reference(obj);
1568                 obj_priv->active = 1;
1569         }
1570
1571         /* Move from whatever list we were on to the tail of execution. */
1572         list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list);
1573         list_move_tail(&obj_priv->ring_list, &ring->active_list);
1574         obj_priv->last_rendering_seqno = seqno;
1575 }
1576
1577 static void
1578 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1579 {
1580         struct drm_device *dev = obj->dev;
1581         drm_i915_private_t *dev_priv = dev->dev_private;
1582         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1583
1584         BUG_ON(!obj_priv->active);
1585         list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list);
1586         list_del_init(&obj_priv->ring_list);
1587         obj_priv->last_rendering_seqno = 0;
1588 }
1589
1590 /* Immediately discard the backing storage */
1591 static void
1592 i915_gem_object_truncate(struct drm_gem_object *obj)
1593 {
1594         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1595         struct inode *inode;
1596
1597         /* Our goal here is to return as much of the memory as
1598          * is possible back to the system as we are called from OOM.
1599          * To do this we must instruct the shmfs to drop all of its
1600          * backing pages, *now*. Here we mirror the actions taken
1601          * when by shmem_delete_inode() to release the backing store.
1602          */
1603         inode = obj->filp->f_path.dentry->d_inode;
1604         truncate_inode_pages(inode->i_mapping, 0);
1605         if (inode->i_op->truncate_range)
1606                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1607
1608         obj_priv->madv = __I915_MADV_PURGED;
1609 }
1610
1611 static inline int
1612 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1613 {
1614         return obj_priv->madv == I915_MADV_DONTNEED;
1615 }
1616
1617 static void
1618 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1619 {
1620         struct drm_device *dev = obj->dev;
1621         drm_i915_private_t *dev_priv = dev->dev_private;
1622         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1623
1624         if (obj_priv->pin_count != 0)
1625                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list);
1626         else
1627                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1628         list_del_init(&obj_priv->ring_list);
1629
1630         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1631
1632         obj_priv->last_rendering_seqno = 0;
1633         obj_priv->ring = NULL;
1634         if (obj_priv->active) {
1635                 obj_priv->active = 0;
1636                 drm_gem_object_unreference(obj);
1637         }
1638         WARN_ON(i915_verify_lists(dev));
1639 }
1640
1641 static void
1642 i915_gem_process_flushing_list(struct drm_device *dev,
1643                                uint32_t flush_domains,
1644                                struct intel_ring_buffer *ring)
1645 {
1646         drm_i915_private_t *dev_priv = dev->dev_private;
1647         struct drm_i915_gem_object *obj_priv, *next;
1648
1649         list_for_each_entry_safe(obj_priv, next,
1650                                  &ring->gpu_write_list,
1651                                  gpu_write_list) {
1652                 struct drm_gem_object *obj = &obj_priv->base;
1653
1654                 if (obj->write_domain & flush_domains) {
1655                         uint32_t old_write_domain = obj->write_domain;
1656
1657                         obj->write_domain = 0;
1658                         list_del_init(&obj_priv->gpu_write_list);
1659                         i915_gem_object_move_to_active(obj, ring);
1660
1661                         /* update the fence lru list */
1662                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1663                                 struct drm_i915_fence_reg *reg =
1664                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1665                                 list_move_tail(&reg->lru_list,
1666                                                 &dev_priv->mm.fence_list);
1667                         }
1668
1669                         trace_i915_gem_object_change_domain(obj,
1670                                                             obj->read_domains,
1671                                                             old_write_domain);
1672                 }
1673         }
1674 }
1675
1676 uint32_t
1677 i915_add_request(struct drm_device *dev,
1678                  struct drm_file *file,
1679                  struct drm_i915_gem_request *request,
1680                  struct intel_ring_buffer *ring)
1681 {
1682         drm_i915_private_t *dev_priv = dev->dev_private;
1683         struct drm_i915_file_private *file_priv = NULL;
1684         uint32_t seqno;
1685         int was_empty;
1686
1687         if (file != NULL)
1688                 file_priv = file->driver_priv;
1689
1690         if (request == NULL) {
1691                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1692                 if (request == NULL)
1693                         return 0;
1694         }
1695
1696         seqno = ring->add_request(dev, ring, 0);
1697         ring->outstanding_lazy_request = false;
1698
1699         request->seqno = seqno;
1700         request->ring = ring;
1701         request->emitted_jiffies = jiffies;
1702         was_empty = list_empty(&ring->request_list);
1703         list_add_tail(&request->list, &ring->request_list);
1704
1705         if (file_priv) {
1706                 spin_lock(&file_priv->mm.lock);
1707                 request->file_priv = file_priv;
1708                 list_add_tail(&request->client_list,
1709                               &file_priv->mm.request_list);
1710                 spin_unlock(&file_priv->mm.lock);
1711         }
1712
1713         if (!dev_priv->mm.suspended) {
1714                 mod_timer(&dev_priv->hangcheck_timer,
1715                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1716                 if (was_empty)
1717                         queue_delayed_work(dev_priv->wq,
1718                                            &dev_priv->mm.retire_work, HZ);
1719         }
1720         return seqno;
1721 }
1722
1723 /**
1724  * Command execution barrier
1725  *
1726  * Ensures that all commands in the ring are finished
1727  * before signalling the CPU
1728  */
1729 static void
1730 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1731 {
1732         uint32_t flush_domains = 0;
1733
1734         /* The sampler always gets flushed on i965 (sigh) */
1735         if (INTEL_INFO(dev)->gen >= 4)
1736                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1737
1738         ring->flush(dev, ring,
1739                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1740 }
1741
1742 static inline void
1743 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1744 {
1745         struct drm_i915_file_private *file_priv = request->file_priv;
1746
1747         if (!file_priv)
1748                 return;
1749
1750         spin_lock(&file_priv->mm.lock);
1751         list_del(&request->client_list);
1752         request->file_priv = NULL;
1753         spin_unlock(&file_priv->mm.lock);
1754 }
1755
1756 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1757                                       struct intel_ring_buffer *ring)
1758 {
1759         while (!list_empty(&ring->request_list)) {
1760                 struct drm_i915_gem_request *request;
1761
1762                 request = list_first_entry(&ring->request_list,
1763                                            struct drm_i915_gem_request,
1764                                            list);
1765
1766                 list_del(&request->list);
1767                 i915_gem_request_remove_from_client(request);
1768                 kfree(request);
1769         }
1770
1771         while (!list_empty(&ring->active_list)) {
1772                 struct drm_i915_gem_object *obj_priv;
1773
1774                 obj_priv = list_first_entry(&ring->active_list,
1775                                             struct drm_i915_gem_object,
1776                                             ring_list);
1777
1778                 obj_priv->base.write_domain = 0;
1779                 list_del_init(&obj_priv->gpu_write_list);
1780                 i915_gem_object_move_to_inactive(&obj_priv->base);
1781         }
1782 }
1783
1784 void i915_gem_reset(struct drm_device *dev)
1785 {
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         struct drm_i915_gem_object *obj_priv;
1788         int i;
1789
1790         i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1791         i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1792         i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring);
1793
1794         /* Remove anything from the flushing lists. The GPU cache is likely
1795          * to be lost on reset along with the data, so simply move the
1796          * lost bo to the inactive list.
1797          */
1798         while (!list_empty(&dev_priv->mm.flushing_list)) {
1799                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1800                                             struct drm_i915_gem_object,
1801                                             mm_list);
1802
1803                 obj_priv->base.write_domain = 0;
1804                 list_del_init(&obj_priv->gpu_write_list);
1805                 i915_gem_object_move_to_inactive(&obj_priv->base);
1806         }
1807
1808         /* Move everything out of the GPU domains to ensure we do any
1809          * necessary invalidation upon reuse.
1810          */
1811         list_for_each_entry(obj_priv,
1812                             &dev_priv->mm.inactive_list,
1813                             mm_list)
1814         {
1815                 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1816         }
1817
1818         /* The fence registers are invalidated so clear them out */
1819         for (i = 0; i < 16; i++) {
1820                 struct drm_i915_fence_reg *reg;
1821
1822                 reg = &dev_priv->fence_regs[i];
1823                 if (!reg->obj)
1824                         continue;
1825
1826                 i915_gem_clear_fence_reg(reg->obj);
1827         }
1828 }
1829
1830 /**
1831  * This function clears the request list as sequence numbers are passed.
1832  */
1833 static void
1834 i915_gem_retire_requests_ring(struct drm_device *dev,
1835                               struct intel_ring_buffer *ring)
1836 {
1837         drm_i915_private_t *dev_priv = dev->dev_private;
1838         uint32_t seqno;
1839
1840         if (!ring->status_page.page_addr ||
1841             list_empty(&ring->request_list))
1842                 return;
1843
1844         WARN_ON(i915_verify_lists(dev));
1845
1846         seqno = ring->get_seqno(dev, ring);
1847         while (!list_empty(&ring->request_list)) {
1848                 struct drm_i915_gem_request *request;
1849
1850                 request = list_first_entry(&ring->request_list,
1851                                            struct drm_i915_gem_request,
1852                                            list);
1853
1854                 if (!i915_seqno_passed(seqno, request->seqno))
1855                         break;
1856
1857                 trace_i915_gem_request_retire(dev, request->seqno);
1858
1859                 list_del(&request->list);
1860                 i915_gem_request_remove_from_client(request);
1861                 kfree(request);
1862         }
1863
1864         /* Move any buffers on the active list that are no longer referenced
1865          * by the ringbuffer to the flushing/inactive lists as appropriate.
1866          */
1867         while (!list_empty(&ring->active_list)) {
1868                 struct drm_gem_object *obj;
1869                 struct drm_i915_gem_object *obj_priv;
1870
1871                 obj_priv = list_first_entry(&ring->active_list,
1872                                             struct drm_i915_gem_object,
1873                                             ring_list);
1874
1875                 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1876                         break;
1877
1878                 obj = &obj_priv->base;
1879                 if (obj->write_domain != 0)
1880                         i915_gem_object_move_to_flushing(obj);
1881                 else
1882                         i915_gem_object_move_to_inactive(obj);
1883         }
1884
1885         if (unlikely (dev_priv->trace_irq_seqno &&
1886                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1887                 ring->user_irq_put(dev, ring);
1888                 dev_priv->trace_irq_seqno = 0;
1889         }
1890
1891         WARN_ON(i915_verify_lists(dev));
1892 }
1893
1894 void
1895 i915_gem_retire_requests(struct drm_device *dev)
1896 {
1897         drm_i915_private_t *dev_priv = dev->dev_private;
1898
1899         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1900             struct drm_i915_gem_object *obj_priv, *tmp;
1901
1902             /* We must be careful that during unbind() we do not
1903              * accidentally infinitely recurse into retire requests.
1904              * Currently:
1905              *   retire -> free -> unbind -> wait -> retire_ring
1906              */
1907             list_for_each_entry_safe(obj_priv, tmp,
1908                                      &dev_priv->mm.deferred_free_list,
1909                                      mm_list)
1910                     i915_gem_free_object_tail(&obj_priv->base);
1911         }
1912
1913         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1914         i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1915         i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring);
1916 }
1917
1918 static void
1919 i915_gem_retire_work_handler(struct work_struct *work)
1920 {
1921         drm_i915_private_t *dev_priv;
1922         struct drm_device *dev;
1923
1924         dev_priv = container_of(work, drm_i915_private_t,
1925                                 mm.retire_work.work);
1926         dev = dev_priv->dev;
1927
1928         /* Come back later if the device is busy... */
1929         if (!mutex_trylock(&dev->struct_mutex)) {
1930                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1931                 return;
1932         }
1933
1934         i915_gem_retire_requests(dev);
1935
1936         if (!dev_priv->mm.suspended &&
1937                 (!list_empty(&dev_priv->render_ring.request_list) ||
1938                  !list_empty(&dev_priv->bsd_ring.request_list) ||
1939                  !list_empty(&dev_priv->blt_ring.request_list)))
1940                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1941         mutex_unlock(&dev->struct_mutex);
1942 }
1943
1944 int
1945 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1946                      bool interruptible, struct intel_ring_buffer *ring)
1947 {
1948         drm_i915_private_t *dev_priv = dev->dev_private;
1949         u32 ier;
1950         int ret = 0;
1951
1952         BUG_ON(seqno == 0);
1953
1954         if (atomic_read(&dev_priv->mm.wedged))
1955                 return -EAGAIN;
1956
1957         if (ring->outstanding_lazy_request) {
1958                 seqno = i915_add_request(dev, NULL, NULL, ring);
1959                 if (seqno == 0)
1960                         return -ENOMEM;
1961         }
1962         BUG_ON(seqno == dev_priv->next_seqno);
1963
1964         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
1965                 if (HAS_PCH_SPLIT(dev))
1966                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1967                 else
1968                         ier = I915_READ(IER);
1969                 if (!ier) {
1970                         DRM_ERROR("something (likely vbetool) disabled "
1971                                   "interrupts, re-enabling\n");
1972                         i915_driver_irq_preinstall(dev);
1973                         i915_driver_irq_postinstall(dev);
1974                 }
1975
1976                 trace_i915_gem_request_wait_begin(dev, seqno);
1977
1978                 ring->waiting_gem_seqno = seqno;
1979                 ring->user_irq_get(dev, ring);
1980                 if (interruptible)
1981                         ret = wait_event_interruptible(ring->irq_queue,
1982                                 i915_seqno_passed(
1983                                         ring->get_seqno(dev, ring), seqno)
1984                                 || atomic_read(&dev_priv->mm.wedged));
1985                 else
1986                         wait_event(ring->irq_queue,
1987                                 i915_seqno_passed(
1988                                         ring->get_seqno(dev, ring), seqno)
1989                                 || atomic_read(&dev_priv->mm.wedged));
1990
1991                 ring->user_irq_put(dev, ring);
1992                 ring->waiting_gem_seqno = 0;
1993
1994                 trace_i915_gem_request_wait_end(dev, seqno);
1995         }
1996         if (atomic_read(&dev_priv->mm.wedged))
1997                 ret = -EAGAIN;
1998
1999         if (ret && ret != -ERESTARTSYS)
2000                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2001                           __func__, ret, seqno, ring->get_seqno(dev, ring),
2002                           dev_priv->next_seqno);
2003
2004         /* Directly dispatch request retiring.  While we have the work queue
2005          * to handle this, the waiter on a request often wants an associated
2006          * buffer to have made it to the inactive list, and we would need
2007          * a separate wait queue to handle that.
2008          */
2009         if (ret == 0)
2010                 i915_gem_retire_requests_ring(dev, ring);
2011
2012         return ret;
2013 }
2014
2015 /**
2016  * Waits for a sequence number to be signaled, and cleans up the
2017  * request and object lists appropriately for that event.
2018  */
2019 static int
2020 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2021                   struct intel_ring_buffer *ring)
2022 {
2023         return i915_do_wait_request(dev, seqno, 1, ring);
2024 }
2025
2026 static void
2027 i915_gem_flush_ring(struct drm_device *dev,
2028                     struct drm_file *file_priv,
2029                     struct intel_ring_buffer *ring,
2030                     uint32_t invalidate_domains,
2031                     uint32_t flush_domains)
2032 {
2033         ring->flush(dev, ring, invalidate_domains, flush_domains);
2034         i915_gem_process_flushing_list(dev, flush_domains, ring);
2035 }
2036
2037 static void
2038 i915_gem_flush(struct drm_device *dev,
2039                struct drm_file *file_priv,
2040                uint32_t invalidate_domains,
2041                uint32_t flush_domains,
2042                uint32_t flush_rings)
2043 {
2044         drm_i915_private_t *dev_priv = dev->dev_private;
2045
2046         if (flush_domains & I915_GEM_DOMAIN_CPU)
2047                 drm_agp_chipset_flush(dev);
2048
2049         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2050                 if (flush_rings & RING_RENDER)
2051                         i915_gem_flush_ring(dev, file_priv,
2052                                             &dev_priv->render_ring,
2053                                             invalidate_domains, flush_domains);
2054                 if (flush_rings & RING_BSD)
2055                         i915_gem_flush_ring(dev, file_priv,
2056                                             &dev_priv->bsd_ring,
2057                                             invalidate_domains, flush_domains);
2058                 if (flush_rings & RING_BLT)
2059                         i915_gem_flush_ring(dev, file_priv,
2060                                             &dev_priv->blt_ring,
2061                                             invalidate_domains, flush_domains);
2062         }
2063 }
2064
2065 /**
2066  * Ensures that all rendering to the object has completed and the object is
2067  * safe to unbind from the GTT or access from the CPU.
2068  */
2069 static int
2070 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2071                                bool interruptible)
2072 {
2073         struct drm_device *dev = obj->dev;
2074         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2075         int ret;
2076
2077         /* This function only exists to support waiting for existing rendering,
2078          * not for emitting required flushes.
2079          */
2080         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2081
2082         /* If there is rendering queued on the buffer being evicted, wait for
2083          * it.
2084          */
2085         if (obj_priv->active) {
2086                 ret = i915_do_wait_request(dev,
2087                                            obj_priv->last_rendering_seqno,
2088                                            interruptible,
2089                                            obj_priv->ring);
2090                 if (ret)
2091                         return ret;
2092         }
2093
2094         return 0;
2095 }
2096
2097 /**
2098  * Unbinds an object from the GTT aperture.
2099  */
2100 int
2101 i915_gem_object_unbind(struct drm_gem_object *obj)
2102 {
2103         struct drm_device *dev = obj->dev;
2104         struct drm_i915_private *dev_priv = dev->dev_private;
2105         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2106         int ret = 0;
2107
2108         if (obj_priv->gtt_space == NULL)
2109                 return 0;
2110
2111         if (obj_priv->pin_count != 0) {
2112                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2113                 return -EINVAL;
2114         }
2115
2116         /* blow away mappings if mapped through GTT */
2117         i915_gem_release_mmap(obj);
2118
2119         /* Move the object to the CPU domain to ensure that
2120          * any possible CPU writes while it's not in the GTT
2121          * are flushed when we go to remap it. This will
2122          * also ensure that all pending GPU writes are finished
2123          * before we unbind.
2124          */
2125         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2126         if (ret == -ERESTARTSYS)
2127                 return ret;
2128         /* Continue on if we fail due to EIO, the GPU is hung so we
2129          * should be safe and we need to cleanup or else we might
2130          * cause memory corruption through use-after-free.
2131          */
2132         if (ret) {
2133                 i915_gem_clflush_object(obj);
2134                 obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU;
2135         }
2136
2137         /* release the fence reg _after_ flushing */
2138         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2139                 i915_gem_clear_fence_reg(obj);
2140
2141         drm_unbind_agp(obj_priv->agp_mem);
2142         drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2143
2144         i915_gem_object_put_pages(obj);
2145         BUG_ON(obj_priv->pages_refcount);
2146
2147         i915_gem_info_remove_gtt(dev_priv, obj->size);
2148         list_del_init(&obj_priv->mm_list);
2149
2150         drm_mm_put_block(obj_priv->gtt_space);
2151         obj_priv->gtt_space = NULL;
2152         obj_priv->gtt_offset = 0;
2153
2154         if (i915_gem_object_is_purgeable(obj_priv))
2155                 i915_gem_object_truncate(obj);
2156
2157         trace_i915_gem_object_unbind(obj);
2158
2159         return ret;
2160 }
2161
2162 static int i915_ring_idle(struct drm_device *dev,
2163                           struct intel_ring_buffer *ring)
2164 {
2165         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2166                 return 0;
2167
2168         i915_gem_flush_ring(dev, NULL, ring,
2169                             I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2170         return i915_wait_request(dev,
2171                                  i915_gem_next_request_seqno(dev, ring),
2172                                  ring);
2173 }
2174
2175 int
2176 i915_gpu_idle(struct drm_device *dev)
2177 {
2178         drm_i915_private_t *dev_priv = dev->dev_private;
2179         bool lists_empty;
2180         int ret;
2181
2182         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2183                        list_empty(&dev_priv->mm.active_list));
2184         if (lists_empty)
2185                 return 0;
2186
2187         /* Flush everything onto the inactive list. */
2188         ret = i915_ring_idle(dev, &dev_priv->render_ring);
2189         if (ret)
2190                 return ret;
2191
2192         ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2193         if (ret)
2194                 return ret;
2195
2196         ret = i915_ring_idle(dev, &dev_priv->blt_ring);
2197         if (ret)
2198                 return ret;
2199
2200         return 0;
2201 }
2202
2203 static int
2204 i915_gem_object_get_pages(struct drm_gem_object *obj,
2205                           gfp_t gfpmask)
2206 {
2207         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2208         int page_count, i;
2209         struct address_space *mapping;
2210         struct inode *inode;
2211         struct page *page;
2212
2213         BUG_ON(obj_priv->pages_refcount
2214                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2215
2216         if (obj_priv->pages_refcount++ != 0)
2217                 return 0;
2218
2219         /* Get the list of pages out of our struct file.  They'll be pinned
2220          * at this point until we release them.
2221          */
2222         page_count = obj->size / PAGE_SIZE;
2223         BUG_ON(obj_priv->pages != NULL);
2224         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2225         if (obj_priv->pages == NULL) {
2226                 obj_priv->pages_refcount--;
2227                 return -ENOMEM;
2228         }
2229
2230         inode = obj->filp->f_path.dentry->d_inode;
2231         mapping = inode->i_mapping;
2232         for (i = 0; i < page_count; i++) {
2233                 page = read_cache_page_gfp(mapping, i,
2234                                            GFP_HIGHUSER |
2235                                            __GFP_COLD |
2236                                            __GFP_RECLAIMABLE |
2237                                            gfpmask);
2238                 if (IS_ERR(page))
2239                         goto err_pages;
2240
2241                 obj_priv->pages[i] = page;
2242         }
2243
2244         if (obj_priv->tiling_mode != I915_TILING_NONE)
2245                 i915_gem_object_do_bit_17_swizzle(obj);
2246
2247         return 0;
2248
2249 err_pages:
2250         while (i--)
2251                 page_cache_release(obj_priv->pages[i]);
2252
2253         drm_free_large(obj_priv->pages);
2254         obj_priv->pages = NULL;
2255         obj_priv->pages_refcount--;
2256         return PTR_ERR(page);
2257 }
2258
2259 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2260 {
2261         struct drm_gem_object *obj = reg->obj;
2262         struct drm_device *dev = obj->dev;
2263         drm_i915_private_t *dev_priv = dev->dev_private;
2264         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2265         int regnum = obj_priv->fence_reg;
2266         uint64_t val;
2267
2268         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2269                     0xfffff000) << 32;
2270         val |= obj_priv->gtt_offset & 0xfffff000;
2271         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2272                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2273
2274         if (obj_priv->tiling_mode == I915_TILING_Y)
2275                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2276         val |= I965_FENCE_REG_VALID;
2277
2278         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2279 }
2280
2281 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2282 {
2283         struct drm_gem_object *obj = reg->obj;
2284         struct drm_device *dev = obj->dev;
2285         drm_i915_private_t *dev_priv = dev->dev_private;
2286         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2287         int regnum = obj_priv->fence_reg;
2288         uint64_t val;
2289
2290         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2291                     0xfffff000) << 32;
2292         val |= obj_priv->gtt_offset & 0xfffff000;
2293         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2294         if (obj_priv->tiling_mode == I915_TILING_Y)
2295                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2296         val |= I965_FENCE_REG_VALID;
2297
2298         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2299 }
2300
2301 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2302 {
2303         struct drm_gem_object *obj = reg->obj;
2304         struct drm_device *dev = obj->dev;
2305         drm_i915_private_t *dev_priv = dev->dev_private;
2306         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2307         int regnum = obj_priv->fence_reg;
2308         int tile_width;
2309         uint32_t fence_reg, val;
2310         uint32_t pitch_val;
2311
2312         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2313             (obj_priv->gtt_offset & (obj->size - 1))) {
2314                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2315                      __func__, obj_priv->gtt_offset, obj->size);
2316                 return;
2317         }
2318
2319         if (obj_priv->tiling_mode == I915_TILING_Y &&
2320             HAS_128_BYTE_Y_TILING(dev))
2321                 tile_width = 128;
2322         else
2323                 tile_width = 512;
2324
2325         /* Note: pitch better be a power of two tile widths */
2326         pitch_val = obj_priv->stride / tile_width;
2327         pitch_val = ffs(pitch_val) - 1;
2328
2329         if (obj_priv->tiling_mode == I915_TILING_Y &&
2330             HAS_128_BYTE_Y_TILING(dev))
2331                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2332         else
2333                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2334
2335         val = obj_priv->gtt_offset;
2336         if (obj_priv->tiling_mode == I915_TILING_Y)
2337                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2338         val |= I915_FENCE_SIZE_BITS(obj->size);
2339         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2340         val |= I830_FENCE_REG_VALID;
2341
2342         if (regnum < 8)
2343                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2344         else
2345                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2346         I915_WRITE(fence_reg, val);
2347 }
2348
2349 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2350 {
2351         struct drm_gem_object *obj = reg->obj;
2352         struct drm_device *dev = obj->dev;
2353         drm_i915_private_t *dev_priv = dev->dev_private;
2354         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2355         int regnum = obj_priv->fence_reg;
2356         uint32_t val;
2357         uint32_t pitch_val;
2358         uint32_t fence_size_bits;
2359
2360         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2361             (obj_priv->gtt_offset & (obj->size - 1))) {
2362                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2363                      __func__, obj_priv->gtt_offset);
2364                 return;
2365         }
2366
2367         pitch_val = obj_priv->stride / 128;
2368         pitch_val = ffs(pitch_val) - 1;
2369         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2370
2371         val = obj_priv->gtt_offset;
2372         if (obj_priv->tiling_mode == I915_TILING_Y)
2373                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2374         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2375         WARN_ON(fence_size_bits & ~0x00000f00);
2376         val |= fence_size_bits;
2377         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2378         val |= I830_FENCE_REG_VALID;
2379
2380         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2381 }
2382
2383 static int i915_find_fence_reg(struct drm_device *dev,
2384                                bool interruptible)
2385 {
2386         struct drm_i915_fence_reg *reg = NULL;
2387         struct drm_i915_gem_object *obj_priv = NULL;
2388         struct drm_i915_private *dev_priv = dev->dev_private;
2389         struct drm_gem_object *obj = NULL;
2390         int i, avail, ret;
2391
2392         /* First try to find a free reg */
2393         avail = 0;
2394         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2395                 reg = &dev_priv->fence_regs[i];
2396                 if (!reg->obj)
2397                         return i;
2398
2399                 obj_priv = to_intel_bo(reg->obj);
2400                 if (!obj_priv->pin_count)
2401                     avail++;
2402         }
2403
2404         if (avail == 0)
2405                 return -ENOSPC;
2406
2407         /* None available, try to steal one or wait for a user to finish */
2408         i = I915_FENCE_REG_NONE;
2409         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2410                             lru_list) {
2411                 obj = reg->obj;
2412                 obj_priv = to_intel_bo(obj);
2413
2414                 if (obj_priv->pin_count)
2415                         continue;
2416
2417                 /* found one! */
2418                 i = obj_priv->fence_reg;
2419                 break;
2420         }
2421
2422         BUG_ON(i == I915_FENCE_REG_NONE);
2423
2424         /* We only have a reference on obj from the active list. put_fence_reg
2425          * might drop that one, causing a use-after-free in it. So hold a
2426          * private reference to obj like the other callers of put_fence_reg
2427          * (set_tiling ioctl) do. */
2428         drm_gem_object_reference(obj);
2429         ret = i915_gem_object_put_fence_reg(obj, interruptible);
2430         drm_gem_object_unreference(obj);
2431         if (ret != 0)
2432                 return ret;
2433
2434         return i;
2435 }
2436
2437 /**
2438  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2439  * @obj: object to map through a fence reg
2440  *
2441  * When mapping objects through the GTT, userspace wants to be able to write
2442  * to them without having to worry about swizzling if the object is tiled.
2443  *
2444  * This function walks the fence regs looking for a free one for @obj,
2445  * stealing one if it can't find any.
2446  *
2447  * It then sets up the reg based on the object's properties: address, pitch
2448  * and tiling format.
2449  */
2450 int
2451 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2452                               bool interruptible)
2453 {
2454         struct drm_device *dev = obj->dev;
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2457         struct drm_i915_fence_reg *reg = NULL;
2458         int ret;
2459
2460         /* Just update our place in the LRU if our fence is getting used. */
2461         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2462                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2463                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2464                 return 0;
2465         }
2466
2467         switch (obj_priv->tiling_mode) {
2468         case I915_TILING_NONE:
2469                 WARN(1, "allocating a fence for non-tiled object?\n");
2470                 break;
2471         case I915_TILING_X:
2472                 if (!obj_priv->stride)
2473                         return -EINVAL;
2474                 WARN((obj_priv->stride & (512 - 1)),
2475                      "object 0x%08x is X tiled but has non-512B pitch\n",
2476                      obj_priv->gtt_offset);
2477                 break;
2478         case I915_TILING_Y:
2479                 if (!obj_priv->stride)
2480                         return -EINVAL;
2481                 WARN((obj_priv->stride & (128 - 1)),
2482                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2483                      obj_priv->gtt_offset);
2484                 break;
2485         }
2486
2487         ret = i915_find_fence_reg(dev, interruptible);
2488         if (ret < 0)
2489                 return ret;
2490
2491         obj_priv->fence_reg = ret;
2492         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2493         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2494
2495         reg->obj = obj;
2496
2497         switch (INTEL_INFO(dev)->gen) {
2498         case 6:
2499                 sandybridge_write_fence_reg(reg);
2500                 break;
2501         case 5:
2502         case 4:
2503                 i965_write_fence_reg(reg);
2504                 break;
2505         case 3:
2506                 i915_write_fence_reg(reg);
2507                 break;
2508         case 2:
2509                 i830_write_fence_reg(reg);
2510                 break;
2511         }
2512
2513         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2514                         obj_priv->tiling_mode);
2515
2516         return 0;
2517 }
2518
2519 /**
2520  * i915_gem_clear_fence_reg - clear out fence register info
2521  * @obj: object to clear
2522  *
2523  * Zeroes out the fence register itself and clears out the associated
2524  * data structures in dev_priv and obj_priv.
2525  */
2526 static void
2527 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2528 {
2529         struct drm_device *dev = obj->dev;
2530         drm_i915_private_t *dev_priv = dev->dev_private;
2531         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2532         struct drm_i915_fence_reg *reg =
2533                 &dev_priv->fence_regs[obj_priv->fence_reg];
2534         uint32_t fence_reg;
2535
2536         switch (INTEL_INFO(dev)->gen) {
2537         case 6:
2538                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2539                              (obj_priv->fence_reg * 8), 0);
2540                 break;
2541         case 5:
2542         case 4:
2543                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2544                 break;
2545         case 3:
2546                 if (obj_priv->fence_reg >= 8)
2547                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2548                 else
2549         case 2:
2550                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2551
2552                 I915_WRITE(fence_reg, 0);
2553                 break;
2554         }
2555
2556         reg->obj = NULL;
2557         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2558         list_del_init(&reg->lru_list);
2559 }
2560
2561 /**
2562  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2563  * to the buffer to finish, and then resets the fence register.
2564  * @obj: tiled object holding a fence register.
2565  * @bool: whether the wait upon the fence is interruptible
2566  *
2567  * Zeroes out the fence register itself and clears out the associated
2568  * data structures in dev_priv and obj_priv.
2569  */
2570 int
2571 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2572                               bool interruptible)
2573 {
2574         struct drm_device *dev = obj->dev;
2575         struct drm_i915_private *dev_priv = dev->dev_private;
2576         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2577         struct drm_i915_fence_reg *reg;
2578
2579         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2580                 return 0;
2581
2582         /* If we've changed tiling, GTT-mappings of the object
2583          * need to re-fault to ensure that the correct fence register
2584          * setup is in place.
2585          */
2586         i915_gem_release_mmap(obj);
2587
2588         /* On the i915, GPU access to tiled buffers is via a fence,
2589          * therefore we must wait for any outstanding access to complete
2590          * before clearing the fence.
2591          */
2592         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2593         if (reg->gpu) {
2594                 int ret;
2595
2596                 ret = i915_gem_object_flush_gpu_write_domain(obj);
2597                 if (ret)
2598                         return ret;
2599
2600                 ret = i915_gem_object_wait_rendering(obj, interruptible);
2601                 if (ret)
2602                         return ret;
2603
2604                 reg->gpu = false;
2605         }
2606
2607         i915_gem_object_flush_gtt_write_domain(obj);
2608         i915_gem_clear_fence_reg(obj);
2609
2610         return 0;
2611 }
2612
2613 /**
2614  * Finds free space in the GTT aperture and binds the object there.
2615  */
2616 static int
2617 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2618 {
2619         struct drm_device *dev = obj->dev;
2620         drm_i915_private_t *dev_priv = dev->dev_private;
2621         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2622         struct drm_mm_node *free_space;
2623         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2624         int ret;
2625
2626         if (obj_priv->madv != I915_MADV_WILLNEED) {
2627                 DRM_ERROR("Attempting to bind a purgeable object\n");
2628                 return -EINVAL;
2629         }
2630
2631         if (alignment == 0)
2632                 alignment = i915_gem_get_gtt_alignment(obj);
2633         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2634                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2635                 return -EINVAL;
2636         }
2637
2638         /* If the object is bigger than the entire aperture, reject it early
2639          * before evicting everything in a vain attempt to find space.
2640          */
2641         if (obj->size > dev_priv->mm.gtt_total) {
2642                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2643                 return -E2BIG;
2644         }
2645
2646  search_free:
2647         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2648                                         obj->size, alignment, 0);
2649         if (free_space != NULL)
2650                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2651                                                        alignment);
2652         if (obj_priv->gtt_space == NULL) {
2653                 /* If the gtt is empty and we're still having trouble
2654                  * fitting our object in, we're out of memory.
2655                  */
2656                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2657                 if (ret)
2658                         return ret;
2659
2660                 goto search_free;
2661         }
2662
2663         ret = i915_gem_object_get_pages(obj, gfpmask);
2664         if (ret) {
2665                 drm_mm_put_block(obj_priv->gtt_space);
2666                 obj_priv->gtt_space = NULL;
2667
2668                 if (ret == -ENOMEM) {
2669                         /* first try to clear up some space from the GTT */
2670                         ret = i915_gem_evict_something(dev, obj->size,
2671                                                        alignment);
2672                         if (ret) {
2673                                 /* now try to shrink everyone else */
2674                                 if (gfpmask) {
2675                                         gfpmask = 0;
2676                                         goto search_free;
2677                                 }
2678
2679                                 return ret;
2680                         }
2681
2682                         goto search_free;
2683                 }
2684
2685                 return ret;
2686         }
2687
2688         /* Create an AGP memory structure pointing at our pages, and bind it
2689          * into the GTT.
2690          */
2691         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2692                                                obj_priv->pages,
2693                                                obj->size >> PAGE_SHIFT,
2694                                                obj_priv->gtt_space->start,
2695                                                obj_priv->agp_type);
2696         if (obj_priv->agp_mem == NULL) {
2697                 i915_gem_object_put_pages(obj);
2698                 drm_mm_put_block(obj_priv->gtt_space);
2699                 obj_priv->gtt_space = NULL;
2700
2701                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2702                 if (ret)
2703                         return ret;
2704
2705                 goto search_free;
2706         }
2707
2708         /* keep track of bounds object by adding it to the inactive list */
2709         list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
2710         i915_gem_info_add_gtt(dev_priv, obj->size);
2711
2712         /* Assert that the object is not currently in any GPU domain. As it
2713          * wasn't in the GTT, there shouldn't be any way it could have been in
2714          * a GPU cache
2715          */
2716         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2717         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2718
2719         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2720         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2721
2722         return 0;
2723 }
2724
2725 void
2726 i915_gem_clflush_object(struct drm_gem_object *obj)
2727 {
2728         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2729
2730         /* If we don't have a page list set up, then we're not pinned
2731          * to GPU, and we can ignore the cache flush because it'll happen
2732          * again at bind time.
2733          */
2734         if (obj_priv->pages == NULL)
2735                 return;
2736
2737         trace_i915_gem_object_clflush(obj);
2738
2739         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2740 }
2741
2742 /** Flushes any GPU write domain for the object if it's dirty. */
2743 static int
2744 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2745 {
2746         struct drm_device *dev = obj->dev;
2747         uint32_t old_write_domain;
2748
2749         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2750                 return 0;
2751
2752         /* Queue the GPU write cache flushing we need. */
2753         old_write_domain = obj->write_domain;
2754         i915_gem_flush_ring(dev, NULL,
2755                             to_intel_bo(obj)->ring,
2756                             0, obj->write_domain);
2757         BUG_ON(obj->write_domain);
2758
2759         trace_i915_gem_object_change_domain(obj,
2760                                             obj->read_domains,
2761                                             old_write_domain);
2762
2763         return 0;
2764 }
2765
2766 /** Flushes the GTT write domain for the object if it's dirty. */
2767 static void
2768 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2769 {
2770         uint32_t old_write_domain;
2771
2772         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2773                 return;
2774
2775         /* No actual flushing is required for the GTT write domain.   Writes
2776          * to it immediately go to main memory as far as we know, so there's
2777          * no chipset flush.  It also doesn't land in render cache.
2778          */
2779         old_write_domain = obj->write_domain;
2780         obj->write_domain = 0;
2781
2782         trace_i915_gem_object_change_domain(obj,
2783                                             obj->read_domains,
2784                                             old_write_domain);
2785 }
2786
2787 /** Flushes the CPU write domain for the object if it's dirty. */
2788 static void
2789 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2790 {
2791         struct drm_device *dev = obj->dev;
2792         uint32_t old_write_domain;
2793
2794         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2795                 return;
2796
2797         i915_gem_clflush_object(obj);
2798         drm_agp_chipset_flush(dev);
2799         old_write_domain = obj->write_domain;
2800         obj->write_domain = 0;
2801
2802         trace_i915_gem_object_change_domain(obj,
2803                                             obj->read_domains,
2804                                             old_write_domain);
2805 }
2806
2807 /**
2808  * Moves a single object to the GTT read, and possibly write domain.
2809  *
2810  * This function returns when the move is complete, including waiting on
2811  * flushes to occur.
2812  */
2813 int
2814 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2815 {
2816         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2817         uint32_t old_write_domain, old_read_domains;
2818         int ret;
2819
2820         /* Not valid to be called on unbound objects. */
2821         if (obj_priv->gtt_space == NULL)
2822                 return -EINVAL;
2823
2824         ret = i915_gem_object_flush_gpu_write_domain(obj);
2825         if (ret != 0)
2826                 return ret;
2827         ret = i915_gem_object_wait_rendering(obj, true);
2828         if (ret)
2829                 return ret;
2830
2831         i915_gem_object_flush_cpu_write_domain(obj);
2832
2833         old_write_domain = obj->write_domain;
2834         old_read_domains = obj->read_domains;
2835
2836         /* It should now be out of any other write domains, and we can update
2837          * the domain values for our changes.
2838          */
2839         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2840         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2841         if (write) {
2842                 obj->read_domains = I915_GEM_DOMAIN_GTT;
2843                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2844                 obj_priv->dirty = 1;
2845         }
2846
2847         trace_i915_gem_object_change_domain(obj,
2848                                             old_read_domains,
2849                                             old_write_domain);
2850
2851         return 0;
2852 }
2853
2854 /*
2855  * Prepare buffer for display plane. Use uninterruptible for possible flush
2856  * wait, as in modesetting process we're not supposed to be interrupted.
2857  */
2858 int
2859 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2860                                      bool pipelined)
2861 {
2862         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2863         uint32_t old_read_domains;
2864         int ret;
2865
2866         /* Not valid to be called on unbound objects. */
2867         if (obj_priv->gtt_space == NULL)
2868                 return -EINVAL;
2869
2870         ret = i915_gem_object_flush_gpu_write_domain(obj);
2871         if (ret)
2872                 return ret;
2873
2874         /* Currently, we are always called from an non-interruptible context. */
2875         if (!pipelined) {
2876                 ret = i915_gem_object_wait_rendering(obj, false);
2877                 if (ret)
2878                         return ret;
2879         }
2880
2881         i915_gem_object_flush_cpu_write_domain(obj);
2882
2883         old_read_domains = obj->read_domains;
2884         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2885
2886         trace_i915_gem_object_change_domain(obj,
2887                                             old_read_domains,
2888                                             obj->write_domain);
2889
2890         return 0;
2891 }
2892
2893 int
2894 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
2895                           bool interruptible)
2896 {
2897         if (!obj->active)
2898                 return 0;
2899
2900         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2901                 i915_gem_flush_ring(obj->base.dev, NULL, obj->ring,
2902                                     0, obj->base.write_domain);
2903
2904         return i915_gem_object_wait_rendering(&obj->base, interruptible);
2905 }
2906
2907 /**
2908  * Moves a single object to the CPU read, and possibly write domain.
2909  *
2910  * This function returns when the move is complete, including waiting on
2911  * flushes to occur.
2912  */
2913 static int
2914 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2915 {
2916         uint32_t old_write_domain, old_read_domains;
2917         int ret;
2918
2919         ret = i915_gem_object_flush_gpu_write_domain(obj);
2920         if (ret != 0)
2921                 return ret;
2922         ret = i915_gem_object_wait_rendering(obj, true);
2923         if (ret)
2924                 return ret;
2925
2926         i915_gem_object_flush_gtt_write_domain(obj);
2927
2928         /* If we have a partially-valid cache of the object in the CPU,
2929          * finish invalidating it and free the per-page flags.
2930          */
2931         i915_gem_object_set_to_full_cpu_read_domain(obj);
2932
2933         old_write_domain = obj->write_domain;
2934         old_read_domains = obj->read_domains;
2935
2936         /* Flush the CPU cache if it's still invalid. */
2937         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2938                 i915_gem_clflush_object(obj);
2939
2940                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2941         }
2942
2943         /* It should now be out of any other write domains, and we can update
2944          * the domain values for our changes.
2945          */
2946         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2947
2948         /* If we're writing through the CPU, then the GPU read domains will
2949          * need to be invalidated at next use.
2950          */
2951         if (write) {
2952                 obj->read_domains = I915_GEM_DOMAIN_CPU;
2953                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2954         }
2955
2956         trace_i915_gem_object_change_domain(obj,
2957                                             old_read_domains,
2958                                             old_write_domain);
2959
2960         return 0;
2961 }
2962
2963 /*
2964  * Set the next domain for the specified object. This
2965  * may not actually perform the necessary flushing/invaliding though,
2966  * as that may want to be batched with other set_domain operations
2967  *
2968  * This is (we hope) the only really tricky part of gem. The goal
2969  * is fairly simple -- track which caches hold bits of the object
2970  * and make sure they remain coherent. A few concrete examples may
2971  * help to explain how it works. For shorthand, we use the notation
2972  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2973  * a pair of read and write domain masks.
2974  *
2975  * Case 1: the batch buffer
2976  *
2977  *      1. Allocated
2978  *      2. Written by CPU
2979  *      3. Mapped to GTT
2980  *      4. Read by GPU
2981  *      5. Unmapped from GTT
2982  *      6. Freed
2983  *
2984  *      Let's take these a step at a time
2985  *
2986  *      1. Allocated
2987  *              Pages allocated from the kernel may still have
2988  *              cache contents, so we set them to (CPU, CPU) always.
2989  *      2. Written by CPU (using pwrite)
2990  *              The pwrite function calls set_domain (CPU, CPU) and
2991  *              this function does nothing (as nothing changes)
2992  *      3. Mapped by GTT
2993  *              This function asserts that the object is not
2994  *              currently in any GPU-based read or write domains
2995  *      4. Read by GPU
2996  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2997  *              As write_domain is zero, this function adds in the
2998  *              current read domains (CPU+COMMAND, 0).
2999  *              flush_domains is set to CPU.
3000  *              invalidate_domains is set to COMMAND
3001  *              clflush is run to get data out of the CPU caches
3002  *              then i915_dev_set_domain calls i915_gem_flush to
3003  *              emit an MI_FLUSH and drm_agp_chipset_flush
3004  *      5. Unmapped from GTT
3005  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3006  *              flush_domains and invalidate_domains end up both zero
3007  *              so no flushing/invalidating happens
3008  *      6. Freed
3009  *              yay, done
3010  *
3011  * Case 2: The shared render buffer
3012  *
3013  *      1. Allocated
3014  *      2. Mapped to GTT
3015  *      3. Read/written by GPU
3016  *      4. set_domain to (CPU,CPU)
3017  *      5. Read/written by CPU
3018  *      6. Read/written by GPU
3019  *
3020  *      1. Allocated
3021  *              Same as last example, (CPU, CPU)
3022  *      2. Mapped to GTT
3023  *              Nothing changes (assertions find that it is not in the GPU)
3024  *      3. Read/written by GPU
3025  *              execbuffer calls set_domain (RENDER, RENDER)
3026  *              flush_domains gets CPU
3027  *              invalidate_domains gets GPU
3028  *              clflush (obj)
3029  *              MI_FLUSH and drm_agp_chipset_flush
3030  *      4. set_domain (CPU, CPU)
3031  *              flush_domains gets GPU
3032  *              invalidate_domains gets CPU
3033  *              wait_rendering (obj) to make sure all drawing is complete.
3034  *              This will include an MI_FLUSH to get the data from GPU
3035  *              to memory
3036  *              clflush (obj) to invalidate the CPU cache
3037  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3038  *      5. Read/written by CPU
3039  *              cache lines are loaded and dirtied
3040  *      6. Read written by GPU
3041  *              Same as last GPU access
3042  *
3043  * Case 3: The constant buffer
3044  *
3045  *      1. Allocated
3046  *      2. Written by CPU
3047  *      3. Read by GPU
3048  *      4. Updated (written) by CPU again
3049  *      5. Read by GPU
3050  *
3051  *      1. Allocated
3052  *              (CPU, CPU)
3053  *      2. Written by CPU
3054  *              (CPU, CPU)
3055  *      3. Read by GPU
3056  *              (CPU+RENDER, 0)
3057  *              flush_domains = CPU
3058  *              invalidate_domains = RENDER
3059  *              clflush (obj)
3060  *              MI_FLUSH
3061  *              drm_agp_chipset_flush
3062  *      4. Updated (written) by CPU again
3063  *              (CPU, CPU)
3064  *              flush_domains = 0 (no previous write domain)
3065  *              invalidate_domains = 0 (no new read domains)
3066  *      5. Read by GPU
3067  *              (CPU+RENDER, 0)
3068  *              flush_domains = CPU
3069  *              invalidate_domains = RENDER
3070  *              clflush (obj)
3071  *              MI_FLUSH
3072  *              drm_agp_chipset_flush
3073  */
3074 static void
3075 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
3076                                   struct intel_ring_buffer *ring)
3077 {
3078         struct drm_device               *dev = obj->dev;
3079         struct drm_i915_private         *dev_priv = dev->dev_private;
3080         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
3081         uint32_t                        invalidate_domains = 0;
3082         uint32_t                        flush_domains = 0;
3083         uint32_t                        old_read_domains;
3084
3085         intel_mark_busy(dev, obj);
3086
3087         /*
3088          * If the object isn't moving to a new write domain,
3089          * let the object stay in multiple read domains
3090          */
3091         if (obj->pending_write_domain == 0)
3092                 obj->pending_read_domains |= obj->read_domains;
3093         else
3094                 obj_priv->dirty = 1;
3095
3096         /*
3097          * Flush the current write domain if
3098          * the new read domains don't match. Invalidate
3099          * any read domains which differ from the old
3100          * write domain
3101          */
3102         if (obj->write_domain &&
3103             (obj->write_domain != obj->pending_read_domains ||
3104              obj_priv->ring != ring)) {
3105                 flush_domains |= obj->write_domain;
3106                 invalidate_domains |=
3107                         obj->pending_read_domains & ~obj->write_domain;
3108         }
3109         /*
3110          * Invalidate any read caches which may have
3111          * stale data. That is, any new read domains.
3112          */
3113         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3114         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
3115                 i915_gem_clflush_object(obj);
3116
3117         old_read_domains = obj->read_domains;
3118
3119         /* The actual obj->write_domain will be updated with
3120          * pending_write_domain after we emit the accumulated flush for all
3121          * of our domain changes in execbuffers (which clears objects'
3122          * write_domains).  So if we have a current write domain that we
3123          * aren't changing, set pending_write_domain to that.
3124          */
3125         if (flush_domains == 0 && obj->pending_write_domain == 0)
3126                 obj->pending_write_domain = obj->write_domain;
3127         obj->read_domains = obj->pending_read_domains;
3128
3129         dev->invalidate_domains |= invalidate_domains;
3130         dev->flush_domains |= flush_domains;
3131         if (flush_domains & I915_GEM_GPU_DOMAINS)
3132                 dev_priv->mm.flush_rings |= obj_priv->ring->id;
3133         if (invalidate_domains & I915_GEM_GPU_DOMAINS)
3134                 dev_priv->mm.flush_rings |= ring->id;
3135
3136         trace_i915_gem_object_change_domain(obj,
3137                                             old_read_domains,
3138                                             obj->write_domain);
3139 }
3140
3141 /**
3142  * Moves the object from a partially CPU read to a full one.
3143  *
3144  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3145  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3146  */
3147 static void
3148 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3149 {
3150         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3151
3152         if (!obj_priv->page_cpu_valid)
3153                 return;
3154
3155         /* If we're partially in the CPU read domain, finish moving it in.
3156          */
3157         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3158                 int i;
3159
3160                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3161                         if (obj_priv->page_cpu_valid[i])
3162                                 continue;
3163                         drm_clflush_pages(obj_priv->pages + i, 1);
3164                 }
3165         }
3166
3167         /* Free the page_cpu_valid mappings which are now stale, whether
3168          * or not we've got I915_GEM_DOMAIN_CPU.
3169          */
3170         kfree(obj_priv->page_cpu_valid);
3171         obj_priv->page_cpu_valid = NULL;
3172 }
3173
3174 /**
3175  * Set the CPU read domain on a range of the object.
3176  *
3177  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3178  * not entirely valid.  The page_cpu_valid member of the object flags which
3179  * pages have been flushed, and will be respected by
3180  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3181  * of the whole object.
3182  *
3183  * This function returns when the move is complete, including waiting on
3184  * flushes to occur.
3185  */
3186 static int
3187 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3188                                           uint64_t offset, uint64_t size)
3189 {
3190         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3191         uint32_t old_read_domains;
3192         int i, ret;
3193
3194         if (offset == 0 && size == obj->size)
3195                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3196
3197         ret = i915_gem_object_flush_gpu_write_domain(obj);
3198         if (ret != 0)
3199                 return ret;
3200         ret = i915_gem_object_wait_rendering(obj, true);
3201         if (ret)
3202                 return ret;
3203
3204         i915_gem_object_flush_gtt_write_domain(obj);
3205
3206         /* If we're already fully in the CPU read domain, we're done. */
3207         if (obj_priv->page_cpu_valid == NULL &&
3208             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3209                 return 0;
3210
3211         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3212          * newly adding I915_GEM_DOMAIN_CPU
3213          */
3214         if (obj_priv->page_cpu_valid == NULL) {
3215                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3216                                                    GFP_KERNEL);
3217                 if (obj_priv->page_cpu_valid == NULL)
3218                         return -ENOMEM;
3219         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3220                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3221
3222         /* Flush the cache on any pages that are still invalid from the CPU's
3223          * perspective.
3224          */
3225         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3226              i++) {
3227                 if (obj_priv->page_cpu_valid[i])
3228                         continue;
3229
3230                 drm_clflush_pages(obj_priv->pages + i, 1);
3231
3232                 obj_priv->page_cpu_valid[i] = 1;
3233         }
3234
3235         /* It should now be out of any other write domains, and we can update
3236          * the domain values for our changes.
3237          */
3238         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3239
3240         old_read_domains = obj->read_domains;
3241         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3242
3243         trace_i915_gem_object_change_domain(obj,
3244                                             old_read_domains,
3245                                             obj->write_domain);
3246
3247         return 0;
3248 }
3249
3250 static int
3251 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
3252                                    struct drm_file *file_priv,
3253                                    struct drm_i915_gem_exec_object2 *entry,
3254                                    struct drm_i915_gem_relocation_entry *reloc)
3255 {
3256         struct drm_device *dev = obj->base.dev;
3257         struct drm_gem_object *target_obj;
3258         uint32_t target_offset;
3259         int ret = -EINVAL;
3260
3261         target_obj = drm_gem_object_lookup(dev, file_priv,
3262                                            reloc->target_handle);
3263         if (target_obj == NULL)
3264                 return -ENOENT;
3265
3266         target_offset = to_intel_bo(target_obj)->gtt_offset;
3267
3268 #if WATCH_RELOC
3269         DRM_INFO("%s: obj %p offset %08x target %d "
3270                  "read %08x write %08x gtt %08x "
3271                  "presumed %08x delta %08x\n",
3272                  __func__,
3273                  obj,
3274                  (int) reloc->offset,
3275                  (int) reloc->target_handle,