84146ad565daf829b1783a55900ea9d406b2e9ce
[~shefty/rdma-dev.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include <drm/drmP.h>
29 #include <drm/i915_drm.h>
30 #include "i915_drv.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
38
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
42                                                     unsigned alignment,
43                                                     bool map_and_fenceable,
44                                                     bool nonblocking);
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46                                 struct drm_i915_gem_object *obj,
47                                 struct drm_i915_gem_pwrite *args,
48                                 struct drm_file *file);
49
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51                                  struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53                                          struct drm_i915_fence_reg *fence,
54                                          bool enable);
55
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57                                     struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
61
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
63 {
64         if (obj->tiling_mode)
65                 i915_gem_release_mmap(obj);
66
67         /* As we do not have an associated fence register, we will force
68          * a tiling change if we ever need to acquire one.
69          */
70         obj->fence_dirty = false;
71         obj->fence_reg = I915_FENCE_REG_NONE;
72 }
73
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
76                                   size_t size)
77 {
78         dev_priv->mm.object_count++;
79         dev_priv->mm.object_memory += size;
80 }
81
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
83                                      size_t size)
84 {
85         dev_priv->mm.object_count--;
86         dev_priv->mm.object_memory -= size;
87 }
88
89 static int
90 i915_gem_wait_for_error(struct drm_device *dev)
91 {
92         struct drm_i915_private *dev_priv = dev->dev_private;
93         struct completion *x = &dev_priv->error_completion;
94         unsigned long flags;
95         int ret;
96
97         if (!atomic_read(&dev_priv->mm.wedged))
98                 return 0;
99
100         /*
101          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102          * userspace. If it takes that long something really bad is going on and
103          * we should simply try to bail out and fail as gracefully as possible.
104          */
105         ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
106         if (ret == 0) {
107                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
108                 return -EIO;
109         } else if (ret < 0) {
110                 return ret;
111         }
112
113         if (atomic_read(&dev_priv->mm.wedged)) {
114                 /* GPU is hung, bump the completion count to account for
115                  * the token we just consumed so that we never hit zero and
116                  * end up waiting upon a subsequent completion event that
117                  * will never happen.
118                  */
119                 spin_lock_irqsave(&x->wait.lock, flags);
120                 x->done++;
121                 spin_unlock_irqrestore(&x->wait.lock, flags);
122         }
123         return 0;
124 }
125
126 int i915_mutex_lock_interruptible(struct drm_device *dev)
127 {
128         int ret;
129
130         ret = i915_gem_wait_for_error(dev);
131         if (ret)
132                 return ret;
133
134         ret = mutex_lock_interruptible(&dev->struct_mutex);
135         if (ret)
136                 return ret;
137
138         WARN_ON(i915_verify_lists(dev));
139         return 0;
140 }
141
142 static inline bool
143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
144 {
145         return obj->gtt_space && !obj->active;
146 }
147
148 int
149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
150                     struct drm_file *file)
151 {
152         struct drm_i915_gem_init *args = data;
153
154         if (drm_core_check_feature(dev, DRIVER_MODESET))
155                 return -ENODEV;
156
157         if (args->gtt_start >= args->gtt_end ||
158             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
159                 return -EINVAL;
160
161         /* GEM with user mode setting was never supported on ilk and later. */
162         if (INTEL_INFO(dev)->gen >= 5)
163                 return -ENODEV;
164
165         mutex_lock(&dev->struct_mutex);
166         i915_gem_init_global_gtt(dev, args->gtt_start,
167                                  args->gtt_end, args->gtt_end);
168         mutex_unlock(&dev->struct_mutex);
169
170         return 0;
171 }
172
173 int
174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
175                             struct drm_file *file)
176 {
177         struct drm_i915_private *dev_priv = dev->dev_private;
178         struct drm_i915_gem_get_aperture *args = data;
179         struct drm_i915_gem_object *obj;
180         size_t pinned;
181
182         pinned = 0;
183         mutex_lock(&dev->struct_mutex);
184         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
185                 if (obj->pin_count)
186                         pinned += obj->gtt_space->size;
187         mutex_unlock(&dev->struct_mutex);
188
189         args->aper_size = dev_priv->mm.gtt_total;
190         args->aper_available_size = args->aper_size - pinned;
191
192         return 0;
193 }
194
195 static int
196 i915_gem_create(struct drm_file *file,
197                 struct drm_device *dev,
198                 uint64_t size,
199                 uint32_t *handle_p)
200 {
201         struct drm_i915_gem_object *obj;
202         int ret;
203         u32 handle;
204
205         size = roundup(size, PAGE_SIZE);
206         if (size == 0)
207                 return -EINVAL;
208
209         /* Allocate the new object */
210         obj = i915_gem_alloc_object(dev, size);
211         if (obj == NULL)
212                 return -ENOMEM;
213
214         ret = drm_gem_handle_create(file, &obj->base, &handle);
215         if (ret) {
216                 drm_gem_object_release(&obj->base);
217                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
218                 kfree(obj);
219                 return ret;
220         }
221
222         /* drop reference from allocate - handle holds it now */
223         drm_gem_object_unreference(&obj->base);
224         trace_i915_gem_object_create(obj);
225
226         *handle_p = handle;
227         return 0;
228 }
229
230 int
231 i915_gem_dumb_create(struct drm_file *file,
232                      struct drm_device *dev,
233                      struct drm_mode_create_dumb *args)
234 {
235         /* have to work out size/pitch and return them */
236         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
237         args->size = args->pitch * args->height;
238         return i915_gem_create(file, dev,
239                                args->size, &args->handle);
240 }
241
242 int i915_gem_dumb_destroy(struct drm_file *file,
243                           struct drm_device *dev,
244                           uint32_t handle)
245 {
246         return drm_gem_handle_delete(file, handle);
247 }
248
249 /**
250  * Creates a new mm object and returns a handle to it.
251  */
252 int
253 i915_gem_create_ioctl(struct drm_device *dev, void *data,
254                       struct drm_file *file)
255 {
256         struct drm_i915_gem_create *args = data;
257
258         return i915_gem_create(file, dev,
259                                args->size, &args->handle);
260 }
261
262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
263 {
264         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
265
266         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
267                 obj->tiling_mode != I915_TILING_NONE;
268 }
269
270 static inline int
271 __copy_to_user_swizzled(char __user *cpu_vaddr,
272                         const char *gpu_vaddr, int gpu_offset,
273                         int length)
274 {
275         int ret, cpu_offset = 0;
276
277         while (length > 0) {
278                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
279                 int this_length = min(cacheline_end - gpu_offset, length);
280                 int swizzled_gpu_offset = gpu_offset ^ 64;
281
282                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
283                                      gpu_vaddr + swizzled_gpu_offset,
284                                      this_length);
285                 if (ret)
286                         return ret + length;
287
288                 cpu_offset += this_length;
289                 gpu_offset += this_length;
290                 length -= this_length;
291         }
292
293         return 0;
294 }
295
296 static inline int
297 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
298                           const char __user *cpu_vaddr,
299                           int length)
300 {
301         int ret, cpu_offset = 0;
302
303         while (length > 0) {
304                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
305                 int this_length = min(cacheline_end - gpu_offset, length);
306                 int swizzled_gpu_offset = gpu_offset ^ 64;
307
308                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
309                                        cpu_vaddr + cpu_offset,
310                                        this_length);
311                 if (ret)
312                         return ret + length;
313
314                 cpu_offset += this_length;
315                 gpu_offset += this_length;
316                 length -= this_length;
317         }
318
319         return 0;
320 }
321
322 /* Per-page copy function for the shmem pread fastpath.
323  * Flushes invalid cachelines before reading the target if
324  * needs_clflush is set. */
325 static int
326 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
327                  char __user *user_data,
328                  bool page_do_bit17_swizzling, bool needs_clflush)
329 {
330         char *vaddr;
331         int ret;
332
333         if (unlikely(page_do_bit17_swizzling))
334                 return -EINVAL;
335
336         vaddr = kmap_atomic(page);
337         if (needs_clflush)
338                 drm_clflush_virt_range(vaddr + shmem_page_offset,
339                                        page_length);
340         ret = __copy_to_user_inatomic(user_data,
341                                       vaddr + shmem_page_offset,
342                                       page_length);
343         kunmap_atomic(vaddr);
344
345         return ret ? -EFAULT : 0;
346 }
347
348 static void
349 shmem_clflush_swizzled_range(char *addr, unsigned long length,
350                              bool swizzled)
351 {
352         if (unlikely(swizzled)) {
353                 unsigned long start = (unsigned long) addr;
354                 unsigned long end = (unsigned long) addr + length;
355
356                 /* For swizzling simply ensure that we always flush both
357                  * channels. Lame, but simple and it works. Swizzled
358                  * pwrite/pread is far from a hotpath - current userspace
359                  * doesn't use it at all. */
360                 start = round_down(start, 128);
361                 end = round_up(end, 128);
362
363                 drm_clflush_virt_range((void *)start, end - start);
364         } else {
365                 drm_clflush_virt_range(addr, length);
366         }
367
368 }
369
370 /* Only difference to the fast-path function is that this can handle bit17
371  * and uses non-atomic copy and kmap functions. */
372 static int
373 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
374                  char __user *user_data,
375                  bool page_do_bit17_swizzling, bool needs_clflush)
376 {
377         char *vaddr;
378         int ret;
379
380         vaddr = kmap(page);
381         if (needs_clflush)
382                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
383                                              page_length,
384                                              page_do_bit17_swizzling);
385
386         if (page_do_bit17_swizzling)
387                 ret = __copy_to_user_swizzled(user_data,
388                                               vaddr, shmem_page_offset,
389                                               page_length);
390         else
391                 ret = __copy_to_user(user_data,
392                                      vaddr + shmem_page_offset,
393                                      page_length);
394         kunmap(page);
395
396         return ret ? - EFAULT : 0;
397 }
398
399 static int
400 i915_gem_shmem_pread(struct drm_device *dev,
401                      struct drm_i915_gem_object *obj,
402                      struct drm_i915_gem_pread *args,
403                      struct drm_file *file)
404 {
405         char __user *user_data;
406         ssize_t remain;
407         loff_t offset;
408         int shmem_page_offset, page_length, ret = 0;
409         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410         int hit_slowpath = 0;
411         int prefaulted = 0;
412         int needs_clflush = 0;
413         struct scatterlist *sg;
414         int i;
415
416         user_data = (char __user *) (uintptr_t) args->data_ptr;
417         remain = args->size;
418
419         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
420
421         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
422                 /* If we're not in the cpu read domain, set ourself into the gtt
423                  * read domain and manually flush cachelines (if required). This
424                  * optimizes for the case when the gpu will dirty the data
425                  * anyway again before the next pread happens. */
426                 if (obj->cache_level == I915_CACHE_NONE)
427                         needs_clflush = 1;
428                 if (obj->gtt_space) {
429                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
430                         if (ret)
431                                 return ret;
432                 }
433         }
434
435         ret = i915_gem_object_get_pages(obj);
436         if (ret)
437                 return ret;
438
439         i915_gem_object_pin_pages(obj);
440
441         offset = args->offset;
442
443         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
444                 struct page *page;
445
446                 if (i < offset >> PAGE_SHIFT)
447                         continue;
448
449                 if (remain <= 0)
450                         break;
451
452                 /* Operation in this page
453                  *
454                  * shmem_page_offset = offset within page in shmem file
455                  * page_length = bytes to copy for this page
456                  */
457                 shmem_page_offset = offset_in_page(offset);
458                 page_length = remain;
459                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
460                         page_length = PAGE_SIZE - shmem_page_offset;
461
462                 page = sg_page(sg);
463                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
464                         (page_to_phys(page) & (1 << 17)) != 0;
465
466                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
467                                        user_data, page_do_bit17_swizzling,
468                                        needs_clflush);
469                 if (ret == 0)
470                         goto next_page;
471
472                 hit_slowpath = 1;
473                 mutex_unlock(&dev->struct_mutex);
474
475                 if (!prefaulted) {
476                         ret = fault_in_multipages_writeable(user_data, remain);
477                         /* Userspace is tricking us, but we've already clobbered
478                          * its pages with the prefault and promised to write the
479                          * data up to the first fault. Hence ignore any errors
480                          * and just continue. */
481                         (void)ret;
482                         prefaulted = 1;
483                 }
484
485                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
486                                        user_data, page_do_bit17_swizzling,
487                                        needs_clflush);
488
489                 mutex_lock(&dev->struct_mutex);
490
491 next_page:
492                 mark_page_accessed(page);
493
494                 if (ret)
495                         goto out;
496
497                 remain -= page_length;
498                 user_data += page_length;
499                 offset += page_length;
500         }
501
502 out:
503         i915_gem_object_unpin_pages(obj);
504
505         if (hit_slowpath) {
506                 /* Fixup: Kill any reinstated backing storage pages */
507                 if (obj->madv == __I915_MADV_PURGED)
508                         i915_gem_object_truncate(obj);
509         }
510
511         return ret;
512 }
513
514 /**
515  * Reads data from the object referenced by handle.
516  *
517  * On error, the contents of *data are undefined.
518  */
519 int
520 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
521                      struct drm_file *file)
522 {
523         struct drm_i915_gem_pread *args = data;
524         struct drm_i915_gem_object *obj;
525         int ret = 0;
526
527         if (args->size == 0)
528                 return 0;
529
530         if (!access_ok(VERIFY_WRITE,
531                        (char __user *)(uintptr_t)args->data_ptr,
532                        args->size))
533                 return -EFAULT;
534
535         ret = i915_mutex_lock_interruptible(dev);
536         if (ret)
537                 return ret;
538
539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
540         if (&obj->base == NULL) {
541                 ret = -ENOENT;
542                 goto unlock;
543         }
544
545         /* Bounds check source.  */
546         if (args->offset > obj->base.size ||
547             args->size > obj->base.size - args->offset) {
548                 ret = -EINVAL;
549                 goto out;
550         }
551
552         /* prime objects have no backing filp to GEM pread/pwrite
553          * pages from.
554          */
555         if (!obj->base.filp) {
556                 ret = -EINVAL;
557                 goto out;
558         }
559
560         trace_i915_gem_object_pread(obj, args->offset, args->size);
561
562         ret = i915_gem_shmem_pread(dev, obj, args, file);
563
564 out:
565         drm_gem_object_unreference(&obj->base);
566 unlock:
567         mutex_unlock(&dev->struct_mutex);
568         return ret;
569 }
570
571 /* This is the fast write path which cannot handle
572  * page faults in the source data
573  */
574
575 static inline int
576 fast_user_write(struct io_mapping *mapping,
577                 loff_t page_base, int page_offset,
578                 char __user *user_data,
579                 int length)
580 {
581         void __iomem *vaddr_atomic;
582         void *vaddr;
583         unsigned long unwritten;
584
585         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
586         /* We can use the cpu mem copy function because this is X86. */
587         vaddr = (void __force*)vaddr_atomic + page_offset;
588         unwritten = __copy_from_user_inatomic_nocache(vaddr,
589                                                       user_data, length);
590         io_mapping_unmap_atomic(vaddr_atomic);
591         return unwritten;
592 }
593
594 /**
595  * This is the fast pwrite path, where we copy the data directly from the
596  * user into the GTT, uncached.
597  */
598 static int
599 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
600                          struct drm_i915_gem_object *obj,
601                          struct drm_i915_gem_pwrite *args,
602                          struct drm_file *file)
603 {
604         drm_i915_private_t *dev_priv = dev->dev_private;
605         ssize_t remain;
606         loff_t offset, page_base;
607         char __user *user_data;
608         int page_offset, page_length, ret;
609
610         ret = i915_gem_object_pin(obj, 0, true, true);
611         if (ret)
612                 goto out;
613
614         ret = i915_gem_object_set_to_gtt_domain(obj, true);
615         if (ret)
616                 goto out_unpin;
617
618         ret = i915_gem_object_put_fence(obj);
619         if (ret)
620                 goto out_unpin;
621
622         user_data = (char __user *) (uintptr_t) args->data_ptr;
623         remain = args->size;
624
625         offset = obj->gtt_offset + args->offset;
626
627         while (remain > 0) {
628                 /* Operation in this page
629                  *
630                  * page_base = page offset within aperture
631                  * page_offset = offset within page
632                  * page_length = bytes to copy for this page
633                  */
634                 page_base = offset & PAGE_MASK;
635                 page_offset = offset_in_page(offset);
636                 page_length = remain;
637                 if ((page_offset + remain) > PAGE_SIZE)
638                         page_length = PAGE_SIZE - page_offset;
639
640                 /* If we get a fault while copying data, then (presumably) our
641                  * source page isn't available.  Return the error and we'll
642                  * retry in the slow path.
643                  */
644                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
645                                     page_offset, user_data, page_length)) {
646                         ret = -EFAULT;
647                         goto out_unpin;
648                 }
649
650                 remain -= page_length;
651                 user_data += page_length;
652                 offset += page_length;
653         }
654
655 out_unpin:
656         i915_gem_object_unpin(obj);
657 out:
658         return ret;
659 }
660
661 /* Per-page copy function for the shmem pwrite fastpath.
662  * Flushes invalid cachelines before writing to the target if
663  * needs_clflush_before is set and flushes out any written cachelines after
664  * writing if needs_clflush is set. */
665 static int
666 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
667                   char __user *user_data,
668                   bool page_do_bit17_swizzling,
669                   bool needs_clflush_before,
670                   bool needs_clflush_after)
671 {
672         char *vaddr;
673         int ret;
674
675         if (unlikely(page_do_bit17_swizzling))
676                 return -EINVAL;
677
678         vaddr = kmap_atomic(page);
679         if (needs_clflush_before)
680                 drm_clflush_virt_range(vaddr + shmem_page_offset,
681                                        page_length);
682         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
683                                                 user_data,
684                                                 page_length);
685         if (needs_clflush_after)
686                 drm_clflush_virt_range(vaddr + shmem_page_offset,
687                                        page_length);
688         kunmap_atomic(vaddr);
689
690         return ret ? -EFAULT : 0;
691 }
692
693 /* Only difference to the fast-path function is that this can handle bit17
694  * and uses non-atomic copy and kmap functions. */
695 static int
696 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
697                   char __user *user_data,
698                   bool page_do_bit17_swizzling,
699                   bool needs_clflush_before,
700                   bool needs_clflush_after)
701 {
702         char *vaddr;
703         int ret;
704
705         vaddr = kmap(page);
706         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
707                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
708                                              page_length,
709                                              page_do_bit17_swizzling);
710         if (page_do_bit17_swizzling)
711                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
712                                                 user_data,
713                                                 page_length);
714         else
715                 ret = __copy_from_user(vaddr + shmem_page_offset,
716                                        user_data,
717                                        page_length);
718         if (needs_clflush_after)
719                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
720                                              page_length,
721                                              page_do_bit17_swizzling);
722         kunmap(page);
723
724         return ret ? -EFAULT : 0;
725 }
726
727 static int
728 i915_gem_shmem_pwrite(struct drm_device *dev,
729                       struct drm_i915_gem_object *obj,
730                       struct drm_i915_gem_pwrite *args,
731                       struct drm_file *file)
732 {
733         ssize_t remain;
734         loff_t offset;
735         char __user *user_data;
736         int shmem_page_offset, page_length, ret = 0;
737         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
738         int hit_slowpath = 0;
739         int needs_clflush_after = 0;
740         int needs_clflush_before = 0;
741         int i;
742         struct scatterlist *sg;
743
744         user_data = (char __user *) (uintptr_t) args->data_ptr;
745         remain = args->size;
746
747         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
748
749         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
750                 /* If we're not in the cpu write domain, set ourself into the gtt
751                  * write domain and manually flush cachelines (if required). This
752                  * optimizes for the case when the gpu will use the data
753                  * right away and we therefore have to clflush anyway. */
754                 if (obj->cache_level == I915_CACHE_NONE)
755                         needs_clflush_after = 1;
756                 if (obj->gtt_space) {
757                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
758                         if (ret)
759                                 return ret;
760                 }
761         }
762         /* Same trick applies for invalidate partially written cachelines before
763          * writing.  */
764         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
765             && obj->cache_level == I915_CACHE_NONE)
766                 needs_clflush_before = 1;
767
768         ret = i915_gem_object_get_pages(obj);
769         if (ret)
770                 return ret;
771
772         i915_gem_object_pin_pages(obj);
773
774         offset = args->offset;
775         obj->dirty = 1;
776
777         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
778                 struct page *page;
779                 int partial_cacheline_write;
780
781                 if (i < offset >> PAGE_SHIFT)
782                         continue;
783
784                 if (remain <= 0)
785                         break;
786
787                 /* Operation in this page
788                  *
789                  * shmem_page_offset = offset within page in shmem file
790                  * page_length = bytes to copy for this page
791                  */
792                 shmem_page_offset = offset_in_page(offset);
793
794                 page_length = remain;
795                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
796                         page_length = PAGE_SIZE - shmem_page_offset;
797
798                 /* If we don't overwrite a cacheline completely we need to be
799                  * careful to have up-to-date data by first clflushing. Don't
800                  * overcomplicate things and flush the entire patch. */
801                 partial_cacheline_write = needs_clflush_before &&
802                         ((shmem_page_offset | page_length)
803                                 & (boot_cpu_data.x86_clflush_size - 1));
804
805                 page = sg_page(sg);
806                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
807                         (page_to_phys(page) & (1 << 17)) != 0;
808
809                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
810                                         user_data, page_do_bit17_swizzling,
811                                         partial_cacheline_write,
812                                         needs_clflush_after);
813                 if (ret == 0)
814                         goto next_page;
815
816                 hit_slowpath = 1;
817                 mutex_unlock(&dev->struct_mutex);
818                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
819                                         user_data, page_do_bit17_swizzling,
820                                         partial_cacheline_write,
821                                         needs_clflush_after);
822
823                 mutex_lock(&dev->struct_mutex);
824
825 next_page:
826                 set_page_dirty(page);
827                 mark_page_accessed(page);
828
829                 if (ret)
830                         goto out;
831
832                 remain -= page_length;
833                 user_data += page_length;
834                 offset += page_length;
835         }
836
837 out:
838         i915_gem_object_unpin_pages(obj);
839
840         if (hit_slowpath) {
841                 /* Fixup: Kill any reinstated backing storage pages */
842                 if (obj->madv == __I915_MADV_PURGED)
843                         i915_gem_object_truncate(obj);
844                 /* and flush dirty cachelines in case the object isn't in the cpu write
845                  * domain anymore. */
846                 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
847                         i915_gem_clflush_object(obj);
848                         i915_gem_chipset_flush(dev);
849                 }
850         }
851
852         if (needs_clflush_after)
853                 i915_gem_chipset_flush(dev);
854
855         return ret;
856 }
857
858 /**
859  * Writes data to the object referenced by handle.
860  *
861  * On error, the contents of the buffer that were to be modified are undefined.
862  */
863 int
864 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
865                       struct drm_file *file)
866 {
867         struct drm_i915_gem_pwrite *args = data;
868         struct drm_i915_gem_object *obj;
869         int ret;
870
871         if (args->size == 0)
872                 return 0;
873
874         if (!access_ok(VERIFY_READ,
875                        (char __user *)(uintptr_t)args->data_ptr,
876                        args->size))
877                 return -EFAULT;
878
879         ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
880                                            args->size);
881         if (ret)
882                 return -EFAULT;
883
884         ret = i915_mutex_lock_interruptible(dev);
885         if (ret)
886                 return ret;
887
888         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
889         if (&obj->base == NULL) {
890                 ret = -ENOENT;
891                 goto unlock;
892         }
893
894         /* Bounds check destination. */
895         if (args->offset > obj->base.size ||
896             args->size > obj->base.size - args->offset) {
897                 ret = -EINVAL;
898                 goto out;
899         }
900
901         /* prime objects have no backing filp to GEM pread/pwrite
902          * pages from.
903          */
904         if (!obj->base.filp) {
905                 ret = -EINVAL;
906                 goto out;
907         }
908
909         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
910
911         ret = -EFAULT;
912         /* We can only do the GTT pwrite on untiled buffers, as otherwise
913          * it would end up going through the fenced access, and we'll get
914          * different detiling behavior between reading and writing.
915          * pread/pwrite currently are reading and writing from the CPU
916          * perspective, requiring manual detiling by the client.
917          */
918         if (obj->phys_obj) {
919                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
920                 goto out;
921         }
922
923         if (obj->cache_level == I915_CACHE_NONE &&
924             obj->tiling_mode == I915_TILING_NONE &&
925             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
926                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
927                 /* Note that the gtt paths might fail with non-page-backed user
928                  * pointers (e.g. gtt mappings when moving data between
929                  * textures). Fallback to the shmem path in that case. */
930         }
931
932         if (ret == -EFAULT || ret == -ENOSPC)
933                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
934
935 out:
936         drm_gem_object_unreference(&obj->base);
937 unlock:
938         mutex_unlock(&dev->struct_mutex);
939         return ret;
940 }
941
942 int
943 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
944                      bool interruptible)
945 {
946         if (atomic_read(&dev_priv->mm.wedged)) {
947                 struct completion *x = &dev_priv->error_completion;
948                 bool recovery_complete;
949                 unsigned long flags;
950
951                 /* Give the error handler a chance to run. */
952                 spin_lock_irqsave(&x->wait.lock, flags);
953                 recovery_complete = x->done > 0;
954                 spin_unlock_irqrestore(&x->wait.lock, flags);
955
956                 /* Non-interruptible callers can't handle -EAGAIN, hence return
957                  * -EIO unconditionally for these. */
958                 if (!interruptible)
959                         return -EIO;
960
961                 /* Recovery complete, but still wedged means reset failure. */
962                 if (recovery_complete)
963                         return -EIO;
964
965                 return -EAGAIN;
966         }
967
968         return 0;
969 }
970
971 /*
972  * Compare seqno against outstanding lazy request. Emit a request if they are
973  * equal.
974  */
975 static int
976 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
977 {
978         int ret;
979
980         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
981
982         ret = 0;
983         if (seqno == ring->outstanding_lazy_request)
984                 ret = i915_add_request(ring, NULL, NULL);
985
986         return ret;
987 }
988
989 /**
990  * __wait_seqno - wait until execution of seqno has finished
991  * @ring: the ring expected to report seqno
992  * @seqno: duh!
993  * @interruptible: do an interruptible wait (normally yes)
994  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
995  *
996  * Returns 0 if the seqno was found within the alloted time. Else returns the
997  * errno with remaining time filled in timeout argument.
998  */
999 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1000                         bool interruptible, struct timespec *timeout)
1001 {
1002         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1003         struct timespec before, now, wait_time={1,0};
1004         unsigned long timeout_jiffies;
1005         long end;
1006         bool wait_forever = true;
1007         int ret;
1008
1009         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1010                 return 0;
1011
1012         trace_i915_gem_request_wait_begin(ring, seqno);
1013
1014         if (timeout != NULL) {
1015                 wait_time = *timeout;
1016                 wait_forever = false;
1017         }
1018
1019         timeout_jiffies = timespec_to_jiffies(&wait_time);
1020
1021         if (WARN_ON(!ring->irq_get(ring)))
1022                 return -ENODEV;
1023
1024         /* Record current time in case interrupted by signal, or wedged * */
1025         getrawmonotonic(&before);
1026
1027 #define EXIT_COND \
1028         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1029         atomic_read(&dev_priv->mm.wedged))
1030         do {
1031                 if (interruptible)
1032                         end = wait_event_interruptible_timeout(ring->irq_queue,
1033                                                                EXIT_COND,
1034                                                                timeout_jiffies);
1035                 else
1036                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1037                                                  timeout_jiffies);
1038
1039                 ret = i915_gem_check_wedge(dev_priv, interruptible);
1040                 if (ret)
1041                         end = ret;
1042         } while (end == 0 && wait_forever);
1043
1044         getrawmonotonic(&now);
1045
1046         ring->irq_put(ring);
1047         trace_i915_gem_request_wait_end(ring, seqno);
1048 #undef EXIT_COND
1049
1050         if (timeout) {
1051                 struct timespec sleep_time = timespec_sub(now, before);
1052                 *timeout = timespec_sub(*timeout, sleep_time);
1053         }
1054
1055         switch (end) {
1056         case -EIO:
1057         case -EAGAIN: /* Wedged */
1058         case -ERESTARTSYS: /* Signal */
1059                 return (int)end;
1060         case 0: /* Timeout */
1061                 if (timeout)
1062                         set_normalized_timespec(timeout, 0, 0);
1063                 return -ETIME;
1064         default: /* Completed */
1065                 WARN_ON(end < 0); /* We're not aware of other errors */
1066                 return 0;
1067         }
1068 }
1069
1070 /**
1071  * Waits for a sequence number to be signaled, and cleans up the
1072  * request and object lists appropriately for that event.
1073  */
1074 int
1075 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1076 {
1077         struct drm_device *dev = ring->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         bool interruptible = dev_priv->mm.interruptible;
1080         int ret;
1081
1082         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1083         BUG_ON(seqno == 0);
1084
1085         ret = i915_gem_check_wedge(dev_priv, interruptible);
1086         if (ret)
1087                 return ret;
1088
1089         ret = i915_gem_check_olr(ring, seqno);
1090         if (ret)
1091                 return ret;
1092
1093         return __wait_seqno(ring, seqno, interruptible, NULL);
1094 }
1095
1096 /**
1097  * Ensures that all rendering to the object has completed and the object is
1098  * safe to unbind from the GTT or access from the CPU.
1099  */
1100 static __must_check int
1101 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1102                                bool readonly)
1103 {
1104         struct intel_ring_buffer *ring = obj->ring;
1105         u32 seqno;
1106         int ret;
1107
1108         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1109         if (seqno == 0)
1110                 return 0;
1111
1112         ret = i915_wait_seqno(ring, seqno);
1113         if (ret)
1114                 return ret;
1115
1116         i915_gem_retire_requests_ring(ring);
1117
1118         /* Manually manage the write flush as we may have not yet
1119          * retired the buffer.
1120          */
1121         if (obj->last_write_seqno &&
1122             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1123                 obj->last_write_seqno = 0;
1124                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1125         }
1126
1127         return 0;
1128 }
1129
1130 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1131  * as the object state may change during this call.
1132  */
1133 static __must_check int
1134 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1135                                             bool readonly)
1136 {
1137         struct drm_device *dev = obj->base.dev;
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         struct intel_ring_buffer *ring = obj->ring;
1140         u32 seqno;
1141         int ret;
1142
1143         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1144         BUG_ON(!dev_priv->mm.interruptible);
1145
1146         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1147         if (seqno == 0)
1148                 return 0;
1149
1150         ret = i915_gem_check_wedge(dev_priv, true);
1151         if (ret)
1152                 return ret;
1153
1154         ret = i915_gem_check_olr(ring, seqno);
1155         if (ret)
1156                 return ret;
1157
1158         mutex_unlock(&dev->struct_mutex);
1159         ret = __wait_seqno(ring, seqno, true, NULL);
1160         mutex_lock(&dev->struct_mutex);
1161
1162         i915_gem_retire_requests_ring(ring);
1163
1164         /* Manually manage the write flush as we may have not yet
1165          * retired the buffer.
1166          */
1167         if (obj->last_write_seqno &&
1168             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1169                 obj->last_write_seqno = 0;
1170                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1171         }
1172
1173         return ret;
1174 }
1175
1176 /**
1177  * Called when user space prepares to use an object with the CPU, either
1178  * through the mmap ioctl's mapping or a GTT mapping.
1179  */
1180 int
1181 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1182                           struct drm_file *file)
1183 {
1184         struct drm_i915_gem_set_domain *args = data;
1185         struct drm_i915_gem_object *obj;
1186         uint32_t read_domains = args->read_domains;
1187         uint32_t write_domain = args->write_domain;
1188         int ret;
1189
1190         /* Only handle setting domains to types used by the CPU. */
1191         if (write_domain & I915_GEM_GPU_DOMAINS)
1192                 return -EINVAL;
1193
1194         if (read_domains & I915_GEM_GPU_DOMAINS)
1195                 return -EINVAL;
1196
1197         /* Having something in the write domain implies it's in the read
1198          * domain, and only that read domain.  Enforce that in the request.
1199          */
1200         if (write_domain != 0 && read_domains != write_domain)
1201                 return -EINVAL;
1202
1203         ret = i915_mutex_lock_interruptible(dev);
1204         if (ret)
1205                 return ret;
1206
1207         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1208         if (&obj->base == NULL) {
1209                 ret = -ENOENT;
1210                 goto unlock;
1211         }
1212
1213         /* Try to flush the object off the GPU without holding the lock.
1214          * We will repeat the flush holding the lock in the normal manner
1215          * to catch cases where we are gazumped.
1216          */
1217         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218         if (ret)
1219                 goto unref;
1220
1221         if (read_domains & I915_GEM_DOMAIN_GTT) {
1222                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1223
1224                 /* Silently promote "you're not bound, there was nothing to do"
1225                  * to success, since the client was just asking us to
1226                  * make sure everything was done.
1227                  */
1228                 if (ret == -EINVAL)
1229                         ret = 0;
1230         } else {
1231                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232         }
1233
1234 unref:
1235         drm_gem_object_unreference(&obj->base);
1236 unlock:
1237         mutex_unlock(&dev->struct_mutex);
1238         return ret;
1239 }
1240
1241 /**
1242  * Called when user space has done writes to this buffer
1243  */
1244 int
1245 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1246                          struct drm_file *file)
1247 {
1248         struct drm_i915_gem_sw_finish *args = data;
1249         struct drm_i915_gem_object *obj;
1250         int ret = 0;
1251
1252         ret = i915_mutex_lock_interruptible(dev);
1253         if (ret)
1254                 return ret;
1255
1256         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1257         if (&obj->base == NULL) {
1258                 ret = -ENOENT;
1259                 goto unlock;
1260         }
1261
1262         /* Pinned buffers may be scanout, so flush the cache */
1263         if (obj->pin_count)
1264                 i915_gem_object_flush_cpu_write_domain(obj);
1265
1266         drm_gem_object_unreference(&obj->base);
1267 unlock:
1268         mutex_unlock(&dev->struct_mutex);
1269         return ret;
1270 }
1271
1272 /**
1273  * Maps the contents of an object, returning the address it is mapped
1274  * into.
1275  *
1276  * While the mapping holds a reference on the contents of the object, it doesn't
1277  * imply a ref on the object itself.
1278  */
1279 int
1280 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1281                     struct drm_file *file)
1282 {
1283         struct drm_i915_gem_mmap *args = data;
1284         struct drm_gem_object *obj;
1285         unsigned long addr;
1286
1287         obj = drm_gem_object_lookup(dev, file, args->handle);
1288         if (obj == NULL)
1289                 return -ENOENT;
1290
1291         /* prime objects have no backing filp to GEM mmap
1292          * pages from.
1293          */
1294         if (!obj->filp) {
1295                 drm_gem_object_unreference_unlocked(obj);
1296                 return -EINVAL;
1297         }
1298
1299         addr = vm_mmap(obj->filp, 0, args->size,
1300                        PROT_READ | PROT_WRITE, MAP_SHARED,
1301                        args->offset);
1302         drm_gem_object_unreference_unlocked(obj);
1303         if (IS_ERR((void *)addr))
1304                 return addr;
1305
1306         args->addr_ptr = (uint64_t) addr;
1307
1308         return 0;
1309 }
1310
1311 /**
1312  * i915_gem_fault - fault a page into the GTT
1313  * vma: VMA in question
1314  * vmf: fault info
1315  *
1316  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1317  * from userspace.  The fault handler takes care of binding the object to
1318  * the GTT (if needed), allocating and programming a fence register (again,
1319  * only if needed based on whether the old reg is still valid or the object
1320  * is tiled) and inserting a new PTE into the faulting process.
1321  *
1322  * Note that the faulting process may involve evicting existing objects
1323  * from the GTT and/or fence registers to make room.  So performance may
1324  * suffer if the GTT working set is large or there are few fence registers
1325  * left.
1326  */
1327 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1328 {
1329         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1330         struct drm_device *dev = obj->base.dev;
1331         drm_i915_private_t *dev_priv = dev->dev_private;
1332         pgoff_t page_offset;
1333         unsigned long pfn;
1334         int ret = 0;
1335         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1336
1337         /* We don't use vmf->pgoff since that has the fake offset */
1338         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1339                 PAGE_SHIFT;
1340
1341         ret = i915_mutex_lock_interruptible(dev);
1342         if (ret)
1343                 goto out;
1344
1345         trace_i915_gem_object_fault(obj, page_offset, true, write);
1346
1347         /* Now bind it into the GTT if needed */
1348         ret = i915_gem_object_pin(obj, 0, true, false);
1349         if (ret)
1350                 goto unlock;
1351
1352         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1353         if (ret)
1354                 goto unpin;
1355
1356         ret = i915_gem_object_get_fence(obj);
1357         if (ret)
1358                 goto unpin;
1359
1360         obj->fault_mappable = true;
1361
1362         pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1363                 page_offset;
1364
1365         /* Finally, remap it using the new GTT offset */
1366         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1367 unpin:
1368         i915_gem_object_unpin(obj);
1369 unlock:
1370         mutex_unlock(&dev->struct_mutex);
1371 out:
1372         switch (ret) {
1373         case -EIO:
1374                 /* If this -EIO is due to a gpu hang, give the reset code a
1375                  * chance to clean up the mess. Otherwise return the proper
1376                  * SIGBUS. */
1377                 if (!atomic_read(&dev_priv->mm.wedged))
1378                         return VM_FAULT_SIGBUS;
1379         case -EAGAIN:
1380                 /* Give the error handler a chance to run and move the
1381                  * objects off the GPU active list. Next time we service the
1382                  * fault, we should be able to transition the page into the
1383                  * GTT without touching the GPU (and so avoid further
1384                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1385                  * with coherency, just lost writes.
1386                  */
1387                 set_need_resched();
1388         case 0:
1389         case -ERESTARTSYS:
1390         case -EINTR:
1391         case -EBUSY:
1392                 /*
1393                  * EBUSY is ok: this just means that another thread
1394                  * already did the job.
1395                  */
1396                 return VM_FAULT_NOPAGE;
1397         case -ENOMEM:
1398                 return VM_FAULT_OOM;
1399         case -ENOSPC:
1400                 return VM_FAULT_SIGBUS;
1401         default:
1402                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1403                 return VM_FAULT_SIGBUS;
1404         }
1405 }
1406
1407 /**
1408  * i915_gem_release_mmap - remove physical page mappings
1409  * @obj: obj in question
1410  *
1411  * Preserve the reservation of the mmapping with the DRM core code, but
1412  * relinquish ownership of the pages back to the system.
1413  *
1414  * It is vital that we remove the page mapping if we have mapped a tiled
1415  * object through the GTT and then lose the fence register due to
1416  * resource pressure. Similarly if the object has been moved out of the
1417  * aperture, than pages mapped into userspace must be revoked. Removing the
1418  * mapping will then trigger a page fault on the next user access, allowing
1419  * fixup by i915_gem_fault().
1420  */
1421 void
1422 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1423 {
1424         if (!obj->fault_mappable)
1425                 return;
1426
1427         if (obj->base.dev->dev_mapping)
1428                 unmap_mapping_range(obj->base.dev->dev_mapping,
1429                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1430                                     obj->base.size, 1);
1431
1432         obj->fault_mappable = false;
1433 }
1434
1435 static uint32_t
1436 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1437 {
1438         uint32_t gtt_size;
1439
1440         if (INTEL_INFO(dev)->gen >= 4 ||
1441             tiling_mode == I915_TILING_NONE)
1442                 return size;
1443
1444         /* Previous chips need a power-of-two fence region when tiling */
1445         if (INTEL_INFO(dev)->gen == 3)
1446                 gtt_size = 1024*1024;
1447         else
1448                 gtt_size = 512*1024;
1449
1450         while (gtt_size < size)
1451                 gtt_size <<= 1;
1452
1453         return gtt_size;
1454 }
1455
1456 /**
1457  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1458  * @obj: object to check
1459  *
1460  * Return the required GTT alignment for an object, taking into account
1461  * potential fence register mapping.
1462  */
1463 static uint32_t
1464 i915_gem_get_gtt_alignment(struct drm_device *dev,
1465                            uint32_t size,
1466                            int tiling_mode)
1467 {
1468         /*
1469          * Minimum alignment is 4k (GTT page size), but might be greater
1470          * if a fence register is needed for the object.
1471          */
1472         if (INTEL_INFO(dev)->gen >= 4 ||
1473             tiling_mode == I915_TILING_NONE)
1474                 return 4096;
1475
1476         /*
1477          * Previous chips need to be aligned to the size of the smallest
1478          * fence register that can contain the object.
1479          */
1480         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1481 }
1482
1483 /**
1484  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1485  *                                       unfenced object
1486  * @dev: the device
1487  * @size: size of the object
1488  * @tiling_mode: tiling mode of the object
1489  *
1490  * Return the required GTT alignment for an object, only taking into account
1491  * unfenced tiled surface requirements.
1492  */
1493 uint32_t
1494 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1495                                     uint32_t size,
1496                                     int tiling_mode)
1497 {
1498         /*
1499          * Minimum alignment is 4k (GTT page size) for sane hw.
1500          */
1501         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1502             tiling_mode == I915_TILING_NONE)
1503                 return 4096;
1504
1505         /* Previous hardware however needs to be aligned to a power-of-two
1506          * tile height. The simplest method for determining this is to reuse
1507          * the power-of-tile object size.
1508          */
1509         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1510 }
1511
1512 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1513 {
1514         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1515         int ret;
1516
1517         if (obj->base.map_list.map)
1518                 return 0;
1519
1520         dev_priv->mm.shrinker_no_lock_stealing = true;
1521
1522         ret = drm_gem_create_mmap_offset(&obj->base);
1523         if (ret != -ENOSPC)
1524                 goto out;
1525
1526         /* Badly fragmented mmap space? The only way we can recover
1527          * space is by destroying unwanted objects. We can't randomly release
1528          * mmap_offsets as userspace expects them to be persistent for the
1529          * lifetime of the objects. The closest we can is to release the
1530          * offsets on purgeable objects by truncating it and marking it purged,
1531          * which prevents userspace from ever using that object again.
1532          */
1533         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1534         ret = drm_gem_create_mmap_offset(&obj->base);
1535         if (ret != -ENOSPC)
1536                 goto out;
1537
1538         i915_gem_shrink_all(dev_priv);
1539         ret = drm_gem_create_mmap_offset(&obj->base);
1540 out:
1541         dev_priv->mm.shrinker_no_lock_stealing = false;
1542
1543         return ret;
1544 }
1545
1546 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1547 {
1548         if (!obj->base.map_list.map)
1549                 return;
1550
1551         drm_gem_free_mmap_offset(&obj->base);
1552 }
1553
1554 int
1555 i915_gem_mmap_gtt(struct drm_file *file,
1556                   struct drm_device *dev,
1557                   uint32_t handle,
1558                   uint64_t *offset)
1559 {
1560         struct drm_i915_private *dev_priv = dev->dev_private;
1561         struct drm_i915_gem_object *obj;
1562         int ret;
1563
1564         ret = i915_mutex_lock_interruptible(dev);
1565         if (ret)
1566                 return ret;
1567
1568         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1569         if (&obj->base == NULL) {
1570                 ret = -ENOENT;
1571                 goto unlock;
1572         }
1573
1574         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1575                 ret = -E2BIG;
1576                 goto out;
1577         }
1578
1579         if (obj->madv != I915_MADV_WILLNEED) {
1580                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1581                 ret = -EINVAL;
1582                 goto out;
1583         }
1584
1585         ret = i915_gem_object_create_mmap_offset(obj);
1586         if (ret)
1587                 goto out;
1588
1589         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1590
1591 out:
1592         drm_gem_object_unreference(&obj->base);
1593 unlock:
1594         mutex_unlock(&dev->struct_mutex);
1595         return ret;
1596 }
1597
1598 /**
1599  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1600  * @dev: DRM device
1601  * @data: GTT mapping ioctl data
1602  * @file: GEM object info
1603  *
1604  * Simply returns the fake offset to userspace so it can mmap it.
1605  * The mmap call will end up in drm_gem_mmap(), which will set things
1606  * up so we can get faults in the handler above.
1607  *
1608  * The fault handler will take care of binding the object into the GTT
1609  * (since it may have been evicted to make room for something), allocating
1610  * a fence register, and mapping the appropriate aperture address into
1611  * userspace.
1612  */
1613 int
1614 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1615                         struct drm_file *file)
1616 {
1617         struct drm_i915_gem_mmap_gtt *args = data;
1618
1619         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1620 }
1621
1622 /* Immediately discard the backing storage */
1623 static void
1624 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1625 {
1626         struct inode *inode;
1627
1628         i915_gem_object_free_mmap_offset(obj);
1629
1630         if (obj->base.filp == NULL)
1631                 return;
1632
1633         /* Our goal here is to return as much of the memory as
1634          * is possible back to the system as we are called from OOM.
1635          * To do this we must instruct the shmfs to drop all of its
1636          * backing pages, *now*.
1637          */
1638         inode = obj->base.filp->f_path.dentry->d_inode;
1639         shmem_truncate_range(inode, 0, (loff_t)-1);
1640
1641         obj->madv = __I915_MADV_PURGED;
1642 }
1643
1644 static inline int
1645 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1646 {
1647         return obj->madv == I915_MADV_DONTNEED;
1648 }
1649
1650 static void
1651 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1652 {
1653         int page_count = obj->base.size / PAGE_SIZE;
1654         struct scatterlist *sg;
1655         int ret, i;
1656
1657         BUG_ON(obj->madv == __I915_MADV_PURGED);
1658
1659         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1660         if (ret) {
1661                 /* In the event of a disaster, abandon all caches and
1662                  * hope for the best.
1663                  */
1664                 WARN_ON(ret != -EIO);
1665                 i915_gem_clflush_object(obj);
1666                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1667         }
1668
1669         if (i915_gem_object_needs_bit17_swizzle(obj))
1670                 i915_gem_object_save_bit_17_swizzle(obj);
1671
1672         if (obj->madv == I915_MADV_DONTNEED)
1673                 obj->dirty = 0;
1674
1675         for_each_sg(obj->pages->sgl, sg, page_count, i) {
1676                 struct page *page = sg_page(sg);
1677
1678                 if (obj->dirty)
1679                         set_page_dirty(page);
1680
1681                 if (obj->madv == I915_MADV_WILLNEED)
1682                         mark_page_accessed(page);
1683
1684                 page_cache_release(page);
1685         }
1686         obj->dirty = 0;
1687
1688         sg_free_table(obj->pages);
1689         kfree(obj->pages);
1690 }
1691
1692 static int
1693 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1694 {
1695         const struct drm_i915_gem_object_ops *ops = obj->ops;
1696
1697         if (obj->pages == NULL)
1698                 return 0;
1699
1700         BUG_ON(obj->gtt_space);
1701
1702         if (obj->pages_pin_count)
1703                 return -EBUSY;
1704
1705         /* ->put_pages might need to allocate memory for the bit17 swizzle
1706          * array, hence protect them from being reaped by removing them from gtt
1707          * lists early. */
1708         list_del(&obj->gtt_list);
1709
1710         ops->put_pages(obj);
1711         obj->pages = NULL;
1712
1713         if (i915_gem_object_is_purgeable(obj))
1714                 i915_gem_object_truncate(obj);
1715
1716         return 0;
1717 }
1718
1719 static long
1720 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1721 {
1722         struct drm_i915_gem_object *obj, *next;
1723         long count = 0;
1724
1725         list_for_each_entry_safe(obj, next,
1726                                  &dev_priv->mm.unbound_list,
1727                                  gtt_list) {
1728                 if (i915_gem_object_is_purgeable(obj) &&
1729                     i915_gem_object_put_pages(obj) == 0) {
1730                         count += obj->base.size >> PAGE_SHIFT;
1731                         if (count >= target)
1732                                 return count;
1733                 }
1734         }
1735
1736         list_for_each_entry_safe(obj, next,
1737                                  &dev_priv->mm.inactive_list,
1738                                  mm_list) {
1739                 if (i915_gem_object_is_purgeable(obj) &&
1740                     i915_gem_object_unbind(obj) == 0 &&
1741                     i915_gem_object_put_pages(obj) == 0) {
1742                         count += obj->base.size >> PAGE_SHIFT;
1743                         if (count >= target)
1744                                 return count;
1745                 }
1746         }
1747
1748         return count;
1749 }
1750
1751 static void
1752 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1753 {
1754         struct drm_i915_gem_object *obj, *next;
1755
1756         i915_gem_evict_everything(dev_priv->dev);
1757
1758         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1759                 i915_gem_object_put_pages(obj);
1760 }
1761
1762 static int
1763 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1764 {
1765         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1766         int page_count, i;
1767         struct address_space *mapping;
1768         struct sg_table *st;
1769         struct scatterlist *sg;
1770         struct page *page;
1771         gfp_t gfp;
1772
1773         /* Assert that the object is not currently in any GPU domain. As it
1774          * wasn't in the GTT, there shouldn't be any way it could have been in
1775          * a GPU cache
1776          */
1777         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1778         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1779
1780         st = kmalloc(sizeof(*st), GFP_KERNEL);
1781         if (st == NULL)
1782                 return -ENOMEM;
1783
1784         page_count = obj->base.size / PAGE_SIZE;
1785         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1786                 sg_free_table(st);
1787                 kfree(st);
1788                 return -ENOMEM;
1789         }
1790
1791         /* Get the list of pages out of our struct file.  They'll be pinned
1792          * at this point until we release them.
1793          *
1794          * Fail silently without starting the shrinker
1795          */
1796         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1797         gfp = mapping_gfp_mask(mapping);
1798         gfp |= __GFP_NORETRY | __GFP_NOWARN;
1799         gfp &= ~(__GFP_IO | __GFP_WAIT);
1800         for_each_sg(st->sgl, sg, page_count, i) {
1801                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1802                 if (IS_ERR(page)) {
1803                         i915_gem_purge(dev_priv, page_count);
1804                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1805                 }
1806                 if (IS_ERR(page)) {
1807                         /* We've tried hard to allocate the memory by reaping
1808                          * our own buffer, now let the real VM do its job and
1809                          * go down in flames if truly OOM.
1810                          */
1811                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1812                         gfp |= __GFP_IO | __GFP_WAIT;
1813
1814                         i915_gem_shrink_all(dev_priv);
1815                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1816                         if (IS_ERR(page))
1817                                 goto err_pages;
1818
1819                         gfp |= __GFP_NORETRY | __GFP_NOWARN;
1820                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1821                 }
1822
1823                 sg_set_page(sg, page, PAGE_SIZE, 0);
1824         }
1825
1826         obj->pages = st;
1827
1828         if (i915_gem_object_needs_bit17_swizzle(obj))
1829                 i915_gem_object_do_bit_17_swizzle(obj);
1830
1831         return 0;
1832
1833 err_pages:
1834         for_each_sg(st->sgl, sg, i, page_count)
1835                 page_cache_release(sg_page(sg));
1836         sg_free_table(st);
1837         kfree(st);
1838         return PTR_ERR(page);
1839 }
1840
1841 /* Ensure that the associated pages are gathered from the backing storage
1842  * and pinned into our object. i915_gem_object_get_pages() may be called
1843  * multiple times before they are released by a single call to
1844  * i915_gem_object_put_pages() - once the pages are no longer referenced
1845  * either as a result of memory pressure (reaping pages under the shrinker)
1846  * or as the object is itself released.
1847  */
1848 int
1849 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1850 {
1851         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1852         const struct drm_i915_gem_object_ops *ops = obj->ops;
1853         int ret;
1854
1855         if (obj->pages)
1856                 return 0;
1857
1858         BUG_ON(obj->pages_pin_count);
1859
1860         ret = ops->get_pages(obj);
1861         if (ret)
1862                 return ret;
1863
1864         list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1865         return 0;
1866 }
1867
1868 void
1869 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1870                                struct intel_ring_buffer *ring)
1871 {
1872         struct drm_device *dev = obj->base.dev;
1873         struct drm_i915_private *dev_priv = dev->dev_private;
1874         u32 seqno = intel_ring_get_seqno(ring);
1875
1876         BUG_ON(ring == NULL);
1877         obj->ring = ring;
1878
1879         /* Add a reference if we're newly entering the active list. */
1880         if (!obj->active) {
1881                 drm_gem_object_reference(&obj->base);
1882                 obj->active = 1;
1883         }
1884
1885         /* Move from whatever list we were on to the tail of execution. */
1886         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1887         list_move_tail(&obj->ring_list, &ring->active_list);
1888
1889         obj->last_read_seqno = seqno;
1890
1891         if (obj->fenced_gpu_access) {
1892                 obj->last_fenced_seqno = seqno;
1893
1894                 /* Bump MRU to take account of the delayed flush */
1895                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1896                         struct drm_i915_fence_reg *reg;
1897
1898                         reg = &dev_priv->fence_regs[obj->fence_reg];
1899                         list_move_tail(&reg->lru_list,
1900                                        &dev_priv->mm.fence_list);
1901                 }
1902         }
1903 }
1904
1905 static void
1906 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1907 {
1908         struct drm_device *dev = obj->base.dev;
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910
1911         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1912         BUG_ON(!obj->active);
1913
1914         if (obj->pin_count) /* are we a framebuffer? */
1915                 intel_mark_fb_idle(obj);
1916
1917         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1918
1919         list_del_init(&obj->ring_list);
1920         obj->ring = NULL;
1921
1922         obj->last_read_seqno = 0;
1923         obj->last_write_seqno = 0;
1924         obj->base.write_domain = 0;
1925
1926         obj->last_fenced_seqno = 0;
1927         obj->fenced_gpu_access = false;
1928
1929         obj->active = 0;
1930         drm_gem_object_unreference(&obj->base);
1931
1932         WARN_ON(i915_verify_lists(dev));
1933 }
1934
1935 static int
1936 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1937 {
1938         struct drm_i915_private *dev_priv = dev->dev_private;
1939         struct intel_ring_buffer *ring;
1940         int ret, i, j;
1941
1942         /* The hardware uses various monotonic 32-bit counters, if we
1943          * detect that they will wraparound we need to idle the GPU
1944          * and reset those counters.
1945          */
1946         ret = 0;
1947         for_each_ring(ring, dev_priv, i) {
1948                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1949                         ret |= ring->sync_seqno[j] != 0;
1950         }
1951         if (ret == 0)
1952                 return ret;
1953
1954         ret = i915_gpu_idle(dev);
1955         if (ret)
1956                 return ret;
1957
1958         i915_gem_retire_requests(dev);
1959         for_each_ring(ring, dev_priv, i) {
1960                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1961                         ring->sync_seqno[j] = 0;
1962         }
1963
1964         return 0;
1965 }
1966
1967 int
1968 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1969 {
1970         struct drm_i915_private *dev_priv = dev->dev_private;
1971
1972         /* reserve 0 for non-seqno */
1973         if (dev_priv->next_seqno == 0) {
1974                 int ret = i915_gem_handle_seqno_wrap(dev);
1975                 if (ret)
1976                         return ret;
1977
1978                 dev_priv->next_seqno = 1;
1979         }
1980
1981         *seqno = dev_priv->next_seqno++;
1982         return 0;
1983 }
1984
1985 int
1986 i915_add_request(struct intel_ring_buffer *ring,
1987                  struct drm_file *file,
1988                  u32 *out_seqno)
1989 {
1990         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1991         struct drm_i915_gem_request *request;
1992         u32 request_ring_position;
1993         int was_empty;
1994         int ret;
1995
1996         /*
1997          * Emit any outstanding flushes - execbuf can fail to emit the flush
1998          * after having emitted the batchbuffer command. Hence we need to fix
1999          * things up similar to emitting the lazy request. The difference here
2000          * is that the flush _must_ happen before the next request, no matter
2001          * what.
2002          */
2003         ret = intel_ring_flush_all_caches(ring);
2004         if (ret)
2005                 return ret;
2006
2007         request = kmalloc(sizeof(*request), GFP_KERNEL);
2008         if (request == NULL)
2009                 return -ENOMEM;
2010
2011
2012         /* Record the position of the start of the request so that
2013          * should we detect the updated seqno part-way through the
2014          * GPU processing the request, we never over-estimate the
2015          * position of the head.
2016          */
2017         request_ring_position = intel_ring_get_tail(ring);
2018
2019         ret = ring->add_request(ring);
2020         if (ret) {
2021                 kfree(request);
2022                 return ret;
2023         }
2024
2025         request->seqno = intel_ring_get_seqno(ring);
2026         request->ring = ring;
2027         request->tail = request_ring_position;
2028         request->emitted_jiffies = jiffies;
2029         was_empty = list_empty(&ring->request_list);
2030         list_add_tail(&request->list, &ring->request_list);
2031         request->file_priv = NULL;
2032
2033         if (file) {
2034                 struct drm_i915_file_private *file_priv = file->driver_priv;
2035
2036                 spin_lock(&file_priv->mm.lock);
2037                 request->file_priv = file_priv;
2038                 list_add_tail(&request->client_list,
2039                               &file_priv->mm.request_list);
2040                 spin_unlock(&file_priv->mm.lock);
2041         }
2042
2043         trace_i915_gem_request_add(ring, request->seqno);
2044         ring->outstanding_lazy_request = 0;
2045
2046         if (!dev_priv->mm.suspended) {
2047                 if (i915_enable_hangcheck) {
2048                         mod_timer(&dev_priv->hangcheck_timer,
2049                                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2050                 }
2051                 if (was_empty) {
2052                         queue_delayed_work(dev_priv->wq,
2053                                            &dev_priv->mm.retire_work,
2054                                            round_jiffies_up_relative(HZ));
2055                         intel_mark_busy(dev_priv->dev);
2056                 }
2057         }
2058
2059         if (out_seqno)
2060                 *out_seqno = request->seqno;
2061         return 0;
2062 }
2063
2064 static inline void
2065 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2066 {
2067         struct drm_i915_file_private *file_priv = request->file_priv;
2068
2069         if (!file_priv)
2070                 return;
2071
2072         spin_lock(&file_priv->mm.lock);
2073         if (request->file_priv) {
2074                 list_del(&request->client_list);
2075                 request->file_priv = NULL;
2076         }
2077         spin_unlock(&file_priv->mm.lock);
2078 }
2079
2080 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2081                                       struct intel_ring_buffer *ring)
2082 {
2083         while (!list_empty(&ring->request_list)) {
2084                 struct drm_i915_gem_request *request;
2085
2086                 request = list_first_entry(&ring->request_list,
2087                                            struct drm_i915_gem_request,
2088                                            list);
2089
2090                 list_del(&request->list);
2091                 i915_gem_request_remove_from_client(request);
2092                 kfree(request);
2093         }
2094
2095         while (!list_empty(&ring->active_list)) {
2096                 struct drm_i915_gem_object *obj;
2097
2098                 obj = list_first_entry(&ring->active_list,
2099                                        struct drm_i915_gem_object,
2100                                        ring_list);
2101
2102                 i915_gem_object_move_to_inactive(obj);
2103         }
2104 }
2105
2106 static void i915_gem_reset_fences(struct drm_device *dev)
2107 {
2108         struct drm_i915_private *dev_priv = dev->dev_private;
2109         int i;
2110
2111         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2112                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2113
2114                 i915_gem_write_fence(dev, i, NULL);
2115
2116                 if (reg->obj)
2117                         i915_gem_object_fence_lost(reg->obj);
2118
2119                 reg->pin_count = 0;
2120                 reg->obj = NULL;
2121                 INIT_LIST_HEAD(&reg->lru_list);
2122         }
2123
2124         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2125 }
2126
2127 void i915_gem_reset(struct drm_device *dev)
2128 {
2129         struct drm_i915_private *dev_priv = dev->dev_private;
2130         struct drm_i915_gem_object *obj;
2131         struct intel_ring_buffer *ring;
2132         int i;
2133
2134         for_each_ring(ring, dev_priv, i)
2135                 i915_gem_reset_ring_lists(dev_priv, ring);
2136
2137         /* Move everything out of the GPU domains to ensure we do any
2138          * necessary invalidation upon reuse.
2139          */
2140         list_for_each_entry(obj,
2141                             &dev_priv->mm.inactive_list,
2142                             mm_list)
2143         {
2144                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2145         }
2146
2147         /* The fence registers are invalidated so clear them out */
2148         i915_gem_reset_fences(dev);
2149 }
2150
2151 /**
2152  * This function clears the request list as sequence numbers are passed.
2153  */
2154 void
2155 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2156 {
2157         uint32_t seqno;
2158
2159         if (list_empty(&ring->request_list))
2160                 return;
2161
2162         WARN_ON(i915_verify_lists(ring->dev));
2163
2164         seqno = ring->get_seqno(ring, true);
2165
2166         while (!list_empty(&ring->request_list)) {
2167                 struct drm_i915_gem_request *request;
2168
2169                 request = list_first_entry(&ring->request_list,
2170                                            struct drm_i915_gem_request,
2171                                            list);
2172
2173                 if (!i915_seqno_passed(seqno, request->seqno))
2174                         break;
2175
2176                 trace_i915_gem_request_retire(ring, request->seqno);
2177                 /* We know the GPU must have read the request to have
2178                  * sent us the seqno + interrupt, so use the position
2179                  * of tail of the request to update the last known position
2180                  * of the GPU head.
2181                  */
2182                 ring->last_retired_head = request->tail;
2183
2184                 list_del(&request->list);
2185                 i915_gem_request_remove_from_client(request);
2186                 kfree(request);
2187         }
2188
2189         /* Move any buffers on the active list that are no longer referenced
2190          * by the ringbuffer to the flushing/inactive lists as appropriate.
2191          */
2192         while (!list_empty(&ring->active_list)) {
2193                 struct drm_i915_gem_object *obj;
2194
2195                 obj = list_first_entry(&ring->active_list,
2196                                       struct drm_i915_gem_object,
2197                                       ring_list);
2198
2199                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2200                         break;
2201
2202                 i915_gem_object_move_to_inactive(obj);
2203         }
2204
2205         if (unlikely(ring->trace_irq_seqno &&
2206                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2207                 ring->irq_put(ring);
2208                 ring->trace_irq_seqno = 0;
2209         }
2210
2211         WARN_ON(i915_verify_lists(ring->dev));
2212 }
2213
2214 void
2215 i915_gem_retire_requests(struct drm_device *dev)
2216 {
2217         drm_i915_private_t *dev_priv = dev->dev_private;
2218         struct intel_ring_buffer *ring;
2219         int i;
2220
2221         for_each_ring(ring, dev_priv, i)
2222                 i915_gem_retire_requests_ring(ring);
2223 }
2224
2225 static void
2226 i915_gem_retire_work_handler(struct work_struct *work)
2227 {
2228         drm_i915_private_t *dev_priv;
2229         struct drm_device *dev;
2230         struct intel_ring_buffer *ring;
2231         bool idle;
2232         int i;
2233
2234         dev_priv = container_of(work, drm_i915_private_t,
2235                                 mm.retire_work.work);
2236         dev = dev_priv->dev;
2237
2238         /* Come back later if the device is busy... */
2239         if (!mutex_trylock(&dev->struct_mutex)) {
2240                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2241                                    round_jiffies_up_relative(HZ));
2242                 return;
2243         }
2244
2245         i915_gem_retire_requests(dev);
2246
2247         /* Send a periodic flush down the ring so we don't hold onto GEM
2248          * objects indefinitely.
2249          */
2250         idle = true;
2251         for_each_ring(ring, dev_priv, i) {
2252                 if (ring->gpu_caches_dirty)
2253                         i915_add_request(ring, NULL, NULL);
2254
2255                 idle &= list_empty(&ring->request_list);
2256         }
2257
2258         if (!dev_priv->mm.suspended && !idle)
2259                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2260                                    round_jiffies_up_relative(HZ));
2261         if (idle)
2262                 intel_mark_idle(dev);
2263
2264         mutex_unlock(&dev->struct_mutex);
2265 }
2266
2267 /**
2268  * Ensures that an object will eventually get non-busy by flushing any required
2269  * write domains, emitting any outstanding lazy request and retiring and
2270  * completed requests.
2271  */
2272 static int
2273 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2274 {
2275         int ret;
2276
2277         if (obj->active) {
2278                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2279                 if (ret)
2280                         return ret;
2281
2282                 i915_gem_retire_requests_ring(obj->ring);
2283         }
2284
2285         return 0;
2286 }
2287
2288 /**
2289  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2290  * @DRM_IOCTL_ARGS: standard ioctl arguments
2291  *
2292  * Returns 0 if successful, else an error is returned with the remaining time in
2293  * the timeout parameter.
2294  *  -ETIME: object is still busy after timeout
2295  *  -ERESTARTSYS: signal interrupted the wait
2296  *  -ENONENT: object doesn't exist
2297  * Also possible, but rare:
2298  *  -EAGAIN: GPU wedged
2299  *  -ENOMEM: damn
2300  *  -ENODEV: Internal IRQ fail
2301  *  -E?: The add request failed
2302  *
2303  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2304  * non-zero timeout parameter the wait ioctl will wait for the given number of
2305  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2306  * without holding struct_mutex the object may become re-busied before this
2307  * function completes. A similar but shorter * race condition exists in the busy
2308  * ioctl
2309  */
2310 int
2311 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2312 {
2313         struct drm_i915_gem_wait *args = data;
2314         struct drm_i915_gem_object *obj;
2315         struct intel_ring_buffer *ring = NULL;
2316         struct timespec timeout_stack, *timeout = NULL;
2317         u32 seqno = 0;
2318         int ret = 0;
2319
2320         if (args->timeout_ns >= 0) {
2321                 timeout_stack = ns_to_timespec(args->timeout_ns);
2322                 timeout = &timeout_stack;
2323         }
2324
2325         ret = i915_mutex_lock_interruptible(dev);
2326         if (ret)
2327                 return ret;
2328
2329         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2330         if (&obj->base == NULL) {
2331                 mutex_unlock(&dev->struct_mutex);
2332                 return -ENOENT;
2333         }
2334
2335         /* Need to make sure the object gets inactive eventually. */
2336         ret = i915_gem_object_flush_active(obj);
2337         if (ret)
2338                 goto out;
2339
2340         if (obj->active) {
2341                 seqno = obj->last_read_seqno;
2342                 ring = obj->ring;
2343         }
2344
2345         if (seqno == 0)
2346                  goto out;
2347
2348         /* Do this after OLR check to make sure we make forward progress polling
2349          * on this IOCTL with a 0 timeout (like busy ioctl)
2350          */
2351         if (!args->timeout_ns) {
2352                 ret = -ETIME;
2353                 goto out;
2354         }
2355
2356         drm_gem_object_unreference(&obj->base);
2357         mutex_unlock(&dev->struct_mutex);
2358
2359         ret = __wait_seqno(ring, seqno, true, timeout);
2360         if (timeout) {
2361                 WARN_ON(!timespec_valid(timeout));
2362                 args->timeout_ns = timespec_to_ns(timeout);
2363         }
2364         return ret;
2365
2366 out:
2367         drm_gem_object_unreference(&obj->base);
2368         mutex_unlock(&dev->struct_mutex);
2369         return ret;
2370 }
2371
2372 /**
2373  * i915_gem_object_sync - sync an object to a ring.
2374  *
2375  * @obj: object which may be in use on another ring.
2376  * @to: ring we wish to use the object on. May be NULL.
2377  *
2378  * This code is meant to abstract object synchronization with the GPU.
2379  * Calling with NULL implies synchronizing the object with the CPU
2380  * rather than a particular GPU ring.
2381  *
2382  * Returns 0 if successful, else propagates up the lower layer error.
2383  */
2384 int
2385 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2386                      struct intel_ring_buffer *to)
2387 {
2388         struct intel_ring_buffer *from = obj->ring;
2389         u32 seqno;
2390         int ret, idx;
2391
2392         if (from == NULL || to == from)
2393                 return 0;
2394
2395         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2396                 return i915_gem_object_wait_rendering(obj, false);
2397
2398         idx = intel_ring_sync_index(from, to);
2399
2400         seqno = obj->last_read_seqno;
2401         if (seqno <= from->sync_seqno[idx])
2402                 return 0;
2403
2404         ret = i915_gem_check_olr(obj->ring, seqno);
2405         if (ret)
2406                 return ret;
2407
2408         ret = to->sync_to(to, from, seqno);
2409         if (!ret)
2410                 /* We use last_read_seqno because sync_to()
2411                  * might have just caused seqno wrap under
2412                  * the radar.
2413                  */
2414                 from->sync_seqno[idx] = obj->last_read_seqno;
2415
2416         return ret;
2417 }
2418
2419 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2420 {
2421         u32 old_write_domain, old_read_domains;
2422
2423         /* Act a barrier for all accesses through the GTT */
2424         mb();
2425
2426         /* Force a pagefault for domain tracking on next user access */
2427         i915_gem_release_mmap(obj);
2428
2429         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2430                 return;
2431
2432         old_read_domains = obj->base.read_domains;
2433         old_write_domain = obj->base.write_domain;
2434
2435         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2436         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2437
2438         trace_i915_gem_object_change_domain(obj,
2439                                             old_read_domains,
2440                                             old_write_domain);
2441 }
2442
2443 /**
2444  * Unbinds an object from the GTT aperture.
2445  */
2446 int
2447 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2448 {
2449         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2450         int ret = 0;
2451
2452         if (obj->gtt_space == NULL)
2453                 return 0;
2454
2455         if (obj->pin_count)
2456                 return -EBUSY;
2457
2458         BUG_ON(obj->pages == NULL);
2459
2460         ret = i915_gem_object_finish_gpu(obj);
2461         if (ret)
2462                 return ret;
2463         /* Continue on if we fail due to EIO, the GPU is hung so we
2464          * should be safe and we need to cleanup or else we might
2465          * cause memory corruption through use-after-free.
2466          */
2467
2468         i915_gem_object_finish_gtt(obj);
2469
2470         /* release the fence reg _after_ flushing */
2471         ret = i915_gem_object_put_fence(obj);
2472         if (ret)
2473                 return ret;
2474
2475         trace_i915_gem_object_unbind(obj);
2476
2477         if (obj->has_global_gtt_mapping)
2478                 i915_gem_gtt_unbind_object(obj);
2479         if (obj->has_aliasing_ppgtt_mapping) {
2480                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2481                 obj->has_aliasing_ppgtt_mapping = 0;
2482         }
2483         i915_gem_gtt_finish_object(obj);
2484
2485         list_del(&obj->mm_list);
2486         list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2487         /* Avoid an unnecessary call to unbind on rebind. */
2488         obj->map_and_fenceable = true;
2489
2490         drm_mm_put_block(obj->gtt_space);
2491         obj->gtt_space = NULL;
2492         obj->gtt_offset = 0;
2493
2494         return 0;
2495 }
2496
2497 int i915_gpu_idle(struct drm_device *dev)
2498 {
2499         drm_i915_private_t *dev_priv = dev->dev_private;
2500         struct intel_ring_buffer *ring;
2501         int ret, i;
2502
2503         /* Flush everything onto the inactive list. */
2504         for_each_ring(ring, dev_priv, i) {
2505                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2506                 if (ret)
2507                         return ret;
2508
2509                 ret = intel_ring_idle(ring);
2510                 if (ret)
2511                         return ret;
2512         }
2513
2514         return 0;
2515 }
2516
2517 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2518                                         struct drm_i915_gem_object *obj)
2519 {
2520         drm_i915_private_t *dev_priv = dev->dev_private;
2521         uint64_t val;
2522
2523         if (obj) {
2524                 u32 size = obj->gtt_space->size;
2525
2526                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2527                                  0xfffff000) << 32;
2528                 val |= obj->gtt_offset & 0xfffff000;
2529                 val |= (uint64_t)((obj->stride / 128) - 1) <<
2530                         SANDYBRIDGE_FENCE_PITCH_SHIFT;
2531
2532                 if (obj->tiling_mode == I915_TILING_Y)
2533                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2534                 val |= I965_FENCE_REG_VALID;
2535         } else
2536                 val = 0;
2537
2538         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2539         POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2540 }
2541
2542 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2543                                  struct drm_i915_gem_object *obj)
2544 {
2545         drm_i915_private_t *dev_priv = dev->dev_private;
2546         uint64_t val;
2547
2548         if (obj) {
2549                 u32 size = obj->gtt_space->size;
2550
2551                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2552                                  0xfffff000) << 32;
2553                 val |= obj->gtt_offset & 0xfffff000;
2554                 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2555                 if (obj->tiling_mode == I915_TILING_Y)
2556                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2557                 val |= I965_FENCE_REG_VALID;
2558         } else
2559                 val = 0;
2560
2561         I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2562         POSTING_READ(FENCE_REG_965_0 + reg * 8);
2563 }
2564
2565 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2566                                  struct drm_i915_gem_object *obj)
2567 {
2568         drm_i915_private_t *dev_priv = dev->dev_private;
2569         u32 val;
2570
2571         if (obj) {
2572                 u32 size = obj->gtt_space->size;
2573                 int pitch_val;
2574                 int tile_width;
2575
2576                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2577                      (size & -size) != size ||
2578                      (obj->gtt_offset & (size - 1)),
2579                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2580                      obj->gtt_offset, obj->map_and_fenceable, size);
2581
2582                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2583                         tile_width = 128;
2584                 else
2585                         tile_width = 512;
2586
2587                 /* Note: pitch better be a power of two tile widths */
2588                 pitch_val = obj->stride / tile_width;
2589                 pitch_val = ffs(pitch_val) - 1;
2590
2591                 val = obj->gtt_offset;
2592                 if (obj->tiling_mode == I915_TILING_Y)
2593                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2594                 val |= I915_FENCE_SIZE_BITS(size);
2595                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2596                 val |= I830_FENCE_REG_VALID;
2597         } else
2598                 val = 0;
2599
2600         if (reg < 8)
2601                 reg = FENCE_REG_830_0 + reg * 4;
2602         else
2603                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2604
2605         I915_WRITE(reg, val);
2606         POSTING_READ(reg);
2607 }
2608
2609 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2610                                 struct drm_i915_gem_object *obj)
2611 {
2612         drm_i915_private_t *dev_priv = dev->dev_private;
2613         uint32_t val;
2614
2615         if (obj) {
2616                 u32 size = obj->gtt_space->size;
2617                 uint32_t pitch_val;
2618
2619                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2620                      (size & -size) != size ||
2621                      (obj->gtt_offset & (size - 1)),
2622                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2623                      obj->gtt_offset, size);
2624
2625                 pitch_val = obj->stride / 128;
2626                 pitch_val = ffs(pitch_val) - 1;
2627
2628                 val = obj->gtt_offset;
2629                 if (obj->tiling_mode == I915_TILING_Y)
2630                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2631                 val |= I830_FENCE_SIZE_BITS(size);
2632                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2633                 val |= I830_FENCE_REG_VALID;
2634         } else
2635                 val = 0;
2636
2637         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2638         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2639 }
2640
2641 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2642                                  struct drm_i915_gem_object *obj)
2643 {
2644         switch (INTEL_INFO(dev)->gen) {
2645         case 7:
2646         case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2647         case 5:
2648         case 4: i965_write_fence_reg(dev, reg, obj); break;
2649         case 3: i915_write_fence_reg(dev, reg, obj); break;
2650         case 2: i830_write_fence_reg(dev, reg, obj); break;
2651         default: break;
2652         }
2653 }
2654
2655 static inline int fence_number(struct drm_i915_private *dev_priv,
2656                                struct drm_i915_fence_reg *fence)
2657 {
2658         return fence - dev_priv->fence_regs;
2659 }
2660
2661 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2662                                          struct drm_i915_fence_reg *fence,
2663                                          bool enable)
2664 {
2665         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2666         int reg = fence_number(dev_priv, fence);
2667
2668         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2669
2670         if (enable) {
2671                 obj->fence_reg = reg;
2672                 fence->obj = obj;
2673                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2674         } else {
2675                 obj->fence_reg = I915_FENCE_REG_NONE;
2676                 fence->obj = NULL;
2677                 list_del_init(&fence->lru_list);
2678         }
2679 }
2680
2681 static int
2682 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2683 {
2684         if (obj->last_fenced_seqno) {
2685                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2686                 if (ret)
2687                         return ret;
2688
2689                 obj->last_fenced_seqno = 0;
2690         }
2691
2692         /* Ensure that all CPU reads are completed before installing a fence
2693          * and all writes before removing the fence.
2694          */
2695         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2696                 mb();
2697
2698         obj->fenced_gpu_access = false;
2699         return 0;
2700 }
2701
2702 int
2703 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2704 {
2705         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2706         int ret;
2707
2708         ret = i915_gem_object_flush_fence(obj);
2709         if (ret)
2710                 return ret;
2711
2712         if (obj->fence_reg == I915_FENCE_REG_NONE)
2713                 return 0;
2714
2715         i915_gem_object_update_fence(obj,
2716                                      &dev_priv->fence_regs[obj->fence_reg],
2717                                      false);
2718         i915_gem_object_fence_lost(obj);
2719
2720         return 0;
2721 }
2722
2723 static struct drm_i915_fence_reg *
2724 i915_find_fence_reg(struct drm_device *dev)
2725 {
2726         struct drm_i915_private *dev_priv = dev->dev_private;
2727         struct drm_i915_fence_reg *reg, *avail;
2728         int i;
2729
2730         /* First try to find a free reg */
2731         avail = NULL;
2732         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2733                 reg = &dev_priv->fence_regs[i];
2734                 if (!reg->obj)
2735                         return reg;
2736
2737                 if (!reg->pin_count)
2738                         avail = reg;
2739         }
2740
2741         if (avail == NULL)
2742                 return NULL;
2743
2744         /* None available, try to steal one or wait for a user to finish */
2745         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2746                 if (reg->pin_count)
2747                         continue;
2748
2749                 return reg;
2750         }
2751
2752         return NULL;
2753 }
2754
2755 /**
2756  * i915_gem_object_get_fence - set up fencing for an object
2757  * @obj: object to map through a fence reg
2758  *
2759  * When mapping objects through the GTT, userspace wants to be able to write
2760  * to them without having to worry about swizzling if the object is tiled.
2761  * This function walks the fence regs looking for a free one for @obj,
2762  * stealing one if it can't find any.
2763  *
2764  * It then sets up the reg based on the object's properties: address, pitch
2765  * and tiling format.
2766  *
2767  * For an untiled surface, this removes any existing fence.
2768  */
2769 int
2770 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2771 {
2772         struct drm_device *dev = obj->base.dev;
2773         struct drm_i915_private *dev_priv = dev->dev_private;
2774         bool enable = obj->tiling_mode != I915_TILING_NONE;
2775         struct drm_i915_fence_reg *reg;
2776         int ret;
2777
2778         /* Have we updated the tiling parameters upon the object and so
2779          * will need to serialise the write to the associated fence register?
2780          */
2781         if (obj->fence_dirty) {
2782                 ret = i915_gem_object_flush_fence(obj);
2783                 if (ret)
2784                         return ret;
2785         }
2786
2787         /* Just update our place in the LRU if our fence is getting reused. */
2788         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2789                 reg = &dev_priv->fence_regs[obj->fence_reg];
2790                 if (!obj->fence_dirty) {
2791                         list_move_tail(&reg->lru_list,
2792                                        &dev_priv->mm.fence_list);
2793                         return 0;
2794                 }
2795         } else if (enable) {
2796                 reg = i915_find_fence_reg(dev);
2797                 if (reg == NULL)
2798                         return -EDEADLK;
2799
2800                 if (reg->obj) {
2801                         struct drm_i915_gem_object *old = reg->obj;
2802
2803                         ret = i915_gem_object_flush_fence(old);
2804                         if (ret)
2805                                 return ret;
2806
2807                         i915_gem_object_fence_lost(old);
2808                 }
2809         } else
2810                 return 0;
2811
2812         i915_gem_object_update_fence(obj, reg, enable);
2813         obj->fence_dirty = false;
2814
2815         return 0;
2816 }
2817
2818 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2819                                      struct drm_mm_node *gtt_space,
2820                                      unsigned long cache_level)
2821 {
2822         struct drm_mm_node *other;
2823
2824         /* On non-LLC machines we have to be careful when putting differing
2825          * types of snoopable memory together to avoid the prefetcher
2826          * crossing memory domains and dieing.
2827          */
2828         if (HAS_LLC(dev))
2829                 return true;
2830
2831         if (gtt_space == NULL)
2832                 return true;
2833
2834         if (list_empty(&gtt_space->node_list))
2835                 return true;
2836
2837         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2838         if (other->allocated && !other->hole_follows && other->color != cache_level)
2839                 return false;
2840
2841         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2842         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2843                 return false;
2844
2845         return true;
2846 }
2847
2848 static void i915_gem_verify_gtt(struct drm_device *dev)
2849 {
2850 #if WATCH_GTT
2851         struct drm_i915_private *dev_priv = dev->dev_private;
2852         struct drm_i915_gem_object *obj;
2853         int err = 0;
2854
2855         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2856                 if (obj->gtt_space == NULL) {
2857                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
2858                         err++;
2859                         continue;
2860                 }
2861
2862                 if (obj->cache_level != obj->gtt_space->color) {
2863                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2864                                obj->gtt_space->start,
2865                                obj->gtt_space->start + obj->gtt_space->size,
2866                                obj->cache_level,
2867                                obj->gtt_space->color);
2868                         err++;
2869                         continue;
2870                 }
2871
2872                 if (!i915_gem_valid_gtt_space(dev,
2873                                               obj->gtt_space,
2874                                               obj->cache_level)) {
2875                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2876                                obj->gtt_space->start,
2877                                obj->gtt_space->start + obj->gtt_space->size,
2878                                obj->cache_level);
2879                         err++;
2880                         continue;
2881                 }
2882         }
2883
2884         WARN_ON(err);
2885 #endif
2886 }
2887
2888 /**
2889  * Finds free space in the GTT aperture and binds the object there.
2890  */
2891 static int
2892 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2893                             unsigned alignment,
2894                             bool map_and_fenceable,
2895                             bool nonblocking)
2896 {
2897         struct drm_device *dev = obj->base.dev;
2898         drm_i915_private_t *dev_priv = dev->dev_private;
2899         struct drm_mm_node *node;
2900         u32 size, fence_size, fence_alignment, unfenced_alignment;
2901         bool mappable, fenceable;
2902         int ret;
2903
2904         if (obj->madv != I915_MADV_WILLNEED) {
2905                 DRM_ERROR("Attempting to bind a purgeable object\n");
2906                 return -EINVAL;
2907         }
2908
2909         fence_size = i915_gem_get_gtt_size(dev,
2910                                            obj->base.size,
2911                                            obj->tiling_mode);
2912         fence_alignment = i915_gem_get_gtt_alignment(dev,
2913                                                      obj->base.size,
2914                                                      obj->tiling_mode);
2915         unfenced_alignment =
2916                 i915_gem_get_unfenced_gtt_alignment(dev,
2917                                                     obj->base.size,
2918                                                     obj->tiling_mode);
2919
2920         if (alignment == 0)
2921                 alignment = map_and_fenceable ? fence_alignment :
2922                                                 unfenced_alignment;
2923         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2924                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2925                 return -EINVAL;
2926         }
2927
2928         size = map_and_fenceable ? fence_size : obj->base.size;
2929
2930         /* If the object is bigger than the entire aperture, reject it early
2931          * before evicting everything in a vain attempt to find space.
2932          */
2933         if (obj->base.size >
2934             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2935                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2936                 return -E2BIG;
2937         }
2938
2939         ret = i915_gem_object_get_pages(obj);
2940         if (ret)
2941                 return ret;
2942
2943         i915_gem_object_pin_pages(obj);
2944
2945         node = kzalloc(sizeof(*node), GFP_KERNEL);
2946         if (node == NULL) {
2947                 i915_gem_object_unpin_pages(obj);
2948                 return -ENOMEM;
2949         }
2950
2951  search_free:
2952         if (map_and_fenceable)
2953                 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
2954                                                           size, alignment, obj->cache_level,
2955                                                           0, dev_priv->mm.gtt_mappable_end);
2956         else
2957                 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
2958                                                  size, alignment, obj->cache_level);
2959         if (ret) {
2960                 ret = i915_gem_evict_something(dev, size, alignment,
2961                                                obj->cache_level,
2962                                                map_and_fenceable,
2963                                                nonblocking);
2964                 if (ret == 0)
2965                         goto search_free;
2966
2967                 i915_gem_object_unpin_pages(obj);
2968                 kfree(node);
2969                 return ret;
2970         }
2971         if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
2972                 i915_gem_object_unpin_pages(obj);
2973                 drm_mm_put_block(node);
2974                 return -EINVAL;
2975         }
2976
2977         ret = i915_gem_gtt_prepare_object(obj);
2978         if (ret) {
2979                 i915_gem_object_unpin_pages(obj);
2980                 drm_mm_put_block(node);
2981                 return ret;
2982         }
2983
2984         list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2985         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2986
2987         obj->gtt_space = node;
2988         obj->gtt_offset = node->start;
2989
2990         fenceable =
2991                 node->size == fence_size &&
2992                 (node->start & (fence_alignment - 1)) == 0;
2993
2994         mappable =
2995                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2996
2997         obj->map_and_fenceable = mappable && fenceable;
2998
2999         i915_gem_object_unpin_pages(obj);
3000         trace_i915_gem_object_bind(obj, map_and_fenceable);
3001         i915_gem_verify_gtt(dev);
3002         return 0;
3003 }
3004
3005 void
3006 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3007 {
3008         /* If we don't have a page list set up, then we're not pinned
3009          * to GPU, and we can ignore the cache flush because it'll happen
3010          * again at bind time.
3011          */
3012         if (obj->pages == NULL)
3013                 return;
3014
3015         /* If the GPU is snooping the contents of the CPU cache,
3016          * we do not need to manually clear the CPU cache lines.  However,
3017          * the caches are only snooped when the render cache is
3018          * flushed/invalidated.  As we always have to emit invalidations
3019          * and flushes when moving into and out of the RENDER domain, correct
3020          * snooping behaviour occurs naturally as the result of our domain
3021          * tracking.
3022          */
3023         if (obj->cache_level != I915_CACHE_NONE)
3024                 return;
3025
3026         trace_i915_gem_object_clflush(obj);
3027
3028         drm_clflush_sg(obj->pages);
3029 }
3030
3031 /** Flushes the GTT write domain for the object if it's dirty. */
3032 static void
3033 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3034 {
3035         uint32_t old_write_domain;
3036
3037         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3038                 return;
3039
3040         /* No actual flushing is required for the GTT write domain.  Writes
3041          * to it immediately go to main memory as far as we know, so there's
3042          * no chipset flush.  It also doesn't land in render cache.
3043          *
3044          * However, we do have to enforce the order so that all writes through
3045          * the GTT land before any writes to the device, such as updates to
3046          * the GATT itself.
3047          */
3048         wmb();
3049
3050         old_write_domain = obj->base.write_domain;
3051         obj->base.write_domain = 0;
3052
3053         trace_i915_gem_object_change_domain(obj,
3054                                             obj->base.read_domains,
3055                                             old_write_domain);
3056 }
3057
3058 /** Flushes the CPU write domain for the object if it's dirty. */
3059 static void
3060 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3061 {
3062         uint32_t old_write_domain;
3063
3064         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3065                 return;
3066
3067         i915_gem_clflush_object(obj);
3068         i915_gem_chipset_flush(obj->base.dev);
3069         old_write_domain = obj->base.write_domain;
3070         obj->base.write_domain = 0;
3071
3072         trace_i915_gem_object_change_domain(obj,
3073                                             obj->base.read_domains,
3074                                             old_write_domain);
3075 }
3076
3077 /**
3078  * Moves a single object to the GTT read, and possibly write domain.
3079  *
3080  * This function returns when the move is complete, including waiting on
3081  * flushes to occur.
3082  */
3083 int
3084 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3085 {
3086         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3087         uint32_t old_write_domain, old_read_domains;
3088         int ret;
3089
3090         /* Not valid to be called on unbound objects. */
3091         if (obj->gtt_space == NULL)
3092                 return -EINVAL;
3093
3094         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3095                 return 0;
3096
3097         ret = i915_gem_object_wait_rendering(obj, !write);
3098         if (ret)
3099                 return ret;
3100
3101         i915_gem_object_flush_cpu_write_domain(obj);
3102
3103         old_write_domain = obj->base.write_domain;
3104         old_read_domains = obj->base.read_domains;
3105
3106         /* It should now be out of any other write domains, and we can update
3107          * the domain values for our changes.
3108          */
3109         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3110         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3111         if (write) {
3112                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3113                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3114                 obj->dirty = 1;
3115         }
3116
3117         trace_i915_gem_object_change_domain(obj,
3118                                             old_read_domains,
3119                                             old_write_domain);
3120
3121         /* And bump the LRU for this access */
3122         if (i915_gem_object_is_inactive(obj))
3123                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3124
3125         return 0;
3126 }
3127
3128 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3129                                     enum i915_cache_level cache_level)
3130 {
3131         struct drm_device *dev = obj->base.dev;
3132         drm_i915_private_t *dev_priv = dev->dev_private;
3133         int ret;
3134
3135         if (obj->cache_level == cache_level)
3136                 return 0;
3137
3138         if (obj->pin_count) {
3139                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3140                 return -EBUSY;
3141         }
3142
3143         if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3144                 ret = i915_gem_object_unbind(obj);
3145                 if (ret)
3146                         return ret;
3147         }
3148
3149         if (obj->gtt_space) {
3150                 ret = i915_gem_object_finish_gpu(obj);
3151                 if (ret)
3152                         return ret;
3153
3154                 i915_gem_object_finish_gtt(obj);
3155
3156                 /* Before SandyBridge, you could not use tiling or fence
3157                  * registers with snooped memory, so relinquish any fences
3158                  * currently pointing to our region in the aperture.
3159                  */
3160                 if (INTEL_INFO(dev)->gen < 6) {
3161                         ret = i915_gem_object_put_fence(obj);
3162                         if (ret)
3163                                 return ret;
3164                 }
3165
3166                 if (obj->has_global_gtt_mapping)
3167                         i915_gem_gtt_bind_object(obj, cache_level);
3168                 if (obj->has_aliasing_ppgtt_mapping)
3169                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3170                                                obj, cache_level);
3171
3172                 obj->gtt_space->color = cache_level;
3173         }
3174
3175         if (cache_level == I915_CACHE_NONE) {
3176                 u32 old_read_domains, old_write_domain;
3177
3178                 /* If we're coming from LLC cached, then we haven't
3179                  * actually been tracking whether the data is in the
3180                  * CPU cache or not, since we only allow one bit set
3181                  * in obj->write_domain and have been skipping the clflushes.
3182                  * Just set it to the CPU cache for now.
3183                  */
3184                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3185                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3186
3187                 old_read_domains = obj->base.read_domains;
3188                 old_write_domain = obj->base.write_domain;
3189
3190                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3191                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3192
3193                 trace_i915_gem_object_change_domain(obj,
3194                                                     old_read_domains,
3195                                                     old_write_domain);
3196         }
3197
3198         obj->cache_level = cache_level;
3199         i915_gem_verify_gtt(dev);
3200         return 0;
3201 }
3202
3203 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3204                                struct drm_file *file)
3205 {
3206         struct drm_i915_gem_caching *args = data;
3207         struct drm_i915_gem_object *obj;
3208         int ret;
3209
3210         ret = i915_mutex_lock_interruptible(dev);
3211         if (ret)
3212                 return ret;
3213
3214         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3215         if (&obj->base == NULL) {
3216                 ret = -ENOENT;
3217                 goto unlock;
3218         }
3219
3220         args->caching = obj->cache_level != I915_CACHE_NONE;
3221
3222         drm_gem_object_unreference(&obj->base);
3223 unlock:
3224         mutex_unlock(&dev->struct_mutex);
3225         return ret;
3226 }
3227
3228 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3229                                struct drm_file *file)
3230 {
3231         struct drm_i915_gem_caching *args = data;
3232         struct drm_i915_gem_object *obj;
3233         enum i915_cache_level level;
3234         int ret;
3235
3236         switch (args->caching) {
3237         case I915_CACHING_NONE:
3238                 level = I915_CACHE_NONE;
3239                 break;
3240         case I915_CACHING_CACHED:
3241                 level = I915_CACHE_LLC;
3242                 break;
3243         default:
3244                 return -EINVAL;
3245         }
3246
3247         ret = i915_mutex_lock_interruptible(dev);
3248         if (ret)
3249                 return ret;
3250
3251         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3252         if (&obj->base == NULL) {
3253                 ret = -ENOENT;
3254                 goto unlock;
3255         }
3256
3257         ret = i915_gem_object_set_cache_level(obj, level);
3258
3259         drm_gem_object_unreference(&obj->base);
3260 unlock:
3261         mutex_unlock(&dev->struct_mutex);
3262         return ret;
3263 }
3264
3265 /*
3266  * Prepare buffer for display plane (scanout, cursors, etc).
3267  * Can be called from an uninterruptible phase (modesetting) and allows
3268  * any flushes to be pipelined (for pageflips).
3269  */
3270 int
3271 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3272                                      u32 alignment,
3273                                      struct intel_ring_buffer *pipelined)
3274 {
3275         u32 old_read_domains, old_write_domain;
3276         int ret;
3277
3278         if (pipelined != obj->ring) {
3279                 ret = i915_gem_object_sync(obj, pipelined);
3280                 if (ret)
3281                         return ret;
3282         }
3283
3284         /* The display engine is not coherent with the LLC cache on gen6.  As
3285          * a result, we make sure that the pinning that is about to occur is
3286          * done with uncached PTEs. This is lowest common denominator for all
3287          * chipsets.
3288          *
3289          * However for gen6+, we could do better by using the GFDT bit instead
3290          * of uncaching, which would allow us to flush all the LLC-cached data
3291          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3292          */
3293         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3294         if (ret)
3295                 return ret;
3296
3297         /* As the user may map the buffer once pinned in the display plane
3298          * (e.g. libkms for the bootup splash), we have to ensure that we
3299          * always use map_and_fenceable for all scanout buffers.
3300