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Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel...
[~shefty/rdma-dev.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include <drm/drmP.h>
29 #include <drm/i915_drm.h>
30 #include "i915_drv.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
38
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
42                                                     unsigned alignment,
43                                                     bool map_and_fenceable,
44                                                     bool nonblocking);
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46                                 struct drm_i915_gem_object *obj,
47                                 struct drm_i915_gem_pwrite *args,
48                                 struct drm_file *file);
49
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51                                  struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53                                          struct drm_i915_fence_reg *fence,
54                                          bool enable);
55
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57                                     struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
61
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
63 {
64         if (obj->tiling_mode)
65                 i915_gem_release_mmap(obj);
66
67         /* As we do not have an associated fence register, we will force
68          * a tiling change if we ever need to acquire one.
69          */
70         obj->fence_dirty = false;
71         obj->fence_reg = I915_FENCE_REG_NONE;
72 }
73
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
76                                   size_t size)
77 {
78         dev_priv->mm.object_count++;
79         dev_priv->mm.object_memory += size;
80 }
81
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
83                                      size_t size)
84 {
85         dev_priv->mm.object_count--;
86         dev_priv->mm.object_memory -= size;
87 }
88
89 static int
90 i915_gem_wait_for_error(struct drm_device *dev)
91 {
92         struct drm_i915_private *dev_priv = dev->dev_private;
93         struct completion *x = &dev_priv->error_completion;
94         unsigned long flags;
95         int ret;
96
97         if (!atomic_read(&dev_priv->mm.wedged))
98                 return 0;
99
100         /*
101          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102          * userspace. If it takes that long something really bad is going on and
103          * we should simply try to bail out and fail as gracefully as possible.
104          */
105         ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
106         if (ret == 0) {
107                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
108                 return -EIO;
109         } else if (ret < 0) {
110                 return ret;
111         }
112
113         if (atomic_read(&dev_priv->mm.wedged)) {
114                 /* GPU is hung, bump the completion count to account for
115                  * the token we just consumed so that we never hit zero and
116                  * end up waiting upon a subsequent completion event that
117                  * will never happen.
118                  */
119                 spin_lock_irqsave(&x->wait.lock, flags);
120                 x->done++;
121                 spin_unlock_irqrestore(&x->wait.lock, flags);
122         }
123         return 0;
124 }
125
126 int i915_mutex_lock_interruptible(struct drm_device *dev)
127 {
128         int ret;
129
130         ret = i915_gem_wait_for_error(dev);
131         if (ret)
132                 return ret;
133
134         ret = mutex_lock_interruptible(&dev->struct_mutex);
135         if (ret)
136                 return ret;
137
138         WARN_ON(i915_verify_lists(dev));
139         return 0;
140 }
141
142 static inline bool
143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
144 {
145         return obj->gtt_space && !obj->active;
146 }
147
148 int
149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
150                     struct drm_file *file)
151 {
152         struct drm_i915_gem_init *args = data;
153
154         if (drm_core_check_feature(dev, DRIVER_MODESET))
155                 return -ENODEV;
156
157         if (args->gtt_start >= args->gtt_end ||
158             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
159                 return -EINVAL;
160
161         /* GEM with user mode setting was never supported on ilk and later. */
162         if (INTEL_INFO(dev)->gen >= 5)
163                 return -ENODEV;
164
165         mutex_lock(&dev->struct_mutex);
166         i915_gem_init_global_gtt(dev, args->gtt_start,
167                                  args->gtt_end, args->gtt_end);
168         mutex_unlock(&dev->struct_mutex);
169
170         return 0;
171 }
172
173 int
174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
175                             struct drm_file *file)
176 {
177         struct drm_i915_private *dev_priv = dev->dev_private;
178         struct drm_i915_gem_get_aperture *args = data;
179         struct drm_i915_gem_object *obj;
180         size_t pinned;
181
182         pinned = 0;
183         mutex_lock(&dev->struct_mutex);
184         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
185                 if (obj->pin_count)
186                         pinned += obj->gtt_space->size;
187         mutex_unlock(&dev->struct_mutex);
188
189         args->aper_size = dev_priv->mm.gtt_total;
190         args->aper_available_size = args->aper_size - pinned;
191
192         return 0;
193 }
194
195 static int
196 i915_gem_create(struct drm_file *file,
197                 struct drm_device *dev,
198                 uint64_t size,
199                 uint32_t *handle_p)
200 {
201         struct drm_i915_gem_object *obj;
202         int ret;
203         u32 handle;
204
205         size = roundup(size, PAGE_SIZE);
206         if (size == 0)
207                 return -EINVAL;
208
209         /* Allocate the new object */
210         obj = i915_gem_alloc_object(dev, size);
211         if (obj == NULL)
212                 return -ENOMEM;
213
214         ret = drm_gem_handle_create(file, &obj->base, &handle);
215         if (ret) {
216                 drm_gem_object_release(&obj->base);
217                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
218                 kfree(obj);
219                 return ret;
220         }
221
222         /* drop reference from allocate - handle holds it now */
223         drm_gem_object_unreference(&obj->base);
224         trace_i915_gem_object_create(obj);
225
226         *handle_p = handle;
227         return 0;
228 }
229
230 int
231 i915_gem_dumb_create(struct drm_file *file,
232                      struct drm_device *dev,
233                      struct drm_mode_create_dumb *args)
234 {
235         /* have to work out size/pitch and return them */
236         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
237         args->size = args->pitch * args->height;
238         return i915_gem_create(file, dev,
239                                args->size, &args->handle);
240 }
241
242 int i915_gem_dumb_destroy(struct drm_file *file,
243                           struct drm_device *dev,
244                           uint32_t handle)
245 {
246         return drm_gem_handle_delete(file, handle);
247 }
248
249 /**
250  * Creates a new mm object and returns a handle to it.
251  */
252 int
253 i915_gem_create_ioctl(struct drm_device *dev, void *data,
254                       struct drm_file *file)
255 {
256         struct drm_i915_gem_create *args = data;
257
258         return i915_gem_create(file, dev,
259                                args->size, &args->handle);
260 }
261
262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
263 {
264         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
265
266         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
267                 obj->tiling_mode != I915_TILING_NONE;
268 }
269
270 static inline int
271 __copy_to_user_swizzled(char __user *cpu_vaddr,
272                         const char *gpu_vaddr, int gpu_offset,
273                         int length)
274 {
275         int ret, cpu_offset = 0;
276
277         while (length > 0) {
278                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
279                 int this_length = min(cacheline_end - gpu_offset, length);
280                 int swizzled_gpu_offset = gpu_offset ^ 64;
281
282                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
283                                      gpu_vaddr + swizzled_gpu_offset,
284                                      this_length);
285                 if (ret)
286                         return ret + length;
287
288                 cpu_offset += this_length;
289                 gpu_offset += this_length;
290                 length -= this_length;
291         }
292
293         return 0;
294 }
295
296 static inline int
297 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
298                           const char __user *cpu_vaddr,
299                           int length)
300 {
301         int ret, cpu_offset = 0;
302
303         while (length > 0) {
304                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
305                 int this_length = min(cacheline_end - gpu_offset, length);
306                 int swizzled_gpu_offset = gpu_offset ^ 64;
307
308                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
309                                        cpu_vaddr + cpu_offset,
310                                        this_length);
311                 if (ret)
312                         return ret + length;
313
314                 cpu_offset += this_length;
315                 gpu_offset += this_length;
316                 length -= this_length;
317         }
318
319         return 0;
320 }
321
322 /* Per-page copy function for the shmem pread fastpath.
323  * Flushes invalid cachelines before reading the target if
324  * needs_clflush is set. */
325 static int
326 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
327                  char __user *user_data,
328                  bool page_do_bit17_swizzling, bool needs_clflush)
329 {
330         char *vaddr;
331         int ret;
332
333         if (unlikely(page_do_bit17_swizzling))
334                 return -EINVAL;
335
336         vaddr = kmap_atomic(page);
337         if (needs_clflush)
338                 drm_clflush_virt_range(vaddr + shmem_page_offset,
339                                        page_length);
340         ret = __copy_to_user_inatomic(user_data,
341                                       vaddr + shmem_page_offset,
342                                       page_length);
343         kunmap_atomic(vaddr);
344
345         return ret ? -EFAULT : 0;
346 }
347
348 static void
349 shmem_clflush_swizzled_range(char *addr, unsigned long length,
350                              bool swizzled)
351 {
352         if (unlikely(swizzled)) {
353                 unsigned long start = (unsigned long) addr;
354                 unsigned long end = (unsigned long) addr + length;
355
356                 /* For swizzling simply ensure that we always flush both
357                  * channels. Lame, but simple and it works. Swizzled
358                  * pwrite/pread is far from a hotpath - current userspace
359                  * doesn't use it at all. */
360                 start = round_down(start, 128);
361                 end = round_up(end, 128);
362
363                 drm_clflush_virt_range((void *)start, end - start);
364         } else {
365                 drm_clflush_virt_range(addr, length);
366         }
367
368 }
369
370 /* Only difference to the fast-path function is that this can handle bit17
371  * and uses non-atomic copy and kmap functions. */
372 static int
373 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
374                  char __user *user_data,
375                  bool page_do_bit17_swizzling, bool needs_clflush)
376 {
377         char *vaddr;
378         int ret;
379
380         vaddr = kmap(page);
381         if (needs_clflush)
382                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
383                                              page_length,
384                                              page_do_bit17_swizzling);
385
386         if (page_do_bit17_swizzling)
387                 ret = __copy_to_user_swizzled(user_data,
388                                               vaddr, shmem_page_offset,
389                                               page_length);
390         else
391                 ret = __copy_to_user(user_data,
392                                      vaddr + shmem_page_offset,
393                                      page_length);
394         kunmap(page);
395
396         return ret ? - EFAULT : 0;
397 }
398
399 static int
400 i915_gem_shmem_pread(struct drm_device *dev,
401                      struct drm_i915_gem_object *obj,
402                      struct drm_i915_gem_pread *args,
403                      struct drm_file *file)
404 {
405         char __user *user_data;
406         ssize_t remain;
407         loff_t offset;
408         int shmem_page_offset, page_length, ret = 0;
409         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410         int hit_slowpath = 0;
411         int prefaulted = 0;
412         int needs_clflush = 0;
413         struct scatterlist *sg;
414         int i;
415
416         user_data = (char __user *) (uintptr_t) args->data_ptr;
417         remain = args->size;
418
419         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
420
421         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
422                 /* If we're not in the cpu read domain, set ourself into the gtt
423                  * read domain and manually flush cachelines (if required). This
424                  * optimizes for the case when the gpu will dirty the data
425                  * anyway again before the next pread happens. */
426                 if (obj->cache_level == I915_CACHE_NONE)
427                         needs_clflush = 1;
428                 if (obj->gtt_space) {
429                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
430                         if (ret)
431                                 return ret;
432                 }
433         }
434
435         ret = i915_gem_object_get_pages(obj);
436         if (ret)
437                 return ret;
438
439         i915_gem_object_pin_pages(obj);
440
441         offset = args->offset;
442
443         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
444                 struct page *page;
445
446                 if (i < offset >> PAGE_SHIFT)
447                         continue;
448
449                 if (remain <= 0)
450                         break;
451
452                 /* Operation in this page
453                  *
454                  * shmem_page_offset = offset within page in shmem file
455                  * page_length = bytes to copy for this page
456                  */
457                 shmem_page_offset = offset_in_page(offset);
458                 page_length = remain;
459                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
460                         page_length = PAGE_SIZE - shmem_page_offset;
461
462                 page = sg_page(sg);
463                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
464                         (page_to_phys(page) & (1 << 17)) != 0;
465
466                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
467                                        user_data, page_do_bit17_swizzling,
468                                        needs_clflush);
469                 if (ret == 0)
470                         goto next_page;
471
472                 hit_slowpath = 1;
473                 mutex_unlock(&dev->struct_mutex);
474
475                 if (!prefaulted) {
476                         ret = fault_in_multipages_writeable(user_data, remain);
477                         /* Userspace is tricking us, but we've already clobbered
478                          * its pages with the prefault and promised to write the
479                          * data up to the first fault. Hence ignore any errors
480                          * and just continue. */
481                         (void)ret;
482                         prefaulted = 1;
483                 }
484
485                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
486                                        user_data, page_do_bit17_swizzling,
487                                        needs_clflush);
488
489                 mutex_lock(&dev->struct_mutex);
490
491 next_page:
492                 mark_page_accessed(page);
493
494                 if (ret)
495                         goto out;
496
497                 remain -= page_length;
498                 user_data += page_length;
499                 offset += page_length;
500         }
501
502 out:
503         i915_gem_object_unpin_pages(obj);
504
505         if (hit_slowpath) {
506                 /* Fixup: Kill any reinstated backing storage pages */
507                 if (obj->madv == __I915_MADV_PURGED)
508                         i915_gem_object_truncate(obj);
509         }
510
511         return ret;
512 }
513
514 /**
515  * Reads data from the object referenced by handle.
516  *
517  * On error, the contents of *data are undefined.
518  */
519 int
520 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
521                      struct drm_file *file)
522 {
523         struct drm_i915_gem_pread *args = data;
524         struct drm_i915_gem_object *obj;
525         int ret = 0;
526
527         if (args->size == 0)
528                 return 0;
529
530         if (!access_ok(VERIFY_WRITE,
531                        (char __user *)(uintptr_t)args->data_ptr,
532                        args->size))
533                 return -EFAULT;
534
535         ret = i915_mutex_lock_interruptible(dev);
536         if (ret)
537                 return ret;
538
539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
540         if (&obj->base == NULL) {
541                 ret = -ENOENT;
542                 goto unlock;
543         }
544
545         /* Bounds check source.  */
546         if (args->offset > obj->base.size ||
547             args->size > obj->base.size - args->offset) {
548                 ret = -EINVAL;
549                 goto out;
550         }
551
552         /* prime objects have no backing filp to GEM pread/pwrite
553          * pages from.
554          */
555         if (!obj->base.filp) {
556                 ret = -EINVAL;
557                 goto out;
558         }
559
560         trace_i915_gem_object_pread(obj, args->offset, args->size);
561
562         ret = i915_gem_shmem_pread(dev, obj, args, file);
563
564 out:
565         drm_gem_object_unreference(&obj->base);
566 unlock:
567         mutex_unlock(&dev->struct_mutex);
568         return ret;
569 }
570
571 /* This is the fast write path which cannot handle
572  * page faults in the source data
573  */
574
575 static inline int
576 fast_user_write(struct io_mapping *mapping,
577                 loff_t page_base, int page_offset,
578                 char __user *user_data,
579                 int length)
580 {
581         void __iomem *vaddr_atomic;
582         void *vaddr;
583         unsigned long unwritten;
584
585         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
586         /* We can use the cpu mem copy function because this is X86. */
587         vaddr = (void __force*)vaddr_atomic + page_offset;
588         unwritten = __copy_from_user_inatomic_nocache(vaddr,
589                                                       user_data, length);
590         io_mapping_unmap_atomic(vaddr_atomic);
591         return unwritten;
592 }
593
594 /**
595  * This is the fast pwrite path, where we copy the data directly from the
596  * user into the GTT, uncached.
597  */
598 static int
599 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
600                          struct drm_i915_gem_object *obj,
601                          struct drm_i915_gem_pwrite *args,
602                          struct drm_file *file)
603 {
604         drm_i915_private_t *dev_priv = dev->dev_private;
605         ssize_t remain;
606         loff_t offset, page_base;
607         char __user *user_data;
608         int page_offset, page_length, ret;
609
610         ret = i915_gem_object_pin(obj, 0, true, true);
611         if (ret)
612                 goto out;
613
614         ret = i915_gem_object_set_to_gtt_domain(obj, true);
615         if (ret)
616                 goto out_unpin;
617
618         ret = i915_gem_object_put_fence(obj);
619         if (ret)
620                 goto out_unpin;
621
622         user_data = (char __user *) (uintptr_t) args->data_ptr;
623         remain = args->size;
624
625         offset = obj->gtt_offset + args->offset;
626
627         while (remain > 0) {
628                 /* Operation in this page
629                  *
630                  * page_base = page offset within aperture
631                  * page_offset = offset within page
632                  * page_length = bytes to copy for this page
633                  */
634                 page_base = offset & PAGE_MASK;
635                 page_offset = offset_in_page(offset);
636                 page_length = remain;
637                 if ((page_offset + remain) > PAGE_SIZE)
638                         page_length = PAGE_SIZE - page_offset;
639
640                 /* If we get a fault while copying data, then (presumably) our
641                  * source page isn't available.  Return the error and we'll
642                  * retry in the slow path.
643                  */
644                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
645                                     page_offset, user_data, page_length)) {
646                         ret = -EFAULT;
647                         goto out_unpin;
648                 }
649
650                 remain -= page_length;
651                 user_data += page_length;
652                 offset += page_length;
653         }
654
655 out_unpin:
656         i915_gem_object_unpin(obj);
657 out:
658         return ret;
659 }
660
661 /* Per-page copy function for the shmem pwrite fastpath.
662  * Flushes invalid cachelines before writing to the target if
663  * needs_clflush_before is set and flushes out any written cachelines after
664  * writing if needs_clflush is set. */
665 static int
666 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
667                   char __user *user_data,
668                   bool page_do_bit17_swizzling,
669                   bool needs_clflush_before,
670                   bool needs_clflush_after)
671 {
672         char *vaddr;
673         int ret;
674
675         if (unlikely(page_do_bit17_swizzling))
676                 return -EINVAL;
677
678         vaddr = kmap_atomic(page);
679         if (needs_clflush_before)
680                 drm_clflush_virt_range(vaddr + shmem_page_offset,
681                                        page_length);
682         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
683                                                 user_data,
684                                                 page_length);
685         if (needs_clflush_after)
686                 drm_clflush_virt_range(vaddr + shmem_page_offset,
687                                        page_length);
688         kunmap_atomic(vaddr);
689
690         return ret ? -EFAULT : 0;
691 }
692
693 /* Only difference to the fast-path function is that this can handle bit17
694  * and uses non-atomic copy and kmap functions. */
695 static int
696 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
697                   char __user *user_data,
698                   bool page_do_bit17_swizzling,
699                   bool needs_clflush_before,
700                   bool needs_clflush_after)
701 {
702         char *vaddr;
703         int ret;
704
705         vaddr = kmap(page);
706         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
707                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
708                                              page_length,
709                                              page_do_bit17_swizzling);
710         if (page_do_bit17_swizzling)
711                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
712                                                 user_data,
713                                                 page_length);
714         else
715                 ret = __copy_from_user(vaddr + shmem_page_offset,
716                                        user_data,
717                                        page_length);
718         if (needs_clflush_after)
719                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
720                                              page_length,
721                                              page_do_bit17_swizzling);
722         kunmap(page);
723
724         return ret ? -EFAULT : 0;
725 }
726
727 static int
728 i915_gem_shmem_pwrite(struct drm_device *dev,
729                       struct drm_i915_gem_object *obj,
730                       struct drm_i915_gem_pwrite *args,
731                       struct drm_file *file)
732 {
733         ssize_t remain;
734         loff_t offset;
735         char __user *user_data;
736         int shmem_page_offset, page_length, ret = 0;
737         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
738         int hit_slowpath = 0;
739         int needs_clflush_after = 0;
740         int needs_clflush_before = 0;
741         int i;
742         struct scatterlist *sg;
743
744         user_data = (char __user *) (uintptr_t) args->data_ptr;
745         remain = args->size;
746
747         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
748
749         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
750                 /* If we're not in the cpu write domain, set ourself into the gtt
751                  * write domain and manually flush cachelines (if required). This
752                  * optimizes for the case when the gpu will use the data
753                  * right away and we therefore have to clflush anyway. */
754                 if (obj->cache_level == I915_CACHE_NONE)
755                         needs_clflush_after = 1;
756                 if (obj->gtt_space) {
757                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
758                         if (ret)
759                                 return ret;
760                 }
761         }
762         /* Same trick applies for invalidate partially written cachelines before
763          * writing.  */
764         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
765             && obj->cache_level == I915_CACHE_NONE)
766                 needs_clflush_before = 1;
767
768         ret = i915_gem_object_get_pages(obj);
769         if (ret)
770                 return ret;
771
772         i915_gem_object_pin_pages(obj);
773
774         offset = args->offset;
775         obj->dirty = 1;
776
777         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
778                 struct page *page;
779                 int partial_cacheline_write;
780
781                 if (i < offset >> PAGE_SHIFT)
782                         continue;
783
784                 if (remain <= 0)
785                         break;
786
787                 /* Operation in this page
788                  *
789                  * shmem_page_offset = offset within page in shmem file
790                  * page_length = bytes to copy for this page
791                  */
792                 shmem_page_offset = offset_in_page(offset);
793
794                 page_length = remain;
795                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
796                         page_length = PAGE_SIZE - shmem_page_offset;
797
798                 /* If we don't overwrite a cacheline completely we need to be
799                  * careful to have up-to-date data by first clflushing. Don't
800                  * overcomplicate things and flush the entire patch. */
801                 partial_cacheline_write = needs_clflush_before &&
802                         ((shmem_page_offset | page_length)
803                                 & (boot_cpu_data.x86_clflush_size - 1));
804
805                 page = sg_page(sg);
806                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
807                         (page_to_phys(page) & (1 << 17)) != 0;
808
809                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
810                                         user_data, page_do_bit17_swizzling,
811                                         partial_cacheline_write,
812                                         needs_clflush_after);
813                 if (ret == 0)
814                         goto next_page;
815
816                 hit_slowpath = 1;
817                 mutex_unlock(&dev->struct_mutex);
818                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
819                                         user_data, page_do_bit17_swizzling,
820                                         partial_cacheline_write,
821                                         needs_clflush_after);
822
823                 mutex_lock(&dev->struct_mutex);
824
825 next_page:
826                 set_page_dirty(page);
827                 mark_page_accessed(page);
828
829                 if (ret)
830                         goto out;
831
832                 remain -= page_length;
833                 user_data += page_length;
834                 offset += page_length;
835         }
836
837 out:
838         i915_gem_object_unpin_pages(obj);
839
840         if (hit_slowpath) {
841                 /* Fixup: Kill any reinstated backing storage pages */
842                 if (obj->madv == __I915_MADV_PURGED)
843                         i915_gem_object_truncate(obj);
844                 /* and flush dirty cachelines in case the object isn't in the cpu write
845                  * domain anymore. */
846                 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
847                         i915_gem_clflush_object(obj);
848                         intel_gtt_chipset_flush();
849                 }
850         }
851
852         if (needs_clflush_after)
853                 intel_gtt_chipset_flush();
854
855         return ret;
856 }
857
858 /**
859  * Writes data to the object referenced by handle.
860  *
861  * On error, the contents of the buffer that were to be modified are undefined.
862  */
863 int
864 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
865                       struct drm_file *file)
866 {
867         struct drm_i915_gem_pwrite *args = data;
868         struct drm_i915_gem_object *obj;
869         int ret;
870
871         if (args->size == 0)
872                 return 0;
873
874         if (!access_ok(VERIFY_READ,
875                        (char __user *)(uintptr_t)args->data_ptr,
876                        args->size))
877                 return -EFAULT;
878
879         ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
880                                            args->size);
881         if (ret)
882                 return -EFAULT;
883
884         ret = i915_mutex_lock_interruptible(dev);
885         if (ret)
886                 return ret;
887
888         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
889         if (&obj->base == NULL) {
890                 ret = -ENOENT;
891                 goto unlock;
892         }
893
894         /* Bounds check destination. */
895         if (args->offset > obj->base.size ||
896             args->size > obj->base.size - args->offset) {
897                 ret = -EINVAL;
898                 goto out;
899         }
900
901         /* prime objects have no backing filp to GEM pread/pwrite
902          * pages from.
903          */
904         if (!obj->base.filp) {
905                 ret = -EINVAL;
906                 goto out;
907         }
908
909         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
910
911         ret = -EFAULT;
912         /* We can only do the GTT pwrite on untiled buffers, as otherwise
913          * it would end up going through the fenced access, and we'll get
914          * different detiling behavior between reading and writing.
915          * pread/pwrite currently are reading and writing from the CPU
916          * perspective, requiring manual detiling by the client.
917          */
918         if (obj->phys_obj) {
919                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
920                 goto out;
921         }
922
923         if (obj->cache_level == I915_CACHE_NONE &&
924             obj->tiling_mode == I915_TILING_NONE &&
925             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
926                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
927                 /* Note that the gtt paths might fail with non-page-backed user
928                  * pointers (e.g. gtt mappings when moving data between
929                  * textures). Fallback to the shmem path in that case. */
930         }
931
932         if (ret == -EFAULT || ret == -ENOSPC)
933                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
934
935 out:
936         drm_gem_object_unreference(&obj->base);
937 unlock:
938         mutex_unlock(&dev->struct_mutex);
939         return ret;
940 }
941
942 int
943 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
944                      bool interruptible)
945 {
946         if (atomic_read(&dev_priv->mm.wedged)) {
947                 struct completion *x = &dev_priv->error_completion;
948                 bool recovery_complete;
949                 unsigned long flags;
950
951                 /* Give the error handler a chance to run. */
952                 spin_lock_irqsave(&x->wait.lock, flags);
953                 recovery_complete = x->done > 0;
954                 spin_unlock_irqrestore(&x->wait.lock, flags);
955
956                 /* Non-interruptible callers can't handle -EAGAIN, hence return
957                  * -EIO unconditionally for these. */
958                 if (!interruptible)
959                         return -EIO;
960
961                 /* Recovery complete, but still wedged means reset failure. */
962                 if (recovery_complete)
963                         return -EIO;
964
965                 return -EAGAIN;
966         }
967
968         return 0;
969 }
970
971 /*
972  * Compare seqno against outstanding lazy request. Emit a request if they are
973  * equal.
974  */
975 static int
976 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
977 {
978         int ret;
979
980         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
981
982         ret = 0;
983         if (seqno == ring->outstanding_lazy_request)
984                 ret = i915_add_request(ring, NULL, NULL);
985
986         return ret;
987 }
988
989 /**
990  * __wait_seqno - wait until execution of seqno has finished
991  * @ring: the ring expected to report seqno
992  * @seqno: duh!
993  * @interruptible: do an interruptible wait (normally yes)
994  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
995  *
996  * Returns 0 if the seqno was found within the alloted time. Else returns the
997  * errno with remaining time filled in timeout argument.
998  */
999 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1000                         bool interruptible, struct timespec *timeout)
1001 {
1002         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1003         struct timespec before, now, wait_time={1,0};
1004         unsigned long timeout_jiffies;
1005         long end;
1006         bool wait_forever = true;
1007         int ret;
1008
1009         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1010                 return 0;
1011
1012         trace_i915_gem_request_wait_begin(ring, seqno);
1013
1014         if (timeout != NULL) {
1015                 wait_time = *timeout;
1016                 wait_forever = false;
1017         }
1018
1019         timeout_jiffies = timespec_to_jiffies(&wait_time);
1020
1021         if (WARN_ON(!ring->irq_get(ring)))
1022                 return -ENODEV;
1023
1024         /* Record current time in case interrupted by signal, or wedged * */
1025         getrawmonotonic(&before);
1026
1027 #define EXIT_COND \
1028         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1029         atomic_read(&dev_priv->mm.wedged))
1030         do {
1031                 if (interruptible)
1032                         end = wait_event_interruptible_timeout(ring->irq_queue,
1033                                                                EXIT_COND,
1034                                                                timeout_jiffies);
1035                 else
1036                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1037                                                  timeout_jiffies);
1038
1039                 ret = i915_gem_check_wedge(dev_priv, interruptible);
1040                 if (ret)
1041                         end = ret;
1042         } while (end == 0 && wait_forever);
1043
1044         getrawmonotonic(&now);
1045
1046         ring->irq_put(ring);
1047         trace_i915_gem_request_wait_end(ring, seqno);
1048 #undef EXIT_COND
1049
1050         if (timeout) {
1051                 struct timespec sleep_time = timespec_sub(now, before);
1052                 *timeout = timespec_sub(*timeout, sleep_time);
1053         }
1054
1055         switch (end) {
1056         case -EIO:
1057         case -EAGAIN: /* Wedged */
1058         case -ERESTARTSYS: /* Signal */
1059                 return (int)end;
1060         case 0: /* Timeout */
1061                 if (timeout)
1062                         set_normalized_timespec(timeout, 0, 0);
1063                 return -ETIME;
1064         default: /* Completed */
1065                 WARN_ON(end < 0); /* We're not aware of other errors */
1066                 return 0;
1067         }
1068 }
1069
1070 /**
1071  * Waits for a sequence number to be signaled, and cleans up the
1072  * request and object lists appropriately for that event.
1073  */
1074 int
1075 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1076 {
1077         struct drm_device *dev = ring->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         bool interruptible = dev_priv->mm.interruptible;
1080         int ret;
1081
1082         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1083         BUG_ON(seqno == 0);
1084
1085         ret = i915_gem_check_wedge(dev_priv, interruptible);
1086         if (ret)
1087                 return ret;
1088
1089         ret = i915_gem_check_olr(ring, seqno);
1090         if (ret)
1091                 return ret;
1092
1093         return __wait_seqno(ring, seqno, interruptible, NULL);
1094 }
1095
1096 /**
1097  * Ensures that all rendering to the object has completed and the object is
1098  * safe to unbind from the GTT or access from the CPU.
1099  */
1100 static __must_check int
1101 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1102                                bool readonly)
1103 {
1104         struct intel_ring_buffer *ring = obj->ring;
1105         u32 seqno;
1106         int ret;
1107
1108         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1109         if (seqno == 0)
1110                 return 0;
1111
1112         ret = i915_wait_seqno(ring, seqno);
1113         if (ret)
1114                 return ret;
1115
1116         i915_gem_retire_requests_ring(ring);
1117
1118         /* Manually manage the write flush as we may have not yet
1119          * retired the buffer.
1120          */
1121         if (obj->last_write_seqno &&
1122             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1123                 obj->last_write_seqno = 0;
1124                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1125         }
1126
1127         return 0;
1128 }
1129
1130 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1131  * as the object state may change during this call.
1132  */
1133 static __must_check int
1134 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1135                                             bool readonly)
1136 {
1137         struct drm_device *dev = obj->base.dev;
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         struct intel_ring_buffer *ring = obj->ring;
1140         u32 seqno;
1141         int ret;
1142
1143         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1144         BUG_ON(!dev_priv->mm.interruptible);
1145
1146         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1147         if (seqno == 0)
1148                 return 0;
1149
1150         ret = i915_gem_check_wedge(dev_priv, true);
1151         if (ret)
1152                 return ret;
1153
1154         ret = i915_gem_check_olr(ring, seqno);
1155         if (ret)
1156                 return ret;
1157
1158         mutex_unlock(&dev->struct_mutex);
1159         ret = __wait_seqno(ring, seqno, true, NULL);
1160         mutex_lock(&dev->struct_mutex);
1161
1162         i915_gem_retire_requests_ring(ring);
1163
1164         /* Manually manage the write flush as we may have not yet
1165          * retired the buffer.
1166          */
1167         if (obj->last_write_seqno &&
1168             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1169                 obj->last_write_seqno = 0;
1170                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1171         }
1172
1173         return ret;
1174 }
1175
1176 /**
1177  * Called when user space prepares to use an object with the CPU, either
1178  * through the mmap ioctl's mapping or a GTT mapping.
1179  */
1180 int
1181 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1182                           struct drm_file *file)
1183 {
1184         struct drm_i915_gem_set_domain *args = data;
1185         struct drm_i915_gem_object *obj;
1186         uint32_t read_domains = args->read_domains;
1187         uint32_t write_domain = args->write_domain;
1188         int ret;
1189
1190         /* Only handle setting domains to types used by the CPU. */
1191         if (write_domain & I915_GEM_GPU_DOMAINS)
1192                 return -EINVAL;
1193
1194         if (read_domains & I915_GEM_GPU_DOMAINS)
1195                 return -EINVAL;
1196
1197         /* Having something in the write domain implies it's in the read
1198          * domain, and only that read domain.  Enforce that in the request.
1199          */
1200         if (write_domain != 0 && read_domains != write_domain)
1201                 return -EINVAL;
1202
1203         ret = i915_mutex_lock_interruptible(dev);
1204         if (ret)
1205                 return ret;
1206
1207         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1208         if (&obj->base == NULL) {
1209                 ret = -ENOENT;
1210                 goto unlock;
1211         }
1212
1213         /* Try to flush the object off the GPU without holding the lock.
1214          * We will repeat the flush holding the lock in the normal manner
1215          * to catch cases where we are gazumped.
1216          */
1217         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218         if (ret)
1219                 goto unref;
1220
1221         if (read_domains & I915_GEM_DOMAIN_GTT) {
1222                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1223
1224                 /* Silently promote "you're not bound, there was nothing to do"
1225                  * to success, since the client was just asking us to
1226                  * make sure everything was done.
1227                  */
1228                 if (ret == -EINVAL)
1229                         ret = 0;
1230         } else {
1231                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232         }
1233
1234 unref:
1235         drm_gem_object_unreference(&obj->base);
1236 unlock:
1237         mutex_unlock(&dev->struct_mutex);
1238         return ret;
1239 }
1240
1241 /**
1242  * Called when user space has done writes to this buffer
1243  */
1244 int
1245 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1246                          struct drm_file *file)
1247 {
1248         struct drm_i915_gem_sw_finish *args = data;
1249         struct drm_i915_gem_object *obj;
1250         int ret = 0;
1251
1252         ret = i915_mutex_lock_interruptible(dev);
1253         if (ret)
1254                 return ret;
1255
1256         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1257         if (&obj->base == NULL) {
1258                 ret = -ENOENT;
1259                 goto unlock;
1260         }
1261
1262         /* Pinned buffers may be scanout, so flush the cache */
1263         if (obj->pin_count)
1264                 i915_gem_object_flush_cpu_write_domain(obj);
1265
1266         drm_gem_object_unreference(&obj->base);
1267 unlock:
1268         mutex_unlock(&dev->struct_mutex);
1269         return ret;
1270 }
1271
1272 /**
1273  * Maps the contents of an object, returning the address it is mapped
1274  * into.
1275  *
1276  * While the mapping holds a reference on the contents of the object, it doesn't
1277  * imply a ref on the object itself.
1278  */
1279 int
1280 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1281                     struct drm_file *file)
1282 {
1283         struct drm_i915_gem_mmap *args = data;
1284         struct drm_gem_object *obj;
1285         unsigned long addr;
1286
1287         obj = drm_gem_object_lookup(dev, file, args->handle);
1288         if (obj == NULL)
1289                 return -ENOENT;
1290
1291         /* prime objects have no backing filp to GEM mmap
1292          * pages from.
1293          */
1294         if (!obj->filp) {
1295                 drm_gem_object_unreference_unlocked(obj);
1296                 return -EINVAL;
1297         }
1298
1299         addr = vm_mmap(obj->filp, 0, args->size,
1300                        PROT_READ | PROT_WRITE, MAP_SHARED,
1301                        args->offset);
1302         drm_gem_object_unreference_unlocked(obj);
1303         if (IS_ERR((void *)addr))
1304                 return addr;
1305
1306         args->addr_ptr = (uint64_t) addr;
1307
1308         return 0;
1309 }
1310
1311 /**
1312  * i915_gem_fault - fault a page into the GTT
1313  * vma: VMA in question
1314  * vmf: fault info
1315  *
1316  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1317  * from userspace.  The fault handler takes care of binding the object to
1318  * the GTT (if needed), allocating and programming a fence register (again,
1319  * only if needed based on whether the old reg is still valid or the object
1320  * is tiled) and inserting a new PTE into the faulting process.
1321  *
1322  * Note that the faulting process may involve evicting existing objects
1323  * from the GTT and/or fence registers to make room.  So performance may
1324  * suffer if the GTT working set is large or there are few fence registers
1325  * left.
1326  */
1327 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1328 {
1329         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1330         struct drm_device *dev = obj->base.dev;
1331         drm_i915_private_t *dev_priv = dev->dev_private;
1332         pgoff_t page_offset;
1333         unsigned long pfn;
1334         int ret = 0;
1335         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1336
1337         /* We don't use vmf->pgoff since that has the fake offset */
1338         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1339                 PAGE_SHIFT;
1340
1341         ret = i915_mutex_lock_interruptible(dev);
1342         if (ret)
1343                 goto out;
1344
1345         trace_i915_gem_object_fault(obj, page_offset, true, write);
1346
1347         /* Now bind it into the GTT if needed */
1348         if (!obj->map_and_fenceable) {
1349                 ret = i915_gem_object_unbind(obj);
1350                 if (ret)
1351                         goto unlock;
1352         }
1353         if (!obj->gtt_space) {
1354                 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
1355                 if (ret)
1356                         goto unlock;
1357
1358                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1359                 if (ret)
1360                         goto unlock;
1361         }
1362
1363         if (!obj->has_global_gtt_mapping)
1364                 i915_gem_gtt_bind_object(obj, obj->cache_level);
1365
1366         ret = i915_gem_object_get_fence(obj);
1367         if (ret)
1368                 goto unlock;
1369
1370         if (i915_gem_object_is_inactive(obj))
1371                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1372
1373         obj->fault_mappable = true;
1374
1375         pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1376                 page_offset;
1377
1378         /* Finally, remap it using the new GTT offset */
1379         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1380 unlock:
1381         mutex_unlock(&dev->struct_mutex);
1382 out:
1383         switch (ret) {
1384         case -EIO:
1385                 /* If this -EIO is due to a gpu hang, give the reset code a
1386                  * chance to clean up the mess. Otherwise return the proper
1387                  * SIGBUS. */
1388                 if (!atomic_read(&dev_priv->mm.wedged))
1389                         return VM_FAULT_SIGBUS;
1390         case -EAGAIN:
1391                 /* Give the error handler a chance to run and move the
1392                  * objects off the GPU active list. Next time we service the
1393                  * fault, we should be able to transition the page into the
1394                  * GTT without touching the GPU (and so avoid further
1395                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1396                  * with coherency, just lost writes.
1397                  */
1398                 set_need_resched();
1399         case 0:
1400         case -ERESTARTSYS:
1401         case -EINTR:
1402         case -EBUSY:
1403                 /*
1404                  * EBUSY is ok: this just means that another thread
1405                  * already did the job.
1406                  */
1407                 return VM_FAULT_NOPAGE;
1408         case -ENOMEM:
1409                 return VM_FAULT_OOM;
1410         default:
1411                 WARN_ON_ONCE(ret);
1412                 return VM_FAULT_SIGBUS;
1413         }
1414 }
1415
1416 /**
1417  * i915_gem_release_mmap - remove physical page mappings
1418  * @obj: obj in question
1419  *
1420  * Preserve the reservation of the mmapping with the DRM core code, but
1421  * relinquish ownership of the pages back to the system.
1422  *
1423  * It is vital that we remove the page mapping if we have mapped a tiled
1424  * object through the GTT and then lose the fence register due to
1425  * resource pressure. Similarly if the object has been moved out of the
1426  * aperture, than pages mapped into userspace must be revoked. Removing the
1427  * mapping will then trigger a page fault on the next user access, allowing
1428  * fixup by i915_gem_fault().
1429  */
1430 void
1431 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1432 {
1433         if (!obj->fault_mappable)
1434                 return;
1435
1436         if (obj->base.dev->dev_mapping)
1437                 unmap_mapping_range(obj->base.dev->dev_mapping,
1438                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1439                                     obj->base.size, 1);
1440
1441         obj->fault_mappable = false;
1442 }
1443
1444 static uint32_t
1445 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1446 {
1447         uint32_t gtt_size;
1448
1449         if (INTEL_INFO(dev)->gen >= 4 ||
1450             tiling_mode == I915_TILING_NONE)
1451                 return size;
1452
1453         /* Previous chips need a power-of-two fence region when tiling */
1454         if (INTEL_INFO(dev)->gen == 3)
1455                 gtt_size = 1024*1024;
1456         else
1457                 gtt_size = 512*1024;
1458
1459         while (gtt_size < size)
1460                 gtt_size <<= 1;
1461
1462         return gtt_size;
1463 }
1464
1465 /**
1466  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1467  * @obj: object to check
1468  *
1469  * Return the required GTT alignment for an object, taking into account
1470  * potential fence register mapping.
1471  */
1472 static uint32_t
1473 i915_gem_get_gtt_alignment(struct drm_device *dev,
1474                            uint32_t size,
1475                            int tiling_mode)
1476 {
1477         /*
1478          * Minimum alignment is 4k (GTT page size), but might be greater
1479          * if a fence register is needed for the object.
1480          */
1481         if (INTEL_INFO(dev)->gen >= 4 ||
1482             tiling_mode == I915_TILING_NONE)
1483                 return 4096;
1484
1485         /*
1486          * Previous chips need to be aligned to the size of the smallest
1487          * fence register that can contain the object.
1488          */
1489         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1490 }
1491
1492 /**
1493  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1494  *                                       unfenced object
1495  * @dev: the device
1496  * @size: size of the object
1497  * @tiling_mode: tiling mode of the object
1498  *
1499  * Return the required GTT alignment for an object, only taking into account
1500  * unfenced tiled surface requirements.
1501  */
1502 uint32_t
1503 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1504                                     uint32_t size,
1505                                     int tiling_mode)
1506 {
1507         /*
1508          * Minimum alignment is 4k (GTT page size) for sane hw.
1509          */
1510         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1511             tiling_mode == I915_TILING_NONE)
1512                 return 4096;
1513
1514         /* Previous hardware however needs to be aligned to a power-of-two
1515          * tile height. The simplest method for determining this is to reuse
1516          * the power-of-tile object size.
1517          */
1518         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1519 }
1520
1521 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1522 {
1523         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1524         int ret;
1525
1526         if (obj->base.map_list.map)
1527                 return 0;
1528
1529         ret = drm_gem_create_mmap_offset(&obj->base);
1530         if (ret != -ENOSPC)
1531                 return ret;
1532
1533         /* Badly fragmented mmap space? The only way we can recover
1534          * space is by destroying unwanted objects. We can't randomly release
1535          * mmap_offsets as userspace expects them to be persistent for the
1536          * lifetime of the objects. The closest we can is to release the
1537          * offsets on purgeable objects by truncating it and marking it purged,
1538          * which prevents userspace from ever using that object again.
1539          */
1540         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1541         ret = drm_gem_create_mmap_offset(&obj->base);
1542         if (ret != -ENOSPC)
1543                 return ret;
1544
1545         i915_gem_shrink_all(dev_priv);
1546         return drm_gem_create_mmap_offset(&obj->base);
1547 }
1548
1549 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1550 {
1551         if (!obj->base.map_list.map)
1552                 return;
1553
1554         drm_gem_free_mmap_offset(&obj->base);
1555 }
1556
1557 int
1558 i915_gem_mmap_gtt(struct drm_file *file,
1559                   struct drm_device *dev,
1560                   uint32_t handle,
1561                   uint64_t *offset)
1562 {
1563         struct drm_i915_private *dev_priv = dev->dev_private;
1564         struct drm_i915_gem_object *obj;
1565         int ret;
1566
1567         ret = i915_mutex_lock_interruptible(dev);
1568         if (ret)
1569                 return ret;
1570
1571         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1572         if (&obj->base == NULL) {
1573                 ret = -ENOENT;
1574                 goto unlock;
1575         }
1576
1577         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1578                 ret = -E2BIG;
1579                 goto out;
1580         }
1581
1582         if (obj->madv != I915_MADV_WILLNEED) {
1583                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1584                 ret = -EINVAL;
1585                 goto out;
1586         }
1587
1588         ret = i915_gem_object_create_mmap_offset(obj);
1589         if (ret)
1590                 goto out;
1591
1592         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1593
1594 out:
1595         drm_gem_object_unreference(&obj->base);
1596 unlock:
1597         mutex_unlock(&dev->struct_mutex);
1598         return ret;
1599 }
1600
1601 /**
1602  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1603  * @dev: DRM device
1604  * @data: GTT mapping ioctl data
1605  * @file: GEM object info
1606  *
1607  * Simply returns the fake offset to userspace so it can mmap it.
1608  * The mmap call will end up in drm_gem_mmap(), which will set things
1609  * up so we can get faults in the handler above.
1610  *
1611  * The fault handler will take care of binding the object into the GTT
1612  * (since it may have been evicted to make room for something), allocating
1613  * a fence register, and mapping the appropriate aperture address into
1614  * userspace.
1615  */
1616 int
1617 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1618                         struct drm_file *file)
1619 {
1620         struct drm_i915_gem_mmap_gtt *args = data;
1621
1622         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1623 }
1624
1625 /* Immediately discard the backing storage */
1626 static void
1627 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1628 {
1629         struct inode *inode;
1630
1631         i915_gem_object_free_mmap_offset(obj);
1632
1633         if (obj->base.filp == NULL)
1634                 return;
1635
1636         /* Our goal here is to return as much of the memory as
1637          * is possible back to the system as we are called from OOM.
1638          * To do this we must instruct the shmfs to drop all of its
1639          * backing pages, *now*.
1640          */
1641         inode = obj->base.filp->f_path.dentry->d_inode;
1642         shmem_truncate_range(inode, 0, (loff_t)-1);
1643
1644         obj->madv = __I915_MADV_PURGED;
1645 }
1646
1647 static inline int
1648 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1649 {
1650         return obj->madv == I915_MADV_DONTNEED;
1651 }
1652
1653 static void
1654 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1655 {
1656         int page_count = obj->base.size / PAGE_SIZE;
1657         struct scatterlist *sg;
1658         int ret, i;
1659
1660         BUG_ON(obj->madv == __I915_MADV_PURGED);
1661
1662         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1663         if (ret) {
1664                 /* In the event of a disaster, abandon all caches and
1665                  * hope for the best.
1666                  */
1667                 WARN_ON(ret != -EIO);
1668                 i915_gem_clflush_object(obj);
1669                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1670         }
1671
1672         if (i915_gem_object_needs_bit17_swizzle(obj))
1673                 i915_gem_object_save_bit_17_swizzle(obj);
1674
1675         if (obj->madv == I915_MADV_DONTNEED)
1676                 obj->dirty = 0;
1677
1678         for_each_sg(obj->pages->sgl, sg, page_count, i) {
1679                 struct page *page = sg_page(sg);
1680
1681                 if (obj->dirty)
1682                         set_page_dirty(page);
1683
1684                 if (obj->madv == I915_MADV_WILLNEED)
1685                         mark_page_accessed(page);
1686
1687                 page_cache_release(page);
1688         }
1689         obj->dirty = 0;
1690
1691         sg_free_table(obj->pages);
1692         kfree(obj->pages);
1693 }
1694
1695 static int
1696 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1697 {
1698         const struct drm_i915_gem_object_ops *ops = obj->ops;
1699
1700         if (obj->pages == NULL)
1701                 return 0;
1702
1703         BUG_ON(obj->gtt_space);
1704
1705         if (obj->pages_pin_count)
1706                 return -EBUSY;
1707
1708         ops->put_pages(obj);
1709         obj->pages = NULL;
1710
1711         list_del(&obj->gtt_list);
1712         if (i915_gem_object_is_purgeable(obj))
1713                 i915_gem_object_truncate(obj);
1714
1715         return 0;
1716 }
1717
1718 static long
1719 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1720 {
1721         struct drm_i915_gem_object *obj, *next;
1722         long count = 0;
1723
1724         list_for_each_entry_safe(obj, next,
1725                                  &dev_priv->mm.unbound_list,
1726                                  gtt_list) {
1727                 if (i915_gem_object_is_purgeable(obj) &&
1728                     i915_gem_object_put_pages(obj) == 0) {
1729                         count += obj->base.size >> PAGE_SHIFT;
1730                         if (count >= target)
1731                                 return count;
1732                 }
1733         }
1734
1735         list_for_each_entry_safe(obj, next,
1736                                  &dev_priv->mm.inactive_list,
1737                                  mm_list) {
1738                 if (i915_gem_object_is_purgeable(obj) &&
1739                     i915_gem_object_unbind(obj) == 0 &&
1740                     i915_gem_object_put_pages(obj) == 0) {
1741                         count += obj->base.size >> PAGE_SHIFT;
1742                         if (count >= target)
1743                                 return count;
1744                 }
1745         }
1746
1747         return count;
1748 }
1749
1750 static void
1751 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1752 {
1753         struct drm_i915_gem_object *obj, *next;
1754
1755         i915_gem_evict_everything(dev_priv->dev);
1756
1757         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1758                 i915_gem_object_put_pages(obj);
1759 }
1760
1761 static int
1762 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1763 {
1764         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1765         int page_count, i;
1766         struct address_space *mapping;
1767         struct sg_table *st;
1768         struct scatterlist *sg;
1769         struct page *page;
1770         gfp_t gfp;
1771
1772         /* Assert that the object is not currently in any GPU domain. As it
1773          * wasn't in the GTT, there shouldn't be any way it could have been in
1774          * a GPU cache
1775          */
1776         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1777         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1778
1779         st = kmalloc(sizeof(*st), GFP_KERNEL);
1780         if (st == NULL)
1781                 return -ENOMEM;
1782
1783         page_count = obj->base.size / PAGE_SIZE;
1784         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1785                 sg_free_table(st);
1786                 kfree(st);
1787                 return -ENOMEM;
1788         }
1789
1790         /* Get the list of pages out of our struct file.  They'll be pinned
1791          * at this point until we release them.
1792          *
1793          * Fail silently without starting the shrinker
1794          */
1795         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1796         gfp = mapping_gfp_mask(mapping);
1797         gfp |= __GFP_NORETRY | __GFP_NOWARN;
1798         gfp &= ~(__GFP_IO | __GFP_WAIT);
1799         for_each_sg(st->sgl, sg, page_count, i) {
1800                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1801                 if (IS_ERR(page)) {
1802                         i915_gem_purge(dev_priv, page_count);
1803                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1804                 }
1805                 if (IS_ERR(page)) {
1806                         /* We've tried hard to allocate the memory by reaping
1807                          * our own buffer, now let the real VM do its job and
1808                          * go down in flames if truly OOM.
1809                          */
1810                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1811                         gfp |= __GFP_IO | __GFP_WAIT;
1812
1813                         i915_gem_shrink_all(dev_priv);
1814                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1815                         if (IS_ERR(page))
1816                                 goto err_pages;
1817
1818                         gfp |= __GFP_NORETRY | __GFP_NOWARN;
1819                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1820                 }
1821
1822                 sg_set_page(sg, page, PAGE_SIZE, 0);
1823         }
1824
1825         if (i915_gem_object_needs_bit17_swizzle(obj))
1826                 i915_gem_object_do_bit_17_swizzle(obj);
1827
1828         obj->pages = st;
1829         return 0;
1830
1831 err_pages:
1832         for_each_sg(st->sgl, sg, i, page_count)
1833                 page_cache_release(sg_page(sg));
1834         sg_free_table(st);
1835         kfree(st);
1836         return PTR_ERR(page);
1837 }
1838
1839 /* Ensure that the associated pages are gathered from the backing storage
1840  * and pinned into our object. i915_gem_object_get_pages() may be called
1841  * multiple times before they are released by a single call to
1842  * i915_gem_object_put_pages() - once the pages are no longer referenced
1843  * either as a result of memory pressure (reaping pages under the shrinker)
1844  * or as the object is itself released.
1845  */
1846 int
1847 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1848 {
1849         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1850         const struct drm_i915_gem_object_ops *ops = obj->ops;
1851         int ret;
1852
1853         if (obj->pages)
1854                 return 0;
1855
1856         BUG_ON(obj->pages_pin_count);
1857
1858         ret = ops->get_pages(obj);
1859         if (ret)
1860                 return ret;
1861
1862         list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1863         return 0;
1864 }
1865
1866 void
1867 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1868                                struct intel_ring_buffer *ring,
1869                                u32 seqno)
1870 {
1871         struct drm_device *dev = obj->base.dev;
1872         struct drm_i915_private *dev_priv = dev->dev_private;
1873
1874         BUG_ON(ring == NULL);
1875         obj->ring = ring;
1876
1877         /* Add a reference if we're newly entering the active list. */
1878         if (!obj->active) {
1879                 drm_gem_object_reference(&obj->base);
1880                 obj->active = 1;
1881         }
1882
1883         /* Move from whatever list we were on to the tail of execution. */
1884         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1885         list_move_tail(&obj->ring_list, &ring->active_list);
1886
1887         obj->last_read_seqno = seqno;
1888
1889         if (obj->fenced_gpu_access) {
1890                 obj->last_fenced_seqno = seqno;
1891
1892                 /* Bump MRU to take account of the delayed flush */
1893                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1894                         struct drm_i915_fence_reg *reg;
1895
1896                         reg = &dev_priv->fence_regs[obj->fence_reg];
1897                         list_move_tail(&reg->lru_list,
1898                                        &dev_priv->mm.fence_list);
1899                 }
1900         }
1901 }
1902
1903 static void
1904 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1905 {
1906         struct drm_device *dev = obj->base.dev;
1907         struct drm_i915_private *dev_priv = dev->dev_private;
1908
1909         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1910         BUG_ON(!obj->active);
1911
1912         if (obj->pin_count) /* are we a framebuffer? */
1913                 intel_mark_fb_idle(obj);
1914
1915         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1916
1917         list_del_init(&obj->ring_list);
1918         obj->ring = NULL;
1919
1920         obj->last_read_seqno = 0;
1921         obj->last_write_seqno = 0;
1922         obj->base.write_domain = 0;
1923
1924         obj->last_fenced_seqno = 0;
1925         obj->fenced_gpu_access = false;
1926
1927         obj->active = 0;
1928         drm_gem_object_unreference(&obj->base);
1929
1930         WARN_ON(i915_verify_lists(dev));
1931 }
1932
1933 static u32
1934 i915_gem_get_seqno(struct drm_device *dev)
1935 {
1936         drm_i915_private_t *dev_priv = dev->dev_private;
1937         u32 seqno = dev_priv->next_seqno;
1938
1939         /* reserve 0 for non-seqno */
1940         if (++dev_priv->next_seqno == 0)
1941                 dev_priv->next_seqno = 1;
1942
1943         return seqno;
1944 }
1945
1946 u32
1947 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1948 {
1949         if (ring->outstanding_lazy_request == 0)
1950                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1951
1952         return ring->outstanding_lazy_request;
1953 }
1954
1955 int
1956 i915_add_request(struct intel_ring_buffer *ring,
1957                  struct drm_file *file,
1958                  u32 *out_seqno)
1959 {
1960         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1961         struct drm_i915_gem_request *request;
1962         u32 request_ring_position;
1963         u32 seqno;
1964         int was_empty;
1965         int ret;
1966
1967         /*
1968          * Emit any outstanding flushes - execbuf can fail to emit the flush
1969          * after having emitted the batchbuffer command. Hence we need to fix
1970          * things up similar to emitting the lazy request. The difference here
1971          * is that the flush _must_ happen before the next request, no matter
1972          * what.
1973          */
1974         ret = intel_ring_flush_all_caches(ring);
1975         if (ret)
1976                 return ret;
1977
1978         request = kmalloc(sizeof(*request), GFP_KERNEL);
1979         if (request == NULL)
1980                 return -ENOMEM;
1981
1982         seqno = i915_gem_next_request_seqno(ring);
1983
1984         /* Record the position of the start of the request so that
1985          * should we detect the updated seqno part-way through the
1986          * GPU processing the request, we never over-estimate the
1987          * position of the head.
1988          */
1989         request_ring_position = intel_ring_get_tail(ring);
1990
1991         ret = ring->add_request(ring, &seqno);
1992         if (ret) {
1993                 kfree(request);
1994                 return ret;
1995         }
1996
1997         trace_i915_gem_request_add(ring, seqno);
1998
1999         request->seqno = seqno;
2000         request->ring = ring;
2001         request->tail = request_ring_position;
2002         request->emitted_jiffies = jiffies;
2003         was_empty = list_empty(&ring->request_list);
2004         list_add_tail(&request->list, &ring->request_list);
2005         request->file_priv = NULL;
2006
2007         if (file) {
2008                 struct drm_i915_file_private *file_priv = file->driver_priv;
2009
2010                 spin_lock(&file_priv->mm.lock);
2011                 request->file_priv = file_priv;
2012                 list_add_tail(&request->client_list,
2013                               &file_priv->mm.request_list);
2014                 spin_unlock(&file_priv->mm.lock);
2015         }
2016
2017         ring->outstanding_lazy_request = 0;
2018
2019         if (!dev_priv->mm.suspended) {
2020                 if (i915_enable_hangcheck) {
2021                         mod_timer(&dev_priv->hangcheck_timer,
2022                                   jiffies +
2023                                   msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
2024                 }
2025                 if (was_empty) {
2026                         queue_delayed_work(dev_priv->wq,
2027                                            &dev_priv->mm.retire_work, HZ);
2028                         intel_mark_busy(dev_priv->dev);
2029                 }
2030         }
2031
2032         if (out_seqno)
2033                 *out_seqno = seqno;
2034         return 0;
2035 }
2036
2037 static inline void
2038 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2039 {
2040         struct drm_i915_file_private *file_priv = request->file_priv;
2041
2042         if (!file_priv)
2043                 return;
2044
2045         spin_lock(&file_priv->mm.lock);
2046         if (request->file_priv) {
2047                 list_del(&request->client_list);
2048                 request->file_priv = NULL;
2049         }
2050         spin_unlock(&file_priv->mm.lock);
2051 }
2052
2053 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2054                                       struct intel_ring_buffer *ring)
2055 {
2056         while (!list_empty(&ring->request_list)) {
2057                 struct drm_i915_gem_request *request;
2058
2059                 request = list_first_entry(&ring->request_list,
2060                                            struct drm_i915_gem_request,
2061                                            list);
2062
2063                 list_del(&request->list);
2064                 i915_gem_request_remove_from_client(request);
2065                 kfree(request);
2066         }
2067
2068         while (!list_empty(&ring->active_list)) {
2069                 struct drm_i915_gem_object *obj;
2070
2071                 obj = list_first_entry(&ring->active_list,
2072                                        struct drm_i915_gem_object,
2073                                        ring_list);
2074
2075                 i915_gem_object_move_to_inactive(obj);
2076         }
2077 }
2078
2079 static void i915_gem_reset_fences(struct drm_device *dev)
2080 {
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         int i;
2083
2084         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2085                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2086
2087                 i915_gem_write_fence(dev, i, NULL);
2088
2089                 if (reg->obj)
2090                         i915_gem_object_fence_lost(reg->obj);
2091
2092                 reg->pin_count = 0;
2093                 reg->obj = NULL;
2094                 INIT_LIST_HEAD(&reg->lru_list);
2095         }
2096
2097         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2098 }
2099
2100 void i915_gem_reset(struct drm_device *dev)
2101 {
2102         struct drm_i915_private *dev_priv = dev->dev_private;
2103         struct drm_i915_gem_object *obj;
2104         struct intel_ring_buffer *ring;
2105         int i;
2106
2107         for_each_ring(ring, dev_priv, i)
2108                 i915_gem_reset_ring_lists(dev_priv, ring);
2109
2110         /* Move everything out of the GPU domains to ensure we do any
2111          * necessary invalidation upon reuse.
2112          */
2113         list_for_each_entry(obj,
2114                             &dev_priv->mm.inactive_list,
2115                             mm_list)
2116         {
2117                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2118         }
2119
2120         /* The fence registers are invalidated so clear them out */
2121         i915_gem_reset_fences(dev);
2122 }
2123
2124 /**
2125  * This function clears the request list as sequence numbers are passed.
2126  */
2127 void
2128 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2129 {
2130         uint32_t seqno;
2131         int i;
2132
2133         if (list_empty(&ring->request_list))
2134                 return;
2135
2136         WARN_ON(i915_verify_lists(ring->dev));
2137
2138         seqno = ring->get_seqno(ring, true);
2139
2140         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
2141                 if (seqno >= ring->sync_seqno[i])
2142                         ring->sync_seqno[i] = 0;
2143
2144         while (!list_empty(&ring->request_list)) {
2145                 struct drm_i915_gem_request *request;
2146
2147                 request = list_first_entry(&ring->request_list,
2148                                            struct drm_i915_gem_request,
2149                                            list);
2150
2151                 if (!i915_seqno_passed(seqno, request->seqno))
2152                         break;
2153
2154                 trace_i915_gem_request_retire(ring, request->seqno);
2155                 /* We know the GPU must have read the request to have
2156                  * sent us the seqno + interrupt, so use the position
2157                  * of tail of the request to update the last known position
2158                  * of the GPU head.
2159                  */
2160                 ring->last_retired_head = request->tail;
2161
2162                 list_del(&request->list);
2163                 i915_gem_request_remove_from_client(request);
2164                 kfree(request);
2165         }
2166
2167         /* Move any buffers on the active list that are no longer referenced
2168          * by the ringbuffer to the flushing/inactive lists as appropriate.
2169          */
2170         while (!list_empty(&ring->active_list)) {
2171                 struct drm_i915_gem_object *obj;
2172
2173                 obj = list_first_entry(&ring->active_list,
2174                                       struct drm_i915_gem_object,
2175                                       ring_list);
2176
2177                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2178                         break;
2179
2180                 i915_gem_object_move_to_inactive(obj);
2181         }
2182
2183         if (unlikely(ring->trace_irq_seqno &&
2184                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2185                 ring->irq_put(ring);
2186                 ring->trace_irq_seqno = 0;
2187         }
2188
2189         WARN_ON(i915_verify_lists(ring->dev));
2190 }
2191
2192 void
2193 i915_gem_retire_requests(struct drm_device *dev)
2194 {
2195         drm_i915_private_t *dev_priv = dev->dev_private;
2196         struct intel_ring_buffer *ring;
2197         int i;
2198
2199         for_each_ring(ring, dev_priv, i)
2200                 i915_gem_retire_requests_ring(ring);
2201 }
2202
2203 static void
2204 i915_gem_retire_work_handler(struct work_struct *work)
2205 {
2206         drm_i915_private_t *dev_priv;
2207         struct drm_device *dev;
2208         struct intel_ring_buffer *ring;
2209         bool idle;
2210         int i;
2211
2212         dev_priv = container_of(work, drm_i915_private_t,
2213                                 mm.retire_work.work);
2214         dev = dev_priv->dev;
2215
2216         /* Come back later if the device is busy... */
2217         if (!mutex_trylock(&dev->struct_mutex)) {
2218                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2219                 return;
2220         }
2221
2222         i915_gem_retire_requests(dev);
2223
2224         /* Send a periodic flush down the ring so we don't hold onto GEM
2225          * objects indefinitely.
2226          */
2227         idle = true;
2228         for_each_ring(ring, dev_priv, i) {
2229                 if (ring->gpu_caches_dirty)
2230                         i915_add_request(ring, NULL, NULL);
2231
2232                 idle &= list_empty(&ring->request_list);
2233         }
2234
2235         if (!dev_priv->mm.suspended && !idle)
2236                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2237         if (idle)
2238                 intel_mark_idle(dev);
2239
2240         mutex_unlock(&dev->struct_mutex);
2241 }
2242
2243 /**
2244  * Ensures that an object will eventually get non-busy by flushing any required
2245  * write domains, emitting any outstanding lazy request and retiring and
2246  * completed requests.
2247  */
2248 static int
2249 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2250 {
2251         int ret;
2252
2253         if (obj->active) {
2254                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2255                 if (ret)
2256                         return ret;
2257
2258                 i915_gem_retire_requests_ring(obj->ring);
2259         }
2260
2261         return 0;
2262 }
2263
2264 /**
2265  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2266  * @DRM_IOCTL_ARGS: standard ioctl arguments
2267  *
2268  * Returns 0 if successful, else an error is returned with the remaining time in
2269  * the timeout parameter.
2270  *  -ETIME: object is still busy after timeout
2271  *  -ERESTARTSYS: signal interrupted the wait
2272  *  -ENONENT: object doesn't exist
2273  * Also possible, but rare:
2274  *  -EAGAIN: GPU wedged
2275  *  -ENOMEM: damn
2276  *  -ENODEV: Internal IRQ fail
2277  *  -E?: The add request failed
2278  *
2279  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2280  * non-zero timeout parameter the wait ioctl will wait for the given number of
2281  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2282  * without holding struct_mutex the object may become re-busied before this
2283  * function completes. A similar but shorter * race condition exists in the busy
2284  * ioctl
2285  */
2286 int
2287 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2288 {
2289         struct drm_i915_gem_wait *args = data;
2290         struct drm_i915_gem_object *obj;
2291         struct intel_ring_buffer *ring = NULL;
2292         struct timespec timeout_stack, *timeout = NULL;
2293         u32 seqno = 0;
2294         int ret = 0;
2295
2296         if (args->timeout_ns >= 0) {
2297                 timeout_stack = ns_to_timespec(args->timeout_ns);
2298                 timeout = &timeout_stack;
2299         }
2300
2301         ret = i915_mutex_lock_interruptible(dev);
2302         if (ret)
2303                 return ret;
2304
2305         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2306         if (&obj->base == NULL) {
2307                 mutex_unlock(&dev->struct_mutex);
2308                 return -ENOENT;
2309         }
2310
2311         /* Need to make sure the object gets inactive eventually. */
2312         ret = i915_gem_object_flush_active(obj);
2313         if (ret)
2314                 goto out;
2315
2316         if (obj->active) {
2317                 seqno = obj->last_read_seqno;
2318                 ring = obj->ring;
2319         }
2320
2321         if (seqno == 0)
2322                  goto out;
2323
2324         /* Do this after OLR check to make sure we make forward progress polling
2325          * on this IOCTL with a 0 timeout (like busy ioctl)
2326          */
2327         if (!args->timeout_ns) {
2328                 ret = -ETIME;
2329                 goto out;
2330         }
2331
2332         drm_gem_object_unreference(&obj->base);
2333         mutex_unlock(&dev->struct_mutex);
2334
2335         ret = __wait_seqno(ring, seqno, true, timeout);
2336         if (timeout) {
2337                 WARN_ON(!timespec_valid(timeout));
2338                 args->timeout_ns = timespec_to_ns(timeout);
2339         }
2340         return ret;
2341
2342 out:
2343         drm_gem_object_unreference(&obj->base);
2344         mutex_unlock(&dev->struct_mutex);
2345         return ret;
2346 }
2347
2348 /**
2349  * i915_gem_object_sync - sync an object to a ring.
2350  *
2351  * @obj: object which may be in use on another ring.
2352  * @to: ring we wish to use the object on. May be NULL.
2353  *
2354  * This code is meant to abstract object synchronization with the GPU.
2355  * Calling with NULL implies synchronizing the object with the CPU
2356  * rather than a particular GPU ring.
2357  *
2358  * Returns 0 if successful, else propagates up the lower layer error.
2359  */
2360 int
2361 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2362                      struct intel_ring_buffer *to)
2363 {
2364         struct intel_ring_buffer *from = obj->ring;
2365         u32 seqno;
2366         int ret, idx;
2367
2368         if (from == NULL || to == from)
2369                 return 0;
2370
2371         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2372                 return i915_gem_object_wait_rendering(obj, false);
2373
2374         idx = intel_ring_sync_index(from, to);
2375
2376         seqno = obj->last_read_seqno;
2377         if (seqno <= from->sync_seqno[idx])
2378                 return 0;
2379
2380         ret = i915_gem_check_olr(obj->ring, seqno);
2381         if (ret)
2382                 return ret;
2383
2384         ret = to->sync_to(to, from, seqno);
2385         if (!ret)
2386                 from->sync_seqno[idx] = seqno;
2387
2388         return ret;
2389 }
2390
2391 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2392 {
2393         u32 old_write_domain, old_read_domains;
2394
2395         /* Act a barrier for all accesses through the GTT */
2396         mb();
2397
2398         /* Force a pagefault for domain tracking on next user access */
2399         i915_gem_release_mmap(obj);
2400
2401         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2402                 return;
2403
2404         old_read_domains = obj->base.read_domains;
2405         old_write_domain = obj->base.write_domain;
2406
2407         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2408         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2409
2410         trace_i915_gem_object_change_domain(obj,
2411                                             old_read_domains,
2412                                             old_write_domain);
2413 }
2414
2415 /**
2416  * Unbinds an object from the GTT aperture.
2417  */
2418 int
2419 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2420 {
2421         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2422         int ret = 0;
2423
2424         if (obj->gtt_space == NULL)
2425                 return 0;
2426
2427         if (obj->pin_count)
2428                 return -EBUSY;
2429
2430         BUG_ON(obj->pages == NULL);
2431
2432         ret = i915_gem_object_finish_gpu(obj);
2433         if (ret)
2434                 return ret;
2435         /* Continue on if we fail due to EIO, the GPU is hung so we
2436          * should be safe and we need to cleanup or else we might
2437          * cause memory corruption through use-after-free.
2438          */
2439
2440         i915_gem_object_finish_gtt(obj);
2441
2442         /* release the fence reg _after_ flushing */
2443         ret = i915_gem_object_put_fence(obj);
2444         if (ret)
2445                 return ret;
2446
2447         trace_i915_gem_object_unbind(obj);
2448
2449         if (obj->has_global_gtt_mapping)
2450                 i915_gem_gtt_unbind_object(obj);
2451         if (obj->has_aliasing_ppgtt_mapping) {
2452                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2453                 obj->has_aliasing_ppgtt_mapping = 0;
2454         }
2455         i915_gem_gtt_finish_object(obj);
2456
2457         list_del(&obj->mm_list);
2458         list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2459         /* Avoid an unnecessary call to unbind on rebind. */
2460         obj->map_and_fenceable = true;
2461
2462         drm_mm_put_block(obj->gtt_space);
2463         obj->gtt_space = NULL;
2464         obj->gtt_offset = 0;
2465
2466         return 0;
2467 }
2468
2469 static int i915_ring_idle(struct intel_ring_buffer *ring)
2470 {
2471         if (list_empty(&ring->active_list))
2472                 return 0;
2473
2474         return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
2475 }
2476
2477 int i915_gpu_idle(struct drm_device *dev)
2478 {
2479         drm_i915_private_t *dev_priv = dev->dev_private;
2480         struct intel_ring_buffer *ring;
2481         int ret, i;
2482
2483         /* Flush everything onto the inactive list. */
2484         for_each_ring(ring, dev_priv, i) {
2485                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2486                 if (ret)
2487                         return ret;
2488
2489                 ret = i915_ring_idle(ring);
2490                 if (ret)
2491                         return ret;
2492         }
2493
2494         return 0;
2495 }
2496
2497 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2498                                         struct drm_i915_gem_object *obj)
2499 {
2500         drm_i915_private_t *dev_priv = dev->dev_private;
2501         uint64_t val;
2502
2503         if (obj) {
2504                 u32 size = obj->gtt_space->size;
2505
2506                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2507                                  0xfffff000) << 32;
2508                 val |= obj->gtt_offset & 0xfffff000;
2509                 val |= (uint64_t)((obj->stride / 128) - 1) <<
2510                         SANDYBRIDGE_FENCE_PITCH_SHIFT;
2511
2512                 if (obj->tiling_mode == I915_TILING_Y)
2513                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2514                 val |= I965_FENCE_REG_VALID;
2515         } else
2516                 val = 0;
2517
2518         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2519         POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2520 }
2521
2522 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2523                                  struct drm_i915_gem_object *obj)
2524 {
2525         drm_i915_private_t *dev_priv = dev->dev_private;
2526         uint64_t val;
2527
2528         if (obj) {
2529                 u32 size = obj->gtt_space->size;
2530
2531                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2532                                  0xfffff000) << 32;
2533                 val |= obj->gtt_offset & 0xfffff000;
2534                 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2535                 if (obj->tiling_mode == I915_TILING_Y)
2536                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2537                 val |= I965_FENCE_REG_VALID;
2538         } else
2539                 val = 0;
2540
2541         I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2542         POSTING_READ(FENCE_REG_965_0 + reg * 8);
2543 }
2544
2545 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2546                                  struct drm_i915_gem_object *obj)
2547 {
2548         drm_i915_private_t *dev_priv = dev->dev_private;
2549         u32 val;
2550
2551         if (obj) {
2552                 u32 size = obj->gtt_space->size;
2553                 int pitch_val;
2554                 int tile_width;
2555
2556                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2557                      (size & -size) != size ||
2558                      (obj->gtt_offset & (size - 1)),
2559                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2560                      obj->gtt_offset, obj->map_and_fenceable, size);
2561
2562                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2563                         tile_width = 128;
2564                 else
2565                         tile_width = 512;
2566
2567                 /* Note: pitch better be a power of two tile widths */
2568                 pitch_val = obj->stride / tile_width;
2569                 pitch_val = ffs(pitch_val) - 1;
2570
2571                 val = obj->gtt_offset;
2572                 if (obj->tiling_mode == I915_TILING_Y)
2573                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2574                 val |= I915_FENCE_SIZE_BITS(size);
2575                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2576                 val |= I830_FENCE_REG_VALID;
2577         } else
2578                 val = 0;
2579
2580         if (reg < 8)
2581                 reg = FENCE_REG_830_0 + reg * 4;
2582         else
2583                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2584
2585         I915_WRITE(reg, val);
2586         POSTING_READ(reg);
2587 }
2588
2589 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2590                                 struct drm_i915_gem_object *obj)
2591 {
2592         drm_i915_private_t *dev_priv = dev->dev_private;
2593         uint32_t val;
2594
2595         if (obj) {
2596                 u32 size = obj->gtt_space->size;
2597                 uint32_t pitch_val;
2598
2599                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2600                      (size & -size) != size ||
2601                      (obj->gtt_offset & (size - 1)),
2602                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2603                      obj->gtt_offset, size);
2604
2605                 pitch_val = obj->stride / 128;
2606                 pitch_val = ffs(pitch_val) - 1;
2607
2608                 val = obj->gtt_offset;
2609                 if (obj->tiling_mode == I915_TILING_Y)
2610                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2611                 val |= I830_FENCE_SIZE_BITS(size);
2612                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2613                 val |= I830_FENCE_REG_VALID;
2614         } else
2615                 val = 0;
2616
2617         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2618         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2619 }
2620
2621 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2622                                  struct drm_i915_gem_object *obj)
2623 {
2624         switch (INTEL_INFO(dev)->gen) {
2625         case 7:
2626         case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2627         case 5:
2628         case 4: i965_write_fence_reg(dev, reg, obj); break;
2629         case 3: i915_write_fence_reg(dev, reg, obj); break;
2630         case 2: i830_write_fence_reg(dev, reg, obj); break;
2631         default: break;
2632         }
2633 }
2634
2635 static inline int fence_number(struct drm_i915_private *dev_priv,
2636                                struct drm_i915_fence_reg *fence)
2637 {
2638         return fence - dev_priv->fence_regs;
2639 }
2640
2641 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2642                                          struct drm_i915_fence_reg *fence,
2643                                          bool enable)
2644 {
2645         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2646         int reg = fence_number(dev_priv, fence);
2647
2648         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2649
2650         if (enable) {
2651                 obj->fence_reg = reg;
2652                 fence->obj = obj;
2653                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2654         } else {
2655                 obj->fence_reg = I915_FENCE_REG_NONE;
2656                 fence->obj = NULL;
2657                 list_del_init(&fence->lru_list);
2658         }
2659 }
2660
2661 static int
2662 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2663 {
2664         if (obj->last_fenced_seqno) {
2665                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2666                 if (ret)
2667                         return ret;
2668
2669                 obj->last_fenced_seqno = 0;
2670         }
2671
2672         /* Ensure that all CPU reads are completed before installing a fence
2673          * and all writes before removing the fence.
2674          */
2675         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2676                 mb();
2677
2678         obj->fenced_gpu_access = false;
2679         return 0;
2680 }
2681
2682 int
2683 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2684 {
2685         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2686         int ret;
2687
2688         ret = i915_gem_object_flush_fence(obj);
2689         if (ret)
2690                 return ret;
2691
2692         if (obj->fence_reg == I915_FENCE_REG_NONE)
2693                 return 0;
2694
2695         i915_gem_object_update_fence(obj,
2696                                      &dev_priv->fence_regs[obj->fence_reg],
2697                                      false);
2698         i915_gem_object_fence_lost(obj);
2699
2700         return 0;
2701 }
2702
2703 static struct drm_i915_fence_reg *
2704 i915_find_fence_reg(struct drm_device *dev)
2705 {
2706         struct drm_i915_private *dev_priv = dev->dev_private;
2707         struct drm_i915_fence_reg *reg, *avail;
2708         int i;
2709
2710         /* First try to find a free reg */
2711         avail = NULL;
2712         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2713                 reg = &dev_priv->fence_regs[i];
2714                 if (!reg->obj)
2715                         return reg;
2716
2717                 if (!reg->pin_count)
2718                         avail = reg;
2719         }
2720
2721         if (avail == NULL)
2722                 return NULL;
2723
2724         /* None available, try to steal one or wait for a user to finish */
2725         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2726                 if (reg->pin_count)
2727                         continue;
2728
2729                 return reg;
2730         }
2731
2732         return NULL;
2733 }
2734
2735 /**
2736  * i915_gem_object_get_fence - set up fencing for an object
2737  * @obj: object to map through a fence reg
2738  *
2739  * When mapping objects through the GTT, userspace wants to be able to write
2740  * to them without having to worry about swizzling if the object is tiled.
2741  * This function walks the fence regs looking for a free one for @obj,
2742  * stealing one if it can't find any.
2743  *
2744  * It then sets up the reg based on the object's properties: address, pitch
2745  * and tiling format.
2746  *
2747  * For an untiled surface, this removes any existing fence.
2748  */
2749 int
2750 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2751 {
2752         struct drm_device *dev = obj->base.dev;
2753         struct drm_i915_private *dev_priv = dev->dev_private;
2754         bool enable = obj->tiling_mode != I915_TILING_NONE;
2755         struct drm_i915_fence_reg *reg;
2756         int ret;
2757
2758         /* Have we updated the tiling parameters upon the object and so
2759          * will need to serialise the write to the associated fence register?
2760          */
2761         if (obj->fence_dirty) {
2762                 ret = i915_gem_object_flush_fence(obj);
2763                 if (ret)
2764                         return ret;
2765         }
2766
2767         /* Just update our place in the LRU if our fence is getting reused. */
2768         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2769                 reg = &dev_priv->fence_regs[obj->fence_reg];
2770                 if (!obj->fence_dirty) {
2771                         list_move_tail(&reg->lru_list,
2772                                        &dev_priv->mm.fence_list);
2773                         return 0;
2774                 }
2775         } else if (enable) {
2776                 reg = i915_find_fence_reg(dev);
2777                 if (reg == NULL)
2778                         return -EDEADLK;
2779
2780                 if (reg->obj) {
2781                         struct drm_i915_gem_object *old = reg->obj;
2782
2783                         ret = i915_gem_object_flush_fence(old);
2784                         if (ret)
2785                                 return ret;
2786
2787                         i915_gem_object_fence_lost(old);
2788                 }
2789         } else
2790                 return 0;
2791
2792         i915_gem_object_update_fence(obj, reg, enable);
2793         obj->fence_dirty = false;
2794
2795         return 0;
2796 }
2797
2798 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2799                                      struct drm_mm_node *gtt_space,
2800                                      unsigned long cache_level)
2801 {
2802         struct drm_mm_node *other;
2803
2804         /* On non-LLC machines we have to be careful when putting differing
2805          * types of snoopable memory together to avoid the prefetcher
2806          * crossing memory domains and dieing.
2807          */
2808         if (HAS_LLC(dev))
2809                 return true;
2810
2811         if (gtt_space == NULL)
2812                 return true;
2813
2814         if (list_empty(&gtt_space->node_list))
2815                 return true;
2816
2817         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2818         if (other->allocated && !other->hole_follows && other->color != cache_level)
2819                 return false;
2820
2821         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2822         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2823                 return false;
2824
2825         return true;
2826 }
2827
2828 static void i915_gem_verify_gtt(struct drm_device *dev)
2829 {
2830 #if WATCH_GTT
2831         struct drm_i915_private *dev_priv = dev->dev_private;
2832         struct drm_i915_gem_object *obj;
2833         int err = 0;
2834
2835         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2836                 if (obj->gtt_space == NULL) {
2837                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
2838                         err++;
2839                         continue;
2840                 }
2841
2842                 if (obj->cache_level != obj->gtt_space->color) {
2843                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2844                                obj->gtt_space->start,
2845                                obj->gtt_space->start + obj->gtt_space->size,
2846                                obj->cache_level,
2847                                obj->gtt_space->color);
2848                         err++;
2849                         continue;
2850                 }
2851
2852                 if (!i915_gem_valid_gtt_space(dev,
2853                                               obj->gtt_space,
2854                                               obj->cache_level)) {
2855                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2856                                obj->gtt_space->start,
2857                                obj->gtt_space->start + obj->gtt_space->size,
2858                                obj->cache_level);
2859                         err++;
2860                         continue;
2861                 }
2862         }
2863
2864         WARN_ON(err);
2865 #endif
2866 }
2867
2868 /**
2869  * Finds free space in the GTT aperture and binds the object there.
2870  */
2871 static int
2872 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2873                             unsigned alignment,
2874                             bool map_and_fenceable,
2875                             bool nonblocking)
2876 {
2877         struct drm_device *dev = obj->base.dev;
2878         drm_i915_private_t *dev_priv = dev->dev_private;
2879         struct drm_mm_node *free_space;
2880         u32 size, fence_size, fence_alignment, unfenced_alignment;
2881         bool mappable, fenceable;
2882         int ret;
2883
2884         if (obj->madv != I915_MADV_WILLNEED) {
2885                 DRM_ERROR("Attempting to bind a purgeable object\n");
2886                 return -EINVAL;
2887         }
2888
2889         fence_size = i915_gem_get_gtt_size(dev,
2890                                            obj->base.size,
2891                                            obj->tiling_mode);
2892         fence_alignment = i915_gem_get_gtt_alignment(dev,
2893                                                      obj->base.size,
2894                                                      obj->tiling_mode);
2895         unfenced_alignment =
2896                 i915_gem_get_unfenced_gtt_alignment(dev,
2897                                                     obj->base.size,
2898                                                     obj->tiling_mode);
2899
2900         if (alignment == 0)
2901                 alignment = map_and_fenceable ? fence_alignment :
2902                                                 unfenced_alignment;
2903         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2904                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2905                 return -EINVAL;
2906         }
2907
2908         size = map_and_fenceable ? fence_size : obj->base.size;
2909
2910         /* If the object is bigger than the entire aperture, reject it early
2911          * before evicting everything in a vain attempt to find space.
2912          */
2913         if (obj->base.size >
2914             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2915                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2916                 return -E2BIG;
2917         }
2918
2919         ret = i915_gem_object_get_pages(obj);
2920         if (ret)
2921                 return ret;
2922
2923  search_free:
2924         if (map_and_fenceable)
2925                 free_space =
2926                         drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2927                                                           size, alignment, obj->cache_level,
2928                                                           0, dev_priv->mm.gtt_mappable_end,
2929                                                           false);
2930         else
2931                 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2932                                                       size, alignment, obj->cache_level,
2933                                                       false);
2934
2935         if (free_space != NULL) {
2936                 if (map_and_fenceable)
2937                         obj->gtt_space =
2938                                 drm_mm_get_block_range_generic(free_space,
2939                                                                size, alignment, obj->cache_level,
2940                                                                0, dev_priv->mm.gtt_mappable_end,
2941                                                                false);
2942                 else
2943                         obj->gtt_space =
2944                                 drm_mm_get_block_generic(free_space,
2945                                                          size, alignment, obj->cache_level,
2946                                                          false);
2947         }
2948         if (obj->gtt_space == NULL) {
2949                 ret = i915_gem_evict_something(dev, size, alignment,
2950                                                obj->cache_level,
2951                                                map_and_fenceable,
2952                                                nonblocking);
2953                 if (ret)
2954                         return ret;
2955
2956                 goto search_free;
2957         }
2958         if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2959                                               obj->gtt_space,
2960                                               obj->cache_level))) {
2961                 drm_mm_put_block(obj->gtt_space);
2962                 obj->gtt_space = NULL;
2963                 return -EINVAL;
2964         }
2965
2966
2967         ret = i915_gem_gtt_prepare_object(obj);
2968         if (ret) {
2969                 drm_mm_put_block(obj->gtt_space);
2970                 obj->gtt_space = NULL;
2971                 return ret;
2972         }
2973
2974         if (!dev_priv->mm.aliasing_ppgtt)
2975                 i915_gem_gtt_bind_object(obj, obj->cache_level);
2976
2977         list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2978         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2979
2980         obj->gtt_offset = obj->gtt_space->start;
2981
2982         fenceable =
2983                 obj->gtt_space->size == fence_size &&
2984                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2985
2986         mappable =
2987                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2988
2989         obj->map_and_fenceable = mappable && fenceable;
2990
2991         trace_i915_gem_object_bind(obj, map_and_fenceable);
2992         i915_gem_verify_gtt(dev);
2993         return 0;
2994 }
2995
2996 void
2997 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2998 {
2999         /* If we don't have a page list set up, then we're not pinned
3000          * to GPU, and we can ignore the cache flush because it'll happen
3001          * again at bind time.
3002          */
3003         if (obj->pages == NULL)
3004                 return;
3005
3006         /* If the GPU is snooping the contents of the CPU cache,
3007          * we do not need to manually clear the CPU cache lines.  However,
3008          * the caches are only snooped when the render cache is
3009          * flushed/invalidated.  As we always have to emit invalidations
3010          * and flushes when moving into and out of the RENDER domain, correct
3011          * snooping behaviour occurs naturally as the result of our domain
3012          * tracking.
3013          */
3014         if (obj->cache_level != I915_CACHE_NONE)
3015                 return;
3016
3017         trace_i915_gem_object_clflush(obj);
3018
3019         drm_clflush_sg(obj->pages);
3020 }
3021
3022 /** Flushes the GTT write domain for the object if it's dirty. */
3023 static void
3024 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3025 {
3026         uint32_t old_write_domain;
3027
3028         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3029                 return;
3030
3031         /* No actual flushing is required for the GTT write domain.  Writes
3032          * to it immediately go to main memory as far as we know, so there's
3033          * no chipset flush.  It also doesn't land in render cache.
3034          *
3035          * However, we do have to enforce the order so that all writes through
3036          * the GTT land before any writes to the device, such as updates to
3037          * the GATT itself.
3038          */
3039         wmb();
3040
3041         old_write_domain = obj->base.write_domain;
3042         obj->base.write_domain = 0;
3043
3044         trace_i915_gem_object_change_domain(obj,
3045                                             obj->base.read_domains,
3046                                             old_write_domain);
3047 }
3048
3049 /** Flushes the CPU write domain for the object if it's dirty. */
3050 static void
3051 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3052 {
3053         uint32_t old_write_domain;
3054
3055         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3056                 return;
3057
3058         i915_gem_clflush_object(obj);
3059         intel_gtt_chipset_flush();
3060         old_write_domain = obj->base.write_domain;
3061         obj->base.write_domain = 0;
3062
3063         trace_i915_gem_object_change_domain(obj,
3064                                             obj->base.read_domains,
3065                                             old_write_domain);
3066 }
3067
3068 /**
3069  * Moves a single object to the GTT read, and possibly write domain.
3070  *
3071  * This function returns when the move is complete, including waiting on
3072  * flushes to occur.
3073  */
3074 int
3075 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3076 {
3077         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3078         uint32_t old_write_domain, old_read_domains;
3079         int ret;
3080
3081         /* Not valid to be called on unbound objects. */
3082         if (obj->gtt_space == NULL)
3083                 return -EINVAL;
3084
3085         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3086                 return 0;
3087
3088         ret = i915_gem_object_wait_rendering(obj, !write);
3089         if (ret)
3090                 return ret;
3091
3092         i915_gem_object_flush_cpu_write_domain(obj);
3093
3094         old_write_domain = obj->base.write_domain;
3095         old_read_domains = obj->base.read_domains;
3096
3097         /* It should now be out of any other write domains, and we can update
3098          * the domain values for our changes.
3099          */
3100         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3101         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3102         if (write) {
3103                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3104                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3105                 obj->dirty = 1;
3106         }
3107
3108         trace_i915_gem_object_change_domain(obj,
3109                                             old_read_domains,
3110                                             old_write_domain);
3111
3112         /* And bump the LRU for this access */
3113         if (i915_gem_object_is_inactive(obj))
3114                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3115
3116         return 0;
3117 }
3118
3119 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3120                                     enum i915_cache_level cache_level)
3121 {
3122         struct drm_device *dev = obj->base.dev;
3123         drm_i915_private_t *dev_priv = dev->dev_private;
3124         int ret;
3125
3126         if (obj->cache_level == cache_level)
3127                 return 0;
3128
3129         if (obj->pin_count) {
3130                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3131                 return -EBUSY;
3132         }
3133
3134         if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3135                 ret = i915_gem_object_unbind(obj);
3136                 if (ret)
3137                         return ret;
3138         }
3139
3140         if (obj->gtt_space) {
3141                 ret = i915_gem_object_finish_gpu(obj);
3142                 if (ret)
3143                         return ret;
3144
3145                 i915_gem_object_finish_gtt(obj);
3146
3147                 /* Before SandyBridge, you could not use tiling or fence
3148                  * registers with snooped memory, so relinquish any fences
3149                  * currently pointing to our region in the aperture.
3150                  */
3151                 if (INTEL_INFO(dev)->gen < 6) {
3152                         ret = i915_gem_object_put_fence(obj);
3153                         if (ret)
3154                                 return ret;
3155                 }
3156
3157                 if (obj->has_global_gtt_mapping)
3158                         i915_gem_gtt_bind_object(obj, cache_level);
3159                 if (obj->has_aliasing_ppgtt_mapping)
3160                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3161                                                obj, cache_level);
3162
3163                 obj->gtt_space->color = cache_level;
3164         }
3165
3166         if (cache_level == I915_CACHE_NONE) {
3167                 u32 old_read_domains, old_write_domain;
3168
3169                 /* If we're coming from LLC cached, then we haven't
3170                  * actually been tracking whether the data is in the
3171                  * CPU cache or not, since we only allow one bit set
3172                  * in obj->write_domain and have been skipping the clflushes.
3173                  * Just set it to the CPU cache for now.
3174                  */
3175                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3176                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3177
3178                 old_read_domains = obj->base.read_domains;
3179                 old_write_domain = obj->base.write_domain;
3180
3181                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3182                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3183
3184                 trace_i915_gem_object_change_domain(obj,
3185                                                     old_read_domains,
3186                                                     old_write_domain);
3187         }
3188
3189         obj->cache_level = cache_level;
3190         i915_gem_verify_gtt(dev);
3191         return 0;
3192 }
3193
3194 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3195                                struct drm_file *file)
3196 {
3197         struct drm_i915_gem_caching *args = data;
3198         struct drm_i915_gem_object *obj;
3199         int ret;
3200
3201         ret = i915_mutex_lock_interruptible(dev);
3202         if (ret)
3203                 return ret;
3204
3205         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3206         if (&obj->base == NULL) {
3207                 ret = -ENOENT;
3208                 goto unlock;
3209         }
3210
3211         args->caching = obj->cache_level != I915_CACHE_NONE;
3212
3213         drm_gem_object_unreference(&obj->base);
3214 unlock:
3215         mutex_unlock(&dev->struct_mutex);
3216         return ret;
3217 }
3218
3219 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3220                                struct drm_file *file)
3221 {
3222         struct drm_i915_gem_caching *args = data;
3223         struct drm_i915_gem_object *obj;
3224         enum i915_cache_level level;
3225         int ret;
3226
3227         switch (args->caching) {
3228         case I915_CACHING_NONE:
3229                 level = I915_CACHE_NONE;
3230                 break;
3231         case I915_CACHING_CACHED:
3232                 level = I915_CACHE_LLC;
3233                 break;
3234         default:
3235                 return -EINVAL;
3236         }
3237
3238         ret = i915_mutex_lock_interruptible(dev);
3239         if (ret)
3240                 return ret;
3241
3242         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3243         if (&obj->base == NULL) {
3244                 ret = -ENOENT;
3245                 goto unlock;
3246         }
3247
3248         ret = i915_gem_object_set_cache_level(obj, level);
3249
3250         drm_gem_object_unreference(&obj->base);
3251 unlock:
3252         mutex_unlock(&dev->struct_mutex);
3253         return ret;
3254 }
3255
3256 /*
3257  * Prepare buffer for display plane (scanout, cursors, etc).
3258  * Can be called from an uninterruptible phase (modesetting) and allows
3259  * any flushes to be pipelined (for pageflips).
3260  */
3261 int
3262 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3263                                      u32 alignment,
3264                                      struct intel_ring_buffer *pipelined)
3265 {
3266         u32 old_read_domains, old_write_domain;
3267         int ret;
3268
3269         if (pipelined != obj->ring) {
3270                 ret = i915_gem_object_sync(obj, pipelined);
3271                 if (ret)
3272                         return ret;
3273         }
3274
3275         /* The display engine is not coherent with the LLC cache on gen6.  As
3276          * a result, we make sure that the pinning that is about to occur is
3277          * done with uncached PTEs. This is lowest common denominator for all
3278          * chipsets.
3279          *
3280          * However for gen6+, we could do better by using the GFDT bit instead
3281          * of uncaching, which would allow us to flush all the LLC-cached data
3282          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3283          */
3284         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3285         if (ret)
3286                 return ret;
3287
3288         /* As the user may map the buffer once pinned in the display plane
3289          * (e.g. libkms for the