a9fb046b94a140ab169cbd2eb016922fc702dd98
[~shefty/rdma-dev.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49         /* given values */
50         int n;
51         int m1, m2;
52         int p1, p2;
53         /* derived values */
54         int     dot;
55         int     vco;
56         int     m;
57         int     p;
58 } intel_clock_t;
59
60 typedef struct {
61         int     min, max;
62 } intel_range_t;
63
64 typedef struct {
65         int     dot_limit;
66         int     p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM                  2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
73         intel_p2_t          p2;
74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75                         int, int, intel_clock_t *, intel_clock_t *);
76 };
77
78 /* FDI */
79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
80
81 int
82 intel_pch_rawclk(struct drm_device *dev)
83 {
84         struct drm_i915_private *dev_priv = dev->dev_private;
85
86         WARN_ON(!HAS_PCH_SPLIT(dev));
87
88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89 }
90
91 static bool
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93                     int target, int refclk, intel_clock_t *match_clock,
94                     intel_clock_t *best_clock);
95 static bool
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97                         int target, int refclk, intel_clock_t *match_clock,
98                         intel_clock_t *best_clock);
99
100 static bool
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102                       int target, int refclk, intel_clock_t *match_clock,
103                       intel_clock_t *best_clock);
104 static bool
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106                            int target, int refclk, intel_clock_t *match_clock,
107                            intel_clock_t *best_clock);
108
109 static bool
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111                         int target, int refclk, intel_clock_t *match_clock,
112                         intel_clock_t *best_clock);
113
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
116 {
117         if (IS_GEN5(dev)) {
118                 struct drm_i915_private *dev_priv = dev->dev_private;
119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120         } else
121                 return 27;
122 }
123
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125         .dot = { .min = 25000, .max = 350000 },
126         .vco = { .min = 930000, .max = 1400000 },
127         .n = { .min = 3, .max = 16 },
128         .m = { .min = 96, .max = 140 },
129         .m1 = { .min = 18, .max = 26 },
130         .m2 = { .min = 6, .max = 16 },
131         .p = { .min = 4, .max = 128 },
132         .p1 = { .min = 2, .max = 33 },
133         .p2 = { .dot_limit = 165000,
134                 .p2_slow = 4, .p2_fast = 2 },
135         .find_pll = intel_find_best_PLL,
136 };
137
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139         .dot = { .min = 25000, .max = 350000 },
140         .vco = { .min = 930000, .max = 1400000 },
141         .n = { .min = 3, .max = 16 },
142         .m = { .min = 96, .max = 140 },
143         .m1 = { .min = 18, .max = 26 },
144         .m2 = { .min = 6, .max = 16 },
145         .p = { .min = 4, .max = 128 },
146         .p1 = { .min = 1, .max = 6 },
147         .p2 = { .dot_limit = 165000,
148                 .p2_slow = 14, .p2_fast = 7 },
149         .find_pll = intel_find_best_PLL,
150 };
151
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153         .dot = { .min = 20000, .max = 400000 },
154         .vco = { .min = 1400000, .max = 2800000 },
155         .n = { .min = 1, .max = 6 },
156         .m = { .min = 70, .max = 120 },
157         .m1 = { .min = 10, .max = 22 },
158         .m2 = { .min = 5, .max = 9 },
159         .p = { .min = 5, .max = 80 },
160         .p1 = { .min = 1, .max = 8 },
161         .p2 = { .dot_limit = 200000,
162                 .p2_slow = 10, .p2_fast = 5 },
163         .find_pll = intel_find_best_PLL,
164 };
165
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167         .dot = { .min = 20000, .max = 400000 },
168         .vco = { .min = 1400000, .max = 2800000 },
169         .n = { .min = 1, .max = 6 },
170         .m = { .min = 70, .max = 120 },
171         .m1 = { .min = 10, .max = 22 },
172         .m2 = { .min = 5, .max = 9 },
173         .p = { .min = 7, .max = 98 },
174         .p1 = { .min = 1, .max = 8 },
175         .p2 = { .dot_limit = 112000,
176                 .p2_slow = 14, .p2_fast = 7 },
177         .find_pll = intel_find_best_PLL,
178 };
179
180
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182         .dot = { .min = 25000, .max = 270000 },
183         .vco = { .min = 1750000, .max = 3500000},
184         .n = { .min = 1, .max = 4 },
185         .m = { .min = 104, .max = 138 },
186         .m1 = { .min = 17, .max = 23 },
187         .m2 = { .min = 5, .max = 11 },
188         .p = { .min = 10, .max = 30 },
189         .p1 = { .min = 1, .max = 3},
190         .p2 = { .dot_limit = 270000,
191                 .p2_slow = 10,
192                 .p2_fast = 10
193         },
194         .find_pll = intel_g4x_find_best_PLL,
195 };
196
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198         .dot = { .min = 22000, .max = 400000 },
199         .vco = { .min = 1750000, .max = 3500000},
200         .n = { .min = 1, .max = 4 },
201         .m = { .min = 104, .max = 138 },
202         .m1 = { .min = 16, .max = 23 },
203         .m2 = { .min = 5, .max = 11 },
204         .p = { .min = 5, .max = 80 },
205         .p1 = { .min = 1, .max = 8},
206         .p2 = { .dot_limit = 165000,
207                 .p2_slow = 10, .p2_fast = 5 },
208         .find_pll = intel_g4x_find_best_PLL,
209 };
210
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212         .dot = { .min = 20000, .max = 115000 },
213         .vco = { .min = 1750000, .max = 3500000 },
214         .n = { .min = 1, .max = 3 },
215         .m = { .min = 104, .max = 138 },
216         .m1 = { .min = 17, .max = 23 },
217         .m2 = { .min = 5, .max = 11 },
218         .p = { .min = 28, .max = 112 },
219         .p1 = { .min = 2, .max = 8 },
220         .p2 = { .dot_limit = 0,
221                 .p2_slow = 14, .p2_fast = 14
222         },
223         .find_pll = intel_g4x_find_best_PLL,
224 };
225
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227         .dot = { .min = 80000, .max = 224000 },
228         .vco = { .min = 1750000, .max = 3500000 },
229         .n = { .min = 1, .max = 3 },
230         .m = { .min = 104, .max = 138 },
231         .m1 = { .min = 17, .max = 23 },
232         .m2 = { .min = 5, .max = 11 },
233         .p = { .min = 14, .max = 42 },
234         .p1 = { .min = 2, .max = 6 },
235         .p2 = { .dot_limit = 0,
236                 .p2_slow = 7, .p2_fast = 7
237         },
238         .find_pll = intel_g4x_find_best_PLL,
239 };
240
241 static const intel_limit_t intel_limits_g4x_display_port = {
242         .dot = { .min = 161670, .max = 227000 },
243         .vco = { .min = 1750000, .max = 3500000},
244         .n = { .min = 1, .max = 2 },
245         .m = { .min = 97, .max = 108 },
246         .m1 = { .min = 0x10, .max = 0x12 },
247         .m2 = { .min = 0x05, .max = 0x06 },
248         .p = { .min = 10, .max = 20 },
249         .p1 = { .min = 1, .max = 2},
250         .p2 = { .dot_limit = 0,
251                 .p2_slow = 10, .p2_fast = 10 },
252         .find_pll = intel_find_pll_g4x_dp,
253 };
254
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256         .dot = { .min = 20000, .max = 400000},
257         .vco = { .min = 1700000, .max = 3500000 },
258         /* Pineview's Ncounter is a ring counter */
259         .n = { .min = 3, .max = 6 },
260         .m = { .min = 2, .max = 256 },
261         /* Pineview only has one combined m divider, which we treat as m2. */
262         .m1 = { .min = 0, .max = 0 },
263         .m2 = { .min = 0, .max = 254 },
264         .p = { .min = 5, .max = 80 },
265         .p1 = { .min = 1, .max = 8 },
266         .p2 = { .dot_limit = 200000,
267                 .p2_slow = 10, .p2_fast = 5 },
268         .find_pll = intel_find_best_PLL,
269 };
270
271 static const intel_limit_t intel_limits_pineview_lvds = {
272         .dot = { .min = 20000, .max = 400000 },
273         .vco = { .min = 1700000, .max = 3500000 },
274         .n = { .min = 3, .max = 6 },
275         .m = { .min = 2, .max = 256 },
276         .m1 = { .min = 0, .max = 0 },
277         .m2 = { .min = 0, .max = 254 },
278         .p = { .min = 7, .max = 112 },
279         .p1 = { .min = 1, .max = 8 },
280         .p2 = { .dot_limit = 112000,
281                 .p2_slow = 14, .p2_fast = 14 },
282         .find_pll = intel_find_best_PLL,
283 };
284
285 /* Ironlake / Sandybridge
286  *
287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
288  * the range value for them is (actual_value - 2).
289  */
290 static const intel_limit_t intel_limits_ironlake_dac = {
291         .dot = { .min = 25000, .max = 350000 },
292         .vco = { .min = 1760000, .max = 3510000 },
293         .n = { .min = 1, .max = 5 },
294         .m = { .min = 79, .max = 127 },
295         .m1 = { .min = 12, .max = 22 },
296         .m2 = { .min = 5, .max = 9 },
297         .p = { .min = 5, .max = 80 },
298         .p1 = { .min = 1, .max = 8 },
299         .p2 = { .dot_limit = 225000,
300                 .p2_slow = 10, .p2_fast = 5 },
301         .find_pll = intel_g4x_find_best_PLL,
302 };
303
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305         .dot = { .min = 25000, .max = 350000 },
306         .vco = { .min = 1760000, .max = 3510000 },
307         .n = { .min = 1, .max = 3 },
308         .m = { .min = 79, .max = 118 },
309         .m1 = { .min = 12, .max = 22 },
310         .m2 = { .min = 5, .max = 9 },
311         .p = { .min = 28, .max = 112 },
312         .p1 = { .min = 2, .max = 8 },
313         .p2 = { .dot_limit = 225000,
314                 .p2_slow = 14, .p2_fast = 14 },
315         .find_pll = intel_g4x_find_best_PLL,
316 };
317
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319         .dot = { .min = 25000, .max = 350000 },
320         .vco = { .min = 1760000, .max = 3510000 },
321         .n = { .min = 1, .max = 3 },
322         .m = { .min = 79, .max = 127 },
323         .m1 = { .min = 12, .max = 22 },
324         .m2 = { .min = 5, .max = 9 },
325         .p = { .min = 14, .max = 56 },
326         .p1 = { .min = 2, .max = 8 },
327         .p2 = { .dot_limit = 225000,
328                 .p2_slow = 7, .p2_fast = 7 },
329         .find_pll = intel_g4x_find_best_PLL,
330 };
331
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334         .dot = { .min = 25000, .max = 350000 },
335         .vco = { .min = 1760000, .max = 3510000 },
336         .n = { .min = 1, .max = 2 },
337         .m = { .min = 79, .max = 126 },
338         .m1 = { .min = 12, .max = 22 },
339         .m2 = { .min = 5, .max = 9 },
340         .p = { .min = 28, .max = 112 },
341         .p1 = { .min = 2, .max = 8 },
342         .p2 = { .dot_limit = 225000,
343                 .p2_slow = 14, .p2_fast = 14 },
344         .find_pll = intel_g4x_find_best_PLL,
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348         .dot = { .min = 25000, .max = 350000 },
349         .vco = { .min = 1760000, .max = 3510000 },
350         .n = { .min = 1, .max = 3 },
351         .m = { .min = 79, .max = 126 },
352         .m1 = { .min = 12, .max = 22 },
353         .m2 = { .min = 5, .max = 9 },
354         .p = { .min = 14, .max = 42 },
355         .p1 = { .min = 2, .max = 6 },
356         .p2 = { .dot_limit = 225000,
357                 .p2_slow = 7, .p2_fast = 7 },
358         .find_pll = intel_g4x_find_best_PLL,
359 };
360
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362         .dot = { .min = 25000, .max = 350000 },
363         .vco = { .min = 1760000, .max = 3510000},
364         .n = { .min = 1, .max = 2 },
365         .m = { .min = 81, .max = 90 },
366         .m1 = { .min = 12, .max = 22 },
367         .m2 = { .min = 5, .max = 9 },
368         .p = { .min = 10, .max = 20 },
369         .p1 = { .min = 1, .max = 2},
370         .p2 = { .dot_limit = 0,
371                 .p2_slow = 10, .p2_fast = 10 },
372         .find_pll = intel_find_pll_ironlake_dp,
373 };
374
375 static const intel_limit_t intel_limits_vlv_dac = {
376         .dot = { .min = 25000, .max = 270000 },
377         .vco = { .min = 4000000, .max = 6000000 },
378         .n = { .min = 1, .max = 7 },
379         .m = { .min = 22, .max = 450 }, /* guess */
380         .m1 = { .min = 2, .max = 3 },
381         .m2 = { .min = 11, .max = 156 },
382         .p = { .min = 10, .max = 30 },
383         .p1 = { .min = 2, .max = 3 },
384         .p2 = { .dot_limit = 270000,
385                 .p2_slow = 2, .p2_fast = 20 },
386         .find_pll = intel_vlv_find_best_pll,
387 };
388
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390         .dot = { .min = 20000, .max = 165000 },
391         .vco = { .min = 4000000, .max = 5994000},
392         .n = { .min = 1, .max = 7 },
393         .m = { .min = 60, .max = 300 }, /* guess */
394         .m1 = { .min = 2, .max = 3 },
395         .m2 = { .min = 11, .max = 156 },
396         .p = { .min = 10, .max = 30 },
397         .p1 = { .min = 2, .max = 3 },
398         .p2 = { .dot_limit = 270000,
399                 .p2_slow = 2, .p2_fast = 20 },
400         .find_pll = intel_vlv_find_best_pll,
401 };
402
403 static const intel_limit_t intel_limits_vlv_dp = {
404         .dot = { .min = 25000, .max = 270000 },
405         .vco = { .min = 4000000, .max = 6000000 },
406         .n = { .min = 1, .max = 7 },
407         .m = { .min = 22, .max = 450 },
408         .m1 = { .min = 2, .max = 3 },
409         .m2 = { .min = 11, .max = 156 },
410         .p = { .min = 10, .max = 30 },
411         .p1 = { .min = 2, .max = 3 },
412         .p2 = { .dot_limit = 270000,
413                 .p2_slow = 2, .p2_fast = 20 },
414         .find_pll = intel_vlv_find_best_pll,
415 };
416
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418 {
419         unsigned long flags;
420         u32 val = 0;
421
422         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424                 DRM_ERROR("DPIO idle wait timed out\n");
425                 goto out_unlock;
426         }
427
428         I915_WRITE(DPIO_REG, reg);
429         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430                    DPIO_BYTE);
431         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432                 DRM_ERROR("DPIO read wait timed out\n");
433                 goto out_unlock;
434         }
435         val = I915_READ(DPIO_DATA);
436
437 out_unlock:
438         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439         return val;
440 }
441
442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443                              u32 val)
444 {
445         unsigned long flags;
446
447         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449                 DRM_ERROR("DPIO idle wait timed out\n");
450                 goto out_unlock;
451         }
452
453         I915_WRITE(DPIO_DATA, val);
454         I915_WRITE(DPIO_REG, reg);
455         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456                    DPIO_BYTE);
457         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458                 DRM_ERROR("DPIO write wait timed out\n");
459
460 out_unlock:
461        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462 }
463
464 static void vlv_init_dpio(struct drm_device *dev)
465 {
466         struct drm_i915_private *dev_priv = dev->dev_private;
467
468         /* Reset the DPIO config */
469         I915_WRITE(DPIO_CTL, 0);
470         POSTING_READ(DPIO_CTL);
471         I915_WRITE(DPIO_CTL, 1);
472         POSTING_READ(DPIO_CTL);
473 }
474
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476 {
477         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478         return 1;
479 }
480
481 static const struct dmi_system_id intel_dual_link_lvds[] = {
482         {
483                 .callback = intel_dual_link_lvds_callback,
484                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485                 .matches = {
486                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488                 },
489         },
490         { }     /* terminating entry */
491 };
492
493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494                               unsigned int reg)
495 {
496         unsigned int val;
497
498         /* use the module option value if specified */
499         if (i915_lvds_channel_mode > 0)
500                 return i915_lvds_channel_mode == 2;
501
502         if (dmi_check_system(intel_dual_link_lvds))
503                 return true;
504
505         if (dev_priv->lvds_val)
506                 val = dev_priv->lvds_val;
507         else {
508                 /* BIOS should set the proper LVDS register value at boot, but
509                  * in reality, it doesn't set the value when the lid is closed;
510                  * we need to check "the value to be set" in VBT when LVDS
511                  * register is uninitialized.
512                  */
513                 val = I915_READ(reg);
514                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515                         val = dev_priv->bios_lvds_val;
516                 dev_priv->lvds_val = val;
517         }
518         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519 }
520
521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522                                                 int refclk)
523 {
524         struct drm_device *dev = crtc->dev;
525         struct drm_i915_private *dev_priv = dev->dev_private;
526         const intel_limit_t *limit;
527
528         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530                         /* LVDS dual channel */
531                         if (refclk == 100000)
532                                 limit = &intel_limits_ironlake_dual_lvds_100m;
533                         else
534                                 limit = &intel_limits_ironlake_dual_lvds;
535                 } else {
536                         if (refclk == 100000)
537                                 limit = &intel_limits_ironlake_single_lvds_100m;
538                         else
539                                 limit = &intel_limits_ironlake_single_lvds;
540                 }
541         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543                 limit = &intel_limits_ironlake_display_port;
544         else
545                 limit = &intel_limits_ironlake_dac;
546
547         return limit;
548 }
549
550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551 {
552         struct drm_device *dev = crtc->dev;
553         struct drm_i915_private *dev_priv = dev->dev_private;
554         const intel_limit_t *limit;
555
556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557                 if (is_dual_link_lvds(dev_priv, LVDS))
558                         /* LVDS with dual channel */
559                         limit = &intel_limits_g4x_dual_channel_lvds;
560                 else
561                         /* LVDS with dual channel */
562                         limit = &intel_limits_g4x_single_channel_lvds;
563         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565                 limit = &intel_limits_g4x_hdmi;
566         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567                 limit = &intel_limits_g4x_sdvo;
568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569                 limit = &intel_limits_g4x_display_port;
570         } else /* The option is for other outputs */
571                 limit = &intel_limits_i9xx_sdvo;
572
573         return limit;
574 }
575
576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
577 {
578         struct drm_device *dev = crtc->dev;
579         const intel_limit_t *limit;
580
581         if (HAS_PCH_SPLIT(dev))
582                 limit = intel_ironlake_limit(crtc, refclk);
583         else if (IS_G4X(dev)) {
584                 limit = intel_g4x_limit(crtc);
585         } else if (IS_PINEVIEW(dev)) {
586                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587                         limit = &intel_limits_pineview_lvds;
588                 else
589                         limit = &intel_limits_pineview_sdvo;
590         } else if (IS_VALLEYVIEW(dev)) {
591                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592                         limit = &intel_limits_vlv_dac;
593                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594                         limit = &intel_limits_vlv_hdmi;
595                 else
596                         limit = &intel_limits_vlv_dp;
597         } else if (!IS_GEN2(dev)) {
598                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599                         limit = &intel_limits_i9xx_lvds;
600                 else
601                         limit = &intel_limits_i9xx_sdvo;
602         } else {
603                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604                         limit = &intel_limits_i8xx_lvds;
605                 else
606                         limit = &intel_limits_i8xx_dvo;
607         }
608         return limit;
609 }
610
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk, intel_clock_t *clock)
613 {
614         clock->m = clock->m2 + 2;
615         clock->p = clock->p1 * clock->p2;
616         clock->vco = refclk * clock->m / clock->n;
617         clock->dot = clock->vco / clock->p;
618 }
619
620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621 {
622         if (IS_PINEVIEW(dev)) {
623                 pineview_clock(refclk, clock);
624                 return;
625         }
626         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627         clock->p = clock->p1 * clock->p2;
628         clock->vco = refclk * clock->m / (clock->n + 2);
629         clock->dot = clock->vco / clock->p;
630 }
631
632 /**
633  * Returns whether any output on the specified pipe is of the specified type
634  */
635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
636 {
637         struct drm_device *dev = crtc->dev;
638         struct intel_encoder *encoder;
639
640         for_each_encoder_on_crtc(dev, crtc, encoder)
641                 if (encoder->type == type)
642                         return true;
643
644         return false;
645 }
646
647 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
648 /**
649  * Returns whether the given set of divisors are valid for a given refclk with
650  * the given connectors.
651  */
652
653 static bool intel_PLL_is_valid(struct drm_device *dev,
654                                const intel_limit_t *limit,
655                                const intel_clock_t *clock)
656 {
657         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
658                 INTELPllInvalid("p1 out of range\n");
659         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
660                 INTELPllInvalid("p out of range\n");
661         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
662                 INTELPllInvalid("m2 out of range\n");
663         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
664                 INTELPllInvalid("m1 out of range\n");
665         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666                 INTELPllInvalid("m1 <= m2\n");
667         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
668                 INTELPllInvalid("m out of range\n");
669         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
670                 INTELPllInvalid("n out of range\n");
671         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672                 INTELPllInvalid("vco out of range\n");
673         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674          * connector, etc., rather than just a single range.
675          */
676         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677                 INTELPllInvalid("dot out of range\n");
678
679         return true;
680 }
681
682 static bool
683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684                     int target, int refclk, intel_clock_t *match_clock,
685                     intel_clock_t *best_clock)
686
687 {
688         struct drm_device *dev = crtc->dev;
689         struct drm_i915_private *dev_priv = dev->dev_private;
690         intel_clock_t clock;
691         int err = target;
692
693         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694             (I915_READ(LVDS)) != 0) {
695                 /*
696                  * For LVDS, if the panel is on, just rely on its current
697                  * settings for dual-channel.  We haven't figured out how to
698                  * reliably set up different single/dual channel state, if we
699                  * even can.
700                  */
701                 if (is_dual_link_lvds(dev_priv, LVDS))
702                         clock.p2 = limit->p2.p2_fast;
703                 else
704                         clock.p2 = limit->p2.p2_slow;
705         } else {
706                 if (target < limit->p2.dot_limit)
707                         clock.p2 = limit->p2.p2_slow;
708                 else
709                         clock.p2 = limit->p2.p2_fast;
710         }
711
712         memset(best_clock, 0, sizeof(*best_clock));
713
714         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715              clock.m1++) {
716                 for (clock.m2 = limit->m2.min;
717                      clock.m2 <= limit->m2.max; clock.m2++) {
718                         /* m1 is always 0 in Pineview */
719                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
720                                 break;
721                         for (clock.n = limit->n.min;
722                              clock.n <= limit->n.max; clock.n++) {
723                                 for (clock.p1 = limit->p1.min;
724                                         clock.p1 <= limit->p1.max; clock.p1++) {
725                                         int this_err;
726
727                                         intel_clock(dev, refclk, &clock);
728                                         if (!intel_PLL_is_valid(dev, limit,
729                                                                 &clock))
730                                                 continue;
731                                         if (match_clock &&
732                                             clock.p != match_clock->p)
733                                                 continue;
734
735                                         this_err = abs(clock.dot - target);
736                                         if (this_err < err) {
737                                                 *best_clock = clock;
738                                                 err = this_err;
739                                         }
740                                 }
741                         }
742                 }
743         }
744
745         return (err != target);
746 }
747
748 static bool
749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750                         int target, int refclk, intel_clock_t *match_clock,
751                         intel_clock_t *best_clock)
752 {
753         struct drm_device *dev = crtc->dev;
754         struct drm_i915_private *dev_priv = dev->dev_private;
755         intel_clock_t clock;
756         int max_n;
757         bool found;
758         /* approximately equals target * 0.00585 */
759         int err_most = (target >> 8) + (target >> 9);
760         found = false;
761
762         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
763                 int lvds_reg;
764
765                 if (HAS_PCH_SPLIT(dev))
766                         lvds_reg = PCH_LVDS;
767                 else
768                         lvds_reg = LVDS;
769                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
770                     LVDS_CLKB_POWER_UP)
771                         clock.p2 = limit->p2.p2_fast;
772                 else
773                         clock.p2 = limit->p2.p2_slow;
774         } else {
775                 if (target < limit->p2.dot_limit)
776                         clock.p2 = limit->p2.p2_slow;
777                 else
778                         clock.p2 = limit->p2.p2_fast;
779         }
780
781         memset(best_clock, 0, sizeof(*best_clock));
782         max_n = limit->n.max;
783         /* based on hardware requirement, prefer smaller n to precision */
784         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785                 /* based on hardware requirement, prefere larger m1,m2 */
786                 for (clock.m1 = limit->m1.max;
787                      clock.m1 >= limit->m1.min; clock.m1--) {
788                         for (clock.m2 = limit->m2.max;
789                              clock.m2 >= limit->m2.min; clock.m2--) {
790                                 for (clock.p1 = limit->p1.max;
791                                      clock.p1 >= limit->p1.min; clock.p1--) {
792                                         int this_err;
793
794                                         intel_clock(dev, refclk, &clock);
795                                         if (!intel_PLL_is_valid(dev, limit,
796                                                                 &clock))
797                                                 continue;
798                                         if (match_clock &&
799                                             clock.p != match_clock->p)
800                                                 continue;
801
802                                         this_err = abs(clock.dot - target);
803                                         if (this_err < err_most) {
804                                                 *best_clock = clock;
805                                                 err_most = this_err;
806                                                 max_n = clock.n;
807                                                 found = true;
808                                         }
809                                 }
810                         }
811                 }
812         }
813         return found;
814 }
815
816 static bool
817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818                            int target, int refclk, intel_clock_t *match_clock,
819                            intel_clock_t *best_clock)
820 {
821         struct drm_device *dev = crtc->dev;
822         intel_clock_t clock;
823
824         if (target < 200000) {
825                 clock.n = 1;
826                 clock.p1 = 2;
827                 clock.p2 = 10;
828                 clock.m1 = 12;
829                 clock.m2 = 9;
830         } else {
831                 clock.n = 2;
832                 clock.p1 = 1;
833                 clock.p2 = 10;
834                 clock.m1 = 14;
835                 clock.m2 = 8;
836         }
837         intel_clock(dev, refclk, &clock);
838         memcpy(best_clock, &clock, sizeof(intel_clock_t));
839         return true;
840 }
841
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
843 static bool
844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845                       int target, int refclk, intel_clock_t *match_clock,
846                       intel_clock_t *best_clock)
847 {
848         intel_clock_t clock;
849         if (target < 200000) {
850                 clock.p1 = 2;
851                 clock.p2 = 10;
852                 clock.n = 2;
853                 clock.m1 = 23;
854                 clock.m2 = 8;
855         } else {
856                 clock.p1 = 1;
857                 clock.p2 = 10;
858                 clock.n = 1;
859                 clock.m1 = 14;
860                 clock.m2 = 2;
861         }
862         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863         clock.p = (clock.p1 * clock.p2);
864         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865         clock.vco = 0;
866         memcpy(best_clock, &clock, sizeof(intel_clock_t));
867         return true;
868 }
869 static bool
870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871                         int target, int refclk, intel_clock_t *match_clock,
872                         intel_clock_t *best_clock)
873 {
874         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875         u32 m, n, fastclk;
876         u32 updrate, minupdate, fracbits, p;
877         unsigned long bestppm, ppm, absppm;
878         int dotclk, flag;
879
880         flag = 0;
881         dotclk = target * 1000;
882         bestppm = 1000000;
883         ppm = absppm = 0;
884         fastclk = dotclk / (2*100);
885         updrate = 0;
886         minupdate = 19200;
887         fracbits = 1;
888         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889         bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891         /* based on hardware requirement, prefer smaller n to precision */
892         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893                 updrate = refclk / n;
894                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896                                 if (p2 > 10)
897                                         p2 = p2 - 1;
898                                 p = p1 * p2;
899                                 /* based on hardware requirement, prefer bigger m1,m2 values */
900                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901                                         m2 = (((2*(fastclk * p * n / m1 )) +
902                                                refclk) / (2*refclk));
903                                         m = m1 * m2;
904                                         vco = updrate * m;
905                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
906                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907                                                 absppm = (ppm > 0) ? ppm : (-ppm);
908                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909                                                         bestppm = 0;
910                                                         flag = 1;
911                                                 }
912                                                 if (absppm < bestppm - 10) {
913                                                         bestppm = absppm;
914                                                         flag = 1;
915                                                 }
916                                                 if (flag) {
917                                                         bestn = n;
918                                                         bestm1 = m1;
919                                                         bestm2 = m2;
920                                                         bestp1 = p1;
921                                                         bestp2 = p2;
922                                                         flag = 0;
923                                                 }
924                                         }
925                                 }
926                         }
927                 }
928         }
929         best_clock->n = bestn;
930         best_clock->m1 = bestm1;
931         best_clock->m2 = bestm2;
932         best_clock->p1 = bestp1;
933         best_clock->p2 = bestp2;
934
935         return true;
936 }
937
938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939                                              enum pipe pipe)
940 {
941         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944         return intel_crtc->cpu_transcoder;
945 }
946
947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948 {
949         struct drm_i915_private *dev_priv = dev->dev_private;
950         u32 frame, frame_reg = PIPEFRAME(pipe);
951
952         frame = I915_READ(frame_reg);
953
954         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955                 DRM_DEBUG_KMS("vblank wait timed out\n");
956 }
957
958 /**
959  * intel_wait_for_vblank - wait for vblank on a given pipe
960  * @dev: drm device
961  * @pipe: pipe to wait for
962  *
963  * Wait for vblank to occur on a given pipe.  Needed for various bits of
964  * mode setting code.
965  */
966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
967 {
968         struct drm_i915_private *dev_priv = dev->dev_private;
969         int pipestat_reg = PIPESTAT(pipe);
970
971         if (INTEL_INFO(dev)->gen >= 5) {
972                 ironlake_wait_for_vblank(dev, pipe);
973                 return;
974         }
975
976         /* Clear existing vblank status. Note this will clear any other
977          * sticky status fields as well.
978          *
979          * This races with i915_driver_irq_handler() with the result
980          * that either function could miss a vblank event.  Here it is not
981          * fatal, as we will either wait upon the next vblank interrupt or
982          * timeout.  Generally speaking intel_wait_for_vblank() is only
983          * called during modeset at which time the GPU should be idle and
984          * should *not* be performing page flips and thus not waiting on
985          * vblanks...
986          * Currently, the result of us stealing a vblank from the irq
987          * handler is that a single frame will be skipped during swapbuffers.
988          */
989         I915_WRITE(pipestat_reg,
990                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
992         /* Wait for vblank interrupt bit to set */
993         if (wait_for(I915_READ(pipestat_reg) &
994                      PIPE_VBLANK_INTERRUPT_STATUS,
995                      50))
996                 DRM_DEBUG_KMS("vblank wait timed out\n");
997 }
998
999 /*
1000  * intel_wait_for_pipe_off - wait for pipe to turn off
1001  * @dev: drm device
1002  * @pipe: pipe to wait for
1003  *
1004  * After disabling a pipe, we can't wait for vblank in the usual way,
1005  * spinning on the vblank interrupt status bit, since we won't actually
1006  * see an interrupt when the pipe is disabled.
1007  *
1008  * On Gen4 and above:
1009  *   wait for the pipe register state bit to turn off
1010  *
1011  * Otherwise:
1012  *   wait for the display line value to settle (it usually
1013  *   ends up stopping at the start of the next frame).
1014  *
1015  */
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1017 {
1018         struct drm_i915_private *dev_priv = dev->dev_private;
1019         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020                                                                       pipe);
1021
1022         if (INTEL_INFO(dev)->gen >= 4) {
1023                 int reg = PIPECONF(cpu_transcoder);
1024
1025                 /* Wait for the Pipe State to go off */
1026                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027                              100))
1028                         WARN(1, "pipe_off wait timed out\n");
1029         } else {
1030                 u32 last_line, line_mask;
1031                 int reg = PIPEDSL(pipe);
1032                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034                 if (IS_GEN2(dev))
1035                         line_mask = DSL_LINEMASK_GEN2;
1036                 else
1037                         line_mask = DSL_LINEMASK_GEN3;
1038
1039                 /* Wait for the display line to settle */
1040                 do {
1041                         last_line = I915_READ(reg) & line_mask;
1042                         mdelay(5);
1043                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044                          time_after(timeout, jiffies));
1045                 if (time_after(jiffies, timeout))
1046                         WARN(1, "pipe_off wait timed out\n");
1047         }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052         return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057                        enum pipe pipe, bool state)
1058 {
1059         int reg;
1060         u32 val;
1061         bool cur_state;
1062
1063         reg = DPLL(pipe);
1064         val = I915_READ(reg);
1065         cur_state = !!(val & DPLL_VCO_ENABLE);
1066         WARN(cur_state != state,
1067              "PLL state assertion failure (expected %s, current %s)\n",
1068              state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075                            struct intel_pch_pll *pll,
1076                            struct intel_crtc *crtc,
1077                            bool state)
1078 {
1079         u32 val;
1080         bool cur_state;
1081
1082         if (HAS_PCH_LPT(dev_priv->dev)) {
1083                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084                 return;
1085         }
1086
1087         if (WARN (!pll,
1088                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089                 return;
1090
1091         val = I915_READ(pll->pll_reg);
1092         cur_state = !!(val & DPLL_VCO_ENABLE);
1093         WARN(cur_state != state,
1094              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095              pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097         /* Make sure the selected PLL is correctly attached to the transcoder */
1098         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099                 u32 pch_dpll;
1100
1101                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1105                           cur_state, crtc->pipe, pch_dpll)) {
1106                         cur_state = !!(val >> (4*crtc->pipe + 3));
1107                         WARN(cur_state != state,
1108                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1109                              pll->pll_reg == _PCH_DPLL_B,
1110                              state_string(state),
1111                              crtc->pipe,
1112                              val);
1113                 }
1114         }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126                                                                       pipe);
1127
1128         if (IS_HASWELL(dev_priv->dev)) {
1129                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 reg = FDI_TX_CTL(pipe);
1135                 val = I915_READ(reg);
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         int reg;
1149         u32 val;
1150         bool cur_state;
1151
1152         reg = FDI_RX_CTL(pipe);
1153         val = I915_READ(reg);
1154         cur_state = !!(val & FDI_RX_ENABLE);
1155         WARN(cur_state != state,
1156              "FDI RX state assertion failure (expected %s, current %s)\n",
1157              state_string(state), state_string(cur_state));
1158 }
1159 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163                                       enum pipe pipe)
1164 {
1165         int reg;
1166         u32 val;
1167
1168         /* ILK FDI PLL is always enabled */
1169         if (dev_priv->info->gen == 5)
1170                 return;
1171
1172         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173         if (IS_HASWELL(dev_priv->dev))
1174                 return;
1175
1176         reg = FDI_TX_CTL(pipe);
1177         val = I915_READ(reg);
1178         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182                                       enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         reg = FDI_RX_CTL(pipe);
1188         val = I915_READ(reg);
1189         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193                                   enum pipe pipe)
1194 {
1195         int pp_reg, lvds_reg;
1196         u32 val;
1197         enum pipe panel_pipe = PIPE_A;
1198         bool locked = true;
1199
1200         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201                 pp_reg = PCH_PP_CONTROL;
1202                 lvds_reg = PCH_LVDS;
1203         } else {
1204                 pp_reg = PP_CONTROL;
1205                 lvds_reg = LVDS;
1206         }
1207
1208         val = I915_READ(pp_reg);
1209         if (!(val & PANEL_POWER_ON) ||
1210             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211                 locked = false;
1212
1213         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214                 panel_pipe = PIPE_B;
1215
1216         WARN(panel_pipe == pipe && locked,
1217              "panel assertion failure, pipe %c regs locked\n",
1218              pipe_name(pipe));
1219 }
1220
1221 void assert_pipe(struct drm_i915_private *dev_priv,
1222                  enum pipe pipe, bool state)
1223 {
1224         int reg;
1225         u32 val;
1226         bool cur_state;
1227         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228                                                                       pipe);
1229
1230         /* if we need the pipe A quirk it must be always on */
1231         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232                 state = true;
1233
1234         reg = PIPECONF(cpu_transcoder);
1235         val = I915_READ(reg);
1236         cur_state = !!(val & PIPECONF_ENABLE);
1237         WARN(cur_state != state,
1238              "pipe %c assertion failure (expected %s, current %s)\n",
1239              pipe_name(pipe), state_string(state), state_string(cur_state));
1240 }
1241
1242 static void assert_plane(struct drm_i915_private *dev_priv,
1243                          enum plane plane, bool state)
1244 {
1245         int reg;
1246         u32 val;
1247         bool cur_state;
1248
1249         reg = DSPCNTR(plane);
1250         val = I915_READ(reg);
1251         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252         WARN(cur_state != state,
1253              "plane %c assertion failure (expected %s, current %s)\n",
1254              plane_name(plane), state_string(state), state_string(cur_state));
1255 }
1256
1257 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
1260 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261                                    enum pipe pipe)
1262 {
1263         int reg, i;
1264         u32 val;
1265         int cur_pipe;
1266
1267         /* Planes are fixed to pipes on ILK+ */
1268         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269                 reg = DSPCNTR(pipe);
1270                 val = I915_READ(reg);
1271                 WARN((val & DISPLAY_PLANE_ENABLE),
1272                      "plane %c assertion failure, should be disabled but not\n",
1273                      plane_name(pipe));
1274                 return;
1275         }
1276
1277         /* Need to check both planes against the pipe */
1278         for (i = 0; i < 2; i++) {
1279                 reg = DSPCNTR(i);
1280                 val = I915_READ(reg);
1281                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282                         DISPPLANE_SEL_PIPE_SHIFT;
1283                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1284                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285                      plane_name(i), pipe_name(pipe));
1286         }
1287 }
1288
1289 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290 {
1291         u32 val;
1292         bool enabled;
1293
1294         if (HAS_PCH_LPT(dev_priv->dev)) {
1295                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296                 return;
1297         }
1298
1299         val = I915_READ(PCH_DREF_CONTROL);
1300         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301                             DREF_SUPERSPREAD_SOURCE_MASK));
1302         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303 }
1304
1305 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306                                        enum pipe pipe)
1307 {
1308         int reg;
1309         u32 val;
1310         bool enabled;
1311
1312         reg = TRANSCONF(pipe);
1313         val = I915_READ(reg);
1314         enabled = !!(val & TRANS_ENABLE);
1315         WARN(enabled,
1316              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317              pipe_name(pipe));
1318 }
1319
1320 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321                             enum pipe pipe, u32 port_sel, u32 val)
1322 {
1323         if ((val & DP_PORT_EN) == 0)
1324                 return false;
1325
1326         if (HAS_PCH_CPT(dev_priv->dev)) {
1327                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330                         return false;
1331         } else {
1332                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333                         return false;
1334         }
1335         return true;
1336 }
1337
1338 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339                               enum pipe pipe, u32 val)
1340 {
1341         if ((val & PORT_ENABLE) == 0)
1342                 return false;
1343
1344         if (HAS_PCH_CPT(dev_priv->dev)) {
1345                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346                         return false;
1347         } else {
1348                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349                         return false;
1350         }
1351         return true;
1352 }
1353
1354 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355                               enum pipe pipe, u32 val)
1356 {
1357         if ((val & LVDS_PORT_EN) == 0)
1358                 return false;
1359
1360         if (HAS_PCH_CPT(dev_priv->dev)) {
1361                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362                         return false;
1363         } else {
1364                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365                         return false;
1366         }
1367         return true;
1368 }
1369
1370 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371                               enum pipe pipe, u32 val)
1372 {
1373         if ((val & ADPA_DAC_ENABLE) == 0)
1374                 return false;
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe, int reg, u32 port_sel)
1387 {
1388         u32 val = I915_READ(reg);
1389         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1390              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391              reg, pipe_name(pipe));
1392
1393         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394              && (val & DP_PIPEB_SELECT),
1395              "IBX PCH dp port still using transcoder B\n");
1396 }
1397
1398 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399                                      enum pipe pipe, int reg)
1400 {
1401         u32 val = I915_READ(reg);
1402         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1403              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404              reg, pipe_name(pipe));
1405
1406         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407              && (val & SDVO_PIPE_B_SELECT),
1408              "IBX PCH hdmi port still using transcoder B\n");
1409 }
1410
1411 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412                                       enum pipe pipe)
1413 {
1414         int reg;
1415         u32 val;
1416
1417         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1420
1421         reg = PCH_ADPA;
1422         val = I915_READ(reg);
1423         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1424              "PCH VGA enabled on transcoder %c, should be disabled\n",
1425              pipe_name(pipe));
1426
1427         reg = PCH_LVDS;
1428         val = I915_READ(reg);
1429         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1430              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1431              pipe_name(pipe));
1432
1433         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436 }
1437
1438 /**
1439  * intel_enable_pll - enable a PLL
1440  * @dev_priv: i915 private structure
1441  * @pipe: pipe PLL to enable
1442  *
1443  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1444  * make sure the PLL reg is writable first though, since the panel write
1445  * protect mechanism may be enabled.
1446  *
1447  * Note!  This is for pre-ILK only.
1448  *
1449  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1450  */
1451 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452 {
1453         int reg;
1454         u32 val;
1455
1456         /* No really, not for ILK+ */
1457         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1458
1459         /* PLL is protected by panel, make sure we can write it */
1460         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461                 assert_panel_unlocked(dev_priv, pipe);
1462
1463         reg = DPLL(pipe);
1464         val = I915_READ(reg);
1465         val |= DPLL_VCO_ENABLE;
1466
1467         /* We do this three times for luck */
1468         I915_WRITE(reg, val);
1469         POSTING_READ(reg);
1470         udelay(150); /* wait for warmup */
1471         I915_WRITE(reg, val);
1472         POSTING_READ(reg);
1473         udelay(150); /* wait for warmup */
1474         I915_WRITE(reg, val);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477 }
1478
1479 /**
1480  * intel_disable_pll - disable a PLL
1481  * @dev_priv: i915 private structure
1482  * @pipe: pipe PLL to disable
1483  *
1484  * Disable the PLL for @pipe, making sure the pipe is off first.
1485  *
1486  * Note!  This is for pre-ILK only.
1487  */
1488 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489 {
1490         int reg;
1491         u32 val;
1492
1493         /* Don't disable pipe A or pipe A PLLs if needed */
1494         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495                 return;
1496
1497         /* Make sure the pipe isn't still relying on us */
1498         assert_pipe_disabled(dev_priv, pipe);
1499
1500         reg = DPLL(pipe);
1501         val = I915_READ(reg);
1502         val &= ~DPLL_VCO_ENABLE;
1503         I915_WRITE(reg, val);
1504         POSTING_READ(reg);
1505 }
1506
1507 /* SBI access */
1508 static void
1509 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1510                 enum intel_sbi_destination destination)
1511 {
1512         unsigned long flags;
1513         u32 tmp;
1514
1515         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1516         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1517                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1518                 goto out_unlock;
1519         }
1520
1521         I915_WRITE(SBI_ADDR, (reg << 16));
1522         I915_WRITE(SBI_DATA, value);
1523
1524         if (destination == SBI_ICLK)
1525                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1526         else
1527                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1528         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1529
1530         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1531                                 100)) {
1532                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1533                 goto out_unlock;
1534         }
1535
1536 out_unlock:
1537         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1538 }
1539
1540 static u32
1541 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542                enum intel_sbi_destination destination)
1543 {
1544         unsigned long flags;
1545         u32 value = 0;
1546
1547         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1548         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1549                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1550                 goto out_unlock;
1551         }
1552
1553         I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555         if (destination == SBI_ICLK)
1556                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557         else
1558                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1560
1561         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1562                                 100)) {
1563                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1564                 goto out_unlock;
1565         }
1566
1567         value = I915_READ(SBI_DATA);
1568
1569 out_unlock:
1570         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1571         return value;
1572 }
1573
1574 /**
1575  * ironlake_enable_pch_pll - enable PCH PLL
1576  * @dev_priv: i915 private structure
1577  * @pipe: pipe PLL to enable
1578  *
1579  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1580  * drives the transcoder clock.
1581  */
1582 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1583 {
1584         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1585         struct intel_pch_pll *pll;
1586         int reg;
1587         u32 val;
1588
1589         /* PCH PLLs only available on ILK, SNB and IVB */
1590         BUG_ON(dev_priv->info->gen < 5);
1591         pll = intel_crtc->pch_pll;
1592         if (pll == NULL)
1593                 return;
1594
1595         if (WARN_ON(pll->refcount == 0))
1596                 return;
1597
1598         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1599                       pll->pll_reg, pll->active, pll->on,
1600                       intel_crtc->base.base.id);
1601
1602         /* PCH refclock must be enabled first */
1603         assert_pch_refclk_enabled(dev_priv);
1604
1605         if (pll->active++ && pll->on) {
1606                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1607                 return;
1608         }
1609
1610         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1611
1612         reg = pll->pll_reg;
1613         val = I915_READ(reg);
1614         val |= DPLL_VCO_ENABLE;
1615         I915_WRITE(reg, val);
1616         POSTING_READ(reg);
1617         udelay(200);
1618
1619         pll->on = true;
1620 }
1621
1622 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1623 {
1624         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1625         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1626         int reg;
1627         u32 val;
1628
1629         /* PCH only available on ILK+ */
1630         BUG_ON(dev_priv->info->gen < 5);
1631         if (pll == NULL)
1632                return;
1633
1634         if (WARN_ON(pll->refcount == 0))
1635                 return;
1636
1637         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1638                       pll->pll_reg, pll->active, pll->on,
1639                       intel_crtc->base.base.id);
1640
1641         if (WARN_ON(pll->active == 0)) {
1642                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1643                 return;
1644         }
1645
1646         if (--pll->active) {
1647                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1648                 return;
1649         }
1650
1651         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1652
1653         /* Make sure transcoder isn't still depending on us */
1654         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1655
1656         reg = pll->pll_reg;
1657         val = I915_READ(reg);
1658         val &= ~DPLL_VCO_ENABLE;
1659         I915_WRITE(reg, val);
1660         POSTING_READ(reg);
1661         udelay(200);
1662
1663         pll->on = false;
1664 }
1665
1666 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1667                                            enum pipe pipe)
1668 {
1669         struct drm_device *dev = dev_priv->dev;
1670         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1671         uint32_t reg, val, pipeconf_val;
1672
1673         /* PCH only available on ILK+ */
1674         BUG_ON(dev_priv->info->gen < 5);
1675
1676         /* Make sure PCH DPLL is enabled */
1677         assert_pch_pll_enabled(dev_priv,
1678                                to_intel_crtc(crtc)->pch_pll,
1679                                to_intel_crtc(crtc));
1680
1681         /* FDI must be feeding us bits for PCH ports */
1682         assert_fdi_tx_enabled(dev_priv, pipe);
1683         assert_fdi_rx_enabled(dev_priv, pipe);
1684
1685         if (HAS_PCH_CPT(dev)) {
1686                 /* Workaround: Set the timing override bit before enabling the
1687                  * pch transcoder. */
1688                 reg = TRANS_CHICKEN2(pipe);
1689                 val = I915_READ(reg);
1690                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1691                 I915_WRITE(reg, val);
1692         }
1693
1694         reg = TRANSCONF(pipe);
1695         val = I915_READ(reg);
1696         pipeconf_val = I915_READ(PIPECONF(pipe));
1697
1698         if (HAS_PCH_IBX(dev_priv->dev)) {
1699                 /*
1700                  * make the BPC in transcoder be consistent with
1701                  * that in pipeconf reg.
1702                  */
1703                 val &= ~PIPE_BPC_MASK;
1704                 val |= pipeconf_val & PIPE_BPC_MASK;
1705         }
1706
1707         val &= ~TRANS_INTERLACE_MASK;
1708         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1709                 if (HAS_PCH_IBX(dev_priv->dev) &&
1710                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1711                         val |= TRANS_LEGACY_INTERLACED_ILK;
1712                 else
1713                         val |= TRANS_INTERLACED;
1714         else
1715                 val |= TRANS_PROGRESSIVE;
1716
1717         I915_WRITE(reg, val | TRANS_ENABLE);
1718         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1719                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1720 }
1721
1722 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1723                                       enum transcoder cpu_transcoder)
1724 {
1725         u32 val, pipeconf_val;
1726
1727         /* PCH only available on ILK+ */
1728         BUG_ON(dev_priv->info->gen < 5);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1732         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1733
1734         /* Workaround: set timing override bit. */
1735         val = I915_READ(_TRANSA_CHICKEN2);
1736         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1737         I915_WRITE(_TRANSA_CHICKEN2, val);
1738
1739         val = TRANS_ENABLE;
1740         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1741
1742         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1743             PIPECONF_INTERLACED_ILK)
1744                 val |= TRANS_INTERLACED;
1745         else
1746                 val |= TRANS_PROGRESSIVE;
1747
1748         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1749         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1750                 DRM_ERROR("Failed to enable PCH transcoder\n");
1751 }
1752
1753 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1754                                             enum pipe pipe)
1755 {
1756         struct drm_device *dev = dev_priv->dev;
1757         uint32_t reg, val;
1758
1759         /* FDI relies on the transcoder */
1760         assert_fdi_tx_disabled(dev_priv, pipe);
1761         assert_fdi_rx_disabled(dev_priv, pipe);
1762
1763         /* Ports must be off as well */
1764         assert_pch_ports_disabled(dev_priv, pipe);
1765
1766         reg = TRANSCONF(pipe);
1767         val = I915_READ(reg);
1768         val &= ~TRANS_ENABLE;
1769         I915_WRITE(reg, val);
1770         /* wait for PCH transcoder off, transcoder state */
1771         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1772                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1773
1774         if (!HAS_PCH_IBX(dev)) {
1775                 /* Workaround: Clear the timing override chicken bit again. */
1776                 reg = TRANS_CHICKEN2(pipe);
1777                 val = I915_READ(reg);
1778                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1779                 I915_WRITE(reg, val);
1780         }
1781 }
1782
1783 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1784 {
1785         u32 val;
1786
1787         val = I915_READ(_TRANSACONF);
1788         val &= ~TRANS_ENABLE;
1789         I915_WRITE(_TRANSACONF, val);
1790         /* wait for PCH transcoder off, transcoder state */
1791         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1792                 DRM_ERROR("Failed to disable PCH transcoder\n");
1793
1794         /* Workaround: clear timing override bit. */
1795         val = I915_READ(_TRANSA_CHICKEN2);
1796         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1797         I915_WRITE(_TRANSA_CHICKEN2, val);
1798 }
1799
1800 /**
1801  * intel_enable_pipe - enable a pipe, asserting requirements
1802  * @dev_priv: i915 private structure
1803  * @pipe: pipe to enable
1804  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1805  *
1806  * Enable @pipe, making sure that various hardware specific requirements
1807  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1808  *
1809  * @pipe should be %PIPE_A or %PIPE_B.
1810  *
1811  * Will wait until the pipe is actually running (i.e. first vblank) before
1812  * returning.
1813  */
1814 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1815                               bool pch_port)
1816 {
1817         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818                                                                       pipe);
1819         enum transcoder pch_transcoder;
1820         int reg;
1821         u32 val;
1822
1823         if (IS_HASWELL(dev_priv->dev))
1824                 pch_transcoder = TRANSCODER_A;
1825         else
1826                 pch_transcoder = pipe;
1827
1828         /*
1829          * A pipe without a PLL won't actually be able to drive bits from
1830          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1831          * need the check.
1832          */
1833         if (!HAS_PCH_SPLIT(dev_priv->dev))
1834                 assert_pll_enabled(dev_priv, pipe);
1835         else {
1836                 if (pch_port) {
1837                         /* if driving the PCH, we need FDI enabled */
1838                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1839                         assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1840                 }
1841                 /* FIXME: assert CPU port conditions for SNB+ */
1842         }
1843
1844         reg = PIPECONF(cpu_transcoder);
1845         val = I915_READ(reg);
1846         if (val & PIPECONF_ENABLE)
1847                 return;
1848
1849         I915_WRITE(reg, val | PIPECONF_ENABLE);
1850         intel_wait_for_vblank(dev_priv->dev, pipe);
1851 }
1852
1853 /**
1854  * intel_disable_pipe - disable a pipe, asserting requirements
1855  * @dev_priv: i915 private structure
1856  * @pipe: pipe to disable
1857  *
1858  * Disable @pipe, making sure that various hardware specific requirements
1859  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1860  *
1861  * @pipe should be %PIPE_A or %PIPE_B.
1862  *
1863  * Will wait until the pipe has shut down before returning.
1864  */
1865 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1866                                enum pipe pipe)
1867 {
1868         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1869                                                                       pipe);
1870         int reg;
1871         u32 val;
1872
1873         /*
1874          * Make sure planes won't keep trying to pump pixels to us,
1875          * or we might hang the display.
1876          */
1877         assert_planes_disabled(dev_priv, pipe);
1878
1879         /* Don't disable pipe A or pipe A PLLs if needed */
1880         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1881                 return;
1882
1883         reg = PIPECONF(cpu_transcoder);
1884         val = I915_READ(reg);
1885         if ((val & PIPECONF_ENABLE) == 0)
1886                 return;
1887
1888         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1889         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1890 }
1891
1892 /*
1893  * Plane regs are double buffered, going from enabled->disabled needs a
1894  * trigger in order to latch.  The display address reg provides this.
1895  */
1896 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1897                                       enum plane plane)
1898 {
1899         if (dev_priv->info->gen >= 4)
1900                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1901         else
1902                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1903 }
1904
1905 /**
1906  * intel_enable_plane - enable a display plane on a given pipe
1907  * @dev_priv: i915 private structure
1908  * @plane: plane to enable
1909  * @pipe: pipe being fed
1910  *
1911  * Enable @plane on @pipe, making sure that @pipe is running first.
1912  */
1913 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1914                                enum plane plane, enum pipe pipe)
1915 {
1916         int reg;
1917         u32 val;
1918
1919         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1920         assert_pipe_enabled(dev_priv, pipe);
1921
1922         reg = DSPCNTR(plane);
1923         val = I915_READ(reg);
1924         if (val & DISPLAY_PLANE_ENABLE)
1925                 return;
1926
1927         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1928         intel_flush_display_plane(dev_priv, plane);
1929         intel_wait_for_vblank(dev_priv->dev, pipe);
1930 }
1931
1932 /**
1933  * intel_disable_plane - disable a display plane
1934  * @dev_priv: i915 private structure
1935  * @plane: plane to disable
1936  * @pipe: pipe consuming the data
1937  *
1938  * Disable @plane; should be an independent operation.
1939  */
1940 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1941                                 enum plane plane, enum pipe pipe)
1942 {
1943         int reg;
1944         u32 val;
1945
1946         reg = DSPCNTR(plane);
1947         val = I915_READ(reg);
1948         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1949                 return;
1950
1951         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1952         intel_flush_display_plane(dev_priv, plane);
1953         intel_wait_for_vblank(dev_priv->dev, pipe);
1954 }
1955
1956 int
1957 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1958                            struct drm_i915_gem_object *obj,
1959                            struct intel_ring_buffer *pipelined)
1960 {
1961         struct drm_i915_private *dev_priv = dev->dev_private;
1962         u32 alignment;
1963         int ret;
1964
1965         switch (obj->tiling_mode) {
1966         case I915_TILING_NONE:
1967                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1968                         alignment = 128 * 1024;
1969                 else if (INTEL_INFO(dev)->gen >= 4)
1970                         alignment = 4 * 1024;
1971                 else
1972                         alignment = 64 * 1024;
1973                 break;
1974         case I915_TILING_X:
1975                 /* pin() will align the object as required by fence */
1976                 alignment = 0;
1977                 break;
1978         case I915_TILING_Y:
1979                 /* FIXME: Is this true? */
1980                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1981                 return -EINVAL;
1982         default:
1983                 BUG();
1984         }
1985
1986         dev_priv->mm.interruptible = false;
1987         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1988         if (ret)
1989                 goto err_interruptible;
1990
1991         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1992          * fence, whereas 965+ only requires a fence if using
1993          * framebuffer compression.  For simplicity, we always install
1994          * a fence as the cost is not that onerous.
1995          */
1996         ret = i915_gem_object_get_fence(obj);
1997         if (ret)
1998                 goto err_unpin;
1999
2000         i915_gem_object_pin_fence(obj);
2001
2002         dev_priv->mm.interruptible = true;
2003         return 0;
2004
2005 err_unpin:
2006         i915_gem_object_unpin(obj);
2007 err_interruptible:
2008         dev_priv->mm.interruptible = true;
2009         return ret;
2010 }
2011
2012 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2013 {
2014         i915_gem_object_unpin_fence(obj);
2015         i915_gem_object_unpin(obj);
2016 }
2017
2018 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2019  * is assumed to be a power-of-two. */
2020 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2021                                                unsigned int bpp,
2022                                                unsigned int pitch)
2023 {
2024         int tile_rows, tiles;
2025
2026         tile_rows = *y / 8;
2027         *y %= 8;
2028         tiles = *x / (512/bpp);
2029         *x %= 512/bpp;
2030
2031         return tile_rows * pitch * 8 + tiles * 4096;
2032 }
2033
2034 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2035                              int x, int y)
2036 {
2037         struct drm_device *dev = crtc->dev;
2038         struct drm_i915_private *dev_priv = dev->dev_private;
2039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2040         struct intel_framebuffer *intel_fb;
2041         struct drm_i915_gem_object *obj;
2042         int plane = intel_crtc->plane;
2043         unsigned long linear_offset;
2044         u32 dspcntr;
2045         u32 reg;
2046
2047         switch (plane) {
2048         case 0:
2049         case 1:
2050                 break;
2051         default:
2052                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2053                 return -EINVAL;
2054         }
2055
2056         intel_fb = to_intel_framebuffer(fb);
2057         obj = intel_fb->obj;
2058
2059         reg = DSPCNTR(plane);
2060         dspcntr = I915_READ(reg);
2061         /* Mask out pixel format bits in case we change it */
2062         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2063         switch (fb->pixel_format) {
2064         case DRM_FORMAT_C8:
2065                 dspcntr |= DISPPLANE_8BPP;
2066                 break;
2067         case DRM_FORMAT_XRGB1555:
2068         case DRM_FORMAT_ARGB1555:
2069                 dspcntr |= DISPPLANE_BGRX555;
2070                 break;
2071         case DRM_FORMAT_RGB565:
2072                 dspcntr |= DISPPLANE_BGRX565;
2073                 break;
2074         case DRM_FORMAT_XRGB8888:
2075         case DRM_FORMAT_ARGB8888:
2076                 dspcntr |= DISPPLANE_BGRX888;
2077                 break;
2078         case DRM_FORMAT_XBGR8888:
2079         case DRM_FORMAT_ABGR8888:
2080                 dspcntr |= DISPPLANE_RGBX888;
2081                 break;
2082         case DRM_FORMAT_XRGB2101010:
2083         case DRM_FORMAT_ARGB2101010:
2084                 dspcntr |= DISPPLANE_BGRX101010;
2085                 break;
2086         case DRM_FORMAT_XBGR2101010:
2087         case DRM_FORMAT_ABGR2101010:
2088                 dspcntr |= DISPPLANE_RGBX101010;
2089                 break;
2090         default:
2091                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2092                 return -EINVAL;
2093         }
2094
2095         if (INTEL_INFO(dev)->gen >= 4) {
2096                 if (obj->tiling_mode != I915_TILING_NONE)
2097                         dspcntr |= DISPPLANE_TILED;
2098                 else
2099                         dspcntr &= ~DISPPLANE_TILED;
2100         }
2101
2102         I915_WRITE(reg, dspcntr);
2103
2104         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2105
2106         if (INTEL_INFO(dev)->gen >= 4) {
2107                 intel_crtc->dspaddr_offset =
2108                         intel_gen4_compute_offset_xtiled(&x, &y,
2109                                                          fb->bits_per_pixel / 8,
2110                                                          fb->pitches[0]);
2111                 linear_offset -= intel_crtc->dspaddr_offset;
2112         } else {
2113                 intel_crtc->dspaddr_offset = linear_offset;
2114         }
2115
2116         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2118         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119         if (INTEL_INFO(dev)->gen >= 4) {
2120                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2121                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2122                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2123                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2124         } else
2125                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2126         POSTING_READ(reg);
2127
2128         return 0;
2129 }
2130
2131 static int ironlake_update_plane(struct drm_crtc *crtc,
2132                                  struct drm_framebuffer *fb, int x, int y)
2133 {
2134         struct drm_device *dev = crtc->dev;
2135         struct drm_i915_private *dev_priv = dev->dev_private;
2136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137         struct intel_framebuffer *intel_fb;
2138         struct drm_i915_gem_object *obj;
2139         int plane = intel_crtc->plane;
2140         unsigned long linear_offset;
2141         u32 dspcntr;
2142         u32 reg;
2143
2144         switch (plane) {
2145         case 0:
2146         case 1:
2147         case 2:
2148                 break;
2149         default:
2150                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2151                 return -EINVAL;
2152         }
2153
2154         intel_fb = to_intel_framebuffer(fb);
2155         obj = intel_fb->obj;
2156
2157         reg = DSPCNTR(plane);
2158         dspcntr = I915_READ(reg);
2159         /* Mask out pixel format bits in case we change it */
2160         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2161         switch (fb->pixel_format) {
2162         case DRM_FORMAT_C8:
2163                 dspcntr |= DISPPLANE_8BPP;
2164                 break;
2165         case DRM_FORMAT_RGB565:
2166                 dspcntr |= DISPPLANE_BGRX565;
2167                 break;
2168         case DRM_FORMAT_XRGB8888:
2169         case DRM_FORMAT_ARGB8888:
2170                 dspcntr |= DISPPLANE_BGRX888;
2171                 break;
2172         case DRM_FORMAT_XBGR8888:
2173         case DRM_FORMAT_ABGR8888:
2174                 dspcntr |= DISPPLANE_RGBX888;
2175                 break;
2176         case DRM_FORMAT_XRGB2101010:
2177         case DRM_FORMAT_ARGB2101010:
2178                 dspcntr |= DISPPLANE_BGRX101010;
2179                 break;
2180         case DRM_FORMAT_XBGR2101010:
2181         case DRM_FORMAT_ABGR2101010:
2182                 dspcntr |= DISPPLANE_RGBX101010;
2183                 break;
2184         default:
2185                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2186                 return -EINVAL;
2187         }
2188
2189         if (obj->tiling_mode != I915_TILING_NONE)
2190                 dspcntr |= DISPPLANE_TILED;
2191         else
2192                 dspcntr &= ~DISPPLANE_TILED;
2193
2194         /* must disable */
2195         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2196
2197         I915_WRITE(reg, dspcntr);
2198
2199         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2200         intel_crtc->dspaddr_offset =
2201                 intel_gen4_compute_offset_xtiled(&x, &y,
2202                                                  fb->bits_per_pixel / 8,
2203                                                  fb->pitches[0]);
2204         linear_offset -= intel_crtc->dspaddr_offset;
2205
2206         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2207                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2208         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2209         I915_MODIFY_DISPBASE(DSPSURF(plane),
2210                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2211         if (IS_HASWELL(dev)) {
2212                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2213         } else {
2214                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2215                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2216         }
2217         POSTING_READ(reg);
2218
2219         return 0;
2220 }
2221
2222 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2223 static int
2224 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2225                            int x, int y, enum mode_set_atomic state)
2226 {
2227         struct drm_device *dev = crtc->dev;
2228         struct drm_i915_private *dev_priv = dev->dev_private;
2229
2230         if (dev_priv->display.disable_fbc)
2231                 dev_priv->display.disable_fbc(dev);
2232         intel_increase_pllclock(crtc);
2233
2234         return dev_priv->display.update_plane(crtc, fb, x, y);
2235 }
2236
2237 static int
2238 intel_finish_fb(struct drm_framebuffer *old_fb)
2239 {
2240         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2241         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2242         bool was_interruptible = dev_priv->mm.interruptible;
2243         int ret;
2244
2245         wait_event(dev_priv->pending_flip_queue,
2246                    atomic_read(&dev_priv->mm.wedged) ||
2247                    atomic_read(&obj->pending_flip) == 0);
2248
2249         /* Big Hammer, we also need to ensure that any pending
2250          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251          * current scanout is retired before unpinning the old
2252          * framebuffer.
2253          *
2254          * This should only fail upon a hung GPU, in which case we
2255          * can safely continue.
2256          */
2257         dev_priv->mm.interruptible = false;
2258         ret = i915_gem_object_finish_gpu(obj);
2259         dev_priv->mm.interruptible = was_interruptible;
2260
2261         return ret;
2262 }
2263
2264 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2265 {
2266         struct drm_device *dev = crtc->dev;
2267         struct drm_i915_master_private *master_priv;
2268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269
2270         if (!dev->primary->master)
2271                 return;
2272
2273         master_priv = dev->primary->master->driver_priv;
2274         if (!master_priv->sarea_priv)
2275                 return;
2276
2277         switch (intel_crtc->pipe) {
2278         case 0:
2279                 master_priv->sarea_priv->pipeA_x = x;
2280                 master_priv->sarea_priv->pipeA_y = y;
2281                 break;
2282         case 1:
2283                 master_priv->sarea_priv->pipeB_x = x;
2284                 master_priv->sarea_priv->pipeB_y = y;
2285                 break;
2286         default:
2287                 break;
2288         }
2289 }
2290
2291 static int
2292 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2293                     struct drm_framebuffer *fb)
2294 {
2295         struct drm_device *dev = crtc->dev;
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298         struct drm_framebuffer *old_fb;
2299         int ret;
2300
2301         /* no fb bound */
2302         if (!fb) {
2303                 DRM_ERROR("No FB bound\n");
2304                 return 0;
2305         }
2306
2307         if(intel_crtc->plane > dev_priv->num_pipe) {
2308                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2309                                 intel_crtc->plane,
2310                                 dev_priv->num_pipe);
2311                 return -EINVAL;
2312         }
2313
2314         mutex_lock(&dev->struct_mutex);
2315         ret = intel_pin_and_fence_fb_obj(dev,
2316                                          to_intel_framebuffer(fb)->obj,
2317                                          NULL);
2318         if (ret != 0) {
2319                 mutex_unlock(&dev->struct_mutex);
2320                 DRM_ERROR("pin & fence failed\n");
2321                 return ret;
2322         }
2323
2324         if (crtc->fb)
2325                 intel_finish_fb(crtc->fb);
2326
2327         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2328         if (ret) {
2329                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2330                 mutex_unlock(&dev->struct_mutex);
2331                 DRM_ERROR("failed to update base address\n");
2332                 return ret;
2333         }
2334
2335         old_fb = crtc->fb;
2336         crtc->fb = fb;
2337         crtc->x = x;
2338         crtc->y = y;
2339
2340         if (old_fb) {
2341                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2342                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2343         }
2344
2345         intel_update_fbc(dev);
2346         mutex_unlock(&dev->struct_mutex);
2347
2348         intel_crtc_update_sarea_pos(crtc, x, y);
2349
2350         return 0;
2351 }
2352
2353 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2354 {
2355         struct drm_device *dev = crtc->dev;
2356         struct drm_i915_private *dev_priv = dev->dev_private;
2357         u32 dpa_ctl;
2358
2359         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2360         dpa_ctl = I915_READ(DP_A);
2361         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2362
2363         if (clock < 200000) {
2364                 u32 temp;
2365                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2366                 /* workaround for 160Mhz:
2367                    1) program 0x4600c bits 15:0 = 0x8124
2368                    2) program 0x46010 bit 0 = 1
2369                    3) program 0x46034 bit 24 = 1
2370                    4) program 0x64000 bit 14 = 1
2371                    */
2372                 temp = I915_READ(0x4600c);
2373                 temp &= 0xffff0000;
2374                 I915_WRITE(0x4600c, temp | 0x8124);
2375
2376                 temp = I915_READ(0x46010);
2377                 I915_WRITE(0x46010, temp | 1);
2378
2379                 temp = I915_READ(0x46034);
2380                 I915_WRITE(0x46034, temp | (1 << 24));
2381         } else {
2382                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2383         }
2384         I915_WRITE(DP_A, dpa_ctl);
2385
2386         POSTING_READ(DP_A);
2387         udelay(500);
2388 }
2389
2390 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2391 {
2392         struct drm_device *dev = crtc->dev;
2393         struct drm_i915_private *dev_priv = dev->dev_private;
2394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2395         int pipe = intel_crtc->pipe;
2396         u32 reg, temp;
2397
2398         /* enable normal train */
2399         reg = FDI_TX_CTL(pipe);
2400         temp = I915_READ(reg);
2401         if (IS_IVYBRIDGE(dev)) {
2402                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2403                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2404         } else {
2405                 temp &= ~FDI_LINK_TRAIN_NONE;
2406                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2407         }
2408         I915_WRITE(reg, temp);
2409
2410         reg = FDI_RX_CTL(pipe);
2411         temp = I915_READ(reg);
2412         if (HAS_PCH_CPT(dev)) {
2413                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2415         } else {
2416                 temp &= ~FDI_LINK_TRAIN_NONE;
2417                 temp |= FDI_LINK_TRAIN_NONE;
2418         }
2419         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2420
2421         /* wait one idle pattern time */
2422         POSTING_READ(reg);
2423         udelay(1000);
2424
2425         /* IVB wants error correction enabled */
2426         if (IS_IVYBRIDGE(dev))
2427                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2428                            FDI_FE_ERRC_ENABLE);
2429 }
2430
2431 static void ivb_modeset_global_resources(struct drm_device *dev)
2432 {
2433         struct drm_i915_private *dev_priv = dev->dev_private;
2434         struct intel_crtc *pipe_B_crtc =
2435                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2436         struct intel_crtc *pipe_C_crtc =
2437                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2438         uint32_t temp;
2439
2440         /* When everything is off disable fdi C so that we could enable fdi B
2441          * with all lanes. XXX: This misses the case where a pipe is not using
2442          * any pch resources and so doesn't need any fdi lanes. */
2443         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2444                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2445                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2446
2447                 temp = I915_READ(SOUTH_CHICKEN1);
2448                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2449                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2450                 I915_WRITE(SOUTH_CHICKEN1, temp);
2451         }
2452 }
2453
2454 /* The FDI link training functions for ILK/Ibexpeak. */
2455 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2456 {
2457         struct drm_device *dev = crtc->dev;
2458         struct drm_i915_private *dev_priv = dev->dev_private;
2459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2460         int pipe = intel_crtc->pipe;
2461         int plane = intel_crtc->plane;
2462         u32 reg, temp, tries;
2463
2464         /* FDI needs bits from pipe & plane first */
2465         assert_pipe_enabled(dev_priv, pipe);
2466         assert_plane_enabled(dev_priv, plane);
2467
2468         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469            for train result */
2470         reg = FDI_RX_IMR(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_RX_SYMBOL_LOCK;
2473         temp &= ~FDI_RX_BIT_LOCK;
2474         I915_WRITE(reg, temp);
2475         I915_READ(reg);
2476         udelay(150);
2477
2478         /* enable CPU FDI TX and PCH FDI RX */
2479         reg = FDI_TX_CTL(pipe);
2480         temp = I915_READ(reg);
2481         temp &= ~(7 << 19);
2482         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2483         temp &= ~FDI_LINK_TRAIN_NONE;
2484         temp |= FDI_LINK_TRAIN_PATTERN_1;
2485         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2486
2487         reg = FDI_RX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~FDI_LINK_TRAIN_NONE;
2490         temp |= FDI_LINK_TRAIN_PATTERN_1;
2491         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492
2493         POSTING_READ(reg);
2494         udelay(150);
2495
2496         /* Ironlake workaround, enable clock pointer after FDI enable*/
2497         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2498         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2499                    FDI_RX_PHASE_SYNC_POINTER_EN);
2500
2501         reg = FDI_RX_IIR(pipe);
2502         for (tries = 0; tries < 5; tries++) {
2503                 temp = I915_READ(reg);
2504                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505
2506                 if ((temp & FDI_RX_BIT_LOCK)) {
2507                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2508                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2509                         break;
2510                 }
2511         }
2512         if (tries == 5)
2513                 DRM_ERROR("FDI train 1 fail!\n");
2514
2515         /* Train 2 */
2516         reg = FDI_TX_CTL(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_LINK_TRAIN_NONE;
2519         temp |= FDI_LINK_TRAIN_PATTERN_2;
2520         I915_WRITE(reg, temp);
2521
2522         reg = FDI_RX_CTL(pipe);
2523         temp = I915_READ(reg);
2524         temp &= ~FDI_LINK_TRAIN_NONE;
2525         temp |= FDI_LINK_TRAIN_PATTERN_2;
2526         I915_WRITE(reg, temp);
2527
2528         POSTING_READ(reg);
2529         udelay(150);
2530
2531         reg = FDI_RX_IIR(pipe);
2532         for (tries = 0; tries < 5; tries++) {
2533                 temp = I915_READ(reg);
2534                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535
2536                 if (temp & FDI_RX_SYMBOL_LOCK) {
2537                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2539                         break;
2540                 }
2541         }
2542         if (tries == 5)
2543                 DRM_ERROR("FDI train 2 fail!\n");
2544
2545         DRM_DEBUG_KMS("FDI train done\n");
2546
2547 }
2548
2549 static const int snb_b_fdi_train_param[] = {
2550         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2551         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2552         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2553         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2554 };
2555
2556 /* The FDI link training functions for SNB/Cougarpoint. */
2557 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2558 {
2559         struct drm_device *dev = crtc->dev;
2560         struct drm_i915_private *dev_priv = dev->dev_private;
2561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562         int pipe = intel_crtc->pipe;
2563         u32 reg, temp, i, retry;
2564
2565         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2566            for train result */
2567         reg = FDI_RX_IMR(pipe);
2568         temp = I915_READ(reg);
2569         temp &= ~FDI_RX_SYMBOL_LOCK;
2570         temp &= ~FDI_RX_BIT_LOCK;
2571         I915_WRITE(reg, temp);
2572
2573         POSTING_READ(reg);
2574         udelay(150);
2575
2576         /* enable CPU FDI TX and PCH FDI RX */
2577         reg = FDI_TX_CTL(pipe);
2578         temp = I915_READ(reg);
2579         temp &= ~(7 << 19);
2580         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2581         temp &= ~FDI_LINK_TRAIN_NONE;
2582         temp |= FDI_LINK_TRAIN_PATTERN_1;
2583         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2584         /* SNB-B */
2585         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2586         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2587
2588         I915_WRITE(FDI_RX_MISC(pipe),
2589                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2590
2591         reg = FDI_RX_CTL(pipe);
2592         temp = I915_READ(reg);
2593         if (HAS_PCH_CPT(dev)) {
2594                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2595                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2596         } else {
2597                 temp &= ~FDI_LINK_TRAIN_NONE;
2598                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2599         }
2600         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2601
2602         POSTING_READ(reg);
2603         udelay(150);
2604
2605         for (i = 0; i < 4; i++) {
2606                 reg = FDI_TX_CTL(pipe);
2607                 temp = I915_READ(reg);
2608                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2609                 temp |= snb_b_fdi_train_param[i];
2610                 I915_WRITE(reg, temp);
2611
2612                 POSTING_READ(reg);
2613                 udelay(500);
2614
2615                 for (retry = 0; retry < 5; retry++) {
2616                         reg = FDI_RX_IIR(pipe);
2617                         temp = I915_READ(reg);
2618                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619                         if (temp & FDI_RX_BIT_LOCK) {
2620                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2621                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2622                                 break;
2623                         }
2624                         udelay(50);
2625                 }
2626                 if (retry < 5)
2627                         break;
2628         }
2629         if (i == 4)
2630                 DRM_ERROR("FDI train 1 fail!\n");
2631
2632         /* Train 2 */
2633         reg = FDI_TX_CTL(pipe);
2634         temp = I915_READ(reg);
2635         temp &= ~FDI_LINK_TRAIN_NONE;
2636         temp |= FDI_LINK_TRAIN_PATTERN_2;
2637         if (IS_GEN6(dev)) {
2638                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639                 /* SNB-B */
2640                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641         }
2642         I915_WRITE(reg, temp);
2643
2644         reg = FDI_RX_CTL(pipe);
2645         temp = I915_READ(reg);
2646         if (HAS_PCH_CPT(dev)) {
2647                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2648                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2649         } else {
2650                 temp &= ~FDI_LINK_TRAIN_NONE;
2651                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2652         }
2653         I915_WRITE(reg, temp);
2654
2655         POSTING_READ(reg);
2656         udelay(150);
2657
2658         for (i = 0; i < 4; i++) {
2659                 reg = FDI_TX_CTL(pipe);
2660                 temp = I915_READ(reg);
2661                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662                 temp |= snb_b_fdi_train_param[i];
2663                 I915_WRITE(reg, temp);
2664
2665                 POSTING_READ(reg);
2666                 udelay(500);
2667
2668                 for (retry = 0; retry < 5; retry++) {
2669                         reg = FDI_RX_IIR(pipe);
2670                         temp = I915_READ(reg);
2671                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2672                         if (temp & FDI_RX_SYMBOL_LOCK) {
2673                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2674                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2675                                 break;
2676                         }
2677                         udelay(50);
2678                 }
2679                 if (retry < 5)
2680                         break;
2681         }
2682         if (i == 4)
2683                 DRM_ERROR("FDI train 2 fail!\n");
2684
2685         DRM_DEBUG_KMS("FDI train done.\n");
2686 }
2687
2688 /* Manual link training for Ivy Bridge A0 parts */
2689 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2690 {
2691         struct drm_device *dev = crtc->dev;
2692         struct drm_i915_private *dev_priv = dev->dev_private;
2693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694         int pipe = intel_crtc->pipe;
2695         u32 reg, temp, i;
2696
2697         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2698            for train result */
2699         reg = FDI_RX_IMR(pipe);
2700         temp = I915_READ(reg);
2701         temp &= ~FDI_RX_SYMBOL_LOCK;
2702         temp &= ~FDI_RX_BIT_LOCK;
2703         I915_WRITE(reg, temp);
2704
2705         POSTING_READ(reg);
2706         udelay(150);
2707
2708         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2709                       I915_READ(FDI_RX_IIR(pipe)));
2710
2711         /* enable CPU FDI TX and PCH FDI RX */
2712         reg = FDI_TX_CTL(pipe);
2713         temp = I915_READ(reg);
2714         temp &= ~(7 << 19);
2715         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2716         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2717         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2718         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2720         temp |= FDI_COMPOSITE_SYNC;
2721         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2722
2723         I915_WRITE(FDI_RX_MISC(pipe),
2724                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2725
2726         reg = FDI_RX_CTL(pipe);
2727         temp = I915_READ(reg);
2728         temp &= ~FDI_LINK_TRAIN_AUTO;
2729         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2730         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2731         temp |= FDI_COMPOSITE_SYNC;
2732         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2733
2734         POSTING_READ(reg);
2735         udelay(150);
2736
2737         for (i = 0; i < 4; i++) {
2738                 reg = FDI_TX_CTL(pipe);
2739                 temp = I915_READ(reg);
2740                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741                 temp |= snb_b_fdi_train_param[i];
2742                 I915_WRITE(reg, temp);
2743
2744                 POSTING_READ(reg);
2745                 udelay(500);
2746
2747                 reg = FDI_RX_IIR(pipe);
2748                 temp = I915_READ(reg);
2749                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2750
2751                 if (temp & FDI_RX_BIT_LOCK ||
2752                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2753                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2754                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2755                         break;
2756                 }
2757         }
2758         if (i == 4)
2759                 DRM_ERROR("FDI train 1 fail!\n");
2760
2761         /* Train 2 */
2762         reg = FDI_TX_CTL(pipe);
2763         temp = I915_READ(reg);
2764         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2765         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2766         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2768         I915_WRITE(reg, temp);
2769
2770         reg = FDI_RX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2773         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2774         I915_WRITE(reg, temp);
2775
2776         POSTING_READ(reg);
2777         udelay(150);
2778
2779         for (i = 0; i < 4; i++) {
2780                 reg = FDI_TX_CTL(pipe);
2781                 temp = I915_READ(reg);
2782                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783                 temp |= snb_b_fdi_train_param[i];
2784                 I915_WRITE(reg, temp);
2785
2786                 POSTING_READ(reg);
2787                 udelay(500);
2788
2789                 reg = FDI_RX_IIR(pipe);
2790                 temp = I915_READ(reg);
2791                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2792
2793                 if (temp & FDI_RX_SYMBOL_LOCK) {
2794                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2796                         break;
2797                 }
2798         }
2799         if (i == 4)
2800                 DRM_ERROR("FDI train 2 fail!\n");
2801
2802         DRM_DEBUG_KMS("FDI train done.\n");
2803 }
2804
2805 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2806 {
2807         struct drm_device *dev = intel_crtc->base.dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         int pipe = intel_crtc->pipe;
2810         u32 reg, temp;
2811
2812
2813         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~((0x7 << 19) | (0x7 << 16));
2817         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(200);
2823
2824         /* Switch from Rawclk to PCDclk */
2825         temp = I915_READ(reg);
2826         I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828         POSTING_READ(reg);
2829         udelay(200);
2830
2831         /* On Haswell, the PLL configuration for ports and pipes is handled
2832          * separately, as part of DDI setup */
2833         if (!IS_HASWELL(dev)) {
2834                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835                 reg = FDI_TX_CTL(pipe);
2836                 temp = I915_READ(reg);
2837                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2839
2840                         POSTING_READ(reg);
2841                         udelay(100);
2842                 }
2843         }
2844 }
2845
2846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847 {
2848         struct drm_device *dev = intel_crtc->base.dev;
2849         struct drm_i915_private *dev_priv = dev->dev_private;
2850         int pipe = intel_crtc->pipe;
2851         u32 reg, temp;
2852
2853         /* Switch from PCDclk to Rawclk */
2854         reg = FDI_RX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858         /* Disable CPU FDI TX PLL */
2859         reg = FDI_TX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863         POSTING_READ(reg);
2864         udelay(100);
2865
2866         reg = FDI_RX_CTL(pipe);
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870         /* Wait for the clocks to turn off. */
2871         POSTING_READ(reg);
2872         udelay(100);
2873 }
2874
2875 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876 {
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880         int pipe = intel_crtc->pipe;
2881         u32 reg, temp;
2882
2883         /* disable CPU FDI tx and PCH FDI rx */
2884         reg = FDI_TX_CTL(pipe);
2885         temp = I915_READ(reg);
2886         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887         POSTING_READ(reg);
2888
2889         reg = FDI_RX_CTL(pipe);
2890         temp = I915_READ(reg);
2891         temp &= ~(0x7 << 16);
2892         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2893         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895         POSTING_READ(reg);
2896         udelay(100);
2897
2898         /* Ironlake workaround, disable clock pointer after downing FDI */
2899         if (HAS_PCH_IBX(dev)) {
2900                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2901         }
2902
2903         /* still set train pattern 1 */
2904         reg = FDI_TX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         temp &= ~FDI_LINK_TRAIN_NONE;
2907         temp |= FDI_LINK_TRAIN_PATTERN_1;
2908         I915_WRITE(reg, temp);
2909
2910         reg = FDI_RX_CTL(pipe);
2911         temp = I915_READ(reg);
2912         if (HAS_PCH_CPT(dev)) {
2913                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915         } else {
2916                 temp &= ~FDI_LINK_TRAIN_NONE;
2917                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918         }
2919         /* BPC in FDI rx is consistent with that in PIPECONF */
2920         temp &= ~(0x07 << 16);
2921         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2922         I915_WRITE(reg, temp);
2923
2924         POSTING_READ(reg);
2925         udelay(100);
2926 }
2927
2928 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929 {
2930         struct drm_device *dev = crtc->dev;
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932         unsigned long flags;
2933         bool pending;
2934
2935         if (atomic_read(&dev_priv->mm.wedged))
2936                 return false;
2937
2938         spin_lock_irqsave(&dev->event_lock, flags);
2939         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2940         spin_unlock_irqrestore(&dev->event_lock, flags);
2941
2942         return pending;
2943 }
2944
2945 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2946 {
2947         struct drm_device *dev = crtc->dev;
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949
2950         if (crtc->fb == NULL)
2951                 return;
2952
2953         wait_event(dev_priv->pending_flip_queue,
2954                    !intel_crtc_has_pending_flip(crtc));
2955
2956         mutex_lock(&dev->struct_mutex);
2957         intel_finish_fb(crtc->fb);
2958         mutex_unlock(&dev->struct_mutex);
2959 }
2960
2961 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2962 {
2963         struct drm_device *dev = crtc->dev;
2964         struct intel_encoder *intel_encoder;
2965
2966         /*
2967          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2968          * must be driven by its own crtc; no sharing is possible.
2969          */
2970         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2971                 switch (intel_encoder->type) {
2972                 case INTEL_OUTPUT_EDP:
2973                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2974                                 return false;
2975                         continue;
2976                 }
2977         }
2978
2979         return true;
2980 }
2981
2982 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2983 {
2984         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2985 }
2986
2987 /* Program iCLKIP clock to the desired frequency */
2988 static void lpt_program_iclkip(struct drm_crtc *crtc)
2989 {
2990         struct drm_device *dev = crtc->dev;
2991         struct drm_i915_private *dev_priv = dev->dev_private;
2992         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2993         u32 temp;
2994
2995         /* It is necessary to ungate the pixclk gate prior to programming
2996          * the divisors, and gate it back when it is done.
2997          */
2998         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2999
3000         /* Disable SSCCTL */
3001         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3002                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3003                                 SBI_SSCCTL_DISABLE,
3004                         SBI_ICLK);
3005
3006         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007         if (crtc->mode.clock == 20000) {
3008                 auxdiv = 1;
3009                 divsel = 0x41;
3010                 phaseinc = 0x20;
3011         } else {
3012                 /* The iCLK virtual clock root frequency is in MHz,
3013                  * but the crtc->mode.clock in in KHz. To get the divisors,
3014                  * it is necessary to divide one by another, so we
3015                  * convert the virtual clock precision to KHz here for higher
3016                  * precision.
3017                  */
3018                 u32 iclk_virtual_root_freq = 172800 * 1000;
3019                 u32 iclk_pi_range = 64;
3020                 u32 desired_divisor, msb_divisor_value, pi_value;
3021
3022                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3023                 msb_divisor_value = desired_divisor / iclk_pi_range;
3024                 pi_value = desired_divisor % iclk_pi_range;
3025
3026                 auxdiv = 0;
3027                 divsel = msb_divisor_value - 2;
3028                 phaseinc = pi_value;
3029         }
3030
3031         /* This should not happen with any sane values */
3032         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3036
3037         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3038                         crtc->mode.clock,
3039                         auxdiv,
3040                         divsel,
3041                         phasedir,
3042                         phaseinc);
3043
3044         /* Program SSCDIVINTPHASE6 */
3045         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3046         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3052         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3053
3054         /* Program SSCAUXDIV */
3055         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3056         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3058         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3059
3060         /* Enable modulator and associated divider */
3061         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3062         temp &= ~SBI_SSCCTL_DISABLE;
3063         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3064
3065         /* Wait for initialization time */
3066         udelay(24);
3067
3068         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3069 }
3070
3071 /*
3072  * Enable PCH resources required for PCH ports:
3073  *   - PCH PLLs
3074  *   - FDI training & RX/TX
3075  *   - update transcoder timings
3076  *   - DP transcoding bits
3077  *   - transcoder
3078  */
3079 static void ironlake_pch_enable(struct drm_crtc *crtc)
3080 {
3081         struct drm_device *dev = crtc->dev;
3082         struct drm_i915_private *dev_priv = dev->dev_private;
3083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084         int pipe = intel_crtc->pipe;
3085         u32 reg, temp;
3086
3087         assert_transcoder_disabled(dev_priv, pipe);
3088
3089         /* Write the TU size bits before fdi link training, so that error
3090          * detection works. */
3091         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
3094         /* For PCH output, training FDI link */
3095         dev_priv->display.fdi_link_train(crtc);
3096
3097         /* XXX: pch pll's can be enabled any time before we enable the PCH
3098          * transcoder, and we actually should do this to not upset any PCH
3099          * transcoder that already use the clock when we share it.
3100          *
3101          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102          * unconditionally resets the pll - we need that to have the right LVDS
3103          * enable sequence. */
3104         ironlake_enable_pch_pll(intel_crtc);
3105
3106         if (HAS_PCH_CPT(dev)) {
3107                 u32 sel;
3108
3109                 temp = I915_READ(PCH_DPLL_SEL);
3110                 switch (pipe) {
3111                 default:
3112                 case 0:
3113                         temp |= TRANSA_DPLL_ENABLE;
3114                         sel = TRANSA_DPLLB_SEL;
3115                         break;
3116                 case 1:
3117                         temp |= TRANSB_DPLL_ENABLE;
3118                         sel = TRANSB_DPLLB_SEL;
3119                         break;
3120                 case 2:
3121                         temp |= TRANSC_DPLL_ENABLE;
3122                         sel = TRANSC_DPLLB_SEL;
3123                         break;
3124                 }
3125                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3126                         temp |= sel;
3127                 else
3128                         temp &= ~sel;
3129                 I915_WRITE(PCH_DPLL_SEL, temp);
3130         }
3131
3132         /* set transcoder timing, panel must allow it */
3133         assert_panel_unlocked(dev_priv, pipe);
3134         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3137
3138         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3141         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3142
3143         intel_fdi_normal_train(crtc);
3144
3145         /* For PCH DP, enable TRANS_DP_CTL */
3146         if (HAS_PCH_CPT(dev) &&
3147             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3149                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3150                 reg = TRANS_DP_CTL(pipe);
3151                 temp = I915_READ(reg);
3152                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3153                           TRANS_DP_SYNC_MASK |
3154                           TRANS_DP_BPC_MASK);
3155                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156                          TRANS_DP_ENH_FRAMING);
3157                 temp |= bpc << 9; /* same format but at 11:9 */
3158
3159                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3160                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3161                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3162                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3163
3164                 switch (intel_trans_dp_port_sel(crtc)) {
3165                 case PCH_DP_B:
3166                         temp |= TRANS_DP_PORT_SEL_B;
3167                         break;
3168                 case PCH_DP_C:
3169                         temp |= TRANS_DP_PORT_SEL_C;
3170                         break;
3171                 case PCH_DP_D:
3172                         temp |= TRANS_DP_PORT_SEL_D;
3173                         break;
3174                 default:
3175                         BUG();
3176                 }
3177
3178                 I915_WRITE(reg, temp);
3179         }
3180
3181         ironlake_enable_pch_transcoder(dev_priv, pipe);
3182 }
3183