drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         struct drm_i915_private *dev_priv = dev->dev_private;
 649         const intel_limit_t *limit;
 650         int refclk = 120;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 654                         refclk = 100;
 655
 656                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 657                     LVDS_CLKB_POWER_UP) {
 658                         /* LVDS dual channel */
 659                         if (refclk == 100)
 660                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 661                         else
 662                                 limit = &intel_limits_ironlake_dual_lvds;
 663                 } else {
 664                         if (refclk == 100)
 665                                 limit = &intel_limits_ironlake_single_lvds_100m;
 666                         else
 667                                 limit = &intel_limits_ironlake_single_lvds;
 668                 }
 669         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 670                         HAS_eDP)
 671                 limit = &intel_limits_ironlake_display_port;
 672         else
 673                 limit = &intel_limits_ironlake_dac;
 674
 675         return limit;
 676 }
 677
 678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         const intel_limit_t *limit;
 683
 684         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 685                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 686                     LVDS_CLKB_POWER_UP)
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_dual_channel_lvds;
 689                 else
 690                         /* LVDS with dual channel */
 691                         limit = &intel_limits_g4x_single_channel_lvds;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 694                 limit = &intel_limits_g4x_hdmi;
 695         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 696                 limit = &intel_limits_g4x_sdvo;
 697         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 698                 limit = &intel_limits_g4x_display_port;
 699         } else /* The option is for other outputs */
 700                 limit = &intel_limits_i9xx_sdvo;
 701
 702         return limit;
 703 }
 704
 705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 706 {
 707         struct drm_device *dev = crtc->dev;
 708         const intel_limit_t *limit;
 709
 710         if (HAS_PCH_SPLIT(dev))
 711                 limit = intel_ironlake_limit(crtc);
 712         else if (IS_G4X(dev)) {
 713                 limit = intel_g4x_limit(crtc);
 714         } else if (IS_PINEVIEW(dev)) {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_pineview_lvds;
 717                 else
 718                         limit = &intel_limits_pineview_sdvo;
 719         } else if (!IS_GEN2(dev)) {
 720                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 721                         limit = &intel_limits_i9xx_lvds;
 722                 else
 723                         limit = &intel_limits_i9xx_sdvo;
 724         } else {
 725                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 726                         limit = &intel_limits_i8xx_lvds;
 727                 else
 728                         limit = &intel_limits_i8xx_dvo;
 729         }
 730         return limit;
 731 }
 732
 733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 734 static void pineview_clock(int refclk, intel_clock_t *clock)
 735 {
 736         clock->m = clock->m2 + 2;
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / clock->n;
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 743 {
 744         if (IS_PINEVIEW(dev)) {
 745                 pineview_clock(refclk, clock);
 746                 return;
 747         }
 748         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 749         clock->p = clock->p1 * clock->p2;
 750         clock->vco = refclk * clock->m / (clock->n + 2);
 751         clock->dot = clock->vco / clock->p;
 752 }
 753
 754 /**
 755  * Returns whether any output on the specified pipe is of the specified type
 756  */
 757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         struct drm_mode_config *mode_config = &dev->mode_config;
 761         struct intel_encoder *encoder;
 762
 763         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 764                 if (encoder->base.crtc == crtc && encoder->type == type)
 765                         return true;
 766
 767         return false;
 768 }
 769
 770 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 771 /**
 772  * Returns whether the given set of divisors are valid for a given refclk with
 773  * the given connectors.
 774  */
 775
 776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 777 {
 778         const intel_limit_t *limit = intel_limit (crtc);
 779         struct drm_device *dev = crtc->dev;
 780
 781         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 782                 INTELPllInvalid ("p1 out of range\n");
 783         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 784                 INTELPllInvalid ("p out of range\n");
 785         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 786                 INTELPllInvalid ("m2 out of range\n");
 787         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 788                 INTELPllInvalid ("m1 out of range\n");
 789         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 790                 INTELPllInvalid ("m1 <= m2\n");
 791         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 792                 INTELPllInvalid ("m out of range\n");
 793         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 794                 INTELPllInvalid ("n out of range\n");
 795         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 796                 INTELPllInvalid ("vco out of range\n");
 797         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 798          * connector, etc., rather than just a single range.
 799          */
 800         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 801                 INTELPllInvalid ("dot out of range\n");
 802
 803         return true;
 804 }
 805
 806 static bool
 807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 808                     int target, int refclk, intel_clock_t *best_clock)
 809
 810 {
 811         struct drm_device *dev = crtc->dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         intel_clock_t clock;
 814         int err = target;
 815
 816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 817             (I915_READ(LVDS)) != 0) {
 818                 /*
 819                  * For LVDS, if the panel is on, just rely on its current
 820                  * settings for dual-channel.  We haven't figured out how to
 821                  * reliably set up different single/dual channel state, if we
 822                  * even can.
 823                  */
 824                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 825                     LVDS_CLKB_POWER_UP)
 826                         clock.p2 = limit->p2.p2_fast;
 827                 else
 828                         clock.p2 = limit->p2.p2_slow;
 829         } else {
 830                 if (target < limit->p2.dot_limit)
 831                         clock.p2 = limit->p2.p2_slow;
 832                 else
 833                         clock.p2 = limit->p2.p2_fast;
 834         }
 835
 836         memset (best_clock, 0, sizeof (*best_clock));
 837
 838         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 839              clock.m1++) {
 840                 for (clock.m2 = limit->m2.min;
 841                      clock.m2 <= limit->m2.max; clock.m2++) {
 842                         /* m1 is always 0 in Pineview */
 843                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 844                                 break;
 845                         for (clock.n = limit->n.min;
 846                              clock.n <= limit->n.max; clock.n++) {
 847                                 for (clock.p1 = limit->p1.min;
 848                                         clock.p1 <= limit->p1.max; clock.p1++) {
 849                                         int this_err;
 850
 851                                         intel_clock(dev, refclk, &clock);
 852
 853                                         if (!intel_PLL_is_valid(crtc, &clock))
 854                                                 continue;
 855
 856                                         this_err = abs(clock.dot - target);
 857                                         if (this_err < err) {
 858                                                 *best_clock = clock;
 859                                                 err = this_err;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865
 866         return (err != target);
 867 }
 868
 869 static bool
 870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *best_clock)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         intel_clock_t clock;
 876         int max_n;
 877         bool found;
 878         /* approximately equals target * 0.00585 */
 879         int err_most = (target >> 8) + (target >> 9);
 880         found = false;
 881
 882         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 883                 int lvds_reg;
 884
 885                 if (HAS_PCH_SPLIT(dev))
 886                         lvds_reg = PCH_LVDS;
 887                 else
 888                         lvds_reg = LVDS;
 889                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 890                     LVDS_CLKB_POWER_UP)
 891                         clock.p2 = limit->p2.p2_fast;
 892                 else
 893                         clock.p2 = limit->p2.p2_slow;
 894         } else {
 895                 if (target < limit->p2.dot_limit)
 896                         clock.p2 = limit->p2.p2_slow;
 897                 else
 898                         clock.p2 = limit->p2.p2_fast;
 899         }
 900
 901         memset(best_clock, 0, sizeof(*best_clock));
 902         max_n = limit->n.max;
 903         /* based on hardware requirement, prefer smaller n to precision */
 904         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 905                 /* based on hardware requirement, prefere larger m1,m2 */
 906                 for (clock.m1 = limit->m1.max;
 907                      clock.m1 >= limit->m1.min; clock.m1--) {
 908                         for (clock.m2 = limit->m2.max;
 909                              clock.m2 >= limit->m2.min; clock.m2--) {
 910                                 for (clock.p1 = limit->p1.max;
 911                                      clock.p1 >= limit->p1.min; clock.p1--) {
 912                                         int this_err;
 913
 914                                         intel_clock(dev, refclk, &clock);
 915                                         if (!intel_PLL_is_valid(crtc, &clock))
 916                                                 continue;
 917                                         this_err = abs(clock.dot - target) ;
 918                                         if (this_err < err_most) {
 919                                                 *best_clock = clock;
 920                                                 err_most = this_err;
 921                                                 max_n = clock.n;
 922                                                 found = true;
 923                                         }
 924                                 }
 925                         }
 926                 }
 927         }
 928         return found;
 929 }
 930
 931 static bool
 932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 933                            int target, int refclk, intel_clock_t *best_clock)
 934 {
 935         struct drm_device *dev = crtc->dev;
 936         intel_clock_t clock;
 937
 938         if (target < 200000) {
 939                 clock.n = 1;
 940                 clock.p1 = 2;
 941                 clock.p2 = 10;
 942                 clock.m1 = 12;
 943                 clock.m2 = 9;
 944         } else {
 945                 clock.n = 2;
 946                 clock.p1 = 1;
 947                 clock.p2 = 10;
 948                 clock.m1 = 14;
 949                 clock.m2 = 8;
 950         }
 951         intel_clock(dev, refclk, &clock);
 952         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 953         return true;
 954 }
 955
 956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 957 static bool
 958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 959                       int target, int refclk, intel_clock_t *best_clock)
 960 {
 961         intel_clock_t clock;
 962         if (target < 200000) {
 963                 clock.p1 = 2;
 964                 clock.p2 = 10;
 965                 clock.n = 2;
 966                 clock.m1 = 23;
 967                 clock.m2 = 8;
 968         } else {
 969                 clock.p1 = 1;
 970                 clock.p2 = 10;
 971                 clock.n = 1;
 972                 clock.m1 = 14;
 973                 clock.m2 = 2;
 974         }
 975         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 976         clock.p = (clock.p1 * clock.p2);
 977         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 978         clock.vco = 0;
 979         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 980         return true;
 981 }
 982
 983 /**
 984  * intel_wait_for_vblank - wait for vblank on a given pipe
 985  * @dev: drm device
 986  * @pipe: pipe to wait for
 987  *
 988  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 989  * mode setting code.
 990  */
 991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 992 {
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 995
 996         /* Clear existing vblank status. Note this will clear any other
 997          * sticky status fields as well.
 998          *
 999          * This races with i915_driver_irq_handler() with the result
1000          * that either function could miss a vblank event.  Here it is not
1001          * fatal, as we will either wait upon the next vblank interrupt or
1002          * timeout.  Generally speaking intel_wait_for_vblank() is only
1003          * called during modeset at which time the GPU should be idle and
1004          * should *not* be performing page flips and thus not waiting on
1005          * vblanks...
1006          * Currently, the result of us stealing a vblank from the irq
1007          * handler is that a single frame will be skipped during swapbuffers.
1008          */
1009         I915_WRITE(pipestat_reg,
1010                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012         /* Wait for vblank interrupt bit to set */
1013         if (wait_for(I915_READ(pipestat_reg) &
1014                      PIPE_VBLANK_INTERRUPT_STATUS,
1015                      50))
1016                 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @dev: drm device
1022  * @pipe: pipe to wait for
1023  *
1024  * After disabling a pipe, we can't wait for vblank in the usual way,
1025  * spinning on the vblank interrupt status bit, since we won't actually
1026  * see an interrupt when the pipe is disabled.
1027  *
1028  * On Gen4 and above:
1029  *   wait for the pipe register state bit to turn off
1030  *
1031  * Otherwise:
1032  *   wait for the display line value to settle (it usually
1033  *   ends up stopping at the start of the next frame).
1034  *
1035  */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040         if (INTEL_INFO(dev)->gen >= 4) {
1041                 int reg = PIPECONF(pipe);
1042
1043                 /* Wait for the Pipe State to go off */
1044                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045                              100))
1046                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047         } else {
1048                 u32 last_line;
1049                 int reg = PIPEDSL(pipe);
1050                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052                 /* Wait for the display line to settle */
1053                 do {
1054                         last_line = I915_READ(reg) & DSL_LINEMASK;
1055                         mdelay(5);
1056                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057                          time_after(timeout, jiffies));
1058                 if (time_after(jiffies, timeout))
1059                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060         }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         struct drm_framebuffer *fb = crtc->fb;
1068         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071         int plane, i;
1072         u32 fbc_ctl, fbc_ctl2;
1073
1074         if (fb->pitch == dev_priv->cfb_pitch &&
1075             obj_priv->fence_reg == dev_priv->cfb_fence &&
1076             intel_crtc->plane == dev_priv->cfb_plane &&
1077             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078                 return;
1079
1080         i8xx_disable_fbc(dev);
1081
1082         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084         if (fb->pitch < dev_priv->cfb_pitch)
1085                 dev_priv->cfb_pitch = fb->pitch;
1086
1087         /* FBC_CTL wants 64B units */
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093         /* Clear old tags */
1094         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095                 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097         /* Set it up... */
1098         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099         if (obj_priv->tiling_mode != I915_TILING_NONE)
1100                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104         /* enable it... */
1105         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106         if (IS_I945GM(dev))
1107                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110         if (obj_priv->tiling_mode != I915_TILING_NONE)
1111                 fbc_ctl |= dev_priv->cfb_fence;
1112         I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 fbc_ctl;
1122
1123         /* Disable compression */
1124         fbc_ctl = I915_READ(FBC_CONTROL);
1125         if ((fbc_ctl & FBC_CTL_EN) == 0)
1126                 return;
1127
1128         fbc_ctl &= ~FBC_CTL_EN;
1129         I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131         /* Wait for compressing bit to clear */
1132         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133                 DRM_DEBUG_KMS("FBC idle timed out\n");
1134                 return;
1135         }
1136
1137         DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_framebuffer *fb = crtc->fb;
1152         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156         unsigned long stall_watermark = 200;
1157         u32 dpfc_ctl;
1158
1159         dpfc_ctl = I915_READ(DPFC_CONTROL);
1160         if (dpfc_ctl & DPFC_CTL_EN) {
1161                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1163                     dev_priv->cfb_plane == intel_crtc->plane &&
1164                     dev_priv->cfb_y == crtc->y)
1165                         return;
1166
1167                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168                 POSTING_READ(DPFC_CONTROL);
1169                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170         }
1171
1172         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173         dev_priv->cfb_fence = obj_priv->fence_reg;
1174         dev_priv->cfb_plane = intel_crtc->plane;
1175         dev_priv->cfb_y = crtc->y;
1176
1177         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181         } else {
1182                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183         }
1184
1185         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190         /* enable it... */
1191         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpfc_ctl;
1200
1201         /* Disable compression */
1202         dpfc_ctl = I915_READ(DPFC_CONTROL);
1203         if (dpfc_ctl & DPFC_CTL_EN) {
1204                 dpfc_ctl &= ~DPFC_CTL_EN;
1205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207                 DRM_DEBUG_KMS("disabled FBC\n");
1208         }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220         struct drm_device *dev = crtc->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         struct drm_framebuffer *fb = crtc->fb;
1223         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227         unsigned long stall_watermark = 200;
1228         u32 dpfc_ctl;
1229
1230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231         if (dpfc_ctl & DPFC_CTL_EN) {
1232                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1234                     dev_priv->cfb_plane == intel_crtc->plane &&
1235                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236                     dev_priv->cfb_y == crtc->y)
1237                         return;
1238
1239                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240                 POSTING_READ(ILK_DPFC_CONTROL);
1241                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242         }
1243
1244         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245         dev_priv->cfb_fence = obj_priv->fence_reg;
1246         dev_priv->cfb_plane = intel_crtc->plane;
1247         dev_priv->cfb_offset = obj_priv->gtt_offset;
1248         dev_priv->cfb_y = crtc->y;
1249
1250         dpfc_ctl &= DPFC_RESERVED;
1251         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255         } else {
1256                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257         }
1258
1259         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264         /* enable it... */
1265         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 dpfc_ctl;
1274
1275         /* Disable compression */
1276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277         if (dpfc_ctl & DPFC_CTL_EN) {
1278                 dpfc_ctl &= ~DPFC_CTL_EN;
1279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281                 DRM_DEBUG_KMS("disabled FBC\n");
1282         }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         if (!dev_priv->display.fbc_enabled)
1297                 return false;
1298
1299         return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306         if (!dev_priv->display.enable_fbc)
1307                 return;
1308
1309         dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         if (!dev_priv->display.disable_fbc)
1317                 return;
1318
1319         dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323  * intel_update_fbc - enable/disable FBC as needed
1324  * @dev: the drm_device
1325  *
1326  * Set up the framebuffer compression hardware at mode set time.  We
1327  * enable it if possible:
1328  *   - plane A only (on pre-965)
1329  *   - no pixel mulitply/line duplication
1330  *   - no alpha buffer discard
1331  *   - no dual wide
1332  *   - framebuffer <= 2048 in width, 1536 in height
1333  *
1334  * We can't assume that any compression will take place (worst case),
1335  * so the compressed buffer has to be the same size as the uncompressed
1336  * one.  It also must reside (along with the line length buffer) in
1337  * stolen memory.
1338  *
1339  * We need to enable/disable FBC on a global basis.
1340  */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct drm_crtc *crtc = NULL, *tmp_crtc;
1345         struct intel_crtc *intel_crtc;
1346         struct drm_framebuffer *fb;
1347         struct intel_framebuffer *intel_fb;
1348         struct drm_i915_gem_object *obj_priv;
1349
1350         DRM_DEBUG_KMS("\n");
1351
1352         if (!i915_powersave)
1353                 return;
1354
1355         if (!I915_HAS_FBC(dev))
1356                 return;
1357
1358         /*
1359          * If FBC is already on, we just have to verify that we can
1360          * keep it that way...
1361          * Need to disable if:
1362          *   - more than one pipe is active
1363          *   - changing FBC params (stride, fence, mode)
1364          *   - new fb is too large to fit in compressed buffer
1365          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1366          */
1367         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368                 if (tmp_crtc->enabled) {
1369                         if (crtc) {
1370                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372                                 goto out_disable;
1373                         }
1374                         crtc = tmp_crtc;
1375                 }
1376         }
1377
1378         if (!crtc || crtc->fb == NULL) {
1379                 DRM_DEBUG_KMS("no output, disabling\n");
1380                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381                 goto out_disable;
1382         }
1383
1384         intel_crtc = to_intel_crtc(crtc);
1385         fb = crtc->fb;
1386         intel_fb = to_intel_framebuffer(fb);
1387         obj_priv = to_intel_bo(intel_fb->obj);
1388
1389         if (intel_fb->obj->size > dev_priv->cfb_size) {
1390                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391                               "compression\n");
1392                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393                 goto out_disable;
1394         }
1395         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397                 DRM_DEBUG_KMS("mode incompatible with compression, "
1398                               "disabling\n");
1399                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400                 goto out_disable;
1401         }
1402         if ((crtc->mode.hdisplay > 2048) ||
1403             (crtc->mode.vdisplay > 1536)) {
1404                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406                 goto out_disable;
1407         }
1408         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411                 goto out_disable;
1412         }
1413         if (obj_priv->tiling_mode != I915_TILING_X) {
1414                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416                 goto out_disable;
1417         }
1418
1419         /* If the kernel debugger is active, always disable compression */
1420         if (in_dbg_master())
1421                 goto out_disable;
1422
1423         intel_enable_fbc(crtc, 500);
1424         return;
1425
1426 out_disable:
1427         /* Multiple disables should be harmless */
1428         if (intel_fbc_enabled(dev)) {
1429                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430                 intel_disable_fbc(dev);
1431         }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436                            struct drm_gem_object *obj,
1437                            bool pipelined)
1438 {
1439         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440         u32 alignment;
1441         int ret;
1442
1443         switch (obj_priv->tiling_mode) {
1444         case I915_TILING_NONE:
1445                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446                         alignment = 128 * 1024;
1447                 else if (INTEL_INFO(dev)->gen >= 4)
1448                         alignment = 4 * 1024;
1449                 else
1450                         alignment = 64 * 1024;
1451                 break;
1452         case I915_TILING_X:
1453                 /* pin() will align the object as required by fence */
1454                 alignment = 0;
1455                 break;
1456         case I915_TILING_Y:
1457                 /* FIXME: Is this true? */
1458                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459                 return -EINVAL;
1460         default:
1461                 BUG();
1462         }
1463
1464         ret = i915_gem_object_pin(obj, alignment);
1465         if (ret)
1466                 return ret;
1467
1468         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1469         if (ret)
1470                 goto err_unpin;
1471
1472         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473          * fence, whereas 965+ only requires a fence if using
1474          * framebuffer compression.  For simplicity, we always install
1475          * a fence as the cost is not that onerous.
1476          */
1477         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1478             obj_priv->tiling_mode != I915_TILING_NONE) {
1479                 ret = i915_gem_object_get_fence_reg(obj, false);
1480                 if (ret)
1481                         goto err_unpin;
1482         }
1483
1484         return 0;
1485
1486 err_unpin:
1487         i915_gem_object_unpin(obj);
1488         return ret;
1489 }
1490
1491 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1492 static int
1493 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1494                            int x, int y, enum mode_set_atomic state)
1495 {
1496         struct drm_device *dev = crtc->dev;
1497         struct drm_i915_private *dev_priv = dev->dev_private;
1498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1499         struct intel_framebuffer *intel_fb;
1500         struct drm_i915_gem_object *obj_priv;
1501         struct drm_gem_object *obj;
1502         int plane = intel_crtc->plane;
1503         unsigned long Start, Offset;
1504         u32 dspcntr;
1505         u32 reg;
1506
1507         switch (plane) {
1508         case 0:
1509         case 1:
1510                 break;
1511         default:
1512                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1513                 return -EINVAL;
1514         }
1515
1516         intel_fb = to_intel_framebuffer(fb);
1517         obj = intel_fb->obj;
1518         obj_priv = to_intel_bo(obj);
1519
1520         reg = DSPCNTR(plane);
1521         dspcntr = I915_READ(reg);
1522         /* Mask out pixel format bits in case we change it */
1523         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1524         switch (fb->bits_per_pixel) {
1525         case 8:
1526                 dspcntr |= DISPPLANE_8BPP;
1527                 break;
1528         case 16:
1529                 if (fb->depth == 15)
1530                         dspcntr |= DISPPLANE_15_16BPP;
1531                 else
1532                         dspcntr |= DISPPLANE_16BPP;
1533                 break;
1534         case 24:
1535         case 32:
1536                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1537                 break;
1538         default:
1539                 DRM_ERROR("Unknown color depth\n");
1540                 return -EINVAL;
1541         }
1542         if (INTEL_INFO(dev)->gen >= 4) {
1543                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1544                         dspcntr |= DISPPLANE_TILED;
1545                 else
1546                         dspcntr &= ~DISPPLANE_TILED;
1547         }
1548
1549         if (HAS_PCH_SPLIT(dev))
1550                 /* must disable */
1551                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1552
1553         I915_WRITE(reg, dspcntr);
1554
1555         Start = obj_priv->gtt_offset;
1556         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1557
1558         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559                       Start, Offset, x, y, fb->pitch);
1560         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1561         if (INTEL_INFO(dev)->gen >= 4) {
1562                 I915_WRITE(DSPSURF(plane), Start);
1563                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1564                 I915_WRITE(DSPADDR(plane), Offset);
1565         } else
1566                 I915_WRITE(DSPADDR(plane), Start + Offset);
1567         POSTING_READ(reg);
1568
1569         intel_update_fbc(dev);
1570         intel_increase_pllclock(crtc);
1571
1572         return 0;
1573 }
1574
1575 static int
1576 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1577                     struct drm_framebuffer *old_fb)
1578 {
1579         struct drm_device *dev = crtc->dev;
1580         struct drm_i915_master_private *master_priv;
1581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582         int ret;
1583
1584         /* no fb bound */
1585         if (!crtc->fb) {
1586                 DRM_DEBUG_KMS("No FB bound\n");
1587                 return 0;
1588         }
1589
1590         switch (intel_crtc->plane) {
1591         case 0:
1592         case 1:
1593                 break;
1594         default:
1595                 return -EINVAL;
1596         }
1597
1598         mutex_lock(&dev->struct_mutex);
1599         ret = intel_pin_and_fence_fb_obj(dev,
1600                                          to_intel_framebuffer(crtc->fb)->obj,
1601                                          false);
1602         if (ret != 0) {
1603                 mutex_unlock(&dev->struct_mutex);
1604                 return ret;
1605         }
1606
1607         if (old_fb) {
1608                 struct drm_i915_private *dev_priv = dev->dev_private;
1609                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1610                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1611
1612                 wait_event(dev_priv->pending_flip_queue,
1613                            atomic_read(&obj_priv->pending_flip) == 0);
1614
1615                 /* Big Hammer, we also need to ensure that any pending
1616                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1617                  * current scanout is retired before unpinning the old
1618                  * framebuffer.
1619                  */
1620                 ret = i915_gem_object_flush_gpu(obj_priv, false);
1621                 if (ret) {
1622                         i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1623                         mutex_unlock(&dev->struct_mutex);
1624                         return ret;
1625                 }
1626         }
1627
1628         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1629                                          LEAVE_ATOMIC_MODE_SET);
1630         if (ret) {
1631                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1632                 mutex_unlock(&dev->struct_mutex);
1633                 return ret;
1634         }
1635
1636         if (old_fb)
1637                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1638
1639         mutex_unlock(&dev->struct_mutex);
1640
1641         if (!dev->primary->master)
1642                 return 0;
1643
1644         master_priv = dev->primary->master->driver_priv;
1645         if (!master_priv->sarea_priv)
1646                 return 0;
1647
1648         if (intel_crtc->pipe) {
1649                 master_priv->sarea_priv->pipeB_x = x;
1650                 master_priv->sarea_priv->pipeB_y = y;
1651         } else {
1652                 master_priv->sarea_priv->pipeA_x = x;
1653                 master_priv->sarea_priv->pipeA_y = y;
1654         }
1655
1656         return 0;
1657 }
1658
1659 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1660 {
1661         struct drm_device *dev = crtc->dev;
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663         u32 dpa_ctl;
1664
1665         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1666         dpa_ctl = I915_READ(DP_A);
1667         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1668
1669         if (clock < 200000) {
1670                 u32 temp;
1671                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1672                 /* workaround for 160Mhz:
1673                    1) program 0x4600c bits 15:0 = 0x8124
1674                    2) program 0x46010 bit 0 = 1
1675                    3) program 0x46034 bit 24 = 1
1676                    4) program 0x64000 bit 14 = 1
1677                    */
1678                 temp = I915_READ(0x4600c);
1679                 temp &= 0xffff0000;
1680                 I915_WRITE(0x4600c, temp | 0x8124);
1681
1682                 temp = I915_READ(0x46010);
1683                 I915_WRITE(0x46010, temp | 1);
1684
1685                 temp = I915_READ(0x46034);
1686                 I915_WRITE(0x46034, temp | (1 << 24));
1687         } else {
1688                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1689         }
1690         I915_WRITE(DP_A, dpa_ctl);
1691
1692         POSTING_READ(DP_A);
1693         udelay(500);
1694 }
1695
1696 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1697 {
1698         struct drm_device *dev = crtc->dev;
1699         struct drm_i915_private *dev_priv = dev->dev_private;
1700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1701         int pipe = intel_crtc->pipe;
1702         u32 reg, temp;
1703
1704         /* enable normal train */
1705         reg = FDI_TX_CTL(pipe);
1706         temp = I915_READ(reg);
1707         temp &= ~FDI_LINK_TRAIN_NONE;
1708         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1709         I915_WRITE(reg, temp);
1710
1711         reg = FDI_RX_CTL(pipe);
1712         temp = I915_READ(reg);
1713         if (HAS_PCH_CPT(dev)) {
1714                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1715                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1716         } else {
1717                 temp &= ~FDI_LINK_TRAIN_NONE;
1718                 temp |= FDI_LINK_TRAIN_NONE;
1719         }
1720         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1721
1722         /* wait one idle pattern time */
1723         POSTING_READ(reg);
1724         udelay(1000);
1725 }
1726
1727 /* The FDI link training functions for ILK/Ibexpeak. */
1728 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1729 {
1730         struct drm_device *dev = crtc->dev;
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1733         int pipe = intel_crtc->pipe;
1734         u32 reg, temp, tries;
1735
1736         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1737            for train result */
1738         reg = FDI_RX_IMR(pipe);
1739         temp = I915_READ(reg);
1740         temp &= ~FDI_RX_SYMBOL_LOCK;
1741         temp &= ~FDI_RX_BIT_LOCK;
1742         I915_WRITE(reg, temp);
1743         I915_READ(reg);
1744         udelay(150);
1745
1746         /* enable CPU FDI TX and PCH FDI RX */
1747         reg = FDI_TX_CTL(pipe);
1748         temp = I915_READ(reg);
1749         temp &= ~(7 << 19);
1750         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1751         temp &= ~FDI_LINK_TRAIN_NONE;
1752         temp |= FDI_LINK_TRAIN_PATTERN_1;
1753         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1754
1755         reg = FDI_RX_CTL(pipe);
1756         temp = I915_READ(reg);
1757         temp &= ~FDI_LINK_TRAIN_NONE;
1758         temp |= FDI_LINK_TRAIN_PATTERN_1;
1759         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1760
1761         POSTING_READ(reg);
1762         udelay(150);
1763
1764         /* Ironlake workaround, enable clock pointer after FDI enable*/
1765         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1766
1767         reg = FDI_RX_IIR(pipe);
1768         for (tries = 0; tries < 5; tries++) {
1769                 temp = I915_READ(reg);
1770                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1771
1772                 if ((temp & FDI_RX_BIT_LOCK)) {
1773                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1774                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1775                         break;
1776                 }
1777         }
1778         if (tries == 5)
1779                 DRM_ERROR("FDI train 1 fail!\n");
1780
1781         /* Train 2 */
1782         reg = FDI_TX_CTL(pipe);
1783         temp = I915_READ(reg);
1784         temp &= ~FDI_LINK_TRAIN_NONE;
1785         temp |= FDI_LINK_TRAIN_PATTERN_2;
1786         I915_WRITE(reg, temp);
1787
1788         reg = FDI_RX_CTL(pipe);
1789         temp = I915_READ(reg);
1790         temp &= ~FDI_LINK_TRAIN_NONE;
1791         temp |= FDI_LINK_TRAIN_PATTERN_2;
1792         I915_WRITE(reg, temp);
1793
1794         POSTING_READ(reg);
1795         udelay(150);
1796
1797         reg = FDI_RX_IIR(pipe);
1798         for (tries = 0; tries < 5; tries++) {
1799                 temp = I915_READ(reg);
1800                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1801
1802                 if (temp & FDI_RX_SYMBOL_LOCK) {
1803                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1804                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1805                         break;
1806                 }
1807         }
1808         if (tries == 5)
1809                 DRM_ERROR("FDI train 2 fail!\n");
1810
1811         DRM_DEBUG_KMS("FDI train done\n");
1812
1813 }
1814
1815 static const int const snb_b_fdi_train_param [] = {
1816         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1817         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1818         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1819         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1820 };
1821
1822 /* The FDI link training functions for SNB/Cougarpoint. */
1823 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1824 {
1825         struct drm_device *dev = crtc->dev;
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1828         int pipe = intel_crtc->pipe;
1829         u32 reg, temp, i;
1830
1831         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1832            for train result */
1833         reg = FDI_RX_IMR(pipe);
1834         temp = I915_READ(reg);
1835         temp &= ~FDI_RX_SYMBOL_LOCK;
1836         temp &= ~FDI_RX_BIT_LOCK;
1837         I915_WRITE(reg, temp);
1838
1839         POSTING_READ(reg);
1840         udelay(150);
1841
1842         /* enable CPU FDI TX and PCH FDI RX */
1843         reg = FDI_TX_CTL(pipe);
1844         temp = I915_READ(reg);
1845         temp &= ~(7 << 19);
1846         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1847         temp &= ~FDI_LINK_TRAIN_NONE;
1848         temp |= FDI_LINK_TRAIN_PATTERN_1;
1849         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1850         /* SNB-B */
1851         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1852         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1853
1854         reg = FDI_RX_CTL(pipe);
1855         temp = I915_READ(reg);
1856         if (HAS_PCH_CPT(dev)) {
1857                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1858                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1859         } else {
1860                 temp &= ~FDI_LINK_TRAIN_NONE;
1861                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1862         }
1863         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1864
1865         POSTING_READ(reg);
1866         udelay(150);
1867
1868         for (i = 0; i < 4; i++ ) {
1869                 reg = FDI_TX_CTL(pipe);
1870                 temp = I915_READ(reg);
1871                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1872                 temp |= snb_b_fdi_train_param[i];
1873                 I915_WRITE(reg, temp);
1874
1875                 POSTING_READ(reg);
1876                 udelay(500);
1877
1878                 reg = FDI_RX_IIR(pipe);
1879                 temp = I915_READ(reg);
1880                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1881
1882                 if (temp & FDI_RX_BIT_LOCK) {
1883                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1884                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1885                         break;
1886                 }
1887         }
1888         if (i == 4)
1889                 DRM_ERROR("FDI train 1 fail!\n");
1890
1891         /* Train 2 */
1892         reg = FDI_TX_CTL(pipe);
1893         temp = I915_READ(reg);
1894         temp &= ~FDI_LINK_TRAIN_NONE;
1895         temp |= FDI_LINK_TRAIN_PATTERN_2;
1896         if (IS_GEN6(dev)) {
1897                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1898                 /* SNB-B */
1899                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1900         }
1901         I915_WRITE(reg, temp);
1902
1903         reg = FDI_RX_CTL(pipe);
1904         temp = I915_READ(reg);
1905         if (HAS_PCH_CPT(dev)) {
1906                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1907                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1908         } else {
1909                 temp &= ~FDI_LINK_TRAIN_NONE;
1910                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1911         }
1912         I915_WRITE(reg, temp);
1913
1914         POSTING_READ(reg);
1915         udelay(150);
1916
1917         for (i = 0; i < 4; i++ ) {
1918                 reg = FDI_TX_CTL(pipe);
1919                 temp = I915_READ(reg);
1920                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1921                 temp |= snb_b_fdi_train_param[i];
1922                 I915_WRITE(reg, temp);
1923
1924                 POSTING_READ(reg);
1925                 udelay(500);
1926
1927                 reg = FDI_RX_IIR(pipe);
1928                 temp = I915_READ(reg);
1929                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1930
1931                 if (temp & FDI_RX_SYMBOL_LOCK) {
1932                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1933                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1934                         break;
1935                 }
1936         }
1937         if (i == 4)
1938                 DRM_ERROR("FDI train 2 fail!\n");
1939
1940         DRM_DEBUG_KMS("FDI train done.\n");
1941 }
1942
1943 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1944 {
1945         struct drm_device *dev = crtc->dev;
1946         struct drm_i915_private *dev_priv = dev->dev_private;
1947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1948         int pipe = intel_crtc->pipe;
1949         u32 reg, temp;
1950
1951         /* Write the TU size bits so error detection works */
1952         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1953                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1954
1955         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1956         reg = FDI_RX_CTL(pipe);
1957         temp = I915_READ(reg);
1958         temp &= ~((0x7 << 19) | (0x7 << 16));
1959         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1960         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1961         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1962
1963         POSTING_READ(reg);
1964         udelay(200);
1965
1966         /* Switch from Rawclk to PCDclk */
1967         temp = I915_READ(reg);
1968         I915_WRITE(reg, temp | FDI_PCDCLK);
1969
1970         POSTING_READ(reg);
1971         udelay(200);
1972
1973         /* Enable CPU FDI TX PLL, always on for Ironlake */
1974         reg = FDI_TX_CTL(pipe);
1975         temp = I915_READ(reg);
1976         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1977                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1978
1979                 POSTING_READ(reg);
1980                 udelay(100);
1981         }
1982 }
1983
1984 static void intel_flush_display_plane(struct drm_device *dev,
1985                                       int plane)
1986 {
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         u32 reg = DSPADDR(plane);
1989         I915_WRITE(reg, I915_READ(reg));
1990 }
1991
1992 /*
1993  * When we disable a pipe, we need to clear any pending scanline wait events
1994  * to avoid hanging the ring, which we assume we are waiting on.
1995  */
1996 static void intel_clear_scanline_wait(struct drm_device *dev)
1997 {
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         u32 tmp;
2000
2001         if (IS_GEN2(dev))
2002                 /* Can't break the hang on i8xx */
2003                 return;
2004
2005         tmp = I915_READ(PRB0_CTL);
2006         if (tmp & RING_WAIT) {
2007                 I915_WRITE(PRB0_CTL, tmp);
2008                 POSTING_READ(PRB0_CTL);
2009         }
2010 }
2011
2012 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2013 {
2014         struct drm_i915_gem_object *obj_priv;
2015         struct drm_i915_private *dev_priv;
2016
2017         if (crtc->fb == NULL)
2018                 return;
2019
2020         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
2021         dev_priv = crtc->dev->dev_private;
2022         wait_event(dev_priv->pending_flip_queue,
2023                    atomic_read(&obj_priv->pending_flip) == 0);
2024 }
2025
2026 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2027 {
2028         struct drm_device *dev = crtc->dev;
2029         struct drm_i915_private *dev_priv = dev->dev_private;
2030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2031         int pipe = intel_crtc->pipe;
2032         int plane = intel_crtc->plane;
2033         u32 reg, temp;
2034
2035         if (intel_crtc->active)
2036                 return;
2037
2038         intel_crtc->active = true;
2039         intel_update_watermarks(dev);
2040
2041         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2042                 temp = I915_READ(PCH_LVDS);
2043                 if ((temp & LVDS_PORT_EN) == 0)
2044                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2045         }
2046
2047         ironlake_fdi_enable(crtc);
2048
2049         /* Enable panel fitting for LVDS */
2050         if (dev_priv->pch_pf_size &&
2051             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2052                 /* Force use of hard-coded filter coefficients
2053                  * as some pre-programmed values are broken,
2054                  * e.g. x201.
2055                  */
2056                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2057                            PF_ENABLE | PF_FILTER_MED_3x3);
2058                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2059                            dev_priv->pch_pf_pos);
2060                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2061                            dev_priv->pch_pf_size);
2062         }
2063
2064         /* Enable CPU pipe */
2065         reg = PIPECONF(pipe);
2066         temp = I915_READ(reg);
2067         if ((temp & PIPECONF_ENABLE) == 0) {
2068                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2069                 POSTING_READ(reg);
2070                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2071         }
2072
2073         /* configure and enable CPU plane */
2074         reg = DSPCNTR(plane);
2075         temp = I915_READ(reg);
2076         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2077                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2078                 intel_flush_display_plane(dev, plane);
2079         }
2080
2081         /* For PCH output, training FDI link */
2082         if (IS_GEN6(dev))
2083                 gen6_fdi_link_train(crtc);
2084         else
2085                 ironlake_fdi_link_train(crtc);
2086
2087         /* enable PCH DPLL */
2088         reg = PCH_DPLL(pipe);
2089         temp = I915_READ(reg);
2090         if ((temp & DPLL_VCO_ENABLE) == 0) {
2091                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2092                 POSTING_READ(reg);
2093                 udelay(200);
2094         }
2095
2096         if (HAS_PCH_CPT(dev)) {
2097                 /* Be sure PCH DPLL SEL is set */
2098                 temp = I915_READ(PCH_DPLL_SEL);
2099                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2100                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2101                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2102                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2103                 I915_WRITE(PCH_DPLL_SEL, temp);
2104         }
2105
2106         /* set transcoder timing */
2107         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2108         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2109         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2110
2111         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2112         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2113         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2114
2115         intel_fdi_normal_train(crtc);
2116
2117         /* For PCH DP, enable TRANS_DP_CTL */
2118         if (HAS_PCH_CPT(dev) &&
2119             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2120                 reg = TRANS_DP_CTL(pipe);
2121                 temp = I915_READ(reg);
2122                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2123                           TRANS_DP_SYNC_MASK |
2124                           TRANS_DP_BPC_MASK);
2125                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2126                          TRANS_DP_ENH_FRAMING);
2127                 temp |= TRANS_DP_8BPC;
2128
2129                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2130                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2131                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2132                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2133
2134                 switch (intel_trans_dp_port_sel(crtc)) {
2135                 case PCH_DP_B:
2136                         temp |= TRANS_DP_PORT_SEL_B;
2137                         break;
2138                 case PCH_DP_C:
2139                         temp |= TRANS_DP_PORT_SEL_C;
2140                         break;
2141                 case PCH_DP_D:
2142                         temp |= TRANS_DP_PORT_SEL_D;
2143                         break;
2144                 default:
2145                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2146                         temp |= TRANS_DP_PORT_SEL_B;
2147                         break;
2148                 }
2149
2150                 I915_WRITE(reg, temp);
2151         }
2152
2153         /* enable PCH transcoder */
2154         reg = TRANSCONF(pipe);
2155         temp = I915_READ(reg);
2156         /*
2157          * make the BPC in transcoder be consistent with
2158          * that in pipeconf reg.
2159          */
2160         temp &= ~PIPE_BPC_MASK;
2161         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2162         I915_WRITE(reg, temp | TRANS_ENABLE);
2163         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2164                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2165
2166         intel_crtc_load_lut(crtc);
2167         intel_update_fbc(dev);
2168         intel_crtc_update_cursor(crtc, true);
2169 }
2170
2171 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2172 {
2173         struct drm_device *dev = crtc->dev;
2174         struct drm_i915_private *dev_priv = dev->dev_private;
2175         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176         int pipe = intel_crtc->pipe;
2177         int plane = intel_crtc->plane;
2178         u32 reg, temp;
2179
2180         if (!intel_crtc->active)
2181                 return;
2182
2183         intel_crtc_wait_for_pending_flips(crtc);
2184         drm_vblank_off(dev, pipe);
2185         intel_crtc_update_cursor(crtc, false);
2186
2187         /* Disable display plane */
2188         reg = DSPCNTR(plane);
2189         temp = I915_READ(reg);
2190         if (temp & DISPLAY_PLANE_ENABLE) {
2191                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2192                 intel_flush_display_plane(dev, plane);
2193         }
2194
2195         if (dev_priv->cfb_plane == plane &&
2196             dev_priv->display.disable_fbc)
2197                 dev_priv->display.disable_fbc(dev);
2198
2199         /* disable cpu pipe, disable after all planes disabled */
2200         reg = PIPECONF(pipe);
2201         temp = I915_READ(reg);
2202         if (temp & PIPECONF_ENABLE) {
2203                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2204                 POSTING_READ(reg);
2205                 /* wait for cpu pipe off, pipe state */
2206                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2207         }
2208
2209         /* Disable PF */
2210         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2211         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2212
2213         /* disable CPU FDI tx and PCH FDI rx */
2214         reg = FDI_TX_CTL(pipe);
2215         temp = I915_READ(reg);
2216         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2217         POSTING_READ(reg);
2218
2219         reg = FDI_RX_CTL(pipe);
2220         temp = I915_READ(reg);
2221         temp &= ~(0x7 << 16);
2222         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2223         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2224
2225         POSTING_READ(reg);
2226         udelay(100);
2227
2228         /* Ironlake workaround, disable clock pointer after downing FDI */
2229         if (HAS_PCH_IBX(dev))
2230                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2231                            I915_READ(FDI_RX_CHICKEN(pipe) &
2232                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2233
2234         /* still set train pattern 1 */
2235         reg = FDI_TX_CTL(pipe);
2236         temp = I915_READ(reg);
2237         temp &= ~FDI_LINK_TRAIN_NONE;
2238         temp |= FDI_LINK_TRAIN_PATTERN_1;
2239         I915_WRITE(reg, temp);
2240
2241         reg = FDI_RX_CTL(pipe);
2242         temp = I915_READ(reg);
2243         if (HAS_PCH_CPT(dev)) {
2244                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2245                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2246         } else {
2247                 temp &= ~FDI_LINK_TRAIN_NONE;
2248                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2249         }
2250         /* BPC in FDI rx is consistent with that in PIPECONF */
2251         temp &= ~(0x07 << 16);
2252         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2253         I915_WRITE(reg, temp);
2254
2255         POSTING_READ(reg);
2256         udelay(100);
2257
2258         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2259                 temp = I915_READ(PCH_LVDS);
2260                 if (temp & LVDS_PORT_EN) {
2261                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2262                         POSTING_READ(PCH_LVDS);
2263                         udelay(100);
2264                 }
2265         }
2266
2267         /* disable PCH transcoder */
2268         reg = TRANSCONF(plane);
2269         temp = I915_READ(reg);
2270         if (temp & TRANS_ENABLE) {
2271                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2272                 /* wait for PCH transcoder off, transcoder state */
2273                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2274                         DRM_ERROR("failed to disable transcoder\n");
2275         }
2276
2277         if (HAS_PCH_CPT(dev)) {
2278                 /* disable TRANS_DP_CTL */
2279                 reg = TRANS_DP_CTL(pipe);
2280                 temp = I915_READ(reg);
2281                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2282                 I915_WRITE(reg, temp);
2283
2284                 /* disable DPLL_SEL */
2285                 temp = I915_READ(PCH_DPLL_SEL);
2286                 if (pipe == 0)
2287                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2288                 else
2289                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2290                 I915_WRITE(PCH_DPLL_SEL, temp);
2291         }
2292
2293         /* disable PCH DPLL */
2294         reg = PCH_DPLL(pipe);
2295         temp = I915_READ(reg);
2296         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2297
2298         /* Switch from PCDclk to Rawclk */
2299         reg = FDI_RX_CTL(pipe);
2300         temp = I915_READ(reg);
2301         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2302
2303         /* Disable CPU FDI TX PLL */
2304         reg = FDI_TX_CTL(pipe);
2305         temp = I915_READ(reg);
2306         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2307
2308         POSTING_READ(reg);
2309         udelay(100);
2310
2311         reg = FDI_RX_CTL(pipe);
2312         temp = I915_READ(reg);
2313         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2314
2315         /* Wait for the clocks to turn off. */
2316         POSTING_READ(reg);
2317         udelay(100);
2318
2319         intel_crtc->active = false;
2320         intel_update_watermarks(dev);
2321         intel_update_fbc(dev);
2322         intel_clear_scanline_wait(dev);
2323 }
2324
2325 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2326 {
2327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2328         int pipe = intel_crtc->pipe;
2329         int plane = intel_crtc->plane;
2330
2331         /* XXX: When our outputs are all unaware of DPMS modes other than off
2332          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2333          */
2334         switch (mode) {
2335         case DRM_MODE_DPMS_ON:
2336         case DRM_MODE_DPMS_STANDBY:
2337         case DRM_MODE_DPMS_SUSPEND:
2338                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2339                 ironlake_crtc_enable(crtc);
2340                 break;
2341
2342         case DRM_MODE_DPMS_OFF:
2343                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2344                 ironlake_crtc_disable(crtc);
2345                 break;
2346         }
2347 }
2348
2349 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2350 {
2351         if (!enable && intel_crtc->overlay) {
2352                 struct drm_device *dev = intel_crtc->base.dev;
2353
2354                 mutex_lock(&dev->struct_mutex);
2355                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2356                 mutex_unlock(&dev->struct_mutex);
2357         }
2358
2359         /* Let userspace switch the overlay on again. In most cases userspace
2360          * has to recompute where to put it anyway.
2361          */
2362 }
2363
2364 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2365 {
2366         struct drm_device *dev = crtc->dev;
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2369         int pipe = intel_crtc->pipe;
2370         int plane = intel_crtc->plane;
2371         u32 reg, temp;
2372
2373         if (intel_crtc->active)
2374                 return;
2375
2376         intel_crtc->active = true;
2377         intel_update_watermarks(dev);
2378
2379         /* Enable the DPLL */
2380         reg = DPLL(pipe);
2381         temp = I915_READ(reg);
2382         if ((temp & DPLL_VCO_ENABLE) == 0) {
2383                 I915_WRITE(reg, temp);
2384
2385                 /* Wait for the clocks to stabilize. */
2386                 POSTING_READ(reg);
2387                 udelay(150);
2388
2389                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2390
2391                 /* Wait for the clocks to stabilize. */
2392                 POSTING_READ(reg);
2393                 udelay(150);
2394
2395                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2396
2397                 /* Wait for the clocks to stabilize. */
2398                 POSTING_READ(reg);
2399                 udelay(150);
2400         }
2401
2402         /* Enable the pipe */
2403         reg = PIPECONF(pipe);
2404         temp = I915_READ(reg);
2405         if ((temp & PIPECONF_ENABLE) == 0)
2406                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2407
2408         /* Enable the plane */
2409         reg = DSPCNTR(plane);
2410         temp = I915_READ(reg);
2411         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2412                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2413                 intel_flush_display_plane(dev, plane);
2414         }
2415
2416         intel_crtc_load_lut(crtc);
2417         intel_update_fbc(dev);
2418
2419         /* Give the overlay scaler a chance to enable if it's on this pipe */
2420         intel_crtc_dpms_overlay(intel_crtc, true);
2421         intel_crtc_update_cursor(crtc, true);
2422 }
2423
2424 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2425 {
2426         struct drm_device *dev = crtc->dev;
2427         struct drm_i915_private *dev_priv = dev->dev_private;
2428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2429         int pipe = intel_crtc->pipe;
2430         int plane = intel_crtc->plane;
2431         u32 reg, temp;
2432
2433         if (!intel_crtc->active)
2434                 return;
2435
2436         /* Give the overlay scaler a chance to disable if it's on this pipe */
2437         intel_crtc_wait_for_pending_flips(crtc);
2438         drm_vblank_off(dev, pipe);
2439         intel_crtc_dpms_overlay(intel_crtc, false);
2440         intel_crtc_update_cursor(crtc, false);
2441
2442         if (dev_priv->cfb_plane == plane &&
2443             dev_priv->display.disable_fbc)
2444                 dev_priv->display.disable_fbc(dev);
2445
2446         /* Disable display plane */
2447         reg = DSPCNTR(plane);
2448         temp = I915_READ(reg);
2449         if (temp & DISPLAY_PLANE_ENABLE) {
2450                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2451                 /* Flush the plane changes */
2452                 intel_flush_display_plane(dev, plane);
2453
2454                 /* Wait for vblank for the disable to take effect */
2455                 if (IS_GEN2(dev))
2456                         intel_wait_for_vblank(dev, pipe);
2457         }
2458
2459         /* Don't disable pipe A or pipe A PLLs if needed */
2460         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2461                 goto done;
2462
2463         /* Next, disable display pipes */
2464         reg = PIPECONF(pipe);
2465         temp = I915_READ(reg);
2466         if (temp & PIPECONF_ENABLE) {
2467                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2468
2469                 /* Wait for the pipe to turn off */
2470                 POSTING_READ(reg);
2471                 intel_wait_for_pipe_off(dev, pipe);
2472         }
2473
2474         reg = DPLL(pipe);
2475         temp = I915_READ(reg);
2476         if (temp & DPLL_VCO_ENABLE) {
2477                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2478
2479                 /* Wait for the clocks to turn off. */
2480                 POSTING_READ(reg);
2481                 udelay(150);
2482         }
2483
2484 done:
2485         intel_crtc->active = false;
2486         intel_update_fbc(dev);
2487         intel_update_watermarks(dev);
2488         intel_clear_scanline_wait(dev);
2489 }
2490
2491 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2492 {
2493         /* XXX: When our outputs are all unaware of DPMS modes other than off
2494          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2495          */
2496         switch (mode) {
2497         case DRM_MODE_DPMS_ON:
2498         case DRM_MODE_DPMS_STANDBY:
2499         case DRM_MODE_DPMS_SUSPEND:
2500                 i9xx_crtc_enable(crtc);
2501                 break;
2502         case DRM_MODE_DPMS_OFF:
2503                 i9xx_crtc_disable(crtc);
2504                 break;
2505         }
2506 }
2507
2508 /**
2509  * Sets the power management mode of the pipe and plane.
2510  */
2511 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515         struct drm_i915_master_private *master_priv;
2516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517         int pipe = intel_crtc->pipe;
2518         bool enabled;
2519
2520         if (intel_crtc->dpms_mode == mode)
2521                 return;
2522
2523         intel_crtc->dpms_mode = mode;
2524
2525         dev_priv->display.dpms(crtc, mode);
2526
2527         if (!dev->primary->master)
2528                 return;
2529
2530         master_priv = dev->primary->master->driver_priv;
2531         if (!master_priv->sarea_priv)
2532                 return;
2533
2534         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2535
2536         switch (pipe) {
2537         case 0:
2538                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2539                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2540                 break;
2541         case 1:
2542                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2543                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2544                 break;
2545         default:
2546                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2547                 break;
2548         }
2549 }
2550
2551 static void intel_crtc_disable(struct drm_crtc *crtc)
2552 {
2553         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2554         struct drm_device *dev = crtc->dev;
2555
2556         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2557
2558         if (crtc->fb) {
2559                 mutex_lock(&dev->struct_mutex);
2560                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2561                 mutex_unlock(&dev->struct_mutex);
2562         }
2563 }
2564
2565 /* Prepare for a mode set.
2566  *
2567  * Note we could be a lot smarter here.  We need to figure out which outputs
2568  * will be enabled, which disabled (in short, how the config will changes)
2569  * and perform the minimum necessary steps to accomplish that, e.g. updating
2570  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2571  * panel fitting is in the proper state, etc.
2572  */
2573 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2574 {
2575         i9xx_crtc_disable(crtc);
2576 }
2577
2578 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2579 {
2580         i9xx_crtc_enable(crtc);
2581 }
2582
2583 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2584 {
2585         ironlake_crtc_disable(crtc);
2586 }
2587
2588 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2589 {
2590         ironlake_crtc_enable(crtc);
2591 }
2592
2593 void intel_encoder_prepare (struct drm_encoder *encoder)
2594 {
2595         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2596         /* lvds has its own version of prepare see intel_lvds_prepare */
2597         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2598 }
2599
2600 void intel_encoder_commit (struct drm_encoder *encoder)
2601 {
2602         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2603         /* lvds has its own version of commit see intel_lvds_commit */
2604         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2605 }
2606
2607 void intel_encoder_destroy(struct drm_encoder *encoder)
2608 {
2609         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2610
2611         drm_encoder_cleanup(encoder);
2612         kfree(intel_encoder);
2613 }
2614
2615 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2616                                   struct drm_display_mode *mode,
2617                                   struct drm_display_mode *adjusted_mode)
2618 {
2619         struct drm_device *dev = crtc->dev;
2620
2621         if (HAS_PCH_SPLIT(dev)) {
2622                 /* FDI link clock is fixed at 2.7G */
2623                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2624                         return false;
2625         }
2626
2627         /* XXX some encoders set the crtcinfo, others don't.
2628          * Obviously we need some form of conflict resolution here...
2629          */
2630         if (adjusted_mode->crtc_htotal == 0)
2631                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2632
2633         return true;
2634 }
2635
2636 static int i945_get_display_clock_speed(struct drm_device *dev)
2637 {
2638         return 400000;
2639 }
2640
2641 static int i915_get_display_clock_speed(struct drm_device *dev)
2642 {
2643         return 333000;
2644 }
2645
2646 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2647 {
2648         return 200000;
2649 }
2650
2651 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2652 {
2653         u16 gcfgc = 0;
2654
2655         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2656
2657         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2658                 return 133000;
2659         else {
2660                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2661                 case GC_DISPLAY_CLOCK_333_MHZ:
2662                         return 333000;
2663                 default:
2664                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2665                         return 190000;
2666                 }
2667         }
2668 }
2669
2670 static int i865_get_display_clock_speed(struct drm_device *dev)
2671 {
2672         return 266000;
2673 }
2674
2675 static int i855_get_display_clock_speed(struct drm_device *dev)
2676 {
2677         u16 hpllcc = 0;
2678         /* Assume that the hardware is in the high speed state.  This
2679          * should be the default.
2680          */
2681         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2682         case GC_CLOCK_133_200:
2683         case GC_CLOCK_100_200:
2684                 return 200000;
2685         case GC_CLOCK_166_250:
2686                 return 250000;
2687         case GC_CLOCK_100_133:
2688                 return 133000;
2689         }
2690
2691         /* Shouldn't happen */
2692         return 0;
2693 }
2694
2695 static int i830_get_display_clock_speed(struct drm_device *dev)
2696 {
2697         return 133000;
2698 }
2699
2700 struct fdi_m_n {
2701         u32        tu;
2702         u32        gmch_m;
2703         u32        gmch_n;
2704         u32        link_m;
2705         u32        link_n;
2706 };
2707
2708 static void
2709 fdi_reduce_ratio(u32 *num, u32 *den)
2710 {
2711         while (*num > 0xffffff || *den > 0xffffff) {
2712                 *num >>= 1;
2713                 *den >>= 1;
2714         }
2715 }
2716
2717 static void
2718 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2719                      int link_clock, struct fdi_m_n *m_n)
2720 {
2721         m_n->tu = 64; /* default size */
2722
2723         /* BUG_ON(pixel_clock > INT_MAX / 36); */
2724         m_n->gmch_m = bits_per_pixel * pixel_clock;
2725         m_n->gmch_n = link_clock * nlanes * 8;
2726         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2727
2728         m_n->link_m = pixel_clock;
2729         m_n->link_n = link_clock;
2730         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2731 }
2732
2733
2734 struct intel_watermark_params {
2735         unsigned long fifo_size;
2736         unsigned long max_wm;
2737         unsigned long default_wm;
2738         unsigned long guard_size;
2739         unsigned long cacheline_size;
2740 };
2741
2742 /* Pineview has different values for various configs */
2743 static struct intel_watermark_params pineview_display_wm = {
2744         PINEVIEW_DISPLAY_FIFO,
2745         PINEVIEW_MAX_WM,
2746         PINEVIEW_DFT_WM,
2747         PINEVIEW_GUARD_WM,
2748         PINEVIEW_FIFO_LINE_SIZE
2749 };
2750 static struct intel_watermark_params pineview_display_hplloff_wm = {
2751         PINEVIEW_DISPLAY_FIFO,
2752         PINEVIEW_MAX_WM,
2753         PINEVIEW_DFT_HPLLOFF_WM,
2754         PINEVIEW_GUARD_WM,
2755         PINEVIEW_FIFO_LINE_SIZE
2756 };
2757 static struct intel_watermark_params pineview_cursor_wm = {
2758         PINEVIEW_CURSOR_FIFO,
2759         PINEVIEW_CURSOR_MAX_WM,
2760         PINEVIEW_CURSOR_DFT_WM,
2761         PINEVIEW_CURSOR_GUARD_WM,
2762         PINEVIEW_FIFO_LINE_SIZE,
2763 };
2764 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2765         PINEVIEW_CURSOR_FIFO,
2766         PINEVIEW_CURSOR_MAX_WM,
2767         PINEVIEW_CURSOR_DFT_WM,
2768         PINEVIEW_CURSOR_GUARD_WM,
2769         PINEVIEW_FIFO_LINE_SIZE
2770 };
2771 static struct intel_watermark_params g4x_wm_info = {
2772         G4X_FIFO_SIZE,
2773         G4X_MAX_WM,
2774         G4X_MAX_WM,
2775         2,
2776         G4X_FIFO_LINE_SIZE,
2777 };
2778 static struct intel_watermark_params g4x_cursor_wm_info = {
2779         I965_CURSOR_FIFO,
2780         I965_CURSOR_MAX_WM,
2781         I965_CURSOR_DFT_WM,
2782         2,
2783         G4X_FIFO_LINE_SIZE,
2784 };
2785 static struct intel_watermark_params i965_cursor_wm_info = {
2786         I965_CURSOR_FIFO,
2787         I965_CURSOR_MAX_WM,
2788         I965_CURSOR_DFT_WM,
2789         2,
2790         I915_FIFO_LINE_SIZE,
2791 };
2792 static struct intel_watermark_params i945_wm_info = {
2793         I945_FIFO_SIZE,
2794         I915_MAX_WM,
2795         1,
2796         2,
2797         I915_FIFO_LINE_SIZE
2798 };
2799 static struct intel_watermark_params i915_wm_info = {
2800         I915_FIFO_SIZE,
2801         I915_MAX_WM,
2802         1,
2803         2,
2804         I915_FIFO_LINE_SIZE
2805 };
2806 static struct intel_watermark_params i855_wm_info = {
2807         I855GM_FIFO_SIZE,
2808         I915_MAX_WM,
2809         1,
2810         2,
2811         I830_FIFO_LINE_SIZE
2812 };
2813 static struct intel_watermark_params i830_wm_info = {
2814         I830_FIFO_SIZE,
2815         I915_MAX_WM,
2816         1,
2817         2,
2818         I830_FIFO_LINE_SIZE
2819 };
2820
2821 static struct intel_watermark_params ironlake_display_wm_info = {
2822         ILK_DISPLAY_FIFO,
2823         ILK_DISPLAY_MAXWM,
2824         ILK_DISPLAY_DFTWM,
2825         2,
2826         ILK_FIFO_LINE_SIZE
2827 };
2828
2829 static struct intel_watermark_params ironlake_cursor_wm_info = {
2830         ILK_CURSOR_FIFO,
2831         ILK_CURSOR_MAXWM,
2832         ILK_CURSOR_DFTWM,
2833         2,
2834         ILK_FIFO_LINE_SIZE
2835 };
2836
2837 static struct intel_watermark_params ironlake_display_srwm_info = {
2838         ILK_DISPLAY_SR_FIFO,
2839         ILK_DISPLAY_MAX_SRWM,
2840         ILK_DISPLAY_DFT_SRWM,
2841         2,
2842         ILK_FIFO_LINE_SIZE
2843 };
2844
2845 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2846         ILK_CURSOR_SR_FIFO,
2847         ILK_CURSOR_MAX_SRWM,
2848         ILK_CURSOR_DFT_SRWM,
2849         2,
2850         ILK_FIFO_LINE_SIZE
2851 };
2852
2853 /**
2854  * intel_calculate_wm - calculate watermark level
2855  * @clock_in_khz: pixel clock
2856  * @wm: chip FIFO params
2857  * @pixel_size: display pixel size
2858  * @latency_ns: memory latency for the platform
2859  *
2860  * Calculate the watermark level (the level at which the display plane will
2861  * start fetching from memory again).  Each chip has a different display
2862  * FIFO size and allocation, so the caller needs to figure that out and pass
2863  * in the correct intel_watermark_params structure.
2864  *
2865  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2866  * on the pixel size.  When it reaches the watermark level, it'll start
2867  * fetching FIFO line sized based chunks from memory until the FIFO fills
2868  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2869  * will occur, and a display engine hang could result.
2870  */
2871 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2872                                         struct intel_watermark_params *wm,
2873                                         int pixel_size,
2874                                         unsigned long latency_ns)
2875 {
2876         long entries_required, wm_size;
2877
2878         /*
2879          * Note: we need to make sure we don't overflow for various clock &
2880          * latency values.
2881          * clocks go from a few thousand to several hundred thousand.
2882          * latency is usually a few thousand
2883          */
2884         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2885                 1000;
2886         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2887
2888         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2889
2890         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2891
2892         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2893
2894         /* Don't promote wm_size to unsigned... */
2895         if (wm_size > (long)wm->max_wm)
2896                 wm_size = wm->max_wm;
2897         if (wm_size <= 0)
2898                 wm_size = wm->default_wm;
2899         return wm_size;
2900 }
2901
2902 struct cxsr_latency {
2903         int is_desktop;
2904         int is_ddr3;
2905         unsigned long fsb_freq;
2906         unsigned long mem_freq;
2907         unsigned long display_sr;
2908         unsigned long display_hpll_disable;
2909         unsigned long cursor_sr;
2910         unsigned long cursor_hpll_disable;
2911 };
2912
2913 static const struct cxsr_latency cxsr_latency_table[] = {
2914         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2915         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2916         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2917         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2918         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2919
2920         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2921         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2922         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2923         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2924         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2925
2926         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2927         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2928         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2929         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2930         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2931
2932         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2933         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2934         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2935         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2936         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2937
2938         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2939         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2940         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2941         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2942         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2943
2944         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2945         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2946         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2947         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2948         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2949 };
2950
2951 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2952                                                          int is_ddr3,
2953                                                          int fsb,
2954                                                          int mem)
2955 {
2956         const struct cxsr_latency *latency;
2957         int i;
2958
2959         if (fsb == 0 || mem == 0)
2960                 return NULL;
2961
2962         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2963                 latency = &cxsr_latency_table[i];
2964                 if (is_desktop == latency->is_desktop &&
2965                     is_ddr3 == latency->is_ddr3 &&
2966                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2967                         return latency;
2968         }
2969
2970         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2971
2972         return NULL;
2973 }
2974
2975 static void pineview_disable_cxsr(struct drm_device *dev)
2976 {
2977         struct drm_i915_private *dev_priv = dev->dev_private;
2978
2979         /* deactivate cxsr */
2980         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2981 }
2982
2983 /*
2984  * Latency for FIFO fetches is dependent on several factors:
2985  *   - memory configuration (speed, channels)
2986  *   - chipset
2987  *   - current MCH state
2988  * It can be fairly high in some situations, so here we assume a fairly
2989  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2990  * set this value too high, the FIFO will fetch frequently to stay full)
2991  * and power consumption (set it too low to save power and we might see
2992  * FIFO underruns and display "flicker").
2993  *
2994  * A value of 5us seems to be a good balance; safe for very low end
2995  * platforms but not overly aggressive on lower latency configs.
2996  */
2997 static const int latency_ns = 5000;
2998
2999 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3000 {
3001         struct drm_i915_private *dev_priv = dev->dev_private;
3002         uint32_t dsparb = I915_READ(DSPARB);
3003         int size;
3004
3005         size = dsparb & 0x7f;
3006         if (plane)
3007                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3008
3009         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3010                       plane ? "B" : "A", size);
3011
3012         return size;
3013 }
3014
3015 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3016 {
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         uint32_t dsparb = I915_READ(DSPARB);
3019         int size;
3020
3021         size = dsparb & 0x1ff;
3022         if (plane)
3023                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3024         size >>= 1; /* Convert to cachelines */
3025
3026         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3027                       plane ? "B" : "A", size);
3028
3029         return size;
3030 }
3031
3032 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3033 {
3034         struct drm_i915_private *dev_priv = dev->dev_private;
3035         uint32_t dsparb = I915_READ(DSPARB);
3036         int size;
3037
3038         size = dsparb & 0x7f;
3039         size >>= 2; /* Convert to cachelines */
3040
3041         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3042                       plane ? "B" : "A",
3043                       size);
3044
3045         return size;
3046 }
3047
3048 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3049 {
3050         struct drm_i915_private *dev_priv = dev->dev_private;
3051         uint32_t dsparb = I915_READ(DSPARB);
3052         int size;
3053
3054         size = dsparb & 0x7f;
3055         size >>= 1; /* Convert to cachelines */
3056
3057         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3058                       plane ? "B" : "A", size);
3059
3060         return size;
3061 }
3062
3063 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3064                                int planeb_clock, int sr_hdisplay, int unused,
3065                                int pixel_size)
3066 {
3067         struct drm_i915_private *dev_priv = dev->dev_private;
3068         const struct cxsr_latency *latency;
3069         u32 reg;
3070         unsigned long wm;
3071         int sr_clock;
3072
3073         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3074                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3075         if (!latency) {
3076                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3077                 pineview_disable_cxsr(dev);
3078                 return;
3079         }
3080
3081         if (!planea_clock || !planeb_clock) {
3082                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3083
3084                 /* Display SR */
3085                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3086                                         pixel_size, latency->display_sr);
3087                 reg = I915_READ(DSPFW1);
3088                 reg &= ~DSPFW_SR_MASK;
3089                 reg |= wm << DSPFW_SR_SHIFT;
3090                 I915_WRITE(DSPFW1, reg);
3091                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3092
3093                 /* cursor SR */
3094                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3095                                         pixel_size, latency->cursor_sr);
3096                 reg = I915_READ(DSPFW3);
3097                 reg &= ~DSPFW_CURSOR_SR_MASK;
3098                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3099                 I915_WRITE(DSPFW3, reg);
3100
3101                 /* Display HPLL off SR */
3102                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3103                                         pixel_size, latency->display_hpll_disable);
3104                 reg = I915_READ(DSPFW3);
3105                 reg &= ~DSPFW_HPLL_SR_MASK;
3106                 reg |= wm & DSPFW_HPLL_SR_MASK;
3107                 I915_WRITE(DSPFW3, reg);
3108
3109                 /* cursor HPLL off SR */
3110                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3111                                         pixel_size, latency->cursor_hpll_disable);
3112                 reg = I915_READ(DSPFW3);
3113                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3114                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3115                 I915_WRITE(DSPFW3, reg);
3116                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3117
3118                 /* activate cxsr */
3119                 I915_WRITE(DSPFW3,
3120                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3121                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3122         } else {
3123                 pineview_disable_cxsr(dev);
3124                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3125         }
3126 }
3127
3128 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3129                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3130                           int pixel_size)
3131 {
3132         struct drm_i915_private *dev_priv = dev->dev_private;
3133         int total_size, cacheline_size;
3134         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3135         struct intel_watermark_params planea_params, planeb_params;
3136         unsigned long line_time_us;
3137         int sr_clock, sr_entries = 0, entries_required;
3138
3139         /* Create copies of the base settings for each pipe */
3140         planea_params = planeb_params = g4x_wm_info;
3141
3142         /* Grab a couple of global values before we overwrite them */
3143         total_size = planea_params.fifo_size;
3144         cacheline_size = planea_params.cacheline_size;
3145
3146         /*
3147          * Note: we need to make sure we don't overflow for various clock &
3148          * latency values.
3149          * clocks go from a few thousand to several hundred thousand.
3150          * latency is usually a few thousand
3151          */
3152         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3153                 1000;
3154         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3155         planea_wm = entries_required + planea_params.guard_size;
3156
3157         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3158                 1000;
3159         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3160         planeb_wm = entries_required + planeb_params.guard_size;
3161
3162         cursora_wm = cursorb_wm = 16;
3163         cursor_sr = 32;
3164
3165         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3166
3167         /* Calc sr entries for one plane configs */
3168         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3169                 /* self-refresh has much higher latency */
3170                 static const int sr_latency_ns = 12000;
3171
3172                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3173                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3174
3175                 /* Use ns/us then divide to preserve precision */
3176                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3177                         pixel_size * sr_hdisplay;
3178                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3179
3180                 entries_required = (((sr_latency_ns / line_time_us) +
3181                                      1000) / 1000) * pixel_size * 64;
3182                 entries_required = DIV_ROUND_UP(entries_required,
3183                                                 g4x_cursor_wm_info.cacheline_size);
3184                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3185
3186                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3187                         cursor_sr = g4x_cursor_wm_info.max_wm;
3188                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3189                               "cursor %d\n", sr_entries, cursor_sr);
3190
3191                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3192         } else {
3193                 /* Turn off self refresh if both pipes are enabled */
3194                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3195                            & ~FW_BLC_SELF_EN);
3196         }
3197
3198         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3199                   planea_wm, planeb_wm, sr_entries);
3200
3201         planea_wm &= 0x3f;
3202         planeb_wm &= 0x3f;
3203
3204         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3205                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3206                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3207         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3208                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3209         /* HPLL off in SR has some issues on G4x... disable it */
3210         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3211                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3212 }
3213
3214 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3215                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3216                            int pixel_size)
3217 {
3218         struct drm_i915_private *dev_priv = dev->dev_private;
3219         unsigned long line_time_us;
3220         int sr_clock, sr_entries, srwm = 1;
3221         int cursor_sr = 16;
3222
3223         /* Calc sr entries for one plane configs */
3224         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3225                 /* self-refresh has much higher latency */
3226                 static const int sr_latency_ns = 12000;
3227
3228                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3229                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3230
3231                 /* Use ns/us then divide to preserve precision */
3232                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3233                         pixel_size * sr_hdisplay;
3234                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3235                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3236                 srwm = I965_FIFO_SIZE - sr_entries;
3237                 if (srwm < 0)
3238                         srwm = 1;
3239                 srwm &= 0x1ff;
3240
3241                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3242                         pixel_size * 64;
3243                 sr_entries = DIV_ROUND_UP(sr_entries,
3244                                           i965_cursor_wm_info.cacheline_size);
3245                 cursor_sr = i965_cursor_wm_info.fifo_size -
3246                         (sr_entries + i965_cursor_wm_info.guard_size);
3247
3248                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3249                         cursor_sr = i965_cursor_wm_info.max_wm;
3250
3251                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3252                               "cursor %d\n", srwm, cursor_sr);
3253
3254                 if (IS_CRESTLINE(dev))
3255                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3256         } else {
3257                 /* Turn off self refresh if both pipes are enabled */
3258                 if (IS_CRESTLINE(dev))
3259                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3260                                    & ~FW_BLC_SELF_EN);
3261         }
3262
3263         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3264                       srwm);
3265
3266         /* 965 has limitations... */
3267         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3268                    (8 << 0));
3269         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3270         /* update cursor SR watermark */
3271         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3272 }
3273
3274 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3275                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3276                            int pixel_size)
3277 {
3278         struct drm_i915_private *dev_priv = dev->dev_private;
3279         uint32_t fwater_lo;
3280         uint32_t fwater_hi;
3281         int total_size, cacheline_size, cwm, srwm = 1;
3282         int planea_wm, planeb_wm;
3283         struct intel_watermark_params planea_params, planeb_params;
3284         unsigned long line_time_us;
3285         int sr_clock, sr_entries = 0;
3286
3287         /* Create copies of the base settings for each pipe */
3288         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3289                 planea_params = planeb_params = i945_wm_info;
3290         else if (!IS_GEN2(dev))
3291                 planea_params = planeb_params = i915_wm_info;
3292         else
3293                 planea_params = planeb_params = i855_wm_info;
3294
3295         /* Grab a couple of global values before we overwrite them */
3296         total_size = planea_params.fifo_size;
3297         cacheline_size = planea_params.cacheline_size;
3298
3299         /* Update per-plane FIFO sizes */
3300         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3301         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3302
3303         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3304                                        pixel_size, latency_ns);
3305         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3306                                        pixel_size, latency_ns);
3307         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3308
3309         /*
3310          * Overlay gets an aggressive default since video jitter is bad.
3311          */
3312         cwm = 2;
3313
3314         /* Calc sr entries for one plane configs */
3315         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3316             (!planea_clock || !planeb_clock)) {
3317                 /* self-refresh has much higher latency */
3318                 static const int sr_latency_ns = 6000;
3319
3320                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3321                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3322
3323                 /* Use ns/us then divide to preserve precision */
3324                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3325                         pixel_size * sr_hdisplay;
3326                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3327                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3328                 srwm = total_size - sr_entries;
3329                 if (srwm < 0)
3330                         srwm = 1;
3331
3332                 if (IS_I945G(dev) || IS_I945GM(dev))
3333                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3334                 else if (IS_I915GM(dev)) {
3335                         /* 915M has a smaller SRWM field */
3336                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3337                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3338                 }
3339         } else {
3340                 /* Turn off self refresh if both pipes are enabled */
3341                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3342                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3343                                    & ~FW_BLC_SELF_EN);
3344                 } else if (IS_I915GM(dev)) {
3345                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3346                 }
3347         }
3348
3349         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3350                       planea_wm, planeb_wm, cwm, srwm);
3351
3352         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3353         fwater_hi = (cwm & 0x1f);
3354
3355         /* Set request length to 8 cachelines per fetch */
3356         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3357         fwater_hi = fwater_hi | (1 << 8);
3358
3359         I915_WRITE(FW_BLC, fwater_lo);
3360         I915_WRITE(FW_BLC2, fwater_hi);
3361 }
3362
3363 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3364                            int unused2, int unused3, int pixel_size)
3365 {
3366         struct drm_i915_private *dev_priv = dev->dev_private;
3367         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3368         int planea_wm;
3369
3370         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3371
3372         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3373                                        pixel_size, latency_ns);
3374         fwater_lo |= (3<<8) | planea_wm;
3375
3376         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3377
3378         I915_WRITE(FW_BLC, fwater_lo);
3379 }
3380
3381 #define ILK_LP0_PLANE_LATENCY           700
3382 #define ILK_LP0_CURSOR_LATENCY          1300
3383
3384 static bool ironlake_compute_wm0(struct drm_device *dev,
3385                                  int pipe,
3386                                  int *plane_wm,
3387                                  int *cursor_wm)
3388 {
3389         struct drm_crtc *crtc;
3390         int htotal, hdisplay, clock, pixel_size = 0;
3391         int line_time_us, line_count, entries;
3392
3393         crtc = intel_get_crtc_for_pipe(dev, pipe);
3394         if (crtc->fb == NULL || !crtc->enabled)
3395                 return false;
3396
3397         htotal = crtc->mode.htotal;
3398         hdisplay = crtc->mode.hdisplay;
3399         clock = crtc->mode.clock;
3400         pixel_size = crtc->fb->bits_per_pixel / 8;
3401
3402         /* Use the small buffer method to calculate plane watermark */
3403         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3404         entries = DIV_ROUND_UP(entries,
3405                                ironlake_display_wm_info.cacheline_size);
3406         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3407         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3408                 *plane_wm = ironlake_display_wm_info.max_wm;
3409
3410         /* Use the large buffer method to calculate cursor watermark */
3411         line_time_us = ((htotal * 1000) / clock);
3412         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3413         entries = line_count * 64 * pixel_size;
3414         entries = DIV_ROUND_UP(entries,
3415                                ironlake_cursor_wm_info.cacheline_size);
3416         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3417         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3418                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3419
3420         return true;
3421 }
3422
3423 static void ironlake_update_wm(struct drm_device *dev,
3424                                int planea_clock, int planeb_clock,
3425                                int sr_hdisplay, int sr_htotal,
3426                                int pixel_size)
3427 {
3428         struct drm_i915_private *dev_priv = dev->dev_private;
3429         int plane_wm, cursor_wm, enabled;
3430         int tmp;
3431
3432         enabled = 0;
3433         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3434                 I915_WRITE(WM0_PIPEA_ILK,
3435                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3436                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3437                               " plane %d, " "cursor: %d\n",
3438                               plane_wm, cursor_wm);
3439                 enabled++;
3440         }
3441
3442         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3443                 I915_WRITE(WM0_PIPEB_ILK,
3444                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3445                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3446                               " plane %d, cursor: %d\n",
3447                               plane_wm, cursor_wm);
3448                 enabled++;
3449         }
3450
3451         /*
3452          * Calculate and update the self-refresh watermark only when one
3453          * display plane is used.
3454          */
3455         tmp = 0;
3456         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3457                 unsigned long line_time_us;
3458                 int small, large, plane_fbc;
3459                 int sr_clock, entries;
3460                 int line_count, line_size;
3461                 /* Read the self-refresh latency. The unit is 0.5us */
3462                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3463
3464                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3465                 line_time_us = (sr_htotal * 1000) / sr_clock;
3466
3467                 /* Use ns/us then divide to preserve precision */
3468                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3469                         / 1000;
3470                 line_size = sr_hdisplay * pixel_size;
3471
3472                 /* Use the minimum of the small and large buffer method for primary */
3473                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3474                 large = line_count * line_size;
3475
3476                 entries = DIV_ROUND_UP(min(small, large),
3477                                        ironlake_display_srwm_info.cacheline_size);
3478
3479                 plane_fbc = entries * 64;
3480                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3481
3482                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3483                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3484                         plane_wm = ironlake_display_srwm_info.max_wm;
3485
3486                 /* calculate the self-refresh watermark for display cursor */
3487                 entries = line_count * pixel_size * 64;
3488                 entries = DIV_ROUND_UP(entries,
3489                                        ironlake_cursor_srwm_info.cacheline_size);
3490
3491                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3492                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3493                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3494
3495                 /* configure watermark and enable self-refresh */
3496                 tmp = (WM1_LP_SR_EN |
3497                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3498                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3499                        (plane_wm << WM1_LP_SR_SHIFT) |
3500                        cursor_wm);
3501                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3502                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3503         }
3504         I915_WRITE(WM1_LP_ILK, tmp);
3505         /* XXX setup WM2 and WM3 */
3506 }
3507
3508 /**
3509  * intel_update_watermarks - update FIFO watermark values based on current modes
3510  *
3511  * Calculate watermark values for the various WM regs based on current mode
3512  * and plane configuration.
3513  *
3514  * There are several cases to deal with here:
3515  *   - normal (i.e. non-self-refresh)
3516  *   - self-refresh (SR) mode
3517  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3518  *   - lines are small relative to FIFO size (buffer can hold more than 2
3519  *     lines), so need to account for TLB latency
3520  *
3521  *   The normal calculation is:
3522  *     watermark = dotclock * bytes per pixel * latency
3523  *   where latency is platform & configuration dependent (we assume pessimal
3524  *   values here).
3525  *
3526  *   The SR calculation is:
3527  *     watermark = (trunc(latency/line time)+1) * surface width *
3528  *       bytes per pixel
3529  *   where
3530  *     line time = htotal / dotclock
3531  *     surface width = hdisplay for normal plane and 64 for cursor
3532  *   and latency is assumed to be high, as above.
3533  *
3534  * The final value programmed to the register should always be rounded up,
3535  * and include an extra 2 entries to account for clock crossings.
3536  *
3537  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3538  * to set the non-SR watermarks to 8.
3539  */
3540 static void intel_update_watermarks(struct drm_device *dev)
3541 {
3542         struct drm_i915_private *dev_priv = dev->dev_private;
3543         struct drm_crtc *crtc;
3544         int sr_hdisplay = 0;
3545         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3546         int enabled = 0, pixel_size = 0;
3547         int sr_htotal = 0;
3548
3549         if (!dev_priv->display.update_wm)
3550                 return;
3551
3552         /* Get the clock config from both planes */
3553         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3554                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3555                 if (intel_crtc->active) {
3556                         enabled++;
3557                         if (intel_crtc->plane == 0) {
3558                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3559                                               intel_crtc->pipe, crtc->mode.clock);
3560                                 planea_clock = crtc->mode.clock;
3561                         } else {
3562                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3563                                               intel_crtc->pipe, crtc->mode.clock);
3564                                 planeb_clock = crtc->mode.clock;
3565                         }
3566                         sr_hdisplay = crtc->mode.hdisplay;
3567                         sr_clock = crtc->mode.clock;
3568                         sr_htotal = crtc->mode.htotal;
3569                         if (crtc->fb)
3570                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3571                         else
3572                                 pixel_size = 4; /* by default */
3573                 }
3574         }
3575
3576         if (enabled <= 0)
3577                 return;
3578
3579         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3580                                     sr_hdisplay, sr_htotal, pixel_size);
3581 }
3582
3583 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3584                                struct drm_display_mode *mode,
3585                                struct drm_display_mode *adjusted_mode,
3586                                int x, int y,
3587                                struct drm_framebuffer *old_fb)
3588 {
3589         struct drm_device *dev = crtc->dev;
3590         struct drm_i915_private *dev_priv = dev->dev_private;
3591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3592         int pipe = intel_crtc->pipe;
3593         int plane = intel_crtc->plane;
3594         u32 fp_reg, dpll_reg;
3595         int refclk, num_connectors = 0;
3596         intel_clock_t clock, reduced_clock;
3597         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3598         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3599         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3600         struct intel_encoder *has_edp_encoder = NULL;
3601         struct drm_mode_config *mode_config = &dev->mode_config;
3602         struct intel_encoder *encoder;
3603         const intel_limit_t *limit;
3604         int ret;
3605         struct fdi_m_n m_n = {0};
3606         u32 reg, temp;
3607         int target_clock;
3608
3609         drm_vblank_pre_modeset(dev, pipe);
3610
3611         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3612                 if (encoder->base.crtc != crtc)
3613                         continue;
3614
3615                 switch (encoder->type) {
3616                 case INTEL_OUTPUT_LVDS:
3617                         is_lvds = true;
3618                         break;
3619                 case INTEL_OUTPUT_SDVO:
3620                 case INTEL_OUTPUT_HDMI:
3621                         is_sdvo = true;
3622                         if (encoder->needs_tv_clock)
3623                                 is_tv = true;
3624                         break;
3625                 case INTEL_OUTPUT_DVO:
3626                         is_dvo = true;
3627                         break;
3628                 case INTEL_OUTPUT_TVOUT:
3629                         is_tv = true;
3630                         break;
3631                 case INTEL_OUTPUT_ANALOG:
3632                         is_crt = true;
3633                         break;
3634                 case INTEL_OUTPUT_DISPLAYPORT:
3635                         is_dp = true;
3636                         break;
3637                 case INTEL_OUTPUT_EDP:
3638                         has_edp_encoder = encoder;
3639                         break;
3640                 }
3641
3642                 num_connectors++;
3643         }
3644
3645         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3646                 refclk = dev_priv->lvds_ssc_freq * 1000;