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drm/i915: Apply a workaround for transitioning from DP on pipe B to HDMI.
[~shefty/rdma-dev.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Keith Packard <keithp@keithp.com>
25  *
26  */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE     6
41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE      9
44
45 struct intel_dp {
46         struct intel_encoder base;
47         uint32_t output_reg;
48         uint32_t DP;
49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
50         bool has_audio;
51         int force_audio;
52         int dpms_mode;
53         uint8_t link_bw;
54         uint8_t lane_count;
55         uint8_t dpcd[4];
56         struct i2c_adapter adapter;
57         struct i2c_algo_dp_aux_data algo;
58         bool is_pch_edp;
59         uint8_t train_set[4];
60         uint8_t link_status[DP_LINK_STATUS_SIZE];
61
62         struct drm_property *force_audio_property;
63 };
64
65 /**
66  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
67  * @intel_dp: DP struct
68  *
69  * If a CPU or PCH DP output is attached to an eDP panel, this function
70  * will return true, and false otherwise.
71  */
72 static bool is_edp(struct intel_dp *intel_dp)
73 {
74         return intel_dp->base.type == INTEL_OUTPUT_EDP;
75 }
76
77 /**
78  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
79  * @intel_dp: DP struct
80  *
81  * Returns true if the given DP struct corresponds to a PCH DP port attached
82  * to an eDP panel, false otherwise.  Helpful for determining whether we
83  * may need FDI resources for a given DP output or not.
84  */
85 static bool is_pch_edp(struct intel_dp *intel_dp)
86 {
87         return intel_dp->is_pch_edp;
88 }
89
90 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
91 {
92         return container_of(encoder, struct intel_dp, base.base);
93 }
94
95 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
96 {
97         return container_of(intel_attached_encoder(connector),
98                             struct intel_dp, base);
99 }
100
101 /**
102  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
103  * @encoder: DRM encoder
104  *
105  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
106  * by intel_display.c.
107  */
108 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
109 {
110         struct intel_dp *intel_dp;
111
112         if (!encoder)
113                 return false;
114
115         intel_dp = enc_to_intel_dp(encoder);
116
117         return is_pch_edp(intel_dp);
118 }
119
120 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
122 static void intel_dp_link_down(struct intel_dp *intel_dp);
123
124 void
125 intel_edp_link_config (struct intel_encoder *intel_encoder,
126                        int *lane_num, int *link_bw)
127 {
128         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
129
130         *lane_num = intel_dp->lane_count;
131         if (intel_dp->link_bw == DP_LINK_BW_1_62)
132                 *link_bw = 162000;
133         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
134                 *link_bw = 270000;
135 }
136
137 static int
138 intel_dp_max_lane_count(struct intel_dp *intel_dp)
139 {
140         int max_lane_count = 4;
141
142         if (intel_dp->dpcd[0] >= 0x11) {
143                 max_lane_count = intel_dp->dpcd[2] & 0x1f;
144                 switch (max_lane_count) {
145                 case 1: case 2: case 4:
146                         break;
147                 default:
148                         max_lane_count = 4;
149                 }
150         }
151         return max_lane_count;
152 }
153
154 static int
155 intel_dp_max_link_bw(struct intel_dp *intel_dp)
156 {
157         int max_link_bw = intel_dp->dpcd[1];
158
159         switch (max_link_bw) {
160         case DP_LINK_BW_1_62:
161         case DP_LINK_BW_2_7:
162                 break;
163         default:
164                 max_link_bw = DP_LINK_BW_1_62;
165                 break;
166         }
167         return max_link_bw;
168 }
169
170 static int
171 intel_dp_link_clock(uint8_t link_bw)
172 {
173         if (link_bw == DP_LINK_BW_2_7)
174                 return 270000;
175         else
176                 return 162000;
177 }
178
179 /* I think this is a fiction */
180 static int
181 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
182 {
183         struct drm_i915_private *dev_priv = dev->dev_private;
184
185         if (is_edp(intel_dp))
186                 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
187         else
188                 return pixel_clock * 3;
189 }
190
191 static int
192 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
193 {
194         return (max_link_clock * max_lanes * 8) / 10;
195 }
196
197 static int
198 intel_dp_mode_valid(struct drm_connector *connector,
199                     struct drm_display_mode *mode)
200 {
201         struct intel_dp *intel_dp = intel_attached_dp(connector);
202         struct drm_device *dev = connector->dev;
203         struct drm_i915_private *dev_priv = dev->dev_private;
204         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
205         int max_lanes = intel_dp_max_lane_count(intel_dp);
206
207         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
208                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
209                         return MODE_PANEL;
210
211                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
212                         return MODE_PANEL;
213         }
214
215         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
216            which are outside spec tolerances but somehow work by magic */
217         if (!is_edp(intel_dp) &&
218             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
219              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
220                 return MODE_CLOCK_HIGH;
221
222         if (mode->clock < 10000)
223                 return MODE_CLOCK_LOW;
224
225         return MODE_OK;
226 }
227
228 static uint32_t
229 pack_aux(uint8_t *src, int src_bytes)
230 {
231         int     i;
232         uint32_t v = 0;
233
234         if (src_bytes > 4)
235                 src_bytes = 4;
236         for (i = 0; i < src_bytes; i++)
237                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
238         return v;
239 }
240
241 static void
242 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
243 {
244         int i;
245         if (dst_bytes > 4)
246                 dst_bytes = 4;
247         for (i = 0; i < dst_bytes; i++)
248                 dst[i] = src >> ((3-i) * 8);
249 }
250
251 /* hrawclock is 1/4 the FSB frequency */
252 static int
253 intel_hrawclk(struct drm_device *dev)
254 {
255         struct drm_i915_private *dev_priv = dev->dev_private;
256         uint32_t clkcfg;
257
258         clkcfg = I915_READ(CLKCFG);
259         switch (clkcfg & CLKCFG_FSB_MASK) {
260         case CLKCFG_FSB_400:
261                 return 100;
262         case CLKCFG_FSB_533:
263                 return 133;
264         case CLKCFG_FSB_667:
265                 return 166;
266         case CLKCFG_FSB_800:
267                 return 200;
268         case CLKCFG_FSB_1067:
269                 return 266;
270         case CLKCFG_FSB_1333:
271                 return 333;
272         /* these two are just a guess; one of them might be right */
273         case CLKCFG_FSB_1600:
274         case CLKCFG_FSB_1600_ALT:
275                 return 400;
276         default:
277                 return 133;
278         }
279 }
280
281 static int
282 intel_dp_aux_ch(struct intel_dp *intel_dp,
283                 uint8_t *send, int send_bytes,
284                 uint8_t *recv, int recv_size)
285 {
286         uint32_t output_reg = intel_dp->output_reg;
287         struct drm_device *dev = intel_dp->base.base.dev;
288         struct drm_i915_private *dev_priv = dev->dev_private;
289         uint32_t ch_ctl = output_reg + 0x10;
290         uint32_t ch_data = ch_ctl + 4;
291         int i;
292         int recv_bytes;
293         uint32_t status;
294         uint32_t aux_clock_divider;
295         int try, precharge;
296
297         /* The clock divider is based off the hrawclk,
298          * and would like to run at 2MHz. So, take the
299          * hrawclk value and divide by 2 and use that
300          *
301          * Note that PCH attached eDP panels should use a 125MHz input
302          * clock divider.
303          */
304         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
305                 if (IS_GEN6(dev))
306                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
307                 else
308                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
309         } else if (HAS_PCH_SPLIT(dev))
310                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
311         else
312                 aux_clock_divider = intel_hrawclk(dev) / 2;
313
314         if (IS_GEN6(dev))
315                 precharge = 3;
316         else
317                 precharge = 5;
318
319         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
320                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
321                           I915_READ(ch_ctl));
322                 return -EBUSY;
323         }
324
325         /* Must try at least 3 times according to DP spec */
326         for (try = 0; try < 5; try++) {
327                 /* Load the send data into the aux channel data registers */
328                 for (i = 0; i < send_bytes; i += 4)
329                         I915_WRITE(ch_data + i,
330                                    pack_aux(send + i, send_bytes - i));
331         
332                 /* Send the command and wait for it to complete */
333                 I915_WRITE(ch_ctl,
334                            DP_AUX_CH_CTL_SEND_BUSY |
335                            DP_AUX_CH_CTL_TIME_OUT_400us |
336                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
337                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
338                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
339                            DP_AUX_CH_CTL_DONE |
340                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
341                            DP_AUX_CH_CTL_RECEIVE_ERROR);
342                 for (;;) {
343                         status = I915_READ(ch_ctl);
344                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
345                                 break;
346                         udelay(100);
347                 }
348         
349                 /* Clear done status and any errors */
350                 I915_WRITE(ch_ctl,
351                            status |
352                            DP_AUX_CH_CTL_DONE |
353                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
354                            DP_AUX_CH_CTL_RECEIVE_ERROR);
355                 if (status & DP_AUX_CH_CTL_DONE)
356                         break;
357         }
358
359         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
360                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
361                 return -EBUSY;
362         }
363
364         /* Check for timeout or receive error.
365          * Timeouts occur when the sink is not connected
366          */
367         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
368                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
369                 return -EIO;
370         }
371
372         /* Timeouts occur when the device isn't connected, so they're
373          * "normal" -- don't fill the kernel log with these */
374         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
375                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
376                 return -ETIMEDOUT;
377         }
378
379         /* Unload any bytes sent back from the other side */
380         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
381                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
382         if (recv_bytes > recv_size)
383                 recv_bytes = recv_size;
384         
385         for (i = 0; i < recv_bytes; i += 4)
386                 unpack_aux(I915_READ(ch_data + i),
387                            recv + i, recv_bytes - i);
388
389         return recv_bytes;
390 }
391
392 /* Write data to the aux channel in native mode */
393 static int
394 intel_dp_aux_native_write(struct intel_dp *intel_dp,
395                           uint16_t address, uint8_t *send, int send_bytes)
396 {
397         int ret;
398         uint8_t msg[20];
399         int msg_bytes;
400         uint8_t ack;
401
402         if (send_bytes > 16)
403                 return -1;
404         msg[0] = AUX_NATIVE_WRITE << 4;
405         msg[1] = address >> 8;
406         msg[2] = address & 0xff;
407         msg[3] = send_bytes - 1;
408         memcpy(&msg[4], send, send_bytes);
409         msg_bytes = send_bytes + 4;
410         for (;;) {
411                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
412                 if (ret < 0)
413                         return ret;
414                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
415                         break;
416                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
417                         udelay(100);
418                 else
419                         return -EIO;
420         }
421         return send_bytes;
422 }
423
424 /* Write a single byte to the aux channel in native mode */
425 static int
426 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
427                             uint16_t address, uint8_t byte)
428 {
429         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
430 }
431
432 /* read bytes from a native aux channel */
433 static int
434 intel_dp_aux_native_read(struct intel_dp *intel_dp,
435                          uint16_t address, uint8_t *recv, int recv_bytes)
436 {
437         uint8_t msg[4];
438         int msg_bytes;
439         uint8_t reply[20];
440         int reply_bytes;
441         uint8_t ack;
442         int ret;
443
444         msg[0] = AUX_NATIVE_READ << 4;
445         msg[1] = address >> 8;
446         msg[2] = address & 0xff;
447         msg[3] = recv_bytes - 1;
448
449         msg_bytes = 4;
450         reply_bytes = recv_bytes + 1;
451
452         for (;;) {
453                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
454                                       reply, reply_bytes);
455                 if (ret == 0)
456                         return -EPROTO;
457                 if (ret < 0)
458                         return ret;
459                 ack = reply[0];
460                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
461                         memcpy(recv, reply + 1, ret - 1);
462                         return ret - 1;
463                 }
464                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
465                         udelay(100);
466                 else
467                         return -EIO;
468         }
469 }
470
471 static int
472 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
473                     uint8_t write_byte, uint8_t *read_byte)
474 {
475         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
476         struct intel_dp *intel_dp = container_of(adapter,
477                                                 struct intel_dp,
478                                                 adapter);
479         uint16_t address = algo_data->address;
480         uint8_t msg[5];
481         uint8_t reply[2];
482         int msg_bytes;
483         int reply_bytes;
484         int ret;
485
486         /* Set up the command byte */
487         if (mode & MODE_I2C_READ)
488                 msg[0] = AUX_I2C_READ << 4;
489         else
490                 msg[0] = AUX_I2C_WRITE << 4;
491
492         if (!(mode & MODE_I2C_STOP))
493                 msg[0] |= AUX_I2C_MOT << 4;
494
495         msg[1] = address >> 8;
496         msg[2] = address;
497
498         switch (mode) {
499         case MODE_I2C_WRITE:
500                 msg[3] = 0;
501                 msg[4] = write_byte;
502                 msg_bytes = 5;
503                 reply_bytes = 1;
504                 break;
505         case MODE_I2C_READ:
506                 msg[3] = 0;
507                 msg_bytes = 4;
508                 reply_bytes = 2;
509                 break;
510         default:
511                 msg_bytes = 3;
512                 reply_bytes = 1;
513                 break;
514         }
515
516         for (;;) {
517           ret = intel_dp_aux_ch(intel_dp,
518                                 msg, msg_bytes,
519                                 reply, reply_bytes);
520                 if (ret < 0) {
521                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
522                         return ret;
523                 }
524                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
525                 case AUX_I2C_REPLY_ACK:
526                         if (mode == MODE_I2C_READ) {
527                                 *read_byte = reply[1];
528                         }
529                         return reply_bytes - 1;
530                 case AUX_I2C_REPLY_NACK:
531                         DRM_DEBUG_KMS("aux_ch nack\n");
532                         return -EREMOTEIO;
533                 case AUX_I2C_REPLY_DEFER:
534                         DRM_DEBUG_KMS("aux_ch defer\n");
535                         udelay(100);
536                         break;
537                 default:
538                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
539                         return -EREMOTEIO;
540                 }
541         }
542 }
543
544 static int
545 intel_dp_i2c_init(struct intel_dp *intel_dp,
546                   struct intel_connector *intel_connector, const char *name)
547 {
548         DRM_DEBUG_KMS("i2c_init %s\n", name);
549         intel_dp->algo.running = false;
550         intel_dp->algo.address = 0;
551         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
552
553         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
554         intel_dp->adapter.owner = THIS_MODULE;
555         intel_dp->adapter.class = I2C_CLASS_DDC;
556         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
557         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
558         intel_dp->adapter.algo_data = &intel_dp->algo;
559         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
560
561         return i2c_dp_aux_add_bus(&intel_dp->adapter);
562 }
563
564 static bool
565 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
566                     struct drm_display_mode *adjusted_mode)
567 {
568         struct drm_device *dev = encoder->dev;
569         struct drm_i915_private *dev_priv = dev->dev_private;
570         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
571         int lane_count, clock;
572         int max_lane_count = intel_dp_max_lane_count(intel_dp);
573         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
574         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
575
576         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
577                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
578                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
579                                         mode, adjusted_mode);
580                 /*
581                  * the mode->clock is used to calculate the Data&Link M/N
582                  * of the pipe. For the eDP the fixed clock should be used.
583                  */
584                 mode->clock = dev_priv->panel_fixed_mode->clock;
585         }
586
587         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
588                 for (clock = 0; clock <= max_clock; clock++) {
589                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
590
591                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
592                                         <= link_avail) {
593                                 intel_dp->link_bw = bws[clock];
594                                 intel_dp->lane_count = lane_count;
595                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
596                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
597                                                 "count %d clock %d\n",
598                                        intel_dp->link_bw, intel_dp->lane_count,
599                                        adjusted_mode->clock);
600                                 return true;
601                         }
602                 }
603         }
604
605         if (is_edp(intel_dp)) {
606                 /* okay we failed just pick the highest */
607                 intel_dp->lane_count = max_lane_count;
608                 intel_dp->link_bw = bws[max_clock];
609                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
610                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
611                               "count %d clock %d\n",
612                               intel_dp->link_bw, intel_dp->lane_count,
613                               adjusted_mode->clock);
614
615                 return true;
616         }
617
618         return false;
619 }
620
621 struct intel_dp_m_n {
622         uint32_t        tu;
623         uint32_t        gmch_m;
624         uint32_t        gmch_n;
625         uint32_t        link_m;
626         uint32_t        link_n;
627 };
628
629 static void
630 intel_reduce_ratio(uint32_t *num, uint32_t *den)
631 {
632         while (*num > 0xffffff || *den > 0xffffff) {
633                 *num >>= 1;
634                 *den >>= 1;
635         }
636 }
637
638 static void
639 intel_dp_compute_m_n(int bpp,
640                      int nlanes,
641                      int pixel_clock,
642                      int link_clock,
643                      struct intel_dp_m_n *m_n)
644 {
645         m_n->tu = 64;
646         m_n->gmch_m = (pixel_clock * bpp) >> 3;
647         m_n->gmch_n = link_clock * nlanes;
648         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
649         m_n->link_m = pixel_clock;
650         m_n->link_n = link_clock;
651         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
652 }
653
654 void
655 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
656                  struct drm_display_mode *adjusted_mode)
657 {
658         struct drm_device *dev = crtc->dev;
659         struct drm_mode_config *mode_config = &dev->mode_config;
660         struct drm_encoder *encoder;
661         struct drm_i915_private *dev_priv = dev->dev_private;
662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
663         int lane_count = 4, bpp = 24;
664         struct intel_dp_m_n m_n;
665
666         /*
667          * Find the lane count in the intel_encoder private
668          */
669         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
670                 struct intel_dp *intel_dp;
671
672                 if (encoder->crtc != crtc)
673                         continue;
674
675                 intel_dp = enc_to_intel_dp(encoder);
676                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
677                         lane_count = intel_dp->lane_count;
678                         break;
679                 } else if (is_edp(intel_dp)) {
680                         lane_count = dev_priv->edp.lanes;
681                         bpp = dev_priv->edp.bpp;
682                         break;
683                 }
684         }
685
686         /*
687          * Compute the GMCH and Link ratios. The '3' here is
688          * the number of bytes_per_pixel post-LUT, which we always
689          * set up for 8-bits of R/G/B, or 3 bytes total.
690          */
691         intel_dp_compute_m_n(bpp, lane_count,
692                              mode->clock, adjusted_mode->clock, &m_n);
693
694         if (HAS_PCH_SPLIT(dev)) {
695                 if (intel_crtc->pipe == 0) {
696                         I915_WRITE(TRANSA_DATA_M1,
697                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
698                                    m_n.gmch_m);
699                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
700                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
701                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
702                 } else {
703                         I915_WRITE(TRANSB_DATA_M1,
704                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
705                                    m_n.gmch_m);
706                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
707                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
708                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
709                 }
710         } else {
711                 if (intel_crtc->pipe == 0) {
712                         I915_WRITE(PIPEA_GMCH_DATA_M,
713                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
714                                    m_n.gmch_m);
715                         I915_WRITE(PIPEA_GMCH_DATA_N,
716                                    m_n.gmch_n);
717                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
718                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
719                 } else {
720                         I915_WRITE(PIPEB_GMCH_DATA_M,
721                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
722                                    m_n.gmch_m);
723                         I915_WRITE(PIPEB_GMCH_DATA_N,
724                                         m_n.gmch_n);
725                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
726                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
727                 }
728         }
729 }
730
731 static void
732 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
733                   struct drm_display_mode *adjusted_mode)
734 {
735         struct drm_device *dev = encoder->dev;
736         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
737         struct drm_crtc *crtc = intel_dp->base.base.crtc;
738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740         intel_dp->DP = (DP_VOLTAGE_0_4 |
741                        DP_PRE_EMPHASIS_0);
742
743         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
744                 intel_dp->DP |= DP_SYNC_HS_HIGH;
745         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
746                 intel_dp->DP |= DP_SYNC_VS_HIGH;
747
748         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
749                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
750         else
751                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
752
753         switch (intel_dp->lane_count) {
754         case 1:
755                 intel_dp->DP |= DP_PORT_WIDTH_1;
756                 break;
757         case 2:
758                 intel_dp->DP |= DP_PORT_WIDTH_2;
759                 break;
760         case 4:
761                 intel_dp->DP |= DP_PORT_WIDTH_4;
762                 break;
763         }
764         if (intel_dp->has_audio)
765                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
766
767         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
768         intel_dp->link_configuration[0] = intel_dp->link_bw;
769         intel_dp->link_configuration[1] = intel_dp->lane_count;
770
771         /*
772          * Check for DPCD version > 1.1 and enhanced framing support
773          */
774         if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
775                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
776                 intel_dp->DP |= DP_ENHANCED_FRAMING;
777         }
778
779         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
780         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
781                 intel_dp->DP |= DP_PIPEB_SELECT;
782
783         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
784                 /* don't miss out required setting for eDP */
785                 intel_dp->DP |= DP_PLL_ENABLE;
786                 if (adjusted_mode->clock < 200000)
787                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
788                 else
789                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
790         }
791 }
792
793 /* Returns true if the panel was already on when called */
794 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
795 {
796         struct drm_device *dev = intel_dp->base.base.dev;
797         struct drm_i915_private *dev_priv = dev->dev_private;
798         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
799
800         if (I915_READ(PCH_PP_STATUS) & PP_ON)
801                 return true;
802
803         pp = I915_READ(PCH_PP_CONTROL);
804
805         /* ILK workaround: disable reset around power sequence */
806         pp &= ~PANEL_POWER_RESET;
807         I915_WRITE(PCH_PP_CONTROL, pp);
808         POSTING_READ(PCH_PP_CONTROL);
809
810         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
811         I915_WRITE(PCH_PP_CONTROL, pp);
812         POSTING_READ(PCH_PP_CONTROL);
813
814         /* Ouch. We need to wait here for some panels, like Dell e6510
815          * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
816          */
817         msleep(300);
818
819         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
820                      5000))
821                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
822                           I915_READ(PCH_PP_STATUS));
823
824         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
825         I915_WRITE(PCH_PP_CONTROL, pp);
826         POSTING_READ(PCH_PP_CONTROL);
827
828         return false;
829 }
830
831 static void ironlake_edp_panel_off (struct drm_device *dev)
832 {
833         struct drm_i915_private *dev_priv = dev->dev_private;
834         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
835                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
836
837         pp = I915_READ(PCH_PP_CONTROL);
838
839         /* ILK workaround: disable reset around power sequence */
840         pp &= ~PANEL_POWER_RESET;
841         I915_WRITE(PCH_PP_CONTROL, pp);
842         POSTING_READ(PCH_PP_CONTROL);
843
844         pp &= ~POWER_TARGET_ON;
845         I915_WRITE(PCH_PP_CONTROL, pp);
846         POSTING_READ(PCH_PP_CONTROL);
847
848         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
849                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
850                           I915_READ(PCH_PP_STATUS));
851
852         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
853         I915_WRITE(PCH_PP_CONTROL, pp);
854         POSTING_READ(PCH_PP_CONTROL);
855
856         /* Ouch. We need to wait here for some panels, like Dell e6510
857          * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
858          */
859         msleep(300);
860 }
861
862 static void ironlake_edp_backlight_on (struct drm_device *dev)
863 {
864         struct drm_i915_private *dev_priv = dev->dev_private;
865         u32 pp;
866
867         DRM_DEBUG_KMS("\n");
868         /*
869          * If we enable the backlight right away following a panel power
870          * on, we may see slight flicker as the panel syncs with the eDP
871          * link.  So delay a bit to make sure the image is solid before
872          * allowing it to appear.
873          */
874         msleep(300);
875         pp = I915_READ(PCH_PP_CONTROL);
876         pp |= EDP_BLC_ENABLE;
877         I915_WRITE(PCH_PP_CONTROL, pp);
878 }
879
880 static void ironlake_edp_backlight_off (struct drm_device *dev)
881 {
882         struct drm_i915_private *dev_priv = dev->dev_private;
883         u32 pp;
884
885         DRM_DEBUG_KMS("\n");
886         pp = I915_READ(PCH_PP_CONTROL);
887         pp &= ~EDP_BLC_ENABLE;
888         I915_WRITE(PCH_PP_CONTROL, pp);
889 }
890
891 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
892 {
893         struct drm_device *dev = encoder->dev;
894         struct drm_i915_private *dev_priv = dev->dev_private;
895         u32 dpa_ctl;
896
897         DRM_DEBUG_KMS("\n");
898         dpa_ctl = I915_READ(DP_A);
899         dpa_ctl |= DP_PLL_ENABLE;
900         I915_WRITE(DP_A, dpa_ctl);
901         POSTING_READ(DP_A);
902         udelay(200);
903 }
904
905 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
906 {
907         struct drm_device *dev = encoder->dev;
908         struct drm_i915_private *dev_priv = dev->dev_private;
909         u32 dpa_ctl;
910
911         dpa_ctl = I915_READ(DP_A);
912         dpa_ctl &= ~DP_PLL_ENABLE;
913         I915_WRITE(DP_A, dpa_ctl);
914         POSTING_READ(DP_A);
915         udelay(200);
916 }
917
918 static void intel_dp_prepare(struct drm_encoder *encoder)
919 {
920         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
921         struct drm_device *dev = encoder->dev;
922
923         if (is_edp(intel_dp)) {
924                 ironlake_edp_backlight_off(dev);
925                 ironlake_edp_panel_on(intel_dp);
926                 if (!is_pch_edp(intel_dp))
927                         ironlake_edp_pll_on(encoder);
928                 else
929                         ironlake_edp_pll_off(encoder);
930         }
931         intel_dp_link_down(intel_dp);
932 }
933
934 static void intel_dp_commit(struct drm_encoder *encoder)
935 {
936         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
937         struct drm_device *dev = encoder->dev;
938
939         intel_dp_start_link_train(intel_dp);
940
941         if (is_edp(intel_dp))
942                 ironlake_edp_panel_on(intel_dp);
943
944         intel_dp_complete_link_train(intel_dp);
945
946         if (is_edp(intel_dp))
947                 ironlake_edp_backlight_on(dev);
948 }
949
950 static void
951 intel_dp_dpms(struct drm_encoder *encoder, int mode)
952 {
953         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
954         struct drm_device *dev = encoder->dev;
955         struct drm_i915_private *dev_priv = dev->dev_private;
956         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
957
958         if (mode != DRM_MODE_DPMS_ON) {
959                 if (is_edp(intel_dp))
960                         ironlake_edp_backlight_off(dev);
961                 intel_dp_link_down(intel_dp);
962                 if (is_edp(intel_dp))
963                         ironlake_edp_panel_off(dev);
964                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
965                         ironlake_edp_pll_off(encoder);
966         } else {
967                 if (is_edp(intel_dp))
968                         ironlake_edp_panel_on(intel_dp);
969                 if (!(dp_reg & DP_PORT_EN)) {
970                         intel_dp_start_link_train(intel_dp);
971                         intel_dp_complete_link_train(intel_dp);
972                 }
973                 if (is_edp(intel_dp))
974                         ironlake_edp_backlight_on(dev);
975         }
976         intel_dp->dpms_mode = mode;
977 }
978
979 /*
980  * Fetch AUX CH registers 0x202 - 0x207 which contain
981  * link status information
982  */
983 static bool
984 intel_dp_get_link_status(struct intel_dp *intel_dp)
985 {
986         int ret;
987
988         ret = intel_dp_aux_native_read(intel_dp,
989                                        DP_LANE0_1_STATUS,
990                                        intel_dp->link_status, DP_LINK_STATUS_SIZE);
991         if (ret != DP_LINK_STATUS_SIZE)
992                 return false;
993         return true;
994 }
995
996 static uint8_t
997 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
998                      int r)
999 {
1000         return link_status[r - DP_LANE0_1_STATUS];
1001 }
1002
1003 static uint8_t
1004 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1005                                  int lane)
1006 {
1007         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1008         int         s = ((lane & 1) ?
1009                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1010                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1011         uint8_t l = intel_dp_link_status(link_status, i);
1012
1013         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1014 }
1015
1016 static uint8_t
1017 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1018                                       int lane)
1019 {
1020         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1021         int         s = ((lane & 1) ?
1022                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1023                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1024         uint8_t l = intel_dp_link_status(link_status, i);
1025
1026         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1027 }
1028
1029
1030 #if 0
1031 static char     *voltage_names[] = {
1032         "0.4V", "0.6V", "0.8V", "1.2V"
1033 };
1034 static char     *pre_emph_names[] = {
1035         "0dB", "3.5dB", "6dB", "9.5dB"
1036 };
1037 static char     *link_train_names[] = {
1038         "pattern 1", "pattern 2", "idle", "off"
1039 };
1040 #endif
1041
1042 /*
1043  * These are source-specific values; current Intel hardware supports
1044  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1045  */
1046 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1047
1048 static uint8_t
1049 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1050 {
1051         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1052         case DP_TRAIN_VOLTAGE_SWING_400:
1053                 return DP_TRAIN_PRE_EMPHASIS_6;
1054         case DP_TRAIN_VOLTAGE_SWING_600:
1055                 return DP_TRAIN_PRE_EMPHASIS_6;
1056         case DP_TRAIN_VOLTAGE_SWING_800:
1057                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1058         case DP_TRAIN_VOLTAGE_SWING_1200:
1059         default:
1060                 return DP_TRAIN_PRE_EMPHASIS_0;
1061         }
1062 }
1063
1064 static void
1065 intel_get_adjust_train(struct intel_dp *intel_dp)
1066 {
1067         uint8_t v = 0;
1068         uint8_t p = 0;
1069         int lane;
1070
1071         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1072                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1073                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1074
1075                 if (this_v > v)
1076                         v = this_v;
1077                 if (this_p > p)
1078                         p = this_p;
1079         }
1080
1081         if (v >= I830_DP_VOLTAGE_MAX)
1082                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1083
1084         if (p >= intel_dp_pre_emphasis_max(v))
1085                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1086
1087         for (lane = 0; lane < 4; lane++)
1088                 intel_dp->train_set[lane] = v | p;
1089 }
1090
1091 static uint32_t
1092 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1093 {
1094         uint32_t        signal_levels = 0;
1095
1096         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1097         case DP_TRAIN_VOLTAGE_SWING_400:
1098         default:
1099                 signal_levels |= DP_VOLTAGE_0_4;
1100                 break;
1101         case DP_TRAIN_VOLTAGE_SWING_600:
1102                 signal_levels |= DP_VOLTAGE_0_6;
1103                 break;
1104         case DP_TRAIN_VOLTAGE_SWING_800:
1105                 signal_levels |= DP_VOLTAGE_0_8;
1106                 break;
1107         case DP_TRAIN_VOLTAGE_SWING_1200:
1108                 signal_levels |= DP_VOLTAGE_1_2;
1109                 break;
1110         }
1111         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1112         case DP_TRAIN_PRE_EMPHASIS_0:
1113         default:
1114                 signal_levels |= DP_PRE_EMPHASIS_0;
1115                 break;
1116         case DP_TRAIN_PRE_EMPHASIS_3_5:
1117                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1118                 break;
1119         case DP_TRAIN_PRE_EMPHASIS_6:
1120                 signal_levels |= DP_PRE_EMPHASIS_6;
1121                 break;
1122         case DP_TRAIN_PRE_EMPHASIS_9_5:
1123                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1124                 break;
1125         }
1126         return signal_levels;
1127 }
1128
1129 /* Gen6's DP voltage swing and pre-emphasis control */
1130 static uint32_t
1131 intel_gen6_edp_signal_levels(uint8_t train_set)
1132 {
1133         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1134         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1135                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1136         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1137                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1138         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1139                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1140         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1141                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1142         default:
1143                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1144                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1145         }
1146 }
1147
1148 static uint8_t
1149 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1150                       int lane)
1151 {
1152         int i = DP_LANE0_1_STATUS + (lane >> 1);
1153         int s = (lane & 1) * 4;
1154         uint8_t l = intel_dp_link_status(link_status, i);
1155
1156         return (l >> s) & 0xf;
1157 }
1158
1159 /* Check for clock recovery is done on all channels */
1160 static bool
1161 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1162 {
1163         int lane;
1164         uint8_t lane_status;
1165
1166         for (lane = 0; lane < lane_count; lane++) {
1167                 lane_status = intel_get_lane_status(link_status, lane);
1168                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1169                         return false;
1170         }
1171         return true;
1172 }
1173
1174 /* Check to see if channel eq is done on all channels */
1175 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1176                          DP_LANE_CHANNEL_EQ_DONE|\
1177                          DP_LANE_SYMBOL_LOCKED)
1178 static bool
1179 intel_channel_eq_ok(struct intel_dp *intel_dp)
1180 {
1181         uint8_t lane_align;
1182         uint8_t lane_status;
1183         int lane;
1184
1185         lane_align = intel_dp_link_status(intel_dp->link_status,
1186                                           DP_LANE_ALIGN_STATUS_UPDATED);
1187         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1188                 return false;
1189         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1190                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1191                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1192                         return false;
1193         }
1194         return true;
1195 }
1196
1197 static bool
1198 intel_dp_set_link_train(struct intel_dp *intel_dp,
1199                         uint32_t dp_reg_value,
1200                         uint8_t dp_train_pat)
1201 {
1202         struct drm_device *dev = intel_dp->base.base.dev;
1203         struct drm_i915_private *dev_priv = dev->dev_private;
1204         int ret;
1205
1206         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1207         POSTING_READ(intel_dp->output_reg);
1208
1209         intel_dp_aux_native_write_1(intel_dp,
1210                                     DP_TRAINING_PATTERN_SET,
1211                                     dp_train_pat);
1212
1213         ret = intel_dp_aux_native_write(intel_dp,
1214                                         DP_TRAINING_LANE0_SET,
1215                                         intel_dp->train_set, 4);
1216         if (ret != 4)
1217                 return false;
1218
1219         return true;
1220 }
1221
1222 /* Enable corresponding port and start training pattern 1 */
1223 static void
1224 intel_dp_start_link_train(struct intel_dp *intel_dp)
1225 {
1226         struct drm_device *dev = intel_dp->base.base.dev;
1227         struct drm_i915_private *dev_priv = dev->dev_private;
1228         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1229         int i;
1230         uint8_t voltage;
1231         bool clock_recovery = false;
1232         int tries;
1233         u32 reg;
1234         uint32_t DP = intel_dp->DP;
1235
1236         /* Enable output, wait for it to become active */
1237         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1238         POSTING_READ(intel_dp->output_reg);
1239         intel_wait_for_vblank(dev, intel_crtc->pipe);
1240
1241         /* Write the link configuration data */
1242         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1243                                   intel_dp->link_configuration,
1244                                   DP_LINK_CONFIGURATION_SIZE);
1245
1246         DP |= DP_PORT_EN;
1247         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1248                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1249         else
1250                 DP &= ~DP_LINK_TRAIN_MASK;
1251         memset(intel_dp->train_set, 0, 4);
1252         voltage = 0xff;
1253         tries = 0;
1254         clock_recovery = false;
1255         for (;;) {
1256                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1257                 uint32_t    signal_levels;
1258                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1259                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1260                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1261                 } else {
1262                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1263                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1264                 }
1265
1266                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1267                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1268                 else
1269                         reg = DP | DP_LINK_TRAIN_PAT_1;
1270
1271                 if (!intel_dp_set_link_train(intel_dp, reg,
1272                                              DP_TRAINING_PATTERN_1))
1273                         break;
1274                 /* Set training pattern 1 */
1275
1276                 udelay(100);
1277                 if (!intel_dp_get_link_status(intel_dp))
1278                         break;
1279
1280                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1281                         clock_recovery = true;
1282                         break;
1283                 }
1284
1285                 /* Check to see if we've tried the max voltage */
1286                 for (i = 0; i < intel_dp->lane_count; i++)
1287                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1288                                 break;
1289                 if (i == intel_dp->lane_count)
1290                         break;
1291
1292                 /* Check to see if we've tried the same voltage 5 times */
1293                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1294                         ++tries;
1295                         if (tries == 5)
1296                                 break;
1297                 } else
1298                         tries = 0;
1299                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1300
1301                 /* Compute new intel_dp->train_set as requested by target */
1302                 intel_get_adjust_train(intel_dp);
1303         }
1304
1305         intel_dp->DP = DP;
1306 }
1307
1308 static void
1309 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1310 {
1311         struct drm_device *dev = intel_dp->base.base.dev;
1312         struct drm_i915_private *dev_priv = dev->dev_private;
1313         bool channel_eq = false;
1314         int tries;
1315         u32 reg;
1316         uint32_t DP = intel_dp->DP;
1317
1318         /* channel equalization */
1319         tries = 0;
1320         channel_eq = false;
1321         for (;;) {
1322                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1323                 uint32_t    signal_levels;
1324
1325                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1326                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1327                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1328                 } else {
1329                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1330                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1331                 }
1332
1333                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1334                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1335                 else
1336                         reg = DP | DP_LINK_TRAIN_PAT_2;
1337
1338                 /* channel eq pattern */
1339                 if (!intel_dp_set_link_train(intel_dp, reg,
1340                                              DP_TRAINING_PATTERN_2))
1341                         break;
1342
1343                 udelay(400);
1344                 if (!intel_dp_get_link_status(intel_dp))
1345                         break;
1346
1347                 if (intel_channel_eq_ok(intel_dp)) {
1348                         channel_eq = true;
1349                         break;
1350                 }
1351
1352                 /* Try 5 times */
1353                 if (tries > 5)
1354                         break;
1355
1356                 /* Compute new intel_dp->train_set as requested by target */
1357                 intel_get_adjust_train(intel_dp);
1358                 ++tries;
1359         }
1360
1361         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1362                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1363         else
1364                 reg = DP | DP_LINK_TRAIN_OFF;
1365
1366         I915_WRITE(intel_dp->output_reg, reg);
1367         POSTING_READ(intel_dp->output_reg);
1368         intel_dp_aux_native_write_1(intel_dp,
1369                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1370 }
1371
1372 static void
1373 intel_dp_link_down(struct intel_dp *intel_dp)
1374 {
1375         struct drm_device *dev = intel_dp->base.base.dev;
1376         struct drm_i915_private *dev_priv = dev->dev_private;
1377         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1378         uint32_t DP = intel_dp->DP;
1379
1380         DRM_DEBUG_KMS("\n");
1381
1382         if (is_edp(intel_dp)) {
1383                 DP &= ~DP_PLL_ENABLE;
1384                 I915_WRITE(intel_dp->output_reg, DP);
1385                 POSTING_READ(intel_dp->output_reg);
1386                 udelay(100);
1387         }
1388
1389         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1390                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1391                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1392         } else {
1393                 DP &= ~DP_LINK_TRAIN_MASK;
1394                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1395         }
1396         POSTING_READ(intel_dp->output_reg);
1397
1398         msleep(17);
1399
1400         if (is_edp(intel_dp))
1401                 DP |= DP_LINK_TRAIN_OFF;
1402
1403         if (!HAS_PCH_CPT(dev) && (DP & DP_PIPEB_SELECT)) {
1404                 /* Hardware workaround: leaving our transcoder select
1405                  * set to transcoder B while it's off will prevent the
1406                  * corresponding HDMI output on transcoder A.
1407                  *
1408                  * Combine this with another hardware workaround:
1409                  * transcoder select bit can only be cleared while the
1410                  * port is enabled.
1411                  */
1412                 DP &= ~DP_PIPEB_SELECT;
1413                 I915_WRITE(intel_dp->output_reg, DP);
1414
1415                 /* Changes to enable or select take place the vblank
1416                  * after being written.
1417                  */
1418                 intel_wait_for_vblank(intel_dp->base.base.dev,
1419                                       intel_crtc->pipe);
1420         }
1421
1422         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1423         POSTING_READ(intel_dp->output_reg);
1424 }
1425
1426 /*
1427  * According to DP spec
1428  * 5.1.2:
1429  *  1. Read DPCD
1430  *  2. Configure link according to Receiver Capabilities
1431  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1432  *  4. Check link status on receipt of hot-plug interrupt
1433  */
1434
1435 static void
1436 intel_dp_check_link_status(struct intel_dp *intel_dp)
1437 {
1438         if (!intel_dp->base.base.crtc)
1439                 return;
1440
1441         if (!intel_dp_get_link_status(intel_dp)) {
1442                 intel_dp_link_down(intel_dp);
1443                 return;
1444         }
1445
1446         if (!intel_channel_eq_ok(intel_dp)) {
1447                 intel_dp_start_link_train(intel_dp);
1448                 intel_dp_complete_link_train(intel_dp);
1449         }
1450 }
1451
1452 static enum drm_connector_status
1453 ironlake_dp_detect(struct intel_dp *intel_dp)
1454 {
1455         enum drm_connector_status status;
1456
1457         /* Can't disconnect eDP */
1458         if (is_edp(intel_dp))
1459                 return connector_status_connected;
1460
1461         status = connector_status_disconnected;
1462         if (intel_dp_aux_native_read(intel_dp,
1463                                      0x000, intel_dp->dpcd,
1464                                      sizeof (intel_dp->dpcd))
1465             == sizeof(intel_dp->dpcd)) {
1466                 if (intel_dp->dpcd[0] != 0)
1467                         status = connector_status_connected;
1468         }
1469         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1470                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1471         return status;
1472 }
1473
1474 static enum drm_connector_status
1475 g4x_dp_detect(struct intel_dp *intel_dp)
1476 {
1477         struct drm_device *dev = intel_dp->base.base.dev;
1478         struct drm_i915_private *dev_priv = dev->dev_private;
1479         enum drm_connector_status status;
1480         uint32_t temp, bit;
1481
1482         switch (intel_dp->output_reg) {
1483         case DP_B:
1484                 bit = DPB_HOTPLUG_INT_STATUS;
1485                 break;
1486         case DP_C:
1487                 bit = DPC_HOTPLUG_INT_STATUS;
1488                 break;
1489         case DP_D:
1490                 bit = DPD_HOTPLUG_INT_STATUS;
1491                 break;
1492         default:
1493                 return connector_status_unknown;
1494         }
1495
1496         temp = I915_READ(PORT_HOTPLUG_STAT);
1497
1498         if ((temp & bit) == 0)
1499                 return connector_status_disconnected;
1500
1501         status = connector_status_disconnected;
1502         if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1503                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1504         {
1505                 if (intel_dp->dpcd[0] != 0)
1506                         status = connector_status_connected;
1507         }
1508
1509         return status;
1510 }
1511
1512 /**
1513  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1514  *
1515  * \return true if DP port is connected.
1516  * \return false if DP port is disconnected.
1517  */
1518 static enum drm_connector_status
1519 intel_dp_detect(struct drm_connector *connector, bool force)
1520 {
1521         struct intel_dp *intel_dp = intel_attached_dp(connector);
1522         struct drm_device *dev = intel_dp->base.base.dev;
1523         enum drm_connector_status status;
1524         struct edid *edid = NULL;
1525
1526         intel_dp->has_audio = false;
1527
1528         if (HAS_PCH_SPLIT(dev))
1529                 status = ironlake_dp_detect(intel_dp);
1530         else
1531                 status = g4x_dp_detect(intel_dp);
1532         if (status != connector_status_connected)
1533                 return status;
1534
1535         if (intel_dp->force_audio) {
1536                 intel_dp->has_audio = intel_dp->force_audio > 0;
1537         } else {
1538                 edid = drm_get_edid(connector, &intel_dp->adapter);
1539                 if (edid) {
1540                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1541                         connector->display_info.raw_edid = NULL;
1542                         kfree(edid);
1543                 }
1544         }
1545
1546         return connector_status_connected;
1547 }
1548
1549 static int intel_dp_get_modes(struct drm_connector *connector)
1550 {
1551         struct intel_dp *intel_dp = intel_attached_dp(connector);
1552         struct drm_device *dev = intel_dp->base.base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         int ret;
1555
1556         /* We should parse the EDID data and find out if it has an audio sink
1557          */
1558
1559         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1560         if (ret) {
1561                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1562                         struct drm_display_mode *newmode;
1563                         list_for_each_entry(newmode, &connector->probed_modes,
1564                                             head) {
1565                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1566                                         dev_priv->panel_fixed_mode =
1567                                                 drm_mode_duplicate(dev, newmode);
1568                                         break;
1569                                 }
1570                         }
1571                 }
1572
1573                 return ret;
1574         }
1575
1576         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1577         if (is_edp(intel_dp)) {
1578                 if (dev_priv->panel_fixed_mode != NULL) {
1579                         struct drm_display_mode *mode;
1580                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1581                         drm_mode_probed_add(connector, mode);
1582                         return 1;
1583                 }
1584         }
1585         return 0;
1586 }
1587
1588 static int
1589 intel_dp_set_property(struct drm_connector *connector,
1590                       struct drm_property *property,
1591                       uint64_t val)
1592 {
1593         struct intel_dp *intel_dp = intel_attached_dp(connector);
1594         int ret;
1595
1596         ret = drm_connector_property_set_value(connector, property, val);
1597         if (ret)
1598                 return ret;
1599
1600         if (property == intel_dp->force_audio_property) {
1601                 if (val == intel_dp->force_audio)
1602                         return 0;
1603
1604                 intel_dp->force_audio = val;
1605
1606                 if (val > 0 && intel_dp->has_audio)
1607                         return 0;
1608                 if (val < 0 && !intel_dp->has_audio)
1609                         return 0;
1610
1611                 intel_dp->has_audio = val > 0;
1612                 goto done;
1613         }
1614
1615         return -EINVAL;
1616
1617 done:
1618         if (intel_dp->base.base.crtc) {
1619                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1620                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1621                                          crtc->x, crtc->y,
1622                                          crtc->fb);
1623         }
1624
1625         return 0;
1626 }
1627
1628 static void
1629 intel_dp_destroy (struct drm_connector *connector)
1630 {
1631         drm_sysfs_connector_remove(connector);
1632         drm_connector_cleanup(connector);
1633         kfree(connector);
1634 }
1635
1636 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1637 {
1638         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1639
1640         i2c_del_adapter(&intel_dp->adapter);
1641         drm_encoder_cleanup(encoder);
1642         kfree(intel_dp);
1643 }
1644
1645 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1646         .dpms = intel_dp_dpms,
1647         .mode_fixup = intel_dp_mode_fixup,
1648         .prepare = intel_dp_prepare,
1649         .mode_set = intel_dp_mode_set,
1650         .commit = intel_dp_commit,
1651 };
1652
1653 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1654         .dpms = drm_helper_connector_dpms,
1655         .detect = intel_dp_detect,
1656         .fill_modes = drm_helper_probe_single_connector_modes,
1657         .set_property = intel_dp_set_property,
1658         .destroy = intel_dp_destroy,
1659 };
1660
1661 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1662         .get_modes = intel_dp_get_modes,
1663         .mode_valid = intel_dp_mode_valid,
1664         .best_encoder = intel_best_encoder,
1665 };
1666
1667 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1668         .destroy = intel_dp_encoder_destroy,
1669 };
1670
1671 static void
1672 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1673 {
1674         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1675
1676         if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1677                 intel_dp_check_link_status(intel_dp);
1678 }
1679
1680 /* Return which DP Port should be selected for Transcoder DP control */
1681 int
1682 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1683 {
1684         struct drm_device *dev = crtc->dev;
1685         struct drm_mode_config *mode_config = &dev->mode_config;
1686         struct drm_encoder *encoder;
1687
1688         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1689                 struct intel_dp *intel_dp;
1690
1691                 if (encoder->crtc != crtc)
1692                         continue;
1693
1694                 intel_dp = enc_to_intel_dp(encoder);
1695                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1696                         return intel_dp->output_reg;
1697         }
1698
1699         return -1;
1700 }
1701
1702 /* check the VBT to see whether the eDP is on DP-D port */
1703 bool intel_dpd_is_edp(struct drm_device *dev)
1704 {
1705         struct drm_i915_private *dev_priv = dev->dev_private;
1706         struct child_device_config *p_child;
1707         int i;
1708
1709         if (!dev_priv->child_dev_num)
1710                 return false;
1711
1712         for (i = 0; i < dev_priv->child_dev_num; i++) {
1713                 p_child = dev_priv->child_dev + i;
1714
1715                 if (p_child->dvo_port == PORT_IDPD &&
1716                     p_child->device_type == DEVICE_TYPE_eDP)
1717                         return true;
1718         }
1719         return false;
1720 }
1721
1722 static void
1723 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1724 {
1725         struct drm_device *dev = connector->dev;
1726
1727         intel_dp->force_audio_property =
1728                 drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2);
1729         if (intel_dp->force_audio_property) {
1730                 intel_dp->force_audio_property->values[0] = -1;
1731                 intel_dp->force_audio_property->values[1] = 1;
1732                 drm_connector_attach_property(connector, intel_dp->force_audio_property, 0);
1733         }
1734 }
1735
1736 void
1737 intel_dp_init(struct drm_device *dev, int output_reg)
1738 {
1739         struct drm_i915_private *dev_priv = dev->dev_private;
1740         struct drm_connector *connector;
1741         struct intel_dp *intel_dp;
1742         struct intel_encoder *intel_encoder;
1743         struct intel_connector *intel_connector;
1744         const char *name = NULL;
1745         int type;
1746
1747         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1748         if (!intel_dp)
1749                 return;
1750
1751         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1752         if (!intel_connector) {
1753                 kfree(intel_dp);
1754                 return;
1755         }
1756         intel_encoder = &intel_dp->base;
1757
1758         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1759                 if (intel_dpd_is_edp(dev))
1760                         intel_dp->is_pch_edp = true;
1761
1762         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1763                 type = DRM_MODE_CONNECTOR_eDP;
1764                 intel_encoder->type = INTEL_OUTPUT_EDP;
1765         } else {
1766                 type = DRM_MODE_CONNECTOR_DisplayPort;
1767                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1768         }
1769
1770         connector = &intel_connector->base;
1771         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1772         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1773
1774         connector->polled = DRM_CONNECTOR_POLL_HPD;
1775
1776         if (output_reg == DP_B || output_reg == PCH_DP_B)
1777                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1778         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1779                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1780         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1781                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1782
1783         if (is_edp(intel_dp))
1784                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1785
1786         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1787         connector->interlace_allowed = true;
1788         connector->doublescan_allowed = 0;
1789
1790         intel_dp->output_reg = output_reg;
1791         intel_dp->has_audio = false;
1792         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1793
1794         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1795                          DRM_MODE_ENCODER_TMDS);
1796         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1797
1798         intel_connector_attach_encoder(intel_connector, intel_encoder);
1799         drm_sysfs_connector_add(connector);
1800
1801         /* Set up the DDC bus. */
1802         switch (output_reg) {
1803                 case DP_A:
1804                         name = "DPDDC-A";
1805                         break;
1806                 case DP_B:
1807                 case PCH_DP_B:
1808                         dev_priv->hotplug_supported_mask |=
1809                                 HDMIB_HOTPLUG_INT_STATUS;
1810                         name = "DPDDC-B";
1811                         break;
1812                 case DP_C:
1813                 case PCH_DP_C:
1814                         dev_priv->hotplug_supported_mask |=
1815                                 HDMIC_HOTPLUG_INT_STATUS;
1816                         name = "DPDDC-C";
1817                         break;
1818                 case DP_D:
1819                 case PCH_DP_D:
1820                         dev_priv->hotplug_supported_mask |=
1821                                 HDMID_HOTPLUG_INT_STATUS;
1822                         name = "DPDDC-D";
1823                         break;
1824         }
1825
1826         intel_dp_i2c_init(intel_dp, intel_connector, name);
1827
1828         /* Cache some DPCD data in the eDP case */
1829         if (is_edp(intel_dp)) {
1830                 int ret;
1831                 bool was_on;
1832
1833                 was_on = ironlake_edp_panel_on(intel_dp);
1834                 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1835                                                intel_dp->dpcd,
1836                                                sizeof(intel_dp->dpcd));
1837                 if (ret == sizeof(intel_dp->dpcd)) {
1838                         if (intel_dp->dpcd[0] >= 0x11)
1839                                 dev_priv->no_aux_handshake = intel_dp->dpcd[3] &
1840                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1841                 } else {
1842                         DRM_ERROR("failed to retrieve link info\n");
1843                 }
1844                 if (!was_on)
1845                         ironlake_edp_panel_off(dev);
1846         }
1847
1848         intel_encoder->hot_plug = intel_dp_hot_plug;
1849
1850         if (is_edp(intel_dp)) {
1851                 /* initialize panel mode from VBT if available for eDP */
1852                 if (dev_priv->lfp_lvds_vbt_mode) {
1853                         dev_priv->panel_fixed_mode =
1854                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1855                         if (dev_priv->panel_fixed_mode) {
1856                                 dev_priv->panel_fixed_mode->type |=
1857                                         DRM_MODE_TYPE_PREFERRED;
1858                         }
1859                 }
1860         }
1861
1862         intel_dp_add_properties(intel_dp, connector);
1863
1864         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1865          * 0xd.  Failure to do so will result in spurious interrupts being
1866          * generated on the port when a cable is not attached.
1867          */
1868         if (IS_G4X(dev) && !IS_GM45(dev)) {
1869                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1870                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1871         }
1872 }