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[~shefty/rdma-dev.git] / drivers / gpu / drm / nouveau / core / subdev / device / nve0.c
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24
25 #include <subdev/device.h>
26 #include <subdev/bios.h>
27 #include <subdev/gpio.h>
28 #include <subdev/i2c.h>
29 #include <subdev/clock.h>
30 #include <subdev/therm.h>
31 #include <subdev/mxm.h>
32 #include <subdev/devinit.h>
33 #include <subdev/mc.h>
34 #include <subdev/timer.h>
35 #include <subdev/fb.h>
36 #include <subdev/ltcg.h>
37 #include <subdev/ibus.h>
38 #include <subdev/instmem.h>
39 #include <subdev/vm.h>
40 #include <subdev/bar.h>
41
42 #include <engine/dmaobj.h>
43 #include <engine/fifo.h>
44 #include <engine/software.h>
45 #include <engine/graph.h>
46 #include <engine/disp.h>
47 #include <engine/copy.h>
48 #include <engine/bsp.h>
49 #include <engine/vp.h>
50 #include <engine/ppp.h>
51
52 int
53 nve0_identify(struct nouveau_device *device)
54 {
55         switch (device->chipset) {
56         case 0xe4:
57                 device->cname = "GK104";
58                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
59                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
60                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
61                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
62                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
63                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
64                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
65                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
66                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
67                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
68                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
69                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
70                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
71                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
72                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
73                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
74                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
75                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
76                 device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
77                 device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
78                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
79                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
80                 device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
81                 device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
82                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
83                 break;
84         case 0xe7:
85                 device->cname = "GK107";
86                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
87                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
88                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
89                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
90                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
91                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
92                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
93                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
94                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
95                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
96                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
97                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
98                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
99                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
100                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
101                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
102                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
103                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
104                 device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
105                 device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
106                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
107                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
108                 device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
109                 device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
110                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
111                 break;
112         default:
113                 nv_fatal(device, "unknown Kepler chipset\n");
114                 return -EINVAL;
115         }
116
117         return 0;
118 }