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[~shefty/rdma-dev.git] / drivers / gpu / drm / nouveau / nouveau_state.c
1 /*
2  * Copyright 2005 Stephane Marchesin
3  * Copyright 2008 Stuart Bennett
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_gpio.h"
40 #include "nouveau_pm.h"
41 #include "nv50_display.h"
42
43 static void nouveau_stub_takedown(struct drm_device *dev) {}
44 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
45
46 static int nouveau_init_engine_ptrs(struct drm_device *dev)
47 {
48         struct drm_nouveau_private *dev_priv = dev->dev_private;
49         struct nouveau_engine *engine = &dev_priv->engine;
50
51         switch (dev_priv->chipset & 0xf0) {
52         case 0x00:
53                 engine->instmem.init            = nv04_instmem_init;
54                 engine->instmem.takedown        = nv04_instmem_takedown;
55                 engine->instmem.suspend         = nv04_instmem_suspend;
56                 engine->instmem.resume          = nv04_instmem_resume;
57                 engine->instmem.get             = nv04_instmem_get;
58                 engine->instmem.put             = nv04_instmem_put;
59                 engine->instmem.map             = nv04_instmem_map;
60                 engine->instmem.unmap           = nv04_instmem_unmap;
61                 engine->instmem.flush           = nv04_instmem_flush;
62                 engine->mc.init                 = nv04_mc_init;
63                 engine->mc.takedown             = nv04_mc_takedown;
64                 engine->timer.init              = nv04_timer_init;
65                 engine->timer.read              = nv04_timer_read;
66                 engine->timer.takedown          = nv04_timer_takedown;
67                 engine->fb.init                 = nv04_fb_init;
68                 engine->fb.takedown             = nv04_fb_takedown;
69                 engine->fifo.channels           = 16;
70                 engine->fifo.init               = nv04_fifo_init;
71                 engine->fifo.takedown           = nv04_fifo_fini;
72                 engine->fifo.disable            = nv04_fifo_disable;
73                 engine->fifo.enable             = nv04_fifo_enable;
74                 engine->fifo.reassign           = nv04_fifo_reassign;
75                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
76                 engine->fifo.channel_id         = nv04_fifo_channel_id;
77                 engine->fifo.create_context     = nv04_fifo_create_context;
78                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
79                 engine->fifo.load_context       = nv04_fifo_load_context;
80                 engine->fifo.unload_context     = nv04_fifo_unload_context;
81                 engine->display.early_init      = nv04_display_early_init;
82                 engine->display.late_takedown   = nv04_display_late_takedown;
83                 engine->display.create          = nv04_display_create;
84                 engine->display.destroy         = nv04_display_destroy;
85                 engine->display.init            = nv04_display_init;
86                 engine->display.fini            = nv04_display_fini;
87                 engine->pm.clocks_get           = nv04_pm_clocks_get;
88                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
89                 engine->pm.clocks_set           = nv04_pm_clocks_set;
90                 engine->vram.init               = nv04_fb_vram_init;
91                 engine->vram.takedown           = nouveau_stub_takedown;
92                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
93                 break;
94         case 0x10:
95                 engine->instmem.init            = nv04_instmem_init;
96                 engine->instmem.takedown        = nv04_instmem_takedown;
97                 engine->instmem.suspend         = nv04_instmem_suspend;
98                 engine->instmem.resume          = nv04_instmem_resume;
99                 engine->instmem.get             = nv04_instmem_get;
100                 engine->instmem.put             = nv04_instmem_put;
101                 engine->instmem.map             = nv04_instmem_map;
102                 engine->instmem.unmap           = nv04_instmem_unmap;
103                 engine->instmem.flush           = nv04_instmem_flush;
104                 engine->mc.init                 = nv04_mc_init;
105                 engine->mc.takedown             = nv04_mc_takedown;
106                 engine->timer.init              = nv04_timer_init;
107                 engine->timer.read              = nv04_timer_read;
108                 engine->timer.takedown          = nv04_timer_takedown;
109                 engine->fb.init                 = nv10_fb_init;
110                 engine->fb.takedown             = nv10_fb_takedown;
111                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
112                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
113                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
114                 engine->fifo.channels           = 32;
115                 engine->fifo.init               = nv10_fifo_init;
116                 engine->fifo.takedown           = nv04_fifo_fini;
117                 engine->fifo.disable            = nv04_fifo_disable;
118                 engine->fifo.enable             = nv04_fifo_enable;
119                 engine->fifo.reassign           = nv04_fifo_reassign;
120                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
121                 engine->fifo.channel_id         = nv10_fifo_channel_id;
122                 engine->fifo.create_context     = nv10_fifo_create_context;
123                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
124                 engine->fifo.load_context       = nv10_fifo_load_context;
125                 engine->fifo.unload_context     = nv10_fifo_unload_context;
126                 engine->display.early_init      = nv04_display_early_init;
127                 engine->display.late_takedown   = nv04_display_late_takedown;
128                 engine->display.create          = nv04_display_create;
129                 engine->display.destroy         = nv04_display_destroy;
130                 engine->display.init            = nv04_display_init;
131                 engine->display.fini            = nv04_display_fini;
132                 engine->gpio.drive              = nv10_gpio_drive;
133                 engine->gpio.sense              = nv10_gpio_sense;
134                 engine->pm.clocks_get           = nv04_pm_clocks_get;
135                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
136                 engine->pm.clocks_set           = nv04_pm_clocks_set;
137                 if (dev_priv->chipset == 0x1a ||
138                     dev_priv->chipset == 0x1f)
139                         engine->vram.init       = nv1a_fb_vram_init;
140                 else
141                         engine->vram.init       = nv10_fb_vram_init;
142                 engine->vram.takedown           = nouveau_stub_takedown;
143                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
144                 break;
145         case 0x20:
146                 engine->instmem.init            = nv04_instmem_init;
147                 engine->instmem.takedown        = nv04_instmem_takedown;
148                 engine->instmem.suspend         = nv04_instmem_suspend;
149                 engine->instmem.resume          = nv04_instmem_resume;
150                 engine->instmem.get             = nv04_instmem_get;
151                 engine->instmem.put             = nv04_instmem_put;
152                 engine->instmem.map             = nv04_instmem_map;
153                 engine->instmem.unmap           = nv04_instmem_unmap;
154                 engine->instmem.flush           = nv04_instmem_flush;
155                 engine->mc.init                 = nv04_mc_init;
156                 engine->mc.takedown             = nv04_mc_takedown;
157                 engine->timer.init              = nv04_timer_init;
158                 engine->timer.read              = nv04_timer_read;
159                 engine->timer.takedown          = nv04_timer_takedown;
160                 engine->fb.init                 = nv20_fb_init;
161                 engine->fb.takedown             = nv20_fb_takedown;
162                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
163                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
164                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
165                 engine->fifo.channels           = 32;
166                 engine->fifo.init               = nv10_fifo_init;
167                 engine->fifo.takedown           = nv04_fifo_fini;
168                 engine->fifo.disable            = nv04_fifo_disable;
169                 engine->fifo.enable             = nv04_fifo_enable;
170                 engine->fifo.reassign           = nv04_fifo_reassign;
171                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
172                 engine->fifo.channel_id         = nv10_fifo_channel_id;
173                 engine->fifo.create_context     = nv10_fifo_create_context;
174                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
175                 engine->fifo.load_context       = nv10_fifo_load_context;
176                 engine->fifo.unload_context     = nv10_fifo_unload_context;
177                 engine->display.early_init      = nv04_display_early_init;
178                 engine->display.late_takedown   = nv04_display_late_takedown;
179                 engine->display.create          = nv04_display_create;
180                 engine->display.destroy         = nv04_display_destroy;
181                 engine->display.init            = nv04_display_init;
182                 engine->display.fini            = nv04_display_fini;
183                 engine->gpio.drive              = nv10_gpio_drive;
184                 engine->gpio.sense              = nv10_gpio_sense;
185                 engine->pm.clocks_get           = nv04_pm_clocks_get;
186                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
187                 engine->pm.clocks_set           = nv04_pm_clocks_set;
188                 engine->vram.init               = nv20_fb_vram_init;
189                 engine->vram.takedown           = nouveau_stub_takedown;
190                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
191                 break;
192         case 0x30:
193                 engine->instmem.init            = nv04_instmem_init;
194                 engine->instmem.takedown        = nv04_instmem_takedown;
195                 engine->instmem.suspend         = nv04_instmem_suspend;
196                 engine->instmem.resume          = nv04_instmem_resume;
197                 engine->instmem.get             = nv04_instmem_get;
198                 engine->instmem.put             = nv04_instmem_put;
199                 engine->instmem.map             = nv04_instmem_map;
200                 engine->instmem.unmap           = nv04_instmem_unmap;
201                 engine->instmem.flush           = nv04_instmem_flush;
202                 engine->mc.init                 = nv04_mc_init;
203                 engine->mc.takedown             = nv04_mc_takedown;
204                 engine->timer.init              = nv04_timer_init;
205                 engine->timer.read              = nv04_timer_read;
206                 engine->timer.takedown          = nv04_timer_takedown;
207                 engine->fb.init                 = nv30_fb_init;
208                 engine->fb.takedown             = nv30_fb_takedown;
209                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
210                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
211                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
212                 engine->fifo.channels           = 32;
213                 engine->fifo.init               = nv10_fifo_init;
214                 engine->fifo.takedown           = nv04_fifo_fini;
215                 engine->fifo.disable            = nv04_fifo_disable;
216                 engine->fifo.enable             = nv04_fifo_enable;
217                 engine->fifo.reassign           = nv04_fifo_reassign;
218                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
219                 engine->fifo.channel_id         = nv10_fifo_channel_id;
220                 engine->fifo.create_context     = nv10_fifo_create_context;
221                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
222                 engine->fifo.load_context       = nv10_fifo_load_context;
223                 engine->fifo.unload_context     = nv10_fifo_unload_context;
224                 engine->display.early_init      = nv04_display_early_init;
225                 engine->display.late_takedown   = nv04_display_late_takedown;
226                 engine->display.create          = nv04_display_create;
227                 engine->display.destroy         = nv04_display_destroy;
228                 engine->display.init            = nv04_display_init;
229                 engine->display.fini            = nv04_display_fini;
230                 engine->gpio.drive              = nv10_gpio_drive;
231                 engine->gpio.sense              = nv10_gpio_sense;
232                 engine->pm.clocks_get           = nv04_pm_clocks_get;
233                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
234                 engine->pm.clocks_set           = nv04_pm_clocks_set;
235                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
236                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
237                 engine->vram.init               = nv20_fb_vram_init;
238                 engine->vram.takedown           = nouveau_stub_takedown;
239                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
240                 break;
241         case 0x40:
242         case 0x60:
243                 engine->instmem.init            = nv04_instmem_init;
244                 engine->instmem.takedown        = nv04_instmem_takedown;
245                 engine->instmem.suspend         = nv04_instmem_suspend;
246                 engine->instmem.resume          = nv04_instmem_resume;
247                 engine->instmem.get             = nv04_instmem_get;
248                 engine->instmem.put             = nv04_instmem_put;
249                 engine->instmem.map             = nv04_instmem_map;
250                 engine->instmem.unmap           = nv04_instmem_unmap;
251                 engine->instmem.flush           = nv04_instmem_flush;
252                 engine->mc.init                 = nv40_mc_init;
253                 engine->mc.takedown             = nv40_mc_takedown;
254                 engine->timer.init              = nv04_timer_init;
255                 engine->timer.read              = nv04_timer_read;
256                 engine->timer.takedown          = nv04_timer_takedown;
257                 engine->fb.init                 = nv40_fb_init;
258                 engine->fb.takedown             = nv40_fb_takedown;
259                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
260                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
261                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
262                 engine->fifo.channels           = 32;
263                 engine->fifo.init               = nv40_fifo_init;
264                 engine->fifo.takedown           = nv04_fifo_fini;
265                 engine->fifo.disable            = nv04_fifo_disable;
266                 engine->fifo.enable             = nv04_fifo_enable;
267                 engine->fifo.reassign           = nv04_fifo_reassign;
268                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
269                 engine->fifo.channel_id         = nv10_fifo_channel_id;
270                 engine->fifo.create_context     = nv40_fifo_create_context;
271                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
272                 engine->fifo.load_context       = nv40_fifo_load_context;
273                 engine->fifo.unload_context     = nv40_fifo_unload_context;
274                 engine->display.early_init      = nv04_display_early_init;
275                 engine->display.late_takedown   = nv04_display_late_takedown;
276                 engine->display.create          = nv04_display_create;
277                 engine->display.destroy         = nv04_display_destroy;
278                 engine->display.init            = nv04_display_init;
279                 engine->display.fini            = nv04_display_fini;
280                 engine->gpio.init               = nv10_gpio_init;
281                 engine->gpio.fini               = nv10_gpio_fini;
282                 engine->gpio.drive              = nv10_gpio_drive;
283                 engine->gpio.sense              = nv10_gpio_sense;
284                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
285                 engine->pm.clocks_get           = nv40_pm_clocks_get;
286                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
287                 engine->pm.clocks_set           = nv40_pm_clocks_set;
288                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
289                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
290                 engine->pm.temp_get             = nv40_temp_get;
291                 engine->pm.pwm_get              = nv40_pm_pwm_get;
292                 engine->pm.pwm_set              = nv40_pm_pwm_set;
293                 engine->vram.init               = nv40_fb_vram_init;
294                 engine->vram.takedown           = nouveau_stub_takedown;
295                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
296                 break;
297         case 0x50:
298         case 0x80: /* gotta love NVIDIA's consistency.. */
299         case 0x90:
300         case 0xa0:
301                 engine->instmem.init            = nv50_instmem_init;
302                 engine->instmem.takedown        = nv50_instmem_takedown;
303                 engine->instmem.suspend         = nv50_instmem_suspend;
304                 engine->instmem.resume          = nv50_instmem_resume;
305                 engine->instmem.get             = nv50_instmem_get;
306                 engine->instmem.put             = nv50_instmem_put;
307                 engine->instmem.map             = nv50_instmem_map;
308                 engine->instmem.unmap           = nv50_instmem_unmap;
309                 if (dev_priv->chipset == 0x50)
310                         engine->instmem.flush   = nv50_instmem_flush;
311                 else
312                         engine->instmem.flush   = nv84_instmem_flush;
313                 engine->mc.init                 = nv50_mc_init;
314                 engine->mc.takedown             = nv50_mc_takedown;
315                 engine->timer.init              = nv04_timer_init;
316                 engine->timer.read              = nv04_timer_read;
317                 engine->timer.takedown          = nv04_timer_takedown;
318                 engine->fb.init                 = nv50_fb_init;
319                 engine->fb.takedown             = nv50_fb_takedown;
320                 engine->fifo.channels           = 128;
321                 engine->fifo.init               = nv50_fifo_init;
322                 engine->fifo.takedown           = nv50_fifo_takedown;
323                 engine->fifo.disable            = nv04_fifo_disable;
324                 engine->fifo.enable             = nv04_fifo_enable;
325                 engine->fifo.reassign           = nv04_fifo_reassign;
326                 engine->fifo.channel_id         = nv50_fifo_channel_id;
327                 engine->fifo.create_context     = nv50_fifo_create_context;
328                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
329                 engine->fifo.load_context       = nv50_fifo_load_context;
330                 engine->fifo.unload_context     = nv50_fifo_unload_context;
331                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
332                 engine->display.early_init      = nv50_display_early_init;
333                 engine->display.late_takedown   = nv50_display_late_takedown;
334                 engine->display.create          = nv50_display_create;
335                 engine->display.destroy         = nv50_display_destroy;
336                 engine->display.init            = nv50_display_init;
337                 engine->display.fini            = nv50_display_fini;
338                 engine->gpio.init               = nv50_gpio_init;
339                 engine->gpio.fini               = nv50_gpio_fini;
340                 engine->gpio.drive              = nv50_gpio_drive;
341                 engine->gpio.sense              = nv50_gpio_sense;
342                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
343                 switch (dev_priv->chipset) {
344                 case 0x84:
345                 case 0x86:
346                 case 0x92:
347                 case 0x94:
348                 case 0x96:
349                 case 0x98:
350                 case 0xa0:
351                 case 0xaa:
352                 case 0xac:
353                 case 0x50:
354                         engine->pm.clocks_get   = nv50_pm_clocks_get;
355                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
356                         engine->pm.clocks_set   = nv50_pm_clocks_set;
357                         break;
358                 default:
359                         engine->pm.clocks_get   = nva3_pm_clocks_get;
360                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
361                         engine->pm.clocks_set   = nva3_pm_clocks_set;
362                         break;
363                 }
364                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
365                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
366                 if (dev_priv->chipset >= 0x84)
367                         engine->pm.temp_get     = nv84_temp_get;
368                 else
369                         engine->pm.temp_get     = nv40_temp_get;
370                 engine->pm.pwm_get              = nv50_pm_pwm_get;
371                 engine->pm.pwm_set              = nv50_pm_pwm_set;
372                 engine->vram.init               = nv50_vram_init;
373                 engine->vram.takedown           = nv50_vram_fini;
374                 engine->vram.get                = nv50_vram_new;
375                 engine->vram.put                = nv50_vram_del;
376                 engine->vram.flags_valid        = nv50_vram_flags_valid;
377                 break;
378         case 0xc0:
379                 engine->instmem.init            = nvc0_instmem_init;
380                 engine->instmem.takedown        = nvc0_instmem_takedown;
381                 engine->instmem.suspend         = nvc0_instmem_suspend;
382                 engine->instmem.resume          = nvc0_instmem_resume;
383                 engine->instmem.get             = nv50_instmem_get;
384                 engine->instmem.put             = nv50_instmem_put;
385                 engine->instmem.map             = nv50_instmem_map;
386                 engine->instmem.unmap           = nv50_instmem_unmap;
387                 engine->instmem.flush           = nv84_instmem_flush;
388                 engine->mc.init                 = nv50_mc_init;
389                 engine->mc.takedown             = nv50_mc_takedown;
390                 engine->timer.init              = nv04_timer_init;
391                 engine->timer.read              = nv04_timer_read;
392                 engine->timer.takedown          = nv04_timer_takedown;
393                 engine->fb.init                 = nvc0_fb_init;
394                 engine->fb.takedown             = nvc0_fb_takedown;
395                 engine->fifo.channels           = 128;
396                 engine->fifo.init               = nvc0_fifo_init;
397                 engine->fifo.takedown           = nvc0_fifo_takedown;
398                 engine->fifo.disable            = nvc0_fifo_disable;
399                 engine->fifo.enable             = nvc0_fifo_enable;
400                 engine->fifo.reassign           = nvc0_fifo_reassign;
401                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
402                 engine->fifo.create_context     = nvc0_fifo_create_context;
403                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
404                 engine->fifo.load_context       = nvc0_fifo_load_context;
405                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
406                 engine->display.early_init      = nv50_display_early_init;
407                 engine->display.late_takedown   = nv50_display_late_takedown;
408                 engine->display.create          = nv50_display_create;
409                 engine->display.destroy         = nv50_display_destroy;
410                 engine->display.init            = nv50_display_init;
411                 engine->display.fini            = nv50_display_fini;
412                 engine->gpio.init               = nv50_gpio_init;
413                 engine->gpio.fini               = nv50_gpio_fini;
414                 engine->gpio.drive              = nv50_gpio_drive;
415                 engine->gpio.sense              = nv50_gpio_sense;
416                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
417                 engine->vram.init               = nvc0_vram_init;
418                 engine->vram.takedown           = nv50_vram_fini;
419                 engine->vram.get                = nvc0_vram_new;
420                 engine->vram.put                = nv50_vram_del;
421                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
422                 engine->pm.temp_get             = nv84_temp_get;
423                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
424                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
425                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
426                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
427                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
428                 engine->pm.pwm_get              = nv50_pm_pwm_get;
429                 engine->pm.pwm_set              = nv50_pm_pwm_set;
430                 break;
431         case 0xd0:
432                 engine->instmem.init            = nvc0_instmem_init;
433                 engine->instmem.takedown        = nvc0_instmem_takedown;
434                 engine->instmem.suspend         = nvc0_instmem_suspend;
435                 engine->instmem.resume          = nvc0_instmem_resume;
436                 engine->instmem.get             = nv50_instmem_get;
437                 engine->instmem.put             = nv50_instmem_put;
438                 engine->instmem.map             = nv50_instmem_map;
439                 engine->instmem.unmap           = nv50_instmem_unmap;
440                 engine->instmem.flush           = nv84_instmem_flush;
441                 engine->mc.init                 = nv50_mc_init;
442                 engine->mc.takedown             = nv50_mc_takedown;
443                 engine->timer.init              = nv04_timer_init;
444                 engine->timer.read              = nv04_timer_read;
445                 engine->timer.takedown          = nv04_timer_takedown;
446                 engine->fb.init                 = nvc0_fb_init;
447                 engine->fb.takedown             = nvc0_fb_takedown;
448                 engine->fifo.channels           = 128;
449                 engine->fifo.init               = nvc0_fifo_init;
450                 engine->fifo.takedown           = nvc0_fifo_takedown;
451                 engine->fifo.disable            = nvc0_fifo_disable;
452                 engine->fifo.enable             = nvc0_fifo_enable;
453                 engine->fifo.reassign           = nvc0_fifo_reassign;
454                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
455                 engine->fifo.create_context     = nvc0_fifo_create_context;
456                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
457                 engine->fifo.load_context       = nvc0_fifo_load_context;
458                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
459                 engine->display.early_init      = nouveau_stub_init;
460                 engine->display.late_takedown   = nouveau_stub_takedown;
461                 engine->display.create          = nvd0_display_create;
462                 engine->display.destroy         = nvd0_display_destroy;
463                 engine->display.init            = nvd0_display_init;
464                 engine->display.fini            = nvd0_display_fini;
465                 engine->gpio.init               = nv50_gpio_init;
466                 engine->gpio.fini               = nv50_gpio_fini;
467                 engine->gpio.drive              = nvd0_gpio_drive;
468                 engine->gpio.sense              = nvd0_gpio_sense;
469                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
470                 engine->vram.init               = nvc0_vram_init;
471                 engine->vram.takedown           = nv50_vram_fini;
472                 engine->vram.get                = nvc0_vram_new;
473                 engine->vram.put                = nv50_vram_del;
474                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
475                 engine->pm.temp_get             = nv84_temp_get;
476                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
477                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
478                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
479                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
480                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
481                 break;
482         default:
483                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
484                 return 1;
485         }
486
487         /* headless mode */
488         if (nouveau_modeset == 2) {
489                 engine->display.early_init = nouveau_stub_init;
490                 engine->display.late_takedown = nouveau_stub_takedown;
491                 engine->display.create = nouveau_stub_init;
492                 engine->display.init = nouveau_stub_init;
493                 engine->display.destroy = nouveau_stub_takedown;
494         }
495
496         return 0;
497 }
498
499 static unsigned int
500 nouveau_vga_set_decode(void *priv, bool state)
501 {
502         struct drm_device *dev = priv;
503         struct drm_nouveau_private *dev_priv = dev->dev_private;
504
505         if (dev_priv->chipset >= 0x40)
506                 nv_wr32(dev, 0x88054, state);
507         else
508                 nv_wr32(dev, 0x1854, state);
509
510         if (state)
511                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
512                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
513         else
514                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
515 }
516
517 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
518                                          enum vga_switcheroo_state state)
519 {
520         struct drm_device *dev = pci_get_drvdata(pdev);
521         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
522         if (state == VGA_SWITCHEROO_ON) {
523                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
524                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
525                 nouveau_pci_resume(pdev);
526                 drm_kms_helper_poll_enable(dev);
527                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
528         } else {
529                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
530                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
531                 drm_kms_helper_poll_disable(dev);
532                 nouveau_switcheroo_optimus_dsm();
533                 nouveau_pci_suspend(pdev, pmm);
534                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
535         }
536 }
537
538 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
539 {
540         struct drm_device *dev = pci_get_drvdata(pdev);
541         nouveau_fbcon_output_poll_changed(dev);
542 }
543
544 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
545 {
546         struct drm_device *dev = pci_get_drvdata(pdev);
547         bool can_switch;
548
549         spin_lock(&dev->count_lock);
550         can_switch = (dev->open_count == 0);
551         spin_unlock(&dev->count_lock);
552         return can_switch;
553 }
554
555 static void
556 nouveau_card_channel_fini(struct drm_device *dev)
557 {
558         struct drm_nouveau_private *dev_priv = dev->dev_private;
559
560         if (dev_priv->channel)
561                 nouveau_channel_put_unlocked(&dev_priv->channel);
562 }
563
564 static int
565 nouveau_card_channel_init(struct drm_device *dev)
566 {
567         struct drm_nouveau_private *dev_priv = dev->dev_private;
568         struct nouveau_channel *chan;
569         int ret, oclass;
570
571         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
572         dev_priv->channel = chan;
573         if (ret)
574                 return ret;
575
576         mutex_unlock(&dev_priv->channel->mutex);
577
578         if (dev_priv->card_type <= NV_50) {
579                 if (dev_priv->card_type < NV_50)
580                         oclass = 0x0039;
581                 else
582                         oclass = 0x5039;
583
584                 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, oclass);
585                 if (ret)
586                         goto error;
587
588                 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
589                                              &chan->m2mf_ntfy);
590                 if (ret)
591                         goto error;
592
593                 ret = RING_SPACE(chan, 6);
594                 if (ret)
595                         goto error;
596
597                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
598                 OUT_RING  (chan, NvM2MF);
599                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
600                 OUT_RING  (chan, NvNotify0);
601                 OUT_RING  (chan, chan->vram_handle);
602                 OUT_RING  (chan, chan->gart_handle);
603         } else
604         if (dev_priv->card_type <= NV_C0) {
605                 ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
606                 if (ret)
607                         goto error;
608
609                 ret = RING_SPACE(chan, 2);
610                 if (ret)
611                         goto error;
612
613                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0000, 1);
614                 OUT_RING  (chan, 0x00009039);
615         }
616
617         FIRE_RING (chan);
618 error:
619         if (ret)
620                 nouveau_card_channel_fini(dev);
621         return ret;
622 }
623
624 int
625 nouveau_card_init(struct drm_device *dev)
626 {
627         struct drm_nouveau_private *dev_priv = dev->dev_private;
628         struct nouveau_engine *engine;
629         int ret, e = 0;
630
631         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
632         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
633                                        nouveau_switcheroo_reprobe,
634                                        nouveau_switcheroo_can_switch);
635
636         /* Initialise internal driver API hooks */
637         ret = nouveau_init_engine_ptrs(dev);
638         if (ret)
639                 goto out;
640         engine = &dev_priv->engine;
641         spin_lock_init(&dev_priv->channels.lock);
642         spin_lock_init(&dev_priv->tile.lock);
643         spin_lock_init(&dev_priv->context_switch_lock);
644         spin_lock_init(&dev_priv->vm_lock);
645
646         /* Make the CRTCs and I2C buses accessible */
647         ret = engine->display.early_init(dev);
648         if (ret)
649                 goto out;
650
651         /* Parse BIOS tables / Run init tables if card not POSTed */
652         ret = nouveau_bios_init(dev);
653         if (ret)
654                 goto out_display_early;
655
656         /* workaround an odd issue on nvc1 by disabling the device's
657          * nosnoop capability.  hopefully won't cause issues until a
658          * better fix is found - assuming there is one...
659          */
660         if (dev_priv->chipset == 0xc1) {
661                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
662         }
663
664         /* PMC */
665         ret = engine->mc.init(dev);
666         if (ret)
667                 goto out_bios;
668
669         /* PTIMER */
670         ret = engine->timer.init(dev);
671         if (ret)
672                 goto out_mc;
673
674         /* PFB */
675         ret = engine->fb.init(dev);
676         if (ret)
677                 goto out_timer;
678
679         ret = engine->vram.init(dev);
680         if (ret)
681                 goto out_fb;
682
683         /* PGPIO */
684         ret = nouveau_gpio_create(dev);
685         if (ret)
686                 goto out_vram;
687
688         ret = nouveau_gpuobj_init(dev);
689         if (ret)
690                 goto out_gpio;
691
692         ret = engine->instmem.init(dev);
693         if (ret)
694                 goto out_gpuobj;
695
696         ret = nouveau_mem_vram_init(dev);
697         if (ret)
698                 goto out_instmem;
699
700         ret = nouveau_mem_gart_init(dev);
701         if (ret)
702                 goto out_ttmvram;
703
704         if (!dev_priv->noaccel) {
705                 switch (dev_priv->card_type) {
706                 case NV_04:
707                         nv04_graph_create(dev);
708                         break;
709                 case NV_10:
710                         nv10_graph_create(dev);
711                         break;
712                 case NV_20:
713                 case NV_30:
714                         nv20_graph_create(dev);
715                         break;
716                 case NV_40:
717                         nv40_graph_create(dev);
718                         break;
719                 case NV_50:
720                         nv50_graph_create(dev);
721                         break;
722                 case NV_C0:
723                 case NV_D0:
724                         nvc0_graph_create(dev);
725                         break;
726                 default:
727                         break;
728                 }
729
730                 switch (dev_priv->chipset) {
731                 case 0x84:
732                 case 0x86:
733                 case 0x92:
734                 case 0x94:
735                 case 0x96:
736                 case 0xa0:
737                         nv84_crypt_create(dev);
738                         break;
739                 case 0x98:
740                 case 0xaa:
741                 case 0xac:
742                         nv98_crypt_create(dev);
743                         break;
744                 }
745
746                 switch (dev_priv->card_type) {
747                 case NV_50:
748                         switch (dev_priv->chipset) {
749                         case 0xa3:
750                         case 0xa5:
751                         case 0xa8:
752                         case 0xaf:
753                                 nva3_copy_create(dev);
754                                 break;
755                         }
756                         break;
757                 case NV_C0:
758                         nvc0_copy_create(dev, 0);
759                         nvc0_copy_create(dev, 1);
760                         break;
761                 default:
762                         break;
763                 }
764
765                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
766                         nv84_bsp_create(dev);
767                         nv84_vp_create(dev);
768                         nv98_ppp_create(dev);
769                 } else
770                 if (dev_priv->chipset >= 0x84) {
771                         nv50_mpeg_create(dev);
772                         nv84_bsp_create(dev);
773                         nv84_vp_create(dev);
774                 } else
775                 if (dev_priv->chipset >= 0x50) {
776                         nv50_mpeg_create(dev);
777                 } else
778                 if (dev_priv->card_type == NV_40 ||
779                     dev_priv->chipset == 0x31 ||
780                     dev_priv->chipset == 0x34 ||
781                     dev_priv->chipset == 0x36) {
782                         nv31_mpeg_create(dev);
783                 }
784
785                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
786                         if (dev_priv->eng[e]) {
787                                 ret = dev_priv->eng[e]->init(dev, e);
788                                 if (ret)
789                                         goto out_engine;
790                         }
791                 }
792
793                 /* PFIFO */
794                 ret = engine->fifo.init(dev);
795                 if (ret)
796                         goto out_engine;
797         }
798
799         ret = nouveau_irq_init(dev);
800         if (ret)
801                 goto out_fifo;
802
803         ret = nouveau_display_create(dev);
804         if (ret)
805                 goto out_irq;
806
807         nouveau_backlight_init(dev);
808         nouveau_pm_init(dev);
809
810         ret = nouveau_fence_init(dev);
811         if (ret)
812                 goto out_pm;
813
814         if (!dev_priv->noaccel) {
815                 ret = nouveau_card_channel_init(dev);
816                 if (ret)
817                         goto out_fence;
818         }
819
820         if (dev->mode_config.num_crtc) {
821                 ret = nouveau_display_init(dev);
822                 if (ret)
823                         goto out_chan;
824
825                 nouveau_fbcon_init(dev);
826         }
827
828         return 0;
829
830 out_chan:
831         nouveau_card_channel_fini(dev);
832 out_fence:
833         nouveau_fence_fini(dev);
834 out_pm:
835         nouveau_pm_fini(dev);
836         nouveau_backlight_exit(dev);
837         nouveau_display_destroy(dev);
838 out_irq:
839         nouveau_irq_fini(dev);
840 out_fifo:
841         if (!dev_priv->noaccel)
842                 engine->fifo.takedown(dev);
843 out_engine:
844         if (!dev_priv->noaccel) {
845                 for (e = e - 1; e >= 0; e--) {
846                         if (!dev_priv->eng[e])
847                                 continue;
848                         dev_priv->eng[e]->fini(dev, e, false);
849                         dev_priv->eng[e]->destroy(dev,e );
850                 }
851         }
852         nouveau_mem_gart_fini(dev);
853 out_ttmvram:
854         nouveau_mem_vram_fini(dev);
855 out_instmem:
856         engine->instmem.takedown(dev);
857 out_gpuobj:
858         nouveau_gpuobj_takedown(dev);
859 out_gpio:
860         nouveau_gpio_destroy(dev);
861 out_vram:
862         engine->vram.takedown(dev);
863 out_fb:
864         engine->fb.takedown(dev);
865 out_timer:
866         engine->timer.takedown(dev);
867 out_mc:
868         engine->mc.takedown(dev);
869 out_bios:
870         nouveau_bios_takedown(dev);
871 out_display_early:
872         engine->display.late_takedown(dev);
873 out:
874         vga_client_register(dev->pdev, NULL, NULL, NULL);
875         return ret;
876 }
877
878 static void nouveau_card_takedown(struct drm_device *dev)
879 {
880         struct drm_nouveau_private *dev_priv = dev->dev_private;
881         struct nouveau_engine *engine = &dev_priv->engine;
882         int e;
883
884         if (dev->mode_config.num_crtc) {
885                 nouveau_fbcon_fini(dev);
886                 nouveau_display_fini(dev);
887         }
888
889         nouveau_card_channel_fini(dev);
890         nouveau_fence_fini(dev);
891         nouveau_pm_fini(dev);
892         nouveau_backlight_exit(dev);
893         nouveau_display_destroy(dev);
894
895         if (!dev_priv->noaccel) {
896                 engine->fifo.takedown(dev);
897                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
898                         if (dev_priv->eng[e]) {
899                                 dev_priv->eng[e]->fini(dev, e, false);
900                                 dev_priv->eng[e]->destroy(dev,e );
901                         }
902                 }
903         }
904
905         if (dev_priv->vga_ram) {
906                 nouveau_bo_unpin(dev_priv->vga_ram);
907                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
908         }
909
910         mutex_lock(&dev->struct_mutex);
911         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
912         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
913         mutex_unlock(&dev->struct_mutex);
914         nouveau_mem_gart_fini(dev);
915         nouveau_mem_vram_fini(dev);
916
917         engine->instmem.takedown(dev);
918         nouveau_gpuobj_takedown(dev);
919
920         nouveau_gpio_destroy(dev);
921         engine->vram.takedown(dev);
922         engine->fb.takedown(dev);
923         engine->timer.takedown(dev);
924         engine->mc.takedown(dev);
925
926         nouveau_bios_takedown(dev);
927         engine->display.late_takedown(dev);
928
929         nouveau_irq_fini(dev);
930
931         vga_client_register(dev->pdev, NULL, NULL, NULL);
932 }
933
934 int
935 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
936 {
937         struct drm_nouveau_private *dev_priv = dev->dev_private;
938         struct nouveau_fpriv *fpriv;
939         int ret;
940
941         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
942         if (unlikely(!fpriv))
943                 return -ENOMEM;
944
945         spin_lock_init(&fpriv->lock);
946         INIT_LIST_HEAD(&fpriv->channels);
947
948         if (dev_priv->card_type == NV_50) {
949                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
950                                      &fpriv->vm);
951                 if (ret) {
952                         kfree(fpriv);
953                         return ret;
954                 }
955         } else
956         if (dev_priv->card_type >= NV_C0) {
957                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
958                                      &fpriv->vm);
959                 if (ret) {
960                         kfree(fpriv);
961                         return ret;
962                 }
963         }
964
965         file_priv->driver_priv = fpriv;
966         return 0;
967 }
968
969 /* here a client dies, release the stuff that was allocated for its
970  * file_priv */
971 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
972 {
973         nouveau_channel_cleanup(dev, file_priv);
974 }
975
976 void
977 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
978 {
979         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
980         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
981         kfree(fpriv);
982 }
983
984 /* first module load, setup the mmio/fb mapping */
985 /* KMS: we need mmio at load time, not when the first drm client opens. */
986 int nouveau_firstopen(struct drm_device *dev)
987 {
988         return 0;
989 }
990
991 /* if we have an OF card, copy vbios to RAMIN */
992 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
993 {
994 #if defined(__powerpc__)
995         int size, i;
996         const uint32_t *bios;
997         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
998         if (!dn) {
999                 NV_INFO(dev, "Unable to get the OF node\n");
1000                 return;
1001         }
1002
1003         bios = of_get_property(dn, "NVDA,BMP", &size);
1004         if (bios) {
1005                 for (i = 0; i < size; i += 4)
1006                         nv_wi32(dev, i, bios[i/4]);
1007                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
1008         } else {
1009                 NV_INFO(dev, "Unable to get the OF bios\n");
1010         }
1011 #endif
1012 }
1013
1014 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
1015 {
1016         struct pci_dev *pdev = dev->pdev;
1017         struct apertures_struct *aper = alloc_apertures(3);
1018         if (!aper)
1019                 return NULL;
1020
1021         aper->ranges[0].base = pci_resource_start(pdev, 1);
1022         aper->ranges[0].size = pci_resource_len(pdev, 1);
1023         aper->count = 1;
1024
1025         if (pci_resource_len(pdev, 2)) {
1026                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
1027                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1028                 aper->count++;
1029         }
1030
1031         if (pci_resource_len(pdev, 3)) {
1032                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1033                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1034                 aper->count++;
1035         }
1036
1037         return aper;
1038 }
1039
1040 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1041 {
1042         struct drm_nouveau_private *dev_priv = dev->dev_private;
1043         bool primary = false;
1044         dev_priv->apertures = nouveau_get_apertures(dev);
1045         if (!dev_priv->apertures)
1046                 return -ENOMEM;
1047
1048 #ifdef CONFIG_X86
1049         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1050 #endif
1051
1052         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1053         return 0;
1054 }
1055
1056 int nouveau_load(struct drm_device *dev, unsigned long flags)
1057 {
1058         struct drm_nouveau_private *dev_priv;
1059         uint32_t reg0 = ~0, strap;
1060         resource_size_t mmio_start_offs;
1061         int ret;
1062
1063         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1064         if (!dev_priv) {
1065                 ret = -ENOMEM;
1066                 goto err_out;
1067         }
1068         dev->dev_private = dev_priv;
1069         dev_priv->dev = dev;
1070
1071         pci_set_master(dev->pdev);
1072
1073         dev_priv->flags = flags & NOUVEAU_FLAGS;
1074
1075         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1076                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1077
1078         /* first up, map the start of mmio and determine the chipset */
1079         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1080         if (dev_priv->mmio) {
1081 #ifdef __BIG_ENDIAN
1082                 /* put the card into big-endian mode if it's not */
1083                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1084                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1085                 DRM_MEMORYBARRIER();
1086 #endif
1087
1088                 /* determine chipset and derive architecture from it */
1089                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1090                 if ((reg0 & 0x0f000000) > 0) {
1091                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1092                         switch (dev_priv->chipset & 0xf0) {
1093                         case 0x10:
1094                         case 0x20:
1095                         case 0x30:
1096                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1097                                 break;
1098                         case 0x40:
1099                         case 0x60:
1100                                 dev_priv->card_type = NV_40;
1101                                 break;
1102                         case 0x50:
1103                         case 0x80:
1104                         case 0x90:
1105                         case 0xa0:
1106                                 dev_priv->card_type = NV_50;
1107                                 break;
1108                         case 0xc0:
1109                                 dev_priv->card_type = NV_C0;
1110                                 break;
1111                         case 0xd0:
1112                                 dev_priv->card_type = NV_D0;
1113                                 break;
1114                         default:
1115                                 break;
1116                         }
1117                 } else
1118                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1119                         if (reg0 & 0x00f00000)
1120                                 dev_priv->chipset = 0x05;
1121                         else
1122                                 dev_priv->chipset = 0x04;
1123                         dev_priv->card_type = NV_04;
1124                 }
1125
1126                 iounmap(dev_priv->mmio);
1127         }
1128
1129         if (!dev_priv->card_type) {
1130                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1131                 ret = -EINVAL;
1132                 goto err_priv;
1133         }
1134
1135         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1136                      dev_priv->card_type, reg0);
1137
1138         /* map the mmio regs */
1139         mmio_start_offs = pci_resource_start(dev->pdev, 0);
1140         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
1141         if (!dev_priv->mmio) {
1142                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1143                          "Please report your setup to " DRIVER_EMAIL "\n");
1144                 ret = -EINVAL;
1145                 goto err_priv;
1146         }
1147         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
1148                                         (unsigned long long)mmio_start_offs);
1149
1150         /* determine frequency of timing crystal */
1151         strap = nv_rd32(dev, 0x101000);
1152         if ( dev_priv->chipset < 0x17 ||
1153             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1154                 strap &= 0x00000040;
1155         else
1156                 strap &= 0x00400040;
1157
1158         switch (strap) {
1159         case 0x00000000: dev_priv->crystal = 13500; break;
1160         case 0x00000040: dev_priv->crystal = 14318; break;
1161         case 0x00400000: dev_priv->crystal = 27000; break;
1162         case 0x00400040: dev_priv->crystal = 25000; break;
1163         }
1164
1165         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1166
1167         /* Determine whether we'll attempt acceleration or not, some
1168          * cards are disabled by default here due to them being known
1169          * non-functional, or never been tested due to lack of hw.
1170          */
1171         dev_priv->noaccel = !!nouveau_noaccel;
1172         if (nouveau_noaccel == -1) {
1173                 switch (dev_priv->chipset) {
1174                 case 0xd9: /* known broken */
1175                         NV_INFO(dev, "acceleration disabled by default, pass "
1176                                      "noaccel=0 to force enable\n");
1177                         dev_priv->noaccel = true;
1178                         break;
1179                 default:
1180                         dev_priv->noaccel = false;
1181                         break;
1182                 }
1183         }
1184
1185         ret = nouveau_remove_conflicting_drivers(dev);
1186         if (ret)
1187                 goto err_mmio;
1188
1189         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1190         if (dev_priv->card_type >= NV_40) {
1191                 int ramin_bar = 2;
1192                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1193                         ramin_bar = 3;
1194
1195                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1196                 dev_priv->ramin =
1197                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1198                                 dev_priv->ramin_size);
1199                 if (!dev_priv->ramin) {
1200                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1201                         ret = -ENOMEM;
1202                         goto err_mmio;
1203                 }
1204         } else {
1205                 dev_priv->ramin_size = 1 * 1024 * 1024;
1206                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1207                                           dev_priv->ramin_size);
1208                 if (!dev_priv->ramin) {
1209                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1210                         ret = -ENOMEM;
1211                         goto err_mmio;
1212                 }
1213         }
1214
1215         nouveau_OF_copy_vbios_to_ramin(dev);
1216
1217         /* Special flags */
1218         if (dev->pci_device == 0x01a0)
1219                 dev_priv->flags |= NV_NFORCE;
1220         else if (dev->pci_device == 0x01f0)
1221                 dev_priv->flags |= NV_NFORCE2;
1222
1223         /* For kernel modesetting, init card now and bring up fbcon */
1224         ret = nouveau_card_init(dev);
1225         if (ret)
1226                 goto err_ramin;
1227
1228         return 0;
1229
1230 err_ramin:
1231         iounmap(dev_priv->ramin);
1232 err_mmio:
1233         iounmap(dev_priv->mmio);
1234 err_priv:
1235         kfree(dev_priv);
1236         dev->dev_private = NULL;
1237 err_out:
1238         return ret;
1239 }
1240
1241 void nouveau_lastclose(struct drm_device *dev)
1242 {
1243         vga_switcheroo_process_delayed_switch();
1244 }
1245
1246 int nouveau_unload(struct drm_device *dev)
1247 {
1248         struct drm_nouveau_private *dev_priv = dev->dev_private;
1249
1250         nouveau_card_takedown(dev);
1251
1252         iounmap(dev_priv->mmio);
1253         iounmap(dev_priv->ramin);
1254
1255         kfree(dev_priv);
1256         dev->dev_private = NULL;
1257         return 0;
1258 }
1259
1260 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1261                                                 struct drm_file *file_priv)
1262 {
1263         struct drm_nouveau_private *dev_priv = dev->dev_private;
1264         struct drm_nouveau_getparam *getparam = data;
1265
1266         switch (getparam->param) {
1267         case NOUVEAU_GETPARAM_CHIPSET_ID:
1268                 getparam->value = dev_priv->chipset;
1269                 break;
1270         case NOUVEAU_GETPARAM_PCI_VENDOR:
1271                 getparam->value = dev->pci_vendor;
1272                 break;
1273         case NOUVEAU_GETPARAM_PCI_DEVICE:
1274                 getparam->value = dev->pci_device;
1275                 break;
1276         case NOUVEAU_GETPARAM_BUS_TYPE:
1277                 if (drm_pci_device_is_agp(dev))
1278                         getparam->value = NV_AGP;
1279                 else if (pci_is_pcie(dev->pdev))
1280                         getparam->value = NV_PCIE;
1281                 else
1282                         getparam->value = NV_PCI;
1283                 break;
1284         case NOUVEAU_GETPARAM_FB_SIZE:
1285                 getparam->value = dev_priv->fb_available_size;
1286                 break;
1287         case NOUVEAU_GETPARAM_AGP_SIZE:
1288                 getparam->value = dev_priv->gart_info.aper_size;
1289                 break;
1290         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1291                 getparam->value = 0; /* deprecated */
1292                 break;
1293         case NOUVEAU_GETPARAM_PTIMER_TIME:
1294                 getparam->value = dev_priv->engine.timer.read(dev);
1295                 break;
1296         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1297                 getparam->value = 1;
1298                 break;
1299         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1300                 getparam->value = 1;
1301                 break;
1302         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1303                 /* NV40 and NV50 versions are quite different, but register
1304                  * address is the same. User is supposed to know the card
1305                  * family anyway... */
1306                 if (dev_priv->chipset >= 0x40) {
1307                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1308                         break;
1309                 }
1310                 /* FALLTHRU */
1311         default:
1312                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1313                 return -EINVAL;
1314         }
1315
1316         return 0;
1317 }
1318
1319 int
1320 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1321                        struct drm_file *file_priv)
1322 {
1323         struct drm_nouveau_setparam *setparam = data;
1324
1325         switch (setparam->param) {
1326         default:
1327                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1328                 return -EINVAL;
1329         }
1330
1331         return 0;
1332 }
1333
1334 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1335 bool
1336 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1337                 uint32_t reg, uint32_t mask, uint32_t val)
1338 {
1339         struct drm_nouveau_private *dev_priv = dev->dev_private;
1340         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1341         uint64_t start = ptimer->read(dev);
1342
1343         do {
1344                 if ((nv_rd32(dev, reg) & mask) == val)
1345                         return true;
1346         } while (ptimer->read(dev) - start < timeout);
1347
1348         return false;
1349 }
1350
1351 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1352 bool
1353 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1354                 uint32_t reg, uint32_t mask, uint32_t val)
1355 {
1356         struct drm_nouveau_private *dev_priv = dev->dev_private;
1357         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1358         uint64_t start = ptimer->read(dev);
1359
1360         do {
1361                 if ((nv_rd32(dev, reg) & mask) != val)
1362                         return true;
1363         } while (ptimer->read(dev) - start < timeout);
1364
1365         return false;
1366 }
1367
1368 /* Wait until cond(data) == true, up until timeout has hit */
1369 bool
1370 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1371                 bool (*cond)(void *), void *data)
1372 {
1373         struct drm_nouveau_private *dev_priv = dev->dev_private;
1374         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1375         u64 start = ptimer->read(dev);
1376
1377         do {
1378                 if (cond(data) == true)
1379                         return true;
1380         } while (ptimer->read(dev) - start < timeout);
1381
1382         return false;
1383 }
1384
1385 /* Waits for PGRAPH to go completely idle */
1386 bool nouveau_wait_for_idle(struct drm_device *dev)
1387 {
1388         struct drm_nouveau_private *dev_priv = dev->dev_private;
1389         uint32_t mask = ~0;
1390
1391         if (dev_priv->card_type == NV_40)
1392                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1393
1394         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1395                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1396                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1397                 return false;
1398         }
1399
1400         return true;
1401 }
1402