mm, drm/udl: fixup vma flags on mmap
[~shefty/rdma-dev.git] / drivers / gpu / drm / radeon / radeon_object.c
1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include "radeon_drm.h"
36 #include "radeon.h"
37 #include "radeon_trace.h"
38
39
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43
44 /*
45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46  * function are calling it.
47  */
48
49 void radeon_bo_clear_va(struct radeon_bo *bo)
50 {
51         struct radeon_bo_va *bo_va, *tmp;
52
53         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54                 /* remove from all vm address space */
55                 mutex_lock(&bo_va->vm->mutex);
56                 list_del(&bo_va->vm_list);
57                 mutex_unlock(&bo_va->vm->mutex);
58                 list_del(&bo_va->bo_list);
59                 kfree(bo_va);
60         }
61 }
62
63 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
64 {
65         struct radeon_bo *bo;
66
67         bo = container_of(tbo, struct radeon_bo, tbo);
68         mutex_lock(&bo->rdev->gem.mutex);
69         list_del_init(&bo->list);
70         mutex_unlock(&bo->rdev->gem.mutex);
71         radeon_bo_clear_surface_reg(bo);
72         radeon_bo_clear_va(bo);
73         drm_gem_object_release(&bo->gem_base);
74         kfree(bo);
75 }
76
77 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
78 {
79         if (bo->destroy == &radeon_ttm_bo_destroy)
80                 return true;
81         return false;
82 }
83
84 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
85 {
86         u32 c = 0;
87
88         rbo->placement.fpfn = 0;
89         rbo->placement.lpfn = 0;
90         rbo->placement.placement = rbo->placements;
91         rbo->placement.busy_placement = rbo->placements;
92         if (domain & RADEON_GEM_DOMAIN_VRAM)
93                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
94                                         TTM_PL_FLAG_VRAM;
95         if (domain & RADEON_GEM_DOMAIN_GTT)
96                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
97         if (domain & RADEON_GEM_DOMAIN_CPU)
98                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
99         if (!c)
100                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
101         rbo->placement.num_placement = c;
102         rbo->placement.num_busy_placement = c;
103 }
104
105 int radeon_bo_create(struct radeon_device *rdev,
106                      unsigned long size, int byte_align, bool kernel, u32 domain,
107                      struct radeon_bo **bo_ptr)
108 {
109         struct radeon_bo *bo;
110         enum ttm_bo_type type;
111         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
112         unsigned long max_size = 0;
113         size_t acc_size;
114         int r;
115
116         size = ALIGN(size, PAGE_SIZE);
117
118         if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
119                 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
120         }
121         if (kernel) {
122                 type = ttm_bo_type_kernel;
123         } else {
124                 type = ttm_bo_type_device;
125         }
126         *bo_ptr = NULL;
127
128         /* maximun bo size is the minimun btw visible vram and gtt size */
129         max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
130         if ((page_align << PAGE_SHIFT) >= max_size) {
131                 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
132                         __func__, __LINE__, page_align  >> (20 - PAGE_SHIFT), max_size >> 20);
133                 return -ENOMEM;
134         }
135
136         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
137                                        sizeof(struct radeon_bo));
138
139 retry:
140         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
141         if (bo == NULL)
142                 return -ENOMEM;
143         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
144         if (unlikely(r)) {
145                 kfree(bo);
146                 return r;
147         }
148         bo->rdev = rdev;
149         bo->gem_base.driver_private = NULL;
150         bo->surface_reg = -1;
151         INIT_LIST_HEAD(&bo->list);
152         INIT_LIST_HEAD(&bo->va);
153         radeon_ttm_placement_from_domain(bo, domain);
154         /* Kernel allocation are uninterruptible */
155         mutex_lock(&rdev->vram_mutex);
156         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
157                         &bo->placement, page_align, 0, !kernel, NULL,
158                         acc_size, &radeon_ttm_bo_destroy);
159         mutex_unlock(&rdev->vram_mutex);
160         if (unlikely(r != 0)) {
161                 if (r != -ERESTARTSYS) {
162                         if (domain == RADEON_GEM_DOMAIN_VRAM) {
163                                 domain |= RADEON_GEM_DOMAIN_GTT;
164                                 goto retry;
165                         }
166                         dev_err(rdev->dev,
167                                 "object_init failed for (%lu, 0x%08X)\n",
168                                 size, domain);
169                 }
170                 return r;
171         }
172         *bo_ptr = bo;
173
174         trace_radeon_bo_create(bo);
175
176         return 0;
177 }
178
179 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
180 {
181         bool is_iomem;
182         int r;
183
184         if (bo->kptr) {
185                 if (ptr) {
186                         *ptr = bo->kptr;
187                 }
188                 return 0;
189         }
190         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
191         if (r) {
192                 return r;
193         }
194         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
195         if (ptr) {
196                 *ptr = bo->kptr;
197         }
198         radeon_bo_check_tiling(bo, 0, 0);
199         return 0;
200 }
201
202 void radeon_bo_kunmap(struct radeon_bo *bo)
203 {
204         if (bo->kptr == NULL)
205                 return;
206         bo->kptr = NULL;
207         radeon_bo_check_tiling(bo, 0, 0);
208         ttm_bo_kunmap(&bo->kmap);
209 }
210
211 void radeon_bo_unref(struct radeon_bo **bo)
212 {
213         struct ttm_buffer_object *tbo;
214         struct radeon_device *rdev;
215
216         if ((*bo) == NULL)
217                 return;
218         rdev = (*bo)->rdev;
219         tbo = &((*bo)->tbo);
220         mutex_lock(&rdev->vram_mutex);
221         ttm_bo_unref(&tbo);
222         mutex_unlock(&rdev->vram_mutex);
223         if (tbo == NULL)
224                 *bo = NULL;
225 }
226
227 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
228                              u64 *gpu_addr)
229 {
230         int r, i;
231
232         if (bo->pin_count) {
233                 bo->pin_count++;
234                 if (gpu_addr)
235                         *gpu_addr = radeon_bo_gpu_offset(bo);
236
237                 if (max_offset != 0) {
238                         u64 domain_start;
239
240                         if (domain == RADEON_GEM_DOMAIN_VRAM)
241                                 domain_start = bo->rdev->mc.vram_start;
242                         else
243                                 domain_start = bo->rdev->mc.gtt_start;
244                         WARN_ON_ONCE((*gpu_addr - domain_start) > max_offset);
245                 }
246
247                 return 0;
248         }
249         radeon_ttm_placement_from_domain(bo, domain);
250         if (domain == RADEON_GEM_DOMAIN_VRAM) {
251                 /* force to pin into visible video ram */
252                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
253         }
254         if (max_offset) {
255                 u64 lpfn = max_offset >> PAGE_SHIFT;
256
257                 if (!bo->placement.lpfn)
258                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
259
260                 if (lpfn < bo->placement.lpfn)
261                         bo->placement.lpfn = lpfn;
262         }
263         for (i = 0; i < bo->placement.num_placement; i++)
264                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
265         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
266         if (likely(r == 0)) {
267                 bo->pin_count = 1;
268                 if (gpu_addr != NULL)
269                         *gpu_addr = radeon_bo_gpu_offset(bo);
270         }
271         if (unlikely(r != 0))
272                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
273         return r;
274 }
275
276 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
277 {
278         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
279 }
280
281 int radeon_bo_unpin(struct radeon_bo *bo)
282 {
283         int r, i;
284
285         if (!bo->pin_count) {
286                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
287                 return 0;
288         }
289         bo->pin_count--;
290         if (bo->pin_count)
291                 return 0;
292         for (i = 0; i < bo->placement.num_placement; i++)
293                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
294         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
295         if (unlikely(r != 0))
296                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
297         return r;
298 }
299
300 int radeon_bo_evict_vram(struct radeon_device *rdev)
301 {
302         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
303         if (0 && (rdev->flags & RADEON_IS_IGP)) {
304                 if (rdev->mc.igp_sideport_enabled == false)
305                         /* Useless to evict on IGP chips */
306                         return 0;
307         }
308         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
309 }
310
311 void radeon_bo_force_delete(struct radeon_device *rdev)
312 {
313         struct radeon_bo *bo, *n;
314
315         if (list_empty(&rdev->gem.objects)) {
316                 return;
317         }
318         dev_err(rdev->dev, "Userspace still has active objects !\n");
319         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
320                 mutex_lock(&rdev->ddev->struct_mutex);
321                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
322                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
323                         *((unsigned long *)&bo->gem_base.refcount));
324                 mutex_lock(&bo->rdev->gem.mutex);
325                 list_del_init(&bo->list);
326                 mutex_unlock(&bo->rdev->gem.mutex);
327                 /* this should unref the ttm bo */
328                 drm_gem_object_unreference(&bo->gem_base);
329                 mutex_unlock(&rdev->ddev->struct_mutex);
330         }
331 }
332
333 int radeon_bo_init(struct radeon_device *rdev)
334 {
335         /* Add an MTRR for the VRAM */
336         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
337                         MTRR_TYPE_WRCOMB, 1);
338         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
339                 rdev->mc.mc_vram_size >> 20,
340                 (unsigned long long)rdev->mc.aper_size >> 20);
341         DRM_INFO("RAM width %dbits %cDR\n",
342                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
343         return radeon_ttm_init(rdev);
344 }
345
346 void radeon_bo_fini(struct radeon_device *rdev)
347 {
348         radeon_ttm_fini(rdev);
349 }
350
351 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
352                                 struct list_head *head)
353 {
354         if (lobj->wdomain) {
355                 list_add(&lobj->tv.head, head);
356         } else {
357                 list_add_tail(&lobj->tv.head, head);
358         }
359 }
360
361 int radeon_bo_list_validate(struct list_head *head)
362 {
363         struct radeon_bo_list *lobj;
364         struct radeon_bo *bo;
365         u32 domain;
366         int r;
367
368         r = ttm_eu_reserve_buffers(head);
369         if (unlikely(r != 0)) {
370                 return r;
371         }
372         list_for_each_entry(lobj, head, tv.head) {
373                 bo = lobj->bo;
374                 if (!bo->pin_count) {
375                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
376                         
377                 retry:
378                         radeon_ttm_placement_from_domain(bo, domain);
379                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
380                                                 true, false, false);
381                         if (unlikely(r)) {
382                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
383                                         domain |= RADEON_GEM_DOMAIN_GTT;
384                                         goto retry;
385                                 }
386                                 return r;
387                         }
388                 }
389                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
390                 lobj->tiling_flags = bo->tiling_flags;
391         }
392         return 0;
393 }
394
395 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
396                              struct vm_area_struct *vma)
397 {
398         return ttm_fbdev_mmap(vma, &bo->tbo);
399 }
400
401 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
402 {
403         struct radeon_device *rdev = bo->rdev;
404         struct radeon_surface_reg *reg;
405         struct radeon_bo *old_object;
406         int steal;
407         int i;
408
409         BUG_ON(!atomic_read(&bo->tbo.reserved));
410
411         if (!bo->tiling_flags)
412                 return 0;
413
414         if (bo->surface_reg >= 0) {
415                 reg = &rdev->surface_regs[bo->surface_reg];
416                 i = bo->surface_reg;
417                 goto out;
418         }
419
420         steal = -1;
421         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
422
423                 reg = &rdev->surface_regs[i];
424                 if (!reg->bo)
425                         break;
426
427                 old_object = reg->bo;
428                 if (old_object->pin_count == 0)
429                         steal = i;
430         }
431
432         /* if we are all out */
433         if (i == RADEON_GEM_MAX_SURFACES) {
434                 if (steal == -1)
435                         return -ENOMEM;
436                 /* find someone with a surface reg and nuke their BO */
437                 reg = &rdev->surface_regs[steal];
438                 old_object = reg->bo;
439                 /* blow away the mapping */
440                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
441                 ttm_bo_unmap_virtual(&old_object->tbo);
442                 old_object->surface_reg = -1;
443                 i = steal;
444         }
445
446         bo->surface_reg = i;
447         reg->bo = bo;
448
449 out:
450         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
451                                bo->tbo.mem.start << PAGE_SHIFT,
452                                bo->tbo.num_pages << PAGE_SHIFT);
453         return 0;
454 }
455
456 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
457 {
458         struct radeon_device *rdev = bo->rdev;
459         struct radeon_surface_reg *reg;
460
461         if (bo->surface_reg == -1)
462                 return;
463
464         reg = &rdev->surface_regs[bo->surface_reg];
465         radeon_clear_surface_reg(rdev, bo->surface_reg);
466
467         reg->bo = NULL;
468         bo->surface_reg = -1;
469 }
470
471 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
472                                 uint32_t tiling_flags, uint32_t pitch)
473 {
474         struct radeon_device *rdev = bo->rdev;
475         int r;
476
477         if (rdev->family >= CHIP_CEDAR) {
478                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
479
480                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
481                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
482                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
483                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
484                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
485                 switch (bankw) {
486                 case 0:
487                 case 1:
488                 case 2:
489                 case 4:
490                 case 8:
491                         break;
492                 default:
493                         return -EINVAL;
494                 }
495                 switch (bankh) {
496                 case 0:
497                 case 1:
498                 case 2:
499                 case 4:
500                 case 8:
501                         break;
502                 default:
503                         return -EINVAL;
504                 }
505                 switch (mtaspect) {
506                 case 0:
507                 case 1:
508                 case 2:
509                 case 4:
510                 case 8:
511                         break;
512                 default:
513                         return -EINVAL;
514                 }
515                 if (tilesplit > 6) {
516                         return -EINVAL;
517                 }
518                 if (stilesplit > 6) {
519                         return -EINVAL;
520                 }
521         }
522         r = radeon_bo_reserve(bo, false);
523         if (unlikely(r != 0))
524                 return r;
525         bo->tiling_flags = tiling_flags;
526         bo->pitch = pitch;
527         radeon_bo_unreserve(bo);
528         return 0;
529 }
530
531 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
532                                 uint32_t *tiling_flags,
533                                 uint32_t *pitch)
534 {
535         BUG_ON(!atomic_read(&bo->tbo.reserved));
536         if (tiling_flags)
537                 *tiling_flags = bo->tiling_flags;
538         if (pitch)
539                 *pitch = bo->pitch;
540 }
541
542 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
543                                 bool force_drop)
544 {
545         BUG_ON(!atomic_read(&bo->tbo.reserved));
546
547         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
548                 return 0;
549
550         if (force_drop) {
551                 radeon_bo_clear_surface_reg(bo);
552                 return 0;
553         }
554
555         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
556                 if (!has_moved)
557                         return 0;
558
559                 if (bo->surface_reg >= 0)
560                         radeon_bo_clear_surface_reg(bo);
561                 return 0;
562         }
563
564         if ((bo->surface_reg >= 0) && !has_moved)
565                 return 0;
566
567         return radeon_bo_get_surface_reg(bo);
568 }
569
570 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
571                            struct ttm_mem_reg *mem)
572 {
573         struct radeon_bo *rbo;
574         if (!radeon_ttm_bo_is_radeon_bo(bo))
575                 return;
576         rbo = container_of(bo, struct radeon_bo, tbo);
577         radeon_bo_check_tiling(rbo, 0, 1);
578         radeon_vm_bo_invalidate(rbo->rdev, rbo);
579 }
580
581 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
582 {
583         struct radeon_device *rdev;
584         struct radeon_bo *rbo;
585         unsigned long offset, size;
586         int r;
587
588         if (!radeon_ttm_bo_is_radeon_bo(bo))
589                 return 0;
590         rbo = container_of(bo, struct radeon_bo, tbo);
591         radeon_bo_check_tiling(rbo, 0, 0);
592         rdev = rbo->rdev;
593         if (bo->mem.mem_type == TTM_PL_VRAM) {
594                 size = bo->mem.num_pages << PAGE_SHIFT;
595                 offset = bo->mem.start << PAGE_SHIFT;
596                 if ((offset + size) > rdev->mc.visible_vram_size) {
597                         /* hurrah the memory is not visible ! */
598                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
599                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
600                         r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
601                         if (unlikely(r != 0))
602                                 return r;
603                         offset = bo->mem.start << PAGE_SHIFT;
604                         /* this should not happen */
605                         if ((offset + size) > rdev->mc.visible_vram_size)
606                                 return -EINVAL;
607                 }
608         }
609         return 0;
610 }
611
612 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
613 {
614         int r;
615
616         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
617         if (unlikely(r != 0))
618                 return r;
619         spin_lock(&bo->tbo.bdev->fence_lock);
620         if (mem_type)
621                 *mem_type = bo->tbo.mem.mem_type;
622         if (bo->tbo.sync_obj)
623                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
624         spin_unlock(&bo->tbo.bdev->fence_lock);
625         ttm_bo_unreserve(&bo->tbo);
626         return r;
627 }
628
629
630 /**
631  * radeon_bo_reserve - reserve bo
632  * @bo:         bo structure
633  * @no_wait:            don't sleep while trying to reserve (return -EBUSY)
634  *
635  * Returns:
636  * -EBUSY: buffer is busy and @no_wait is true
637  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
638  * a signal. Release all buffer reservations and return to user-space.
639  */
640 int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
641 {
642         int r;
643
644         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
645         if (unlikely(r != 0)) {
646                 if (r != -ERESTARTSYS)
647                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
648                 return r;
649         }
650         return 0;
651 }
652
653 /* object have to be reserved */
654 struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm)
655 {
656         struct radeon_bo_va *bo_va;
657
658         list_for_each_entry(bo_va, &rbo->va, bo_list) {
659                 if (bo_va->vm == vm) {
660                         return bo_va;
661                 }
662         }
663         return NULL;
664 }