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drm: tegra: program only one window during modeset
[~shefty/rdma-dev.git] / drivers / gpu / drm / tegra / dc.c
1 /*
2  * Copyright (C) 2012 Avionic Design GmbH
3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  */
9
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15
16 #include <mach/clk.h>
17
18 #include "drm.h"
19 #include "dc.h"
20
21 struct tegra_dc_window {
22         fixed20_12 x;
23         fixed20_12 y;
24         fixed20_12 w;
25         fixed20_12 h;
26         unsigned int outx;
27         unsigned int outy;
28         unsigned int outw;
29         unsigned int outh;
30         unsigned int stride;
31         unsigned int fmt;
32 };
33
34 static const struct drm_crtc_funcs tegra_crtc_funcs = {
35         .set_config = drm_crtc_helper_set_config,
36         .destroy = drm_crtc_cleanup,
37 };
38
39 static void tegra_crtc_dpms(struct drm_crtc *crtc, int mode)
40 {
41 }
42
43 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
44                                   const struct drm_display_mode *mode,
45                                   struct drm_display_mode *adjusted)
46 {
47         return true;
48 }
49
50 static inline u32 compute_dda_inc(fixed20_12 inf, unsigned int out, bool v,
51                                   unsigned int bpp)
52 {
53         fixed20_12 outf = dfixed_init(out);
54         u32 dda_inc;
55         int max;
56
57         if (v)
58                 max = 15;
59         else {
60                 switch (bpp) {
61                 case 2:
62                         max = 8;
63                         break;
64
65                 default:
66                         WARN_ON_ONCE(1);
67                         /* fallthrough */
68                 case 4:
69                         max = 4;
70                         break;
71                 }
72         }
73
74         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
75         inf.full -= dfixed_const(1);
76
77         dda_inc = dfixed_div(inf, outf);
78         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
79
80         return dda_inc;
81 }
82
83 static inline u32 compute_initial_dda(fixed20_12 in)
84 {
85         return dfixed_frac(in);
86 }
87
88 static int tegra_dc_set_timings(struct tegra_dc *dc,
89                                 struct drm_display_mode *mode)
90 {
91         /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
92         unsigned int h_ref_to_sync = 0;
93         unsigned int v_ref_to_sync = 0;
94         unsigned long value;
95
96         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
97
98         value = (v_ref_to_sync << 16) | h_ref_to_sync;
99         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
100
101         value = ((mode->vsync_end - mode->vsync_start) << 16) |
102                 ((mode->hsync_end - mode->hsync_start) <<  0);
103         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
104
105         value = ((mode->vtotal - mode->vsync_end) << 16) |
106                 ((mode->htotal - mode->hsync_end) <<  0);
107         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
108
109         value = ((mode->vsync_start - mode->vdisplay) << 16) |
110                 ((mode->hsync_start - mode->hdisplay) <<  0);
111         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
112
113         value = (mode->vdisplay << 16) | mode->hdisplay;
114         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
115
116         return 0;
117 }
118
119 static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
120                                 struct drm_display_mode *mode,
121                                 unsigned long *div)
122 {
123         unsigned long pclk = mode->clock * 1000, rate;
124         struct tegra_dc *dc = to_tegra_dc(crtc);
125         struct tegra_output *output = NULL;
126         struct drm_encoder *encoder;
127         long err;
128
129         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
130                 if (encoder->crtc == crtc) {
131                         output = encoder_to_output(encoder);
132                         break;
133                 }
134
135         if (!output)
136                 return -ENODEV;
137
138         /*
139          * This assumes that the display controller will divide its parent
140          * clock by 2 to generate the pixel clock.
141          */
142         err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
143         if (err < 0) {
144                 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
145                 return err;
146         }
147
148         rate = clk_get_rate(dc->clk);
149         *div = (rate * 2 / pclk) - 2;
150
151         DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
152
153         return 0;
154 }
155
156 static int tegra_crtc_mode_set(struct drm_crtc *crtc,
157                                struct drm_display_mode *mode,
158                                struct drm_display_mode *adjusted,
159                                int x, int y, struct drm_framebuffer *old_fb)
160 {
161         struct tegra_framebuffer *fb = to_tegra_fb(crtc->fb);
162         struct tegra_dc *dc = to_tegra_dc(crtc);
163         unsigned int h_dda, v_dda, bpp;
164         struct tegra_dc_window win;
165         unsigned long div, value;
166         int err;
167
168         err = tegra_crtc_setup_clk(crtc, mode, &div);
169         if (err) {
170                 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
171                 return err;
172         }
173
174         mutex_lock(&dc->regs_mutex);
175
176         /* program display mode */
177         tegra_dc_set_timings(dc, mode);
178
179         value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
180         tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
181
182         value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
183         value &= ~LVS_OUTPUT_POLARITY_LOW;
184         value &= ~LHS_OUTPUT_POLARITY_LOW;
185         tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
186
187         value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
188                 DISP_ORDER_RED_BLUE;
189         tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
190
191         tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
192
193         value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
194         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
195
196         /* setup window parameters */
197         memset(&win, 0, sizeof(win));
198         win.x.full = dfixed_const(0);
199         win.y.full = dfixed_const(0);
200         win.w.full = dfixed_const(mode->hdisplay);
201         win.h.full = dfixed_const(mode->vdisplay);
202         win.outx = 0;
203         win.outy = 0;
204         win.outw = mode->hdisplay;
205         win.outh = mode->vdisplay;
206
207         switch (crtc->fb->pixel_format) {
208         case DRM_FORMAT_XRGB8888:
209                 win.fmt = WIN_COLOR_DEPTH_B8G8R8A8;
210                 break;
211
212         case DRM_FORMAT_RGB565:
213                 win.fmt = WIN_COLOR_DEPTH_B5G6R5;
214                 break;
215
216         default:
217                 win.fmt = WIN_COLOR_DEPTH_B8G8R8A8;
218                 WARN_ON(1);
219                 break;
220         }
221
222         bpp = crtc->fb->bits_per_pixel / 8;
223         win.stride = crtc->fb->pitches[0];
224
225         /* program window registers */
226         value = WINDOW_A_SELECT;
227         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
228
229         tegra_dc_writel(dc, win.fmt, DC_WIN_COLOR_DEPTH);
230         tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
231
232         value = V_POSITION(win.outy) | H_POSITION(win.outx);
233         tegra_dc_writel(dc, value, DC_WIN_POSITION);
234
235         value = V_SIZE(win.outh) | H_SIZE(win.outw);
236         tegra_dc_writel(dc, value, DC_WIN_SIZE);
237
238         value = V_PRESCALED_SIZE(dfixed_trunc(win.h)) |
239                 H_PRESCALED_SIZE(dfixed_trunc(win.w) * bpp);
240         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
241
242         h_dda = compute_dda_inc(win.w, win.outw, false, bpp);
243         v_dda = compute_dda_inc(win.h, win.outh, true, bpp);
244
245         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
246         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
247
248         h_dda = compute_initial_dda(win.x);
249         v_dda = compute_initial_dda(win.y);
250
251         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
252         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
253
254         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
255         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
256
257         tegra_dc_writel(dc, fb->obj->paddr, DC_WINBUF_START_ADDR);
258         tegra_dc_writel(dc, win.stride, DC_WIN_LINE_STRIDE);
259         tegra_dc_writel(dc, dfixed_trunc(win.x) * bpp,
260                         DC_WINBUF_ADDR_H_OFFSET);
261         tegra_dc_writel(dc, dfixed_trunc(win.y), DC_WINBUF_ADDR_V_OFFSET);
262
263         value = WIN_ENABLE;
264
265         if (bpp < 24)
266                 value |= COLOR_EXPAND;
267
268         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
269
270         tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_NOKEY);
271         tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_1WIN);
272
273         mutex_unlock(&dc->regs_mutex);
274
275         return 0;
276 }
277
278 static void tegra_crtc_prepare(struct drm_crtc *crtc)
279 {
280         struct tegra_dc *dc = to_tegra_dc(crtc);
281         unsigned int syncpt;
282         unsigned long value;
283
284         /* hardware initialization */
285         tegra_periph_reset_deassert(dc->clk);
286         usleep_range(10000, 20000);
287
288         if (dc->pipe)
289                 syncpt = SYNCPT_VBLANK1;
290         else
291                 syncpt = SYNCPT_VBLANK0;
292
293         mutex_lock(&dc->regs_mutex);
294
295         /* initialize display controller */
296         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
297         tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
298
299         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
300         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
301
302         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
303                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
304         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
305
306         value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
307                 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
308         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
309
310         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
311         value |= DISP_CTRL_MODE_C_DISPLAY;
312         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
313
314         /* initialize timer */
315         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
316                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
317         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
318
319         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
320                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
321         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
322
323         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
324         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
325
326         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
327         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
328
329         mutex_unlock(&dc->regs_mutex);
330 }
331
332 static void tegra_crtc_commit(struct drm_crtc *crtc)
333 {
334         struct tegra_dc *dc = to_tegra_dc(crtc);
335         unsigned long update_mask;
336         unsigned long value;
337
338         update_mask = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
339
340         mutex_lock(&dc->regs_mutex);
341
342         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
343
344         value = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
345         value |= FRAME_END_INT;
346         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
347
348         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
349         value |= FRAME_END_INT;
350         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
351
352         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
353
354         mutex_unlock(&dc->regs_mutex);
355 }
356
357 static void tegra_crtc_load_lut(struct drm_crtc *crtc)
358 {
359 }
360
361 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
362         .dpms = tegra_crtc_dpms,
363         .mode_fixup = tegra_crtc_mode_fixup,
364         .mode_set = tegra_crtc_mode_set,
365         .prepare = tegra_crtc_prepare,
366         .commit = tegra_crtc_commit,
367         .load_lut = tegra_crtc_load_lut,
368 };
369
370 static irqreturn_t tegra_drm_irq(int irq, void *data)
371 {
372         struct tegra_dc *dc = data;
373         unsigned long status;
374
375         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
376         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
377
378         if (status & FRAME_END_INT) {
379                 /*
380                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
381                 */
382         }
383
384         if (status & VBLANK_INT) {
385                 /*
386                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
387                 */
388                 drm_handle_vblank(dc->base.dev, dc->pipe);
389         }
390
391         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
392                 /*
393                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
394                 */
395         }
396
397         return IRQ_HANDLED;
398 }
399
400 static int tegra_dc_show_regs(struct seq_file *s, void *data)
401 {
402         struct drm_info_node *node = s->private;
403         struct tegra_dc *dc = node->info_ent->data;
404
405 #define DUMP_REG(name)                                          \
406         seq_printf(s, "%-40s %#05x %08lx\n", #name, name,       \
407                    tegra_dc_readl(dc, name))
408
409         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
410         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
411         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
412         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
413         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
414         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
415         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
416         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
417         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
418         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
419         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
420         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
421         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
422         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
423         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
424         DUMP_REG(DC_CMD_SIGNAL_RAISE);
425         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
426         DUMP_REG(DC_CMD_INT_STATUS);
427         DUMP_REG(DC_CMD_INT_MASK);
428         DUMP_REG(DC_CMD_INT_ENABLE);
429         DUMP_REG(DC_CMD_INT_TYPE);
430         DUMP_REG(DC_CMD_INT_POLARITY);
431         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
432         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
433         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
434         DUMP_REG(DC_CMD_STATE_ACCESS);
435         DUMP_REG(DC_CMD_STATE_CONTROL);
436         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
437         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
438         DUMP_REG(DC_COM_CRC_CONTROL);
439         DUMP_REG(DC_COM_CRC_CHECKSUM);
440         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
441         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
442         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
443         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
444         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
445         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
446         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
447         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
448         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
449         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
450         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
451         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
452         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
453         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
454         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
455         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
456         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
457         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
458         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
459         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
460         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
461         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
462         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
463         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
464         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
465         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
466         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
467         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
468         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
469         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
470         DUMP_REG(DC_COM_SPI_CONTROL);
471         DUMP_REG(DC_COM_SPI_START_BYTE);
472         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
473         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
474         DUMP_REG(DC_COM_HSPI_CS_DC);
475         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
476         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
477         DUMP_REG(DC_COM_GPIO_CTRL);
478         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
479         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
480         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
481         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
482         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
483         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
484         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
485         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
486         DUMP_REG(DC_DISP_REF_TO_SYNC);
487         DUMP_REG(DC_DISP_SYNC_WIDTH);
488         DUMP_REG(DC_DISP_BACK_PORCH);
489         DUMP_REG(DC_DISP_ACTIVE);
490         DUMP_REG(DC_DISP_FRONT_PORCH);
491         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
492         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
493         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
494         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
495         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
496         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
497         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
498         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
499         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
500         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
501         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
502         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
503         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
504         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
505         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
506         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
507         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
508         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
509         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
510         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
511         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
512         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
513         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
514         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
515         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
516         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
517         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
518         DUMP_REG(DC_DISP_M0_CONTROL);
519         DUMP_REG(DC_DISP_M1_CONTROL);
520         DUMP_REG(DC_DISP_DI_CONTROL);
521         DUMP_REG(DC_DISP_PP_CONTROL);
522         DUMP_REG(DC_DISP_PP_SELECT_A);
523         DUMP_REG(DC_DISP_PP_SELECT_B);
524         DUMP_REG(DC_DISP_PP_SELECT_C);
525         DUMP_REG(DC_DISP_PP_SELECT_D);
526         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
527         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
528         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
529         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
530         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
531         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
532         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
533         DUMP_REG(DC_DISP_BORDER_COLOR);
534         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
535         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
536         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
537         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
538         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
539         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
540         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
541         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
542         DUMP_REG(DC_DISP_CURSOR_POSITION);
543         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
544         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
545         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
546         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
547         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
548         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
549         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
550         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
551         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
552         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
553         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
554         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
555         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
556         DUMP_REG(DC_DISP_SD_CONTROL);
557         DUMP_REG(DC_DISP_SD_CSC_COEFF);
558         DUMP_REG(DC_DISP_SD_LUT(0));
559         DUMP_REG(DC_DISP_SD_LUT(1));
560         DUMP_REG(DC_DISP_SD_LUT(2));
561         DUMP_REG(DC_DISP_SD_LUT(3));
562         DUMP_REG(DC_DISP_SD_LUT(4));
563         DUMP_REG(DC_DISP_SD_LUT(5));
564         DUMP_REG(DC_DISP_SD_LUT(6));
565         DUMP_REG(DC_DISP_SD_LUT(7));
566         DUMP_REG(DC_DISP_SD_LUT(8));
567         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
568         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
569         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
570         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
571         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
572         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
573         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
574         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
575         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
576         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
577         DUMP_REG(DC_DISP_SD_BL_TF(0));
578         DUMP_REG(DC_DISP_SD_BL_TF(1));
579         DUMP_REG(DC_DISP_SD_BL_TF(2));
580         DUMP_REG(DC_DISP_SD_BL_TF(3));
581         DUMP_REG(DC_DISP_SD_BL_CONTROL);
582         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
583         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
584         DUMP_REG(DC_WIN_WIN_OPTIONS);
585         DUMP_REG(DC_WIN_BYTE_SWAP);
586         DUMP_REG(DC_WIN_BUFFER_CONTROL);
587         DUMP_REG(DC_WIN_COLOR_DEPTH);
588         DUMP_REG(DC_WIN_POSITION);
589         DUMP_REG(DC_WIN_SIZE);
590         DUMP_REG(DC_WIN_PRESCALED_SIZE);
591         DUMP_REG(DC_WIN_H_INITIAL_DDA);
592         DUMP_REG(DC_WIN_V_INITIAL_DDA);
593         DUMP_REG(DC_WIN_DDA_INC);
594         DUMP_REG(DC_WIN_LINE_STRIDE);
595         DUMP_REG(DC_WIN_BUF_STRIDE);
596         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
597         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
598         DUMP_REG(DC_WIN_DV_CONTROL);
599         DUMP_REG(DC_WIN_BLEND_NOKEY);
600         DUMP_REG(DC_WIN_BLEND_1WIN);
601         DUMP_REG(DC_WIN_BLEND_2WIN_X);
602         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
603         DUMP_REG(DC_WIN_BLEND32WIN_XY);
604         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
605         DUMP_REG(DC_WINBUF_START_ADDR);
606         DUMP_REG(DC_WINBUF_START_ADDR_NS);
607         DUMP_REG(DC_WINBUF_START_ADDR_U);
608         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
609         DUMP_REG(DC_WINBUF_START_ADDR_V);
610         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
611         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
612         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
613         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
614         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
615         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
616         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
617         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
618         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
619
620 #undef DUMP_REG
621
622         return 0;
623 }
624
625 static struct drm_info_list debugfs_files[] = {
626         { "regs", tegra_dc_show_regs, 0, NULL },
627 };
628
629 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
630 {
631         unsigned int i;
632         char *name;
633         int err;
634
635         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
636         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
637         kfree(name);
638
639         if (!dc->debugfs)
640                 return -ENOMEM;
641
642         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
643                                     GFP_KERNEL);
644         if (!dc->debugfs_files) {
645                 err = -ENOMEM;
646                 goto remove;
647         }
648
649         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
650                 dc->debugfs_files[i].data = dc;
651
652         err = drm_debugfs_create_files(dc->debugfs_files,
653                                        ARRAY_SIZE(debugfs_files),
654                                        dc->debugfs, minor);
655         if (err < 0)
656                 goto free;
657
658         dc->minor = minor;
659
660         return 0;
661
662 free:
663         kfree(dc->debugfs_files);
664         dc->debugfs_files = NULL;
665 remove:
666         debugfs_remove(dc->debugfs);
667         dc->debugfs = NULL;
668
669         return err;
670 }
671
672 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
673 {
674         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
675                                  dc->minor);
676         dc->minor = NULL;
677
678         kfree(dc->debugfs_files);
679         dc->debugfs_files = NULL;
680
681         debugfs_remove(dc->debugfs);
682         dc->debugfs = NULL;
683
684         return 0;
685 }
686
687 static int tegra_dc_drm_init(struct host1x_client *client,
688                              struct drm_device *drm)
689 {
690         struct tegra_dc *dc = host1x_client_to_dc(client);
691         int err;
692
693         dc->pipe = drm->mode_config.num_crtc;
694
695         drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
696         drm_mode_crtc_set_gamma_size(&dc->base, 256);
697         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
698
699         err = tegra_dc_rgb_init(drm, dc);
700         if (err < 0 && err != -ENODEV) {
701                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
702                 return err;
703         }
704
705         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
706                 err = tegra_dc_debugfs_init(dc, drm->primary);
707                 if (err < 0)
708                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
709         }
710
711         err = devm_request_irq(dc->dev, dc->irq, tegra_drm_irq, 0,
712                                dev_name(dc->dev), dc);
713         if (err < 0) {
714                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
715                         err);
716                 return err;
717         }
718
719         return 0;
720 }
721
722 static int tegra_dc_drm_exit(struct host1x_client *client)
723 {
724         struct tegra_dc *dc = host1x_client_to_dc(client);
725         int err;
726
727         devm_free_irq(dc->dev, dc->irq, dc);
728
729         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
730                 err = tegra_dc_debugfs_exit(dc);
731                 if (err < 0)
732                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
733         }
734
735         err = tegra_dc_rgb_exit(dc);
736         if (err) {
737                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
738                 return err;
739         }
740
741         return 0;
742 }
743
744 static const struct host1x_client_ops dc_client_ops = {
745         .drm_init = tegra_dc_drm_init,
746         .drm_exit = tegra_dc_drm_exit,
747 };
748
749 static int tegra_dc_probe(struct platform_device *pdev)
750 {
751         struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
752         struct resource *regs;
753         struct tegra_dc *dc;
754         int err;
755
756         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
757         if (!dc)
758                 return -ENOMEM;
759
760         INIT_LIST_HEAD(&dc->list);
761         mutex_init(&dc->regs_mutex);
762         dc->dev = &pdev->dev;
763
764         dc->clk = devm_clk_get(&pdev->dev, NULL);
765         if (IS_ERR(dc->clk)) {
766                 dev_err(&pdev->dev, "failed to get clock\n");
767                 return PTR_ERR(dc->clk);
768         }
769
770         err = clk_prepare_enable(dc->clk);
771         if (err < 0)
772                 return err;
773
774         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
775         if (!regs) {
776                 dev_err(&pdev->dev, "failed to get registers\n");
777                 return -ENXIO;
778         }
779
780         dc->regs = devm_request_and_ioremap(&pdev->dev, regs);
781         if (!dc->regs) {
782                 dev_err(&pdev->dev, "failed to remap registers\n");
783                 return -ENXIO;
784         }
785
786         dc->irq = platform_get_irq(pdev, 0);
787         if (dc->irq < 0) {
788                 dev_err(&pdev->dev, "failed to get IRQ\n");
789                 return -ENXIO;
790         }
791
792         INIT_LIST_HEAD(&dc->client.list);
793         dc->client.ops = &dc_client_ops;
794         dc->client.dev = &pdev->dev;
795
796         err = tegra_dc_rgb_probe(dc);
797         if (err < 0 && err != -ENODEV) {
798                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
799                 return err;
800         }
801
802         err = host1x_register_client(host1x, &dc->client);
803         if (err < 0) {
804                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
805                         err);
806                 return err;
807         }
808
809         platform_set_drvdata(pdev, dc);
810
811         return 0;
812 }
813
814 static int tegra_dc_remove(struct platform_device *pdev)
815 {
816         struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
817         struct tegra_dc *dc = platform_get_drvdata(pdev);
818         int err;
819
820         err = host1x_unregister_client(host1x, &dc->client);
821         if (err < 0) {
822                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
823                         err);
824                 return err;
825         }
826
827         clk_disable_unprepare(dc->clk);
828
829         return 0;
830 }
831
832 static struct of_device_id tegra_dc_of_match[] = {
833         { .compatible = "nvidia,tegra30-dc", },
834         { .compatible = "nvidia,tegra20-dc", },
835         { },
836 };
837
838 struct platform_driver tegra_dc_driver = {
839         .driver = {
840                 .name = "tegra-dc",
841                 .owner = THIS_MODULE,
842                 .of_match_table = tegra_dc_of_match,
843         },
844         .probe = tegra_dc_probe,
845         .remove = tegra_dc_remove,
846 };