Merge tag 'mfd-for-linus-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo...
[~shefty/rdma-dev.git] / drivers / mfd / omap-usb-host.c
1 /**
2  * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3  *
4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5  * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6  *
7  * This program is free software: you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2  of
9  * the License as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spinlock.h>
28 #include <plat/usb.h>
29 #include <linux/pm_runtime.h>
30
31 #define USBHS_DRIVER_NAME       "usbhs_omap"
32 #define OMAP_EHCI_DEVICE        "ehci-omap"
33 #define OMAP_OHCI_DEVICE        "ohci-omap3"
34
35 /* OMAP USBHOST Register addresses  */
36
37 /* TLL Register Set */
38 #define OMAP_USBTLL_REVISION                            (0x00)
39 #define OMAP_USBTLL_SYSCONFIG                           (0x10)
40 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY                 (1 << 8)
41 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE                 (1 << 3)
42 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP                 (1 << 2)
43 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET                 (1 << 1)
44 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE                  (1 << 0)
45
46 #define OMAP_USBTLL_SYSSTATUS                           (0x14)
47 #define OMAP_USBTLL_SYSSTATUS_RESETDONE                 (1 << 0)
48
49 #define OMAP_USBTLL_IRQSTATUS                           (0x18)
50 #define OMAP_USBTLL_IRQENABLE                           (0x1C)
51
52 #define OMAP_TLL_SHARED_CONF                            (0x30)
53 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN             (1 << 6)
54 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN            (1 << 5)
55 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION              (1 << 2)
56 #define OMAP_TLL_SHARED_CONF_FCLK_REQ                   (1 << 1)
57 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON                 (1 << 0)
58
59 #define OMAP_TLL_CHANNEL_CONF(num)                      (0x040 + 0x004 * num)
60 #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT            24
61 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF            (1 << 11)
62 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE         (1 << 10)
63 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE              (1 << 9)
64 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE               (1 << 8)
65 #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS             (1 << 1)
66 #define OMAP_TLL_CHANNEL_CONF_CHANEN                    (1 << 0)
67
68 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0              0x0
69 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM                0x1
70 #define OMAP_TLL_FSLSMODE_3PIN_PHY                      0x2
71 #define OMAP_TLL_FSLSMODE_4PIN_PHY                      0x3
72 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0              0x4
73 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM                0x5
74 #define OMAP_TLL_FSLSMODE_3PIN_TLL                      0x6
75 #define OMAP_TLL_FSLSMODE_4PIN_TLL                      0x7
76 #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0              0xA
77 #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM                0xB
78
79 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num)                (0x804 + 0x100 * num)
80 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num)               (0x807 + 0x100 * num)
81 #define OMAP_TLL_ULPI_OTG_CTRL(num)                     (0x80A + 0x100 * num)
82 #define OMAP_TLL_ULPI_INT_EN_RISE(num)                  (0x80D + 0x100 * num)
83 #define OMAP_TLL_ULPI_INT_EN_FALL(num)                  (0x810 + 0x100 * num)
84 #define OMAP_TLL_ULPI_INT_STATUS(num)                   (0x813 + 0x100 * num)
85 #define OMAP_TLL_ULPI_INT_LATCH(num)                    (0x814 + 0x100 * num)
86 #define OMAP_TLL_ULPI_DEBUG(num)                        (0x815 + 0x100 * num)
87 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num)             (0x816 + 0x100 * num)
88
89 #define OMAP_TLL_CHANNEL_COUNT                          3
90 #define OMAP_TLL_CHANNEL_1_EN_MASK                      (1 << 0)
91 #define OMAP_TLL_CHANNEL_2_EN_MASK                      (1 << 1)
92 #define OMAP_TLL_CHANNEL_3_EN_MASK                      (1 << 2)
93
94 /* UHH Register Set */
95 #define OMAP_UHH_REVISION                               (0x00)
96 #define OMAP_UHH_SYSCONFIG                              (0x10)
97 #define OMAP_UHH_SYSCONFIG_MIDLEMODE                    (1 << 12)
98 #define OMAP_UHH_SYSCONFIG_CACTIVITY                    (1 << 8)
99 #define OMAP_UHH_SYSCONFIG_SIDLEMODE                    (1 << 3)
100 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP                    (1 << 2)
101 #define OMAP_UHH_SYSCONFIG_SOFTRESET                    (1 << 1)
102 #define OMAP_UHH_SYSCONFIG_AUTOIDLE                     (1 << 0)
103
104 #define OMAP_UHH_SYSSTATUS                              (0x14)
105 #define OMAP_UHH_HOSTCONFIG                             (0x40)
106 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS                 (1 << 0)
107 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS              (1 << 0)
108 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS              (1 << 11)
109 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS              (1 << 12)
110 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN              (1 << 2)
111 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN              (1 << 3)
112 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN             (1 << 4)
113 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN              (1 << 5)
114 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS           (1 << 8)
115 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS           (1 << 9)
116 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS           (1 << 10)
117 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK              (1 << 31)
118
119 /* OMAP4-specific defines */
120 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR              (3 << 2)
121 #define OMAP4_UHH_SYSCONFIG_NOIDLE                      (1 << 2)
122 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR             (3 << 4)
123 #define OMAP4_UHH_SYSCONFIG_NOSTDBY                     (1 << 4)
124 #define OMAP4_UHH_SYSCONFIG_SOFTRESET                   (1 << 0)
125
126 #define OMAP4_P1_MODE_CLEAR                             (3 << 16)
127 #define OMAP4_P1_MODE_TLL                               (1 << 16)
128 #define OMAP4_P1_MODE_HSIC                              (3 << 16)
129 #define OMAP4_P2_MODE_CLEAR                             (3 << 18)
130 #define OMAP4_P2_MODE_TLL                               (1 << 18)
131 #define OMAP4_P2_MODE_HSIC                              (3 << 18)
132
133 #define OMAP_REV2_TLL_CHANNEL_COUNT                     2
134
135 #define OMAP_UHH_DEBUG_CSR                              (0x44)
136
137 /* Values of UHH_REVISION - Note: these are not given in the TRM */
138 #define OMAP_USBHS_REV1         0x00000010      /* OMAP3 */
139 #define OMAP_USBHS_REV2         0x50700100      /* OMAP4 */
140
141 #define is_omap_usbhs_rev1(x)   (x->usbhs_rev == OMAP_USBHS_REV1)
142 #define is_omap_usbhs_rev2(x)   (x->usbhs_rev == OMAP_USBHS_REV2)
143
144 #define is_ehci_phy_mode(x)     (x == OMAP_EHCI_PORT_MODE_PHY)
145 #define is_ehci_tll_mode(x)     (x == OMAP_EHCI_PORT_MODE_TLL)
146 #define is_ehci_hsic_mode(x)    (x == OMAP_EHCI_PORT_MODE_HSIC)
147
148
149 struct usbhs_hcd_omap {
150         struct clk                      *xclk60mhsp1_ck;
151         struct clk                      *xclk60mhsp2_ck;
152         struct clk                      *utmi_p1_fck;
153         struct clk                      *usbhost_p1_fck;
154         struct clk                      *usbtll_p1_fck;
155         struct clk                      *utmi_p2_fck;
156         struct clk                      *usbhost_p2_fck;
157         struct clk                      *usbtll_p2_fck;
158         struct clk                      *init_60m_fclk;
159         struct clk                      *ehci_logic_fck;
160
161         void __iomem                    *uhh_base;
162         void __iomem                    *tll_base;
163
164         struct usbhs_omap_platform_data platdata;
165
166         u32                             usbhs_rev;
167         spinlock_t                      lock;
168 };
169 /*-------------------------------------------------------------------------*/
170
171 const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
172 static u64 usbhs_dmamask = DMA_BIT_MASK(32);
173
174 /*-------------------------------------------------------------------------*/
175
176 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
177 {
178         __raw_writel(val, base + reg);
179 }
180
181 static inline u32 usbhs_read(void __iomem *base, u32 reg)
182 {
183         return __raw_readl(base + reg);
184 }
185
186 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
187 {
188         __raw_writeb(val, base + reg);
189 }
190
191 static inline u8 usbhs_readb(void __iomem *base, u8 reg)
192 {
193         return __raw_readb(base + reg);
194 }
195
196 /*-------------------------------------------------------------------------*/
197
198 static struct platform_device *omap_usbhs_alloc_child(const char *name,
199                         struct resource *res, int num_resources, void *pdata,
200                         size_t pdata_size, struct device *dev)
201 {
202         struct platform_device  *child;
203         int                     ret;
204
205         child = platform_device_alloc(name, 0);
206
207         if (!child) {
208                 dev_err(dev, "platform_device_alloc %s failed\n", name);
209                 goto err_end;
210         }
211
212         ret = platform_device_add_resources(child, res, num_resources);
213         if (ret) {
214                 dev_err(dev, "platform_device_add_resources failed\n");
215                 goto err_alloc;
216         }
217
218         ret = platform_device_add_data(child, pdata, pdata_size);
219         if (ret) {
220                 dev_err(dev, "platform_device_add_data failed\n");
221                 goto err_alloc;
222         }
223
224         child->dev.dma_mask             = &usbhs_dmamask;
225         dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
226         child->dev.parent               = dev;
227
228         ret = platform_device_add(child);
229         if (ret) {
230                 dev_err(dev, "platform_device_add failed\n");
231                 goto err_alloc;
232         }
233
234         return child;
235
236 err_alloc:
237         platform_device_put(child);
238
239 err_end:
240         return NULL;
241 }
242
243 static int omap_usbhs_alloc_children(struct platform_device *pdev)
244 {
245         struct device                           *dev = &pdev->dev;
246         struct usbhs_hcd_omap                   *omap;
247         struct ehci_hcd_omap_platform_data      *ehci_data;
248         struct ohci_hcd_omap_platform_data      *ohci_data;
249         struct platform_device                  *ehci;
250         struct platform_device                  *ohci;
251         struct resource                         *res;
252         struct resource                         resources[2];
253         int                                     ret;
254
255         omap = platform_get_drvdata(pdev);
256         ehci_data = omap->platdata.ehci_data;
257         ohci_data = omap->platdata.ohci_data;
258
259         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
260         if (!res) {
261                 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
262                 ret = -ENODEV;
263                 goto err_end;
264         }
265         resources[0] = *res;
266
267         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
268         if (!res) {
269                 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
270                 ret = -ENODEV;
271                 goto err_end;
272         }
273         resources[1] = *res;
274
275         ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
276                 sizeof(*ehci_data), dev);
277
278         if (!ehci) {
279                 dev_err(dev, "omap_usbhs_alloc_child failed\n");
280                 ret = -ENOMEM;
281                 goto err_end;
282         }
283
284         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
285         if (!res) {
286                 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
287                 ret = -ENODEV;
288                 goto err_ehci;
289         }
290         resources[0] = *res;
291
292         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
293         if (!res) {
294                 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
295                 ret = -ENODEV;
296                 goto err_ehci;
297         }
298         resources[1] = *res;
299
300         ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
301                 sizeof(*ohci_data), dev);
302         if (!ohci) {
303                 dev_err(dev, "omap_usbhs_alloc_child failed\n");
304                 ret = -ENOMEM;
305                 goto err_ehci;
306         }
307
308         return 0;
309
310 err_ehci:
311         platform_device_unregister(ehci);
312
313 err_end:
314         return ret;
315 }
316
317 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
318 {
319         switch (pmode) {
320         case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
321         case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
322         case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
323         case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
324         case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
325         case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
326         case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
327         case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
328         case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
329         case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
330                 return true;
331
332         default:
333                 return false;
334         }
335 }
336
337 /*
338  * convert the port-mode enum to a value we can use in the FSLSMODE
339  * field of USBTLL_CHANNEL_CONF
340  */
341 static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
342 {
343         switch (mode) {
344         case OMAP_USBHS_PORT_MODE_UNUSED:
345         case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
346                 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
347
348         case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
349                 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
350
351         case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
352                 return OMAP_TLL_FSLSMODE_3PIN_PHY;
353
354         case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
355                 return OMAP_TLL_FSLSMODE_4PIN_PHY;
356
357         case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
358                 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
359
360         case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
361                 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
362
363         case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
364                 return OMAP_TLL_FSLSMODE_3PIN_TLL;
365
366         case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
367                 return OMAP_TLL_FSLSMODE_4PIN_TLL;
368
369         case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
370                 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
371
372         case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
373                 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
374         default:
375                 pr_warning("Invalid port mode, using default\n");
376                 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
377         }
378 }
379
380 static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
381 {
382         struct usbhs_hcd_omap           *omap = dev_get_drvdata(dev);
383         struct usbhs_omap_platform_data *pdata = dev->platform_data;
384         unsigned                        reg;
385         int                             i;
386
387         /* Program Common TLL register */
388         reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF);
389         reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
390                 | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
391         reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
392         reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
393
394         usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
395
396         /* Enable channels now */
397         for (i = 0; i < tll_channel_count; i++) {
398                 reg = usbhs_read(omap->tll_base,
399                                 OMAP_TLL_CHANNEL_CONF(i));
400
401                 if (is_ohci_port(pdata->port_mode[i])) {
402                         reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
403                                 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
404                         reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
405                 } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) {
406
407                         /* Disable AutoIdle, BitStuffing and use SDR Mode */
408                         reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
409                                 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
410                                 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
411
412                 } else
413                         continue;
414
415                 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
416                 usbhs_write(omap->tll_base,
417                                 OMAP_TLL_CHANNEL_CONF(i), reg);
418
419                 usbhs_writeb(omap->tll_base,
420                                 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
421         }
422 }
423
424 static int usbhs_runtime_resume(struct device *dev)
425 {
426         struct usbhs_hcd_omap           *omap = dev_get_drvdata(dev);
427         struct usbhs_omap_platform_data *pdata = &omap->platdata;
428         unsigned long                   flags;
429
430         dev_dbg(dev, "usbhs_runtime_resume\n");
431
432         if (!pdata) {
433                 dev_dbg(dev, "missing platform_data\n");
434                 return  -ENODEV;
435         }
436
437         spin_lock_irqsave(&omap->lock, flags);
438
439         if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
440                 clk_enable(omap->ehci_logic_fck);
441
442         if (is_ehci_tll_mode(pdata->port_mode[0])) {
443                 clk_enable(omap->usbhost_p1_fck);
444                 clk_enable(omap->usbtll_p1_fck);
445         }
446         if (is_ehci_tll_mode(pdata->port_mode[1])) {
447                 clk_enable(omap->usbhost_p2_fck);
448                 clk_enable(omap->usbtll_p2_fck);
449         }
450         clk_enable(omap->utmi_p1_fck);
451         clk_enable(omap->utmi_p2_fck);
452
453         spin_unlock_irqrestore(&omap->lock, flags);
454
455         return 0;
456 }
457
458 static int usbhs_runtime_suspend(struct device *dev)
459 {
460         struct usbhs_hcd_omap           *omap = dev_get_drvdata(dev);
461         struct usbhs_omap_platform_data *pdata = &omap->platdata;
462         unsigned long                   flags;
463
464         dev_dbg(dev, "usbhs_runtime_suspend\n");
465
466         if (!pdata) {
467                 dev_dbg(dev, "missing platform_data\n");
468                 return  -ENODEV;
469         }
470
471         spin_lock_irqsave(&omap->lock, flags);
472
473         if (is_ehci_tll_mode(pdata->port_mode[0])) {
474                 clk_disable(omap->usbhost_p1_fck);
475                 clk_disable(omap->usbtll_p1_fck);
476         }
477         if (is_ehci_tll_mode(pdata->port_mode[1])) {
478                 clk_disable(omap->usbhost_p2_fck);
479                 clk_disable(omap->usbtll_p2_fck);
480         }
481         clk_disable(omap->utmi_p2_fck);
482         clk_disable(omap->utmi_p1_fck);
483
484         if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
485                 clk_disable(omap->ehci_logic_fck);
486
487         spin_unlock_irqrestore(&omap->lock, flags);
488
489         return 0;
490 }
491
492 static void omap_usbhs_init(struct device *dev)
493 {
494         struct usbhs_hcd_omap           *omap = dev_get_drvdata(dev);
495         struct usbhs_omap_platform_data *pdata = &omap->platdata;
496         unsigned long                   flags;
497         unsigned                        reg;
498
499         dev_dbg(dev, "starting TI HSUSB Controller\n");
500
501         pm_runtime_get_sync(dev);
502         spin_lock_irqsave(&omap->lock, flags);
503
504         omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
505         dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
506
507         reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
508         /* setup ULPI bypass and burst configurations */
509         reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
510                         | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
511                         | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
512         reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
513         reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
514
515         if (is_omap_usbhs_rev1(omap)) {
516                 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
517                         reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
518                 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
519                         reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
520                 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
521                         reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
522
523                 /* Bypass the TLL module for PHY mode operation */
524                 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
525                         dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
526                         if (is_ehci_phy_mode(pdata->port_mode[0]) ||
527                                 is_ehci_phy_mode(pdata->port_mode[1]) ||
528                                         is_ehci_phy_mode(pdata->port_mode[2]))
529                                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
530                         else
531                                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
532                 } else {
533                         dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
534                         if (is_ehci_phy_mode(pdata->port_mode[0]))
535                                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
536                         else
537                                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
538                         if (is_ehci_phy_mode(pdata->port_mode[1]))
539                                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
540                         else
541                                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
542                         if (is_ehci_phy_mode(pdata->port_mode[2]))
543                                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
544                         else
545                                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
546                 }
547         } else if (is_omap_usbhs_rev2(omap)) {
548                 /* Clear port mode fields for PHY mode*/
549                 reg &= ~OMAP4_P1_MODE_CLEAR;
550                 reg &= ~OMAP4_P2_MODE_CLEAR;
551
552                 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
553                         (is_ohci_port(pdata->port_mode[0])))
554                         reg |= OMAP4_P1_MODE_TLL;
555                 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
556                         reg |= OMAP4_P1_MODE_HSIC;
557
558                 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
559                         (is_ohci_port(pdata->port_mode[1])))
560                         reg |= OMAP4_P2_MODE_TLL;
561                 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
562                         reg |= OMAP4_P2_MODE_HSIC;
563         }
564
565         usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
566         dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
567
568         if (is_ehci_tll_mode(pdata->port_mode[0]) ||
569                 is_ehci_tll_mode(pdata->port_mode[1]) ||
570                 is_ehci_tll_mode(pdata->port_mode[2]) ||
571                 (is_ohci_port(pdata->port_mode[0])) ||
572                 (is_ohci_port(pdata->port_mode[1])) ||
573                 (is_ohci_port(pdata->port_mode[2]))) {
574
575                 /* Enable UTMI mode for required TLL channels */
576                 if (is_omap_usbhs_rev2(omap))
577                         usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT);
578                 else
579                         usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT);
580         }
581
582         spin_unlock_irqrestore(&omap->lock, flags);
583         pm_runtime_put_sync(dev);
584 }
585
586
587 /**
588  * usbhs_omap_probe - initialize TI-based HCDs
589  *
590  * Allocates basic resources for this USB host controller.
591  */
592 static int __devinit usbhs_omap_probe(struct platform_device *pdev)
593 {
594         struct device                   *dev =  &pdev->dev;
595         struct usbhs_omap_platform_data *pdata = dev->platform_data;
596         struct usbhs_hcd_omap           *omap;
597         struct resource                 *res;
598         int                             ret = 0;
599         int                             i;
600
601         if (!pdata) {
602                 dev_err(dev, "Missing platform data\n");
603                 ret = -ENOMEM;
604                 goto end_probe;
605         }
606
607         omap = kzalloc(sizeof(*omap), GFP_KERNEL);
608         if (!omap) {
609                 dev_err(dev, "Memory allocation failed\n");
610                 ret = -ENOMEM;
611                 goto end_probe;
612         }
613
614         spin_lock_init(&omap->lock);
615
616         for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
617                 omap->platdata.port_mode[i] = pdata->port_mode[i];
618
619         omap->platdata.ehci_data = pdata->ehci_data;
620         omap->platdata.ohci_data = pdata->ohci_data;
621
622         pm_runtime_enable(dev);
623
624
625         for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
626                 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
627                         is_ehci_hsic_mode(i)) {
628                         omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
629                         if (IS_ERR(omap->ehci_logic_fck)) {
630                                 ret = PTR_ERR(omap->ehci_logic_fck);
631                                 dev_warn(dev, "ehci_logic_fck failed:%d\n",
632                                          ret);
633                         }
634                         break;
635                 }
636
637         omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
638         if (IS_ERR(omap->utmi_p1_fck)) {
639                 ret = PTR_ERR(omap->utmi_p1_fck);
640                 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
641                 goto err_end;
642         }
643
644         omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
645         if (IS_ERR(omap->xclk60mhsp1_ck)) {
646                 ret = PTR_ERR(omap->xclk60mhsp1_ck);
647                 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
648                 goto err_utmi_p1_fck;
649         }
650
651         omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
652         if (IS_ERR(omap->utmi_p2_fck)) {
653                 ret = PTR_ERR(omap->utmi_p2_fck);
654                 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
655                 goto err_xclk60mhsp1_ck;
656         }
657
658         omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
659         if (IS_ERR(omap->xclk60mhsp2_ck)) {
660                 ret = PTR_ERR(omap->xclk60mhsp2_ck);
661                 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
662                 goto err_utmi_p2_fck;
663         }
664
665         omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
666         if (IS_ERR(omap->usbhost_p1_fck)) {
667                 ret = PTR_ERR(omap->usbhost_p1_fck);
668                 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
669                 goto err_xclk60mhsp2_ck;
670         }
671
672         omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
673         if (IS_ERR(omap->usbtll_p1_fck)) {
674                 ret = PTR_ERR(omap->usbtll_p1_fck);
675                 dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
676                 goto err_usbhost_p1_fck;
677         }
678
679         omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
680         if (IS_ERR(omap->usbhost_p2_fck)) {
681                 ret = PTR_ERR(omap->usbhost_p2_fck);
682                 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
683                 goto err_usbtll_p1_fck;
684         }
685
686         omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
687         if (IS_ERR(omap->usbtll_p2_fck)) {
688                 ret = PTR_ERR(omap->usbtll_p2_fck);
689                 dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
690                 goto err_usbhost_p2_fck;
691         }
692
693         omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
694         if (IS_ERR(omap->init_60m_fclk)) {
695                 ret = PTR_ERR(omap->init_60m_fclk);
696                 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
697                 goto err_usbtll_p2_fck;
698         }
699
700         if (is_ehci_phy_mode(pdata->port_mode[0])) {
701                 /* for OMAP3 , the clk set paretn fails */
702                 ret = clk_set_parent(omap->utmi_p1_fck,
703                                         omap->xclk60mhsp1_ck);
704                 if (ret != 0)
705                         dev_err(dev, "xclk60mhsp1_ck set parent"
706                                 "failed error:%d\n", ret);
707         } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
708                 ret = clk_set_parent(omap->utmi_p1_fck,
709                                         omap->init_60m_fclk);
710                 if (ret != 0)
711                         dev_err(dev, "init_60m_fclk set parent"
712                                 "failed error:%d\n", ret);
713         }
714
715         if (is_ehci_phy_mode(pdata->port_mode[1])) {
716                 ret = clk_set_parent(omap->utmi_p2_fck,
717                                         omap->xclk60mhsp2_ck);
718                 if (ret != 0)
719                         dev_err(dev, "xclk60mhsp2_ck set parent"
720                                         "failed error:%d\n", ret);
721         } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
722                 ret = clk_set_parent(omap->utmi_p2_fck,
723                                                 omap->init_60m_fclk);
724                 if (ret != 0)
725                         dev_err(dev, "init_60m_fclk set parent"
726                                 "failed error:%d\n", ret);
727         }
728
729         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
730         if (!res) {
731                 dev_err(dev, "UHH EHCI get resource failed\n");
732                 ret = -ENODEV;
733                 goto err_init_60m_fclk;
734         }
735
736         omap->uhh_base = ioremap(res->start, resource_size(res));
737         if (!omap->uhh_base) {
738                 dev_err(dev, "UHH ioremap failed\n");
739                 ret = -ENOMEM;
740                 goto err_init_60m_fclk;
741         }
742
743         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
744         if (!res) {
745                 dev_err(dev, "UHH EHCI get resource failed\n");
746                 ret = -ENODEV;
747                 goto err_tll;
748         }
749
750         omap->tll_base = ioremap(res->start, resource_size(res));
751         if (!omap->tll_base) {
752                 dev_err(dev, "TLL ioremap failed\n");
753                 ret = -ENOMEM;
754                 goto err_tll;
755         }
756
757         platform_set_drvdata(pdev, omap);
758
759         omap_usbhs_init(dev);
760         ret = omap_usbhs_alloc_children(pdev);
761         if (ret) {
762                 dev_err(dev, "omap_usbhs_alloc_children failed\n");
763                 goto err_alloc;
764         }
765
766         goto end_probe;
767
768 err_alloc:
769         iounmap(omap->tll_base);
770
771 err_tll:
772         iounmap(omap->uhh_base);
773
774 err_init_60m_fclk:
775         clk_put(omap->init_60m_fclk);
776
777 err_usbtll_p2_fck:
778         clk_put(omap->usbtll_p2_fck);
779
780 err_usbhost_p2_fck:
781         clk_put(omap->usbhost_p2_fck);
782
783 err_usbtll_p1_fck:
784         clk_put(omap->usbtll_p1_fck);
785
786 err_usbhost_p1_fck:
787         clk_put(omap->usbhost_p1_fck);
788
789 err_xclk60mhsp2_ck:
790         clk_put(omap->xclk60mhsp2_ck);
791
792 err_utmi_p2_fck:
793         clk_put(omap->utmi_p2_fck);
794
795 err_xclk60mhsp1_ck:
796         clk_put(omap->xclk60mhsp1_ck);
797
798 err_utmi_p1_fck:
799         clk_put(omap->utmi_p1_fck);
800
801 err_end:
802         clk_put(omap->ehci_logic_fck);
803         pm_runtime_disable(dev);
804         kfree(omap);
805
806 end_probe:
807         return ret;
808 }
809
810 /**
811  * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
812  * @pdev: USB Host Controller being removed
813  *
814  * Reverses the effect of usbhs_omap_probe().
815  */
816 static int __devexit usbhs_omap_remove(struct platform_device *pdev)
817 {
818         struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
819
820         iounmap(omap->tll_base);
821         iounmap(omap->uhh_base);
822         clk_put(omap->init_60m_fclk);
823         clk_put(omap->usbtll_p2_fck);
824         clk_put(omap->usbhost_p2_fck);
825         clk_put(omap->usbtll_p1_fck);
826         clk_put(omap->usbhost_p1_fck);
827         clk_put(omap->xclk60mhsp2_ck);
828         clk_put(omap->utmi_p2_fck);
829         clk_put(omap->xclk60mhsp1_ck);
830         clk_put(omap->utmi_p1_fck);
831         clk_put(omap->ehci_logic_fck);
832         pm_runtime_disable(&pdev->dev);
833         kfree(omap);
834
835         return 0;
836 }
837
838 static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
839         .runtime_suspend        = usbhs_runtime_suspend,
840         .runtime_resume         = usbhs_runtime_resume,
841 };
842
843 static struct platform_driver usbhs_omap_driver = {
844         .driver = {
845                 .name           = (char *)usbhs_driver_name,
846                 .owner          = THIS_MODULE,
847                 .pm             = &usbhsomap_dev_pm_ops,
848         },
849         .remove         = __exit_p(usbhs_omap_remove),
850 };
851
852 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
853 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
854 MODULE_LICENSE("GPL v2");
855 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
856
857 static int __init omap_usbhs_drvinit(void)
858 {
859         return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
860 }
861
862 /*
863  * init before ehci and ohci drivers;
864  * The usbhs core driver should be initialized much before
865  * the omap ehci and ohci probe functions are called.
866  */
867 fs_initcall(omap_usbhs_drvinit);
868
869 static void __exit omap_usbhs_drvexit(void)
870 {
871         platform_driver_unregister(&usbhs_omap_driver);
872 }
873 module_exit(omap_usbhs_drvexit);