Merge tag 'mmc-updates-for-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel...
[~shefty/rdma-dev.git] / drivers / mmc / host / mvsdio.c
1 /*
2  * Marvell MMC/SD/SDIO driver
3  *
4  * Authors: Maen Suleiman, Nicolas Pitre
5  * Copyright (C) 2008-2009 Marvell Ltd.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/platform_device.h>
16 #include <linux/mbus.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21 #include <linux/irq.h>
22 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <linux/of_gpio.h>
25 #include <linux/of_irq.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/pinctrl/consumer.h>
29
30 #include <asm/sizes.h>
31 #include <asm/unaligned.h>
32 #include <linux/platform_data/mmc-mvsdio.h>
33
34 #include "mvsdio.h"
35
36 #define DRIVER_NAME     "mvsdio"
37
38 static int maxfreq = MVSD_CLOCKRATE_MAX;
39 static int nodma;
40
41 struct mvsd_host {
42         void __iomem *base;
43         struct mmc_request *mrq;
44         spinlock_t lock;
45         unsigned int xfer_mode;
46         unsigned int intr_en;
47         unsigned int ctrl;
48         unsigned int pio_size;
49         void *pio_ptr;
50         unsigned int sg_frags;
51         unsigned int ns_per_clk;
52         unsigned int clock;
53         unsigned int base_clock;
54         struct timer_list timer;
55         struct mmc_host *mmc;
56         struct device *dev;
57         struct clk *clk;
58 };
59
60 #define mvsd_write(offs, val)   writel(val, iobase + (offs))
61 #define mvsd_read(offs)         readl(iobase + (offs))
62
63 static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
64 {
65         void __iomem *iobase = host->base;
66         unsigned int tmout;
67         int tmout_index;
68
69         /*
70          * Hardware weirdness.  The FIFO_EMPTY bit of the HW_STATE
71          * register is sometimes not set before a while when some
72          * "unusual" data block sizes are used (such as with the SWITCH
73          * command), even despite the fact that the XFER_DONE interrupt
74          * was raised.  And if another data transfer starts before
75          * this bit comes to good sense (which eventually happens by
76          * itself) then the new transfer simply fails with a timeout.
77          */
78         if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
79                 unsigned long t = jiffies + HZ;
80                 unsigned int hw_state,  count = 0;
81                 do {
82                         if (time_after(jiffies, t)) {
83                                 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
84                                 break;
85                         }
86                         hw_state = mvsd_read(MVSD_HW_STATE);
87                         count++;
88                 } while (!(hw_state & (1 << 13)));
89                 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
90                                    "(hw=0x%04x, count=%d, jiffies=%ld)\n",
91                                    hw_state, count, jiffies - (t - HZ));
92         }
93
94         /* If timeout=0 then maximum timeout index is used. */
95         tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
96         tmout += data->timeout_clks;
97         tmout_index = fls(tmout - 1) - 12;
98         if (tmout_index < 0)
99                 tmout_index = 0;
100         if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
101                 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
102
103         dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
104                 (data->flags & MMC_DATA_READ) ? "read" : "write",
105                 (u32)sg_virt(data->sg), data->blocks, data->blksz,
106                 tmout, tmout_index);
107
108         host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
109         host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
110         mvsd_write(MVSD_HOST_CTRL, host->ctrl);
111         mvsd_write(MVSD_BLK_COUNT, data->blocks);
112         mvsd_write(MVSD_BLK_SIZE, data->blksz);
113
114         if (nodma || (data->blksz | data->sg->offset) & 3) {
115                 /*
116                  * We cannot do DMA on a buffer which offset or size
117                  * is not aligned on a 4-byte boundary.
118                  */
119                 host->pio_size = data->blocks * data->blksz;
120                 host->pio_ptr = sg_virt(data->sg);
121                 if (!nodma)
122                         pr_debug("%s: fallback to PIO for data "
123                                           "at 0x%p size %d\n",
124                                           mmc_hostname(host->mmc),
125                                           host->pio_ptr, host->pio_size);
126                 return 1;
127         } else {
128                 dma_addr_t phys_addr;
129                 int dma_dir = (data->flags & MMC_DATA_READ) ?
130                         DMA_FROM_DEVICE : DMA_TO_DEVICE;
131                 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
132                                             data->sg_len, dma_dir);
133                 phys_addr = sg_dma_address(data->sg);
134                 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
135                 mvsd_write(MVSD_SYS_ADDR_HI,  (u32)phys_addr >> 16);
136                 return 0;
137         }
138 }
139
140 static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
141 {
142         struct mvsd_host *host = mmc_priv(mmc);
143         void __iomem *iobase = host->base;
144         struct mmc_command *cmd = mrq->cmd;
145         u32 cmdreg = 0, xfer = 0, intr = 0;
146         unsigned long flags;
147
148         BUG_ON(host->mrq != NULL);
149         host->mrq = mrq;
150
151         dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
152                 cmd->opcode, mvsd_read(MVSD_HW_STATE));
153
154         cmdreg = MVSD_CMD_INDEX(cmd->opcode);
155
156         if (cmd->flags & MMC_RSP_BUSY)
157                 cmdreg |= MVSD_CMD_RSP_48BUSY;
158         else if (cmd->flags & MMC_RSP_136)
159                 cmdreg |= MVSD_CMD_RSP_136;
160         else if (cmd->flags & MMC_RSP_PRESENT)
161                 cmdreg |= MVSD_CMD_RSP_48;
162         else
163                 cmdreg |= MVSD_CMD_RSP_NONE;
164
165         if (cmd->flags & MMC_RSP_CRC)
166                 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
167
168         if (cmd->flags & MMC_RSP_OPCODE)
169                 cmdreg |= MVSD_CMD_INDX_CHECK;
170
171         if (cmd->flags & MMC_RSP_PRESENT) {
172                 cmdreg |= MVSD_UNEXPECTED_RESP;
173                 intr |= MVSD_NOR_UNEXP_RSP;
174         }
175
176         if (mrq->data) {
177                 struct mmc_data *data = mrq->data;
178                 int pio;
179
180                 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
181                 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
182                 if (data->flags & MMC_DATA_READ)
183                         xfer |= MVSD_XFER_MODE_TO_HOST;
184
185                 pio = mvsd_setup_data(host, data);
186                 if (pio) {
187                         xfer |= MVSD_XFER_MODE_PIO;
188                         /* PIO section of mvsd_irq has comments on those bits */
189                         if (data->flags & MMC_DATA_WRITE)
190                                 intr |= MVSD_NOR_TX_AVAIL;
191                         else if (host->pio_size > 32)
192                                 intr |= MVSD_NOR_RX_FIFO_8W;
193                         else
194                                 intr |= MVSD_NOR_RX_READY;
195                 }
196
197                 if (data->stop) {
198                         struct mmc_command *stop = data->stop;
199                         u32 cmd12reg = 0;
200
201                         mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
202                         mvsd_write(MVSD_AUTOCMD12_ARG_HI,  stop->arg >> 16);
203
204                         if (stop->flags & MMC_RSP_BUSY)
205                                 cmd12reg |= MVSD_AUTOCMD12_BUSY;
206                         if (stop->flags & MMC_RSP_OPCODE)
207                                 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
208                         cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
209                         mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
210
211                         xfer |= MVSD_XFER_MODE_AUTO_CMD12;
212                         intr |= MVSD_NOR_AUTOCMD12_DONE;
213                 } else {
214                         intr |= MVSD_NOR_XFER_DONE;
215                 }
216         } else {
217                 intr |= MVSD_NOR_CMD_DONE;
218         }
219
220         mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
221         mvsd_write(MVSD_ARG_HI,  cmd->arg >> 16);
222
223         spin_lock_irqsave(&host->lock, flags);
224
225         host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
226         host->xfer_mode |= xfer;
227         mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
228
229         mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
230         mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
231         mvsd_write(MVSD_CMD, cmdreg);
232
233         host->intr_en &= MVSD_NOR_CARD_INT;
234         host->intr_en |= intr | MVSD_NOR_ERROR;
235         mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
236         mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
237
238         mod_timer(&host->timer, jiffies + 5 * HZ);
239
240         spin_unlock_irqrestore(&host->lock, flags);
241 }
242
243 static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
244                            u32 err_status)
245 {
246         void __iomem *iobase = host->base;
247
248         if (cmd->flags & MMC_RSP_136) {
249                 unsigned int response[8], i;
250                 for (i = 0; i < 8; i++)
251                         response[i] = mvsd_read(MVSD_RSP(i));
252                 cmd->resp[0] =          ((response[0] & 0x03ff) << 22) |
253                                         ((response[1] & 0xffff) << 6) |
254                                         ((response[2] & 0xfc00) >> 10);
255                 cmd->resp[1] =          ((response[2] & 0x03ff) << 22) |
256                                         ((response[3] & 0xffff) << 6) |
257                                         ((response[4] & 0xfc00) >> 10);
258                 cmd->resp[2] =          ((response[4] & 0x03ff) << 22) |
259                                         ((response[5] & 0xffff) << 6) |
260                                         ((response[6] & 0xfc00) >> 10);
261                 cmd->resp[3] =          ((response[6] & 0x03ff) << 22) |
262                                         ((response[7] & 0x3fff) << 8);
263         } else if (cmd->flags & MMC_RSP_PRESENT) {
264                 unsigned int response[3], i;
265                 for (i = 0; i < 3; i++)
266                         response[i] = mvsd_read(MVSD_RSP(i));
267                 cmd->resp[0] =          ((response[2] & 0x003f) << (8 - 8)) |
268                                         ((response[1] & 0xffff) << (14 - 8)) |
269                                         ((response[0] & 0x03ff) << (30 - 8));
270                 cmd->resp[1] =          ((response[0] & 0xfc00) >> 10);
271                 cmd->resp[2] = 0;
272                 cmd->resp[3] = 0;
273         }
274
275         if (err_status & MVSD_ERR_CMD_TIMEOUT) {
276                 cmd->error = -ETIMEDOUT;
277         } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
278                                  MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
279                 cmd->error = -EILSEQ;
280         }
281         err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
282                         MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
283                         MVSD_ERR_CMD_STARTBIT);
284
285         return err_status;
286 }
287
288 static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
289                             u32 err_status)
290 {
291         void __iomem *iobase = host->base;
292
293         if (host->pio_ptr) {
294                 host->pio_ptr = NULL;
295                 host->pio_size = 0;
296         } else {
297                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
298                              (data->flags & MMC_DATA_READ) ?
299                                 DMA_FROM_DEVICE : DMA_TO_DEVICE);
300         }
301
302         if (err_status & MVSD_ERR_DATA_TIMEOUT)
303                 data->error = -ETIMEDOUT;
304         else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
305                 data->error = -EILSEQ;
306         else if (err_status & MVSD_ERR_XFER_SIZE)
307                 data->error = -EBADE;
308         err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
309                         MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
310
311         dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
312                 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
313         data->bytes_xfered =
314                 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
315         /* We can't be sure about the last block when errors are detected */
316         if (data->bytes_xfered && data->error)
317                 data->bytes_xfered -= data->blksz;
318
319         /* Handle Auto cmd 12 response */
320         if (data->stop) {
321                 unsigned int response[3], i;
322                 for (i = 0; i < 3; i++)
323                         response[i] = mvsd_read(MVSD_AUTO_RSP(i));
324                 data->stop->resp[0] =   ((response[2] & 0x003f) << (8 - 8)) |
325                                         ((response[1] & 0xffff) << (14 - 8)) |
326                                         ((response[0] & 0x03ff) << (30 - 8));
327                 data->stop->resp[1] =   ((response[0] & 0xfc00) >> 10);
328                 data->stop->resp[2] = 0;
329                 data->stop->resp[3] = 0;
330
331                 if (err_status & MVSD_ERR_AUTOCMD12) {
332                         u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
333                         dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
334                         if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
335                                 data->stop->error = -ENOEXEC;
336                         else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
337                                 data->stop->error = -ETIMEDOUT;
338                         else if (err_cmd12)
339                                 data->stop->error = -EILSEQ;
340                         err_status &= ~MVSD_ERR_AUTOCMD12;
341                 }
342         }
343
344         return err_status;
345 }
346
347 static irqreturn_t mvsd_irq(int irq, void *dev)
348 {
349         struct mvsd_host *host = dev;
350         void __iomem *iobase = host->base;
351         u32 intr_status, intr_done_mask;
352         int irq_handled = 0;
353
354         intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
355         dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
356                 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
357                 mvsd_read(MVSD_HW_STATE));
358
359         spin_lock(&host->lock);
360
361         /* PIO handling, if needed. Messy business... */
362         if (host->pio_size &&
363             (intr_status & host->intr_en &
364              (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
365                 u16 *p = host->pio_ptr;
366                 int s = host->pio_size;
367                 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
368                         readsw(iobase + MVSD_FIFO, p, 16);
369                         p += 16;
370                         s -= 32;
371                         intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
372                 }
373                 /*
374                  * Normally we'd use < 32 here, but the RX_FIFO_8W bit
375                  * doesn't appear to assert when there is exactly 32 bytes
376                  * (8 words) left to fetch in a transfer.
377                  */
378                 if (s <= 32) {
379                         while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
380                                 put_unaligned(mvsd_read(MVSD_FIFO), p++);
381                                 put_unaligned(mvsd_read(MVSD_FIFO), p++);
382                                 s -= 4;
383                                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
384                         }
385                         if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
386                                 u16 val[2] = {0, 0};
387                                 val[0] = mvsd_read(MVSD_FIFO);
388                                 val[1] = mvsd_read(MVSD_FIFO);
389                                 memcpy(p, ((void *)&val) + 4 - s, s);
390                                 s = 0;
391                                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
392                         }
393                         if (s == 0) {
394                                 host->intr_en &=
395                                      ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
396                                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
397                         } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
398                                 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
399                                 host->intr_en |= MVSD_NOR_RX_READY;
400                                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
401                         }
402                 }
403                 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
404                         s, intr_status, mvsd_read(MVSD_HW_STATE));
405                 host->pio_ptr = p;
406                 host->pio_size = s;
407                 irq_handled = 1;
408         } else if (host->pio_size &&
409                    (intr_status & host->intr_en &
410                     (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
411                 u16 *p = host->pio_ptr;
412                 int s = host->pio_size;
413                 /*
414                  * The TX_FIFO_8W bit is unreliable. When set, bursting
415                  * 16 halfwords all at once in the FIFO drops data. Actually
416                  * TX_AVAIL does go off after only one word is pushed even if
417                  * TX_FIFO_8W remains set.
418                  */
419                 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
420                         mvsd_write(MVSD_FIFO, get_unaligned(p++));
421                         mvsd_write(MVSD_FIFO, get_unaligned(p++));
422                         s -= 4;
423                         intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
424                 }
425                 if (s < 4) {
426                         if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
427                                 u16 val[2] = {0, 0};
428                                 memcpy(((void *)&val) + 4 - s, p, s);
429                                 mvsd_write(MVSD_FIFO, val[0]);
430                                 mvsd_write(MVSD_FIFO, val[1]);
431                                 s = 0;
432                                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
433                         }
434                         if (s == 0) {
435                                 host->intr_en &=
436                                      ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
437                                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
438                         }
439                 }
440                 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
441                         s, intr_status, mvsd_read(MVSD_HW_STATE));
442                 host->pio_ptr = p;
443                 host->pio_size = s;
444                 irq_handled = 1;
445         }
446
447         mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
448
449         intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
450                          MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
451         if (intr_status & host->intr_en & ~intr_done_mask) {
452                 struct mmc_request *mrq = host->mrq;
453                 struct mmc_command *cmd = mrq->cmd;
454                 u32 err_status = 0;
455
456                 del_timer(&host->timer);
457                 host->mrq = NULL;
458
459                 host->intr_en &= MVSD_NOR_CARD_INT;
460                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
461                 mvsd_write(MVSD_ERR_INTR_EN, 0);
462
463                 spin_unlock(&host->lock);
464
465                 if (intr_status & MVSD_NOR_UNEXP_RSP) {
466                         cmd->error = -EPROTO;
467                 } else if (intr_status & MVSD_NOR_ERROR) {
468                         err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
469                         dev_dbg(host->dev, "err 0x%04x\n", err_status);
470                 }
471
472                 err_status = mvsd_finish_cmd(host, cmd, err_status);
473                 if (mrq->data)
474                         err_status = mvsd_finish_data(host, mrq->data, err_status);
475                 if (err_status) {
476                         pr_err("%s: unhandled error status %#04x\n",
477                                         mmc_hostname(host->mmc), err_status);
478                         cmd->error = -ENOMSG;
479                 }
480
481                 mmc_request_done(host->mmc, mrq);
482                 irq_handled = 1;
483         } else
484                 spin_unlock(&host->lock);
485
486         if (intr_status & MVSD_NOR_CARD_INT) {
487                 mmc_signal_sdio_irq(host->mmc);
488                 irq_handled = 1;
489         }
490
491         if (irq_handled)
492                 return IRQ_HANDLED;
493
494         pr_err("%s: unhandled interrupt status=0x%04x en=0x%04x "
495                         "pio=%d\n", mmc_hostname(host->mmc), intr_status,
496                         host->intr_en, host->pio_size);
497         return IRQ_NONE;
498 }
499
500 static void mvsd_timeout_timer(unsigned long data)
501 {
502         struct mvsd_host *host = (struct mvsd_host *)data;
503         void __iomem *iobase = host->base;
504         struct mmc_request *mrq;
505         unsigned long flags;
506
507         spin_lock_irqsave(&host->lock, flags);
508         mrq = host->mrq;
509         if (mrq) {
510                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
511                                 mmc_hostname(host->mmc));
512                 pr_err("%s: hw_state=0x%04x, intr_status=0x%04x "
513                                 "intr_en=0x%04x\n", mmc_hostname(host->mmc),
514                                 mvsd_read(MVSD_HW_STATE),
515                                 mvsd_read(MVSD_NOR_INTR_STATUS),
516                                 mvsd_read(MVSD_NOR_INTR_EN));
517
518                 host->mrq = NULL;
519
520                 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
521
522                 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
523                 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
524
525                 host->intr_en &= MVSD_NOR_CARD_INT;
526                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
527                 mvsd_write(MVSD_ERR_INTR_EN, 0);
528                 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
529
530                 mrq->cmd->error = -ETIMEDOUT;
531                 mvsd_finish_cmd(host, mrq->cmd, 0);
532                 if (mrq->data) {
533                         mrq->data->error = -ETIMEDOUT;
534                         mvsd_finish_data(host, mrq->data, 0);
535                 }
536         }
537         spin_unlock_irqrestore(&host->lock, flags);
538
539         if (mrq)
540                 mmc_request_done(host->mmc, mrq);
541 }
542
543 static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
544 {
545         struct mvsd_host *host = mmc_priv(mmc);
546         void __iomem *iobase = host->base;
547         unsigned long flags;
548
549         spin_lock_irqsave(&host->lock, flags);
550         if (enable) {
551                 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
552                 host->intr_en |= MVSD_NOR_CARD_INT;
553         } else {
554                 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
555                 host->intr_en &= ~MVSD_NOR_CARD_INT;
556         }
557         mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
558         mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
559         spin_unlock_irqrestore(&host->lock, flags);
560 }
561
562 static void mvsd_power_up(struct mvsd_host *host)
563 {
564         void __iomem *iobase = host->base;
565         dev_dbg(host->dev, "power up\n");
566         mvsd_write(MVSD_NOR_INTR_EN, 0);
567         mvsd_write(MVSD_ERR_INTR_EN, 0);
568         mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
569         mvsd_write(MVSD_XFER_MODE, 0);
570         mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
571         mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
572         mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
573         mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
574 }
575
576 static void mvsd_power_down(struct mvsd_host *host)
577 {
578         void __iomem *iobase = host->base;
579         dev_dbg(host->dev, "power down\n");
580         mvsd_write(MVSD_NOR_INTR_EN, 0);
581         mvsd_write(MVSD_ERR_INTR_EN, 0);
582         mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
583         mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
584         mvsd_write(MVSD_NOR_STATUS_EN, 0);
585         mvsd_write(MVSD_ERR_STATUS_EN, 0);
586         mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
587         mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
588 }
589
590 static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
591 {
592         struct mvsd_host *host = mmc_priv(mmc);
593         void __iomem *iobase = host->base;
594         u32 ctrl_reg = 0;
595
596         if (ios->power_mode == MMC_POWER_UP)
597                 mvsd_power_up(host);
598
599         if (ios->clock == 0) {
600                 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
601                 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
602                 host->clock = 0;
603                 dev_dbg(host->dev, "clock off\n");
604         } else if (ios->clock != host->clock) {
605                 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
606                 if (m > MVSD_BASE_DIV_MAX)
607                         m = MVSD_BASE_DIV_MAX;
608                 mvsd_write(MVSD_CLK_DIV, m);
609                 host->clock = ios->clock;
610                 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
611                 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
612                         ios->clock, host->base_clock / (m+1), m);
613         }
614
615         /* default transfer mode */
616         ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
617         ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
618
619         /* default to maximum timeout */
620         ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
621         ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
622
623         if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
624                 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
625
626         if (ios->bus_width == MMC_BUS_WIDTH_4)
627                 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
628
629         /*
630          * The HI_SPEED_EN bit is causing trouble with many (but not all)
631          * high speed SD, SDHC and SDIO cards.  Not enabling that bit
632          * makes all cards work.  So let's just ignore that bit for now
633          * and revisit this issue if problems for not enabling this bit
634          * are ever reported.
635          */
636 #if 0
637         if (ios->timing == MMC_TIMING_MMC_HS ||
638             ios->timing == MMC_TIMING_SD_HS)
639                 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
640 #endif
641
642         host->ctrl = ctrl_reg;
643         mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
644         dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
645                 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
646                         "push-pull" : "open-drain",
647                 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
648                         "4bit-width" : "1bit-width",
649                 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
650                         "high-speed" : "");
651
652         if (ios->power_mode == MMC_POWER_OFF)
653                 mvsd_power_down(host);
654 }
655
656 static const struct mmc_host_ops mvsd_ops = {
657         .request                = mvsd_request,
658         .get_ro                 = mmc_gpio_get_ro,
659         .set_ios                = mvsd_set_ios,
660         .enable_sdio_irq        = mvsd_enable_sdio_irq,
661 };
662
663 static void __init
664 mv_conf_mbus_windows(struct mvsd_host *host,
665                      const struct mbus_dram_target_info *dram)
666 {
667         void __iomem *iobase = host->base;
668         int i;
669
670         for (i = 0; i < 4; i++) {
671                 writel(0, iobase + MVSD_WINDOW_CTRL(i));
672                 writel(0, iobase + MVSD_WINDOW_BASE(i));
673         }
674
675         for (i = 0; i < dram->num_cs; i++) {
676                 const struct mbus_dram_window *cs = dram->cs + i;
677                 writel(((cs->size - 1) & 0xffff0000) |
678                        (cs->mbus_attr << 8) |
679                        (dram->mbus_dram_target_id << 4) | 1,
680                        iobase + MVSD_WINDOW_CTRL(i));
681                 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
682         }
683 }
684
685 static int __init mvsd_probe(struct platform_device *pdev)
686 {
687         struct device_node *np = pdev->dev.of_node;
688         struct mmc_host *mmc = NULL;
689         struct mvsd_host *host = NULL;
690         const struct mbus_dram_target_info *dram;
691         struct resource *r;
692         int ret, irq;
693         int gpio_card_detect, gpio_write_protect;
694         struct pinctrl *pinctrl;
695
696         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
697         irq = platform_get_irq(pdev, 0);
698         if (!r || irq < 0)
699                 return -ENXIO;
700
701         mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
702         if (!mmc) {
703                 ret = -ENOMEM;
704                 goto out;
705         }
706
707         host = mmc_priv(mmc);
708         host->mmc = mmc;
709         host->dev = &pdev->dev;
710
711         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
712         if (IS_ERR(pinctrl))
713                 dev_warn(&pdev->dev, "no pins associated\n");
714
715         /*
716          * Some non-DT platforms do not pass a clock, and the clock
717          * frequency is passed through platform_data. On DT platforms,
718          * a clock must always be passed, even if there is no gatable
719          * clock associated to the SDIO interface (it can simply be a
720          * fixed rate clock).
721          */
722         host->clk = devm_clk_get(&pdev->dev, NULL);
723         if (!IS_ERR(host->clk))
724                 clk_prepare_enable(host->clk);
725
726         if (np) {
727                 if (IS_ERR(host->clk)) {
728                         dev_err(&pdev->dev, "DT platforms must have a clock associated\n");
729                         ret = -EINVAL;
730                         goto out;
731                 }
732
733                 host->base_clock = clk_get_rate(host->clk) / 2;
734                 gpio_card_detect = of_get_named_gpio(np, "cd-gpios", 0);
735                 gpio_write_protect = of_get_named_gpio(np, "wp-gpios", 0);
736         } else {
737                 const struct mvsdio_platform_data *mvsd_data;
738                 mvsd_data = pdev->dev.platform_data;
739                 if (!mvsd_data) {
740                         ret = -ENXIO;
741                         goto out;
742                 }
743                 host->base_clock = mvsd_data->clock / 2;
744                 gpio_card_detect = mvsd_data->gpio_card_detect;
745                 gpio_write_protect = mvsd_data->gpio_write_protect;
746         }
747
748         mmc->ops = &mvsd_ops;
749
750         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
751         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
752                     MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
753
754         mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
755         mmc->f_max = maxfreq;
756
757         mmc->max_blk_size = 2048;
758         mmc->max_blk_count = 65535;
759
760         mmc->max_segs = 1;
761         mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
762         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
763
764         spin_lock_init(&host->lock);
765
766         host->base = devm_request_and_ioremap(&pdev->dev, r);
767         if (!host->base) {
768                 ret = -ENOMEM;
769                 goto out;
770         }
771
772         /* (Re-)program MBUS remapping windows if we are asked to. */
773         dram = mv_mbus_dram_info();
774         if (dram)
775                 mv_conf_mbus_windows(host, dram);
776
777         mvsd_power_down(host);
778
779         ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
780         if (ret) {
781                 pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq);
782                 goto out;
783         }
784
785         if (gpio_is_valid(gpio_card_detect)) {
786                 ret = mmc_gpio_request_cd(mmc, gpio_card_detect);
787                 if (ret)
788                         goto out;
789         } else
790                 mmc->caps |= MMC_CAP_NEEDS_POLL;
791
792         mmc_gpio_request_ro(mmc, gpio_write_protect);
793
794         setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
795         platform_set_drvdata(pdev, mmc);
796         ret = mmc_add_host(mmc);
797         if (ret)
798                 goto out;
799
800         pr_notice("%s: %s driver initialized, ",
801                            mmc_hostname(mmc), DRIVER_NAME);
802         if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
803                 printk("using GPIO %d for card detection\n",
804                        gpio_card_detect);
805         else
806                 printk("lacking card detect (fall back to polling)\n");
807         return 0;
808
809 out:
810         if (mmc) {
811                 mmc_gpio_free_cd(mmc);
812                 mmc_gpio_free_ro(mmc);
813                 if (!IS_ERR(host->clk))
814                         clk_disable_unprepare(host->clk);
815                 mmc_free_host(mmc);
816         }
817
818         return ret;
819 }
820
821 static int __exit mvsd_remove(struct platform_device *pdev)
822 {
823         struct mmc_host *mmc = platform_get_drvdata(pdev);
824
825         struct mvsd_host *host = mmc_priv(mmc);
826
827         mmc_gpio_free_cd(mmc);
828         mmc_gpio_free_ro(mmc);
829         mmc_remove_host(mmc);
830         del_timer_sync(&host->timer);
831         mvsd_power_down(host);
832
833         if (!IS_ERR(host->clk))
834                 clk_disable_unprepare(host->clk);
835         mmc_free_host(mmc);
836
837         platform_set_drvdata(pdev, NULL);
838         return 0;
839 }
840
841 #ifdef CONFIG_PM
842 static int mvsd_suspend(struct platform_device *dev, pm_message_t state)
843 {
844         struct mmc_host *mmc = platform_get_drvdata(dev);
845         int ret = 0;
846
847         if (mmc)
848                 ret = mmc_suspend_host(mmc);
849
850         return ret;
851 }
852
853 static int mvsd_resume(struct platform_device *dev)
854 {
855         struct mmc_host *mmc = platform_get_drvdata(dev);
856         int ret = 0;
857
858         if (mmc)
859                 ret = mmc_resume_host(mmc);
860
861         return ret;
862 }
863 #else
864 #define mvsd_suspend    NULL
865 #define mvsd_resume     NULL
866 #endif
867
868 static const struct of_device_id mvsdio_dt_ids[] = {
869         { .compatible = "marvell,orion-sdio" },
870         { /* sentinel */ }
871 };
872 MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
873
874 static struct platform_driver mvsd_driver = {
875         .remove         = __exit_p(mvsd_remove),
876         .suspend        = mvsd_suspend,
877         .resume         = mvsd_resume,
878         .driver         = {
879                 .name   = DRIVER_NAME,
880                 .of_match_table = mvsdio_dt_ids,
881         },
882 };
883
884 static int __init mvsd_init(void)
885 {
886         return platform_driver_probe(&mvsd_driver, mvsd_probe);
887 }
888
889 static void __exit mvsd_exit(void)
890 {
891         platform_driver_unregister(&mvsd_driver);
892 }
893
894 module_init(mvsd_init);
895 module_exit(mvsd_exit);
896
897 /* maximum card clock frequency (default 50MHz) */
898 module_param(maxfreq, int, 0);
899
900 /* force PIO transfers all the time */
901 module_param(nodma, int, 0);
902
903 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
904 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
905 MODULE_LICENSE("GPL");
906 MODULE_ALIAS("platform:mvsdio");