Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney...
[~shefty/rdma-dev.git] / drivers / mmc / host / mvsdio.c
1 /*
2  * Marvell MMC/SD/SDIO driver
3  *
4  * Authors: Maen Suleiman, Nicolas Pitre
5  * Copyright (C) 2008-2009 Marvell Ltd.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/platform_device.h>
16 #include <linux/mbus.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21 #include <linux/irq.h>
22 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <linux/mmc/host.h>
25
26 #include <asm/sizes.h>
27 #include <asm/unaligned.h>
28 #include <linux/platform_data/mmc-mvsdio.h>
29
30 #include "mvsdio.h"
31
32 #define DRIVER_NAME     "mvsdio"
33
34 static int maxfreq = MVSD_CLOCKRATE_MAX;
35 static int nodma;
36
37 struct mvsd_host {
38         void __iomem *base;
39         struct mmc_request *mrq;
40         spinlock_t lock;
41         unsigned int xfer_mode;
42         unsigned int intr_en;
43         unsigned int ctrl;
44         unsigned int pio_size;
45         void *pio_ptr;
46         unsigned int sg_frags;
47         unsigned int ns_per_clk;
48         unsigned int clock;
49         unsigned int base_clock;
50         struct timer_list timer;
51         struct mmc_host *mmc;
52         struct device *dev;
53         struct clk *clk;
54         int gpio_card_detect;
55         int gpio_write_protect;
56 };
57
58 #define mvsd_write(offs, val)   writel(val, iobase + (offs))
59 #define mvsd_read(offs)         readl(iobase + (offs))
60
61 static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
62 {
63         void __iomem *iobase = host->base;
64         unsigned int tmout;
65         int tmout_index;
66
67         /*
68          * Hardware weirdness.  The FIFO_EMPTY bit of the HW_STATE
69          * register is sometimes not set before a while when some
70          * "unusual" data block sizes are used (such as with the SWITCH
71          * command), even despite the fact that the XFER_DONE interrupt
72          * was raised.  And if another data transfer starts before
73          * this bit comes to good sense (which eventually happens by
74          * itself) then the new transfer simply fails with a timeout.
75          */
76         if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
77                 unsigned long t = jiffies + HZ;
78                 unsigned int hw_state,  count = 0;
79                 do {
80                         if (time_after(jiffies, t)) {
81                                 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
82                                 break;
83                         }
84                         hw_state = mvsd_read(MVSD_HW_STATE);
85                         count++;
86                 } while (!(hw_state & (1 << 13)));
87                 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
88                                    "(hw=0x%04x, count=%d, jiffies=%ld)\n",
89                                    hw_state, count, jiffies - (t - HZ));
90         }
91
92         /* If timeout=0 then maximum timeout index is used. */
93         tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
94         tmout += data->timeout_clks;
95         tmout_index = fls(tmout - 1) - 12;
96         if (tmout_index < 0)
97                 tmout_index = 0;
98         if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
99                 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
100
101         dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
102                 (data->flags & MMC_DATA_READ) ? "read" : "write",
103                 (u32)sg_virt(data->sg), data->blocks, data->blksz,
104                 tmout, tmout_index);
105
106         host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
107         host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
108         mvsd_write(MVSD_HOST_CTRL, host->ctrl);
109         mvsd_write(MVSD_BLK_COUNT, data->blocks);
110         mvsd_write(MVSD_BLK_SIZE, data->blksz);
111
112         if (nodma || (data->blksz | data->sg->offset) & 3) {
113                 /*
114                  * We cannot do DMA on a buffer which offset or size
115                  * is not aligned on a 4-byte boundary.
116                  */
117                 host->pio_size = data->blocks * data->blksz;
118                 host->pio_ptr = sg_virt(data->sg);
119                 if (!nodma)
120                         pr_debug("%s: fallback to PIO for data "
121                                           "at 0x%p size %d\n",
122                                           mmc_hostname(host->mmc),
123                                           host->pio_ptr, host->pio_size);
124                 return 1;
125         } else {
126                 dma_addr_t phys_addr;
127                 int dma_dir = (data->flags & MMC_DATA_READ) ?
128                         DMA_FROM_DEVICE : DMA_TO_DEVICE;
129                 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
130                                             data->sg_len, dma_dir);
131                 phys_addr = sg_dma_address(data->sg);
132                 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
133                 mvsd_write(MVSD_SYS_ADDR_HI,  (u32)phys_addr >> 16);
134                 return 0;
135         }
136 }
137
138 static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
139 {
140         struct mvsd_host *host = mmc_priv(mmc);
141         void __iomem *iobase = host->base;
142         struct mmc_command *cmd = mrq->cmd;
143         u32 cmdreg = 0, xfer = 0, intr = 0;
144         unsigned long flags;
145
146         BUG_ON(host->mrq != NULL);
147         host->mrq = mrq;
148
149         dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
150                 cmd->opcode, mvsd_read(MVSD_HW_STATE));
151
152         cmdreg = MVSD_CMD_INDEX(cmd->opcode);
153
154         if (cmd->flags & MMC_RSP_BUSY)
155                 cmdreg |= MVSD_CMD_RSP_48BUSY;
156         else if (cmd->flags & MMC_RSP_136)
157                 cmdreg |= MVSD_CMD_RSP_136;
158         else if (cmd->flags & MMC_RSP_PRESENT)
159                 cmdreg |= MVSD_CMD_RSP_48;
160         else
161                 cmdreg |= MVSD_CMD_RSP_NONE;
162
163         if (cmd->flags & MMC_RSP_CRC)
164                 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
165
166         if (cmd->flags & MMC_RSP_OPCODE)
167                 cmdreg |= MVSD_CMD_INDX_CHECK;
168
169         if (cmd->flags & MMC_RSP_PRESENT) {
170                 cmdreg |= MVSD_UNEXPECTED_RESP;
171                 intr |= MVSD_NOR_UNEXP_RSP;
172         }
173
174         if (mrq->data) {
175                 struct mmc_data *data = mrq->data;
176                 int pio;
177
178                 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
179                 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
180                 if (data->flags & MMC_DATA_READ)
181                         xfer |= MVSD_XFER_MODE_TO_HOST;
182
183                 pio = mvsd_setup_data(host, data);
184                 if (pio) {
185                         xfer |= MVSD_XFER_MODE_PIO;
186                         /* PIO section of mvsd_irq has comments on those bits */
187                         if (data->flags & MMC_DATA_WRITE)
188                                 intr |= MVSD_NOR_TX_AVAIL;
189                         else if (host->pio_size > 32)
190                                 intr |= MVSD_NOR_RX_FIFO_8W;
191                         else
192                                 intr |= MVSD_NOR_RX_READY;
193                 }
194
195                 if (data->stop) {
196                         struct mmc_command *stop = data->stop;
197                         u32 cmd12reg = 0;
198
199                         mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
200                         mvsd_write(MVSD_AUTOCMD12_ARG_HI,  stop->arg >> 16);
201
202                         if (stop->flags & MMC_RSP_BUSY)
203                                 cmd12reg |= MVSD_AUTOCMD12_BUSY;
204                         if (stop->flags & MMC_RSP_OPCODE)
205                                 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
206                         cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
207                         mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
208
209                         xfer |= MVSD_XFER_MODE_AUTO_CMD12;
210                         intr |= MVSD_NOR_AUTOCMD12_DONE;
211                 } else {
212                         intr |= MVSD_NOR_XFER_DONE;
213                 }
214         } else {
215                 intr |= MVSD_NOR_CMD_DONE;
216         }
217
218         mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
219         mvsd_write(MVSD_ARG_HI,  cmd->arg >> 16);
220
221         spin_lock_irqsave(&host->lock, flags);
222
223         host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
224         host->xfer_mode |= xfer;
225         mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
226
227         mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
228         mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
229         mvsd_write(MVSD_CMD, cmdreg);
230
231         host->intr_en &= MVSD_NOR_CARD_INT;
232         host->intr_en |= intr | MVSD_NOR_ERROR;
233         mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
234         mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
235
236         mod_timer(&host->timer, jiffies + 5 * HZ);
237
238         spin_unlock_irqrestore(&host->lock, flags);
239 }
240
241 static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
242                            u32 err_status)
243 {
244         void __iomem *iobase = host->base;
245
246         if (cmd->flags & MMC_RSP_136) {
247                 unsigned int response[8], i;
248                 for (i = 0; i < 8; i++)
249                         response[i] = mvsd_read(MVSD_RSP(i));
250                 cmd->resp[0] =          ((response[0] & 0x03ff) << 22) |
251                                         ((response[1] & 0xffff) << 6) |
252                                         ((response[2] & 0xfc00) >> 10);
253                 cmd->resp[1] =          ((response[2] & 0x03ff) << 22) |
254                                         ((response[3] & 0xffff) << 6) |
255                                         ((response[4] & 0xfc00) >> 10);
256                 cmd->resp[2] =          ((response[4] & 0x03ff) << 22) |
257                                         ((response[5] & 0xffff) << 6) |
258                                         ((response[6] & 0xfc00) >> 10);
259                 cmd->resp[3] =          ((response[6] & 0x03ff) << 22) |
260                                         ((response[7] & 0x3fff) << 8);
261         } else if (cmd->flags & MMC_RSP_PRESENT) {
262                 unsigned int response[3], i;
263                 for (i = 0; i < 3; i++)
264                         response[i] = mvsd_read(MVSD_RSP(i));
265                 cmd->resp[0] =          ((response[2] & 0x003f) << (8 - 8)) |
266                                         ((response[1] & 0xffff) << (14 - 8)) |
267                                         ((response[0] & 0x03ff) << (30 - 8));
268                 cmd->resp[1] =          ((response[0] & 0xfc00) >> 10);
269                 cmd->resp[2] = 0;
270                 cmd->resp[3] = 0;
271         }
272
273         if (err_status & MVSD_ERR_CMD_TIMEOUT) {
274                 cmd->error = -ETIMEDOUT;
275         } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
276                                  MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
277                 cmd->error = -EILSEQ;
278         }
279         err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
280                         MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
281                         MVSD_ERR_CMD_STARTBIT);
282
283         return err_status;
284 }
285
286 static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
287                             u32 err_status)
288 {
289         void __iomem *iobase = host->base;
290
291         if (host->pio_ptr) {
292                 host->pio_ptr = NULL;
293                 host->pio_size = 0;
294         } else {
295                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
296                              (data->flags & MMC_DATA_READ) ?
297                                 DMA_FROM_DEVICE : DMA_TO_DEVICE);
298         }
299
300         if (err_status & MVSD_ERR_DATA_TIMEOUT)
301                 data->error = -ETIMEDOUT;
302         else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
303                 data->error = -EILSEQ;
304         else if (err_status & MVSD_ERR_XFER_SIZE)
305                 data->error = -EBADE;
306         err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
307                         MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
308
309         dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
310                 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
311         data->bytes_xfered =
312                 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
313         /* We can't be sure about the last block when errors are detected */
314         if (data->bytes_xfered && data->error)
315                 data->bytes_xfered -= data->blksz;
316
317         /* Handle Auto cmd 12 response */
318         if (data->stop) {
319                 unsigned int response[3], i;
320                 for (i = 0; i < 3; i++)
321                         response[i] = mvsd_read(MVSD_AUTO_RSP(i));
322                 data->stop->resp[0] =   ((response[2] & 0x003f) << (8 - 8)) |
323                                         ((response[1] & 0xffff) << (14 - 8)) |
324                                         ((response[0] & 0x03ff) << (30 - 8));
325                 data->stop->resp[1] =   ((response[0] & 0xfc00) >> 10);
326                 data->stop->resp[2] = 0;
327                 data->stop->resp[3] = 0;
328
329                 if (err_status & MVSD_ERR_AUTOCMD12) {
330                         u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
331                         dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
332                         if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
333                                 data->stop->error = -ENOEXEC;
334                         else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
335                                 data->stop->error = -ETIMEDOUT;
336                         else if (err_cmd12)
337                                 data->stop->error = -EILSEQ;
338                         err_status &= ~MVSD_ERR_AUTOCMD12;
339                 }
340         }
341
342         return err_status;
343 }
344
345 static irqreturn_t mvsd_irq(int irq, void *dev)
346 {
347         struct mvsd_host *host = dev;
348         void __iomem *iobase = host->base;
349         u32 intr_status, intr_done_mask;
350         int irq_handled = 0;
351
352         intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
353         dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
354                 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
355                 mvsd_read(MVSD_HW_STATE));
356
357         spin_lock(&host->lock);
358
359         /* PIO handling, if needed. Messy business... */
360         if (host->pio_size &&
361             (intr_status & host->intr_en &
362              (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
363                 u16 *p = host->pio_ptr;
364                 int s = host->pio_size;
365                 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
366                         readsw(iobase + MVSD_FIFO, p, 16);
367                         p += 16;
368                         s -= 32;
369                         intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
370                 }
371                 /*
372                  * Normally we'd use < 32 here, but the RX_FIFO_8W bit
373                  * doesn't appear to assert when there is exactly 32 bytes
374                  * (8 words) left to fetch in a transfer.
375                  */
376                 if (s <= 32) {
377                         while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
378                                 put_unaligned(mvsd_read(MVSD_FIFO), p++);
379                                 put_unaligned(mvsd_read(MVSD_FIFO), p++);
380                                 s -= 4;
381                                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
382                         }
383                         if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
384                                 u16 val[2] = {0, 0};
385                                 val[0] = mvsd_read(MVSD_FIFO);
386                                 val[1] = mvsd_read(MVSD_FIFO);
387                                 memcpy(p, ((void *)&val) + 4 - s, s);
388                                 s = 0;
389                                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
390                         }
391                         if (s == 0) {
392                                 host->intr_en &=
393                                      ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
394                                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
395                         } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
396                                 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
397                                 host->intr_en |= MVSD_NOR_RX_READY;
398                                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
399                         }
400                 }
401                 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
402                         s, intr_status, mvsd_read(MVSD_HW_STATE));
403                 host->pio_ptr = p;
404                 host->pio_size = s;
405                 irq_handled = 1;
406         } else if (host->pio_size &&
407                    (intr_status & host->intr_en &
408                     (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
409                 u16 *p = host->pio_ptr;
410                 int s = host->pio_size;
411                 /*
412                  * The TX_FIFO_8W bit is unreliable. When set, bursting
413                  * 16 halfwords all at once in the FIFO drops data. Actually
414                  * TX_AVAIL does go off after only one word is pushed even if
415                  * TX_FIFO_8W remains set.
416                  */
417                 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
418                         mvsd_write(MVSD_FIFO, get_unaligned(p++));
419                         mvsd_write(MVSD_FIFO, get_unaligned(p++));
420                         s -= 4;
421                         intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
422                 }
423                 if (s < 4) {
424                         if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
425                                 u16 val[2] = {0, 0};
426                                 memcpy(((void *)&val) + 4 - s, p, s);
427                                 mvsd_write(MVSD_FIFO, val[0]);
428                                 mvsd_write(MVSD_FIFO, val[1]);
429                                 s = 0;
430                                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
431                         }
432                         if (s == 0) {
433                                 host->intr_en &=
434                                      ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
435                                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
436                         }
437                 }
438                 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
439                         s, intr_status, mvsd_read(MVSD_HW_STATE));
440                 host->pio_ptr = p;
441                 host->pio_size = s;
442                 irq_handled = 1;
443         }
444
445         mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
446
447         intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
448                          MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
449         if (intr_status & host->intr_en & ~intr_done_mask) {
450                 struct mmc_request *mrq = host->mrq;
451                 struct mmc_command *cmd = mrq->cmd;
452                 u32 err_status = 0;
453
454                 del_timer(&host->timer);
455                 host->mrq = NULL;
456
457                 host->intr_en &= MVSD_NOR_CARD_INT;
458                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
459                 mvsd_write(MVSD_ERR_INTR_EN, 0);
460
461                 spin_unlock(&host->lock);
462
463                 if (intr_status & MVSD_NOR_UNEXP_RSP) {
464                         cmd->error = -EPROTO;
465                 } else if (intr_status & MVSD_NOR_ERROR) {
466                         err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
467                         dev_dbg(host->dev, "err 0x%04x\n", err_status);
468                 }
469
470                 err_status = mvsd_finish_cmd(host, cmd, err_status);
471                 if (mrq->data)
472                         err_status = mvsd_finish_data(host, mrq->data, err_status);
473                 if (err_status) {
474                         pr_err("%s: unhandled error status %#04x\n",
475                                         mmc_hostname(host->mmc), err_status);
476                         cmd->error = -ENOMSG;
477                 }
478
479                 mmc_request_done(host->mmc, mrq);
480                 irq_handled = 1;
481         } else
482                 spin_unlock(&host->lock);
483
484         if (intr_status & MVSD_NOR_CARD_INT) {
485                 mmc_signal_sdio_irq(host->mmc);
486                 irq_handled = 1;
487         }
488
489         if (irq_handled)
490                 return IRQ_HANDLED;
491
492         pr_err("%s: unhandled interrupt status=0x%04x en=0x%04x "
493                         "pio=%d\n", mmc_hostname(host->mmc), intr_status,
494                         host->intr_en, host->pio_size);
495         return IRQ_NONE;
496 }
497
498 static void mvsd_timeout_timer(unsigned long data)
499 {
500         struct mvsd_host *host = (struct mvsd_host *)data;
501         void __iomem *iobase = host->base;
502         struct mmc_request *mrq;
503         unsigned long flags;
504
505         spin_lock_irqsave(&host->lock, flags);
506         mrq = host->mrq;
507         if (mrq) {
508                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
509                                 mmc_hostname(host->mmc));
510                 pr_err("%s: hw_state=0x%04x, intr_status=0x%04x "
511                                 "intr_en=0x%04x\n", mmc_hostname(host->mmc),
512                                 mvsd_read(MVSD_HW_STATE),
513                                 mvsd_read(MVSD_NOR_INTR_STATUS),
514                                 mvsd_read(MVSD_NOR_INTR_EN));
515
516                 host->mrq = NULL;
517
518                 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
519
520                 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
521                 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
522
523                 host->intr_en &= MVSD_NOR_CARD_INT;
524                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
525                 mvsd_write(MVSD_ERR_INTR_EN, 0);
526                 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
527
528                 mrq->cmd->error = -ETIMEDOUT;
529                 mvsd_finish_cmd(host, mrq->cmd, 0);
530                 if (mrq->data) {
531                         mrq->data->error = -ETIMEDOUT;
532                         mvsd_finish_data(host, mrq->data, 0);
533                 }
534         }
535         spin_unlock_irqrestore(&host->lock, flags);
536
537         if (mrq)
538                 mmc_request_done(host->mmc, mrq);
539 }
540
541 static irqreturn_t mvsd_card_detect_irq(int irq, void *dev)
542 {
543         struct mvsd_host *host = dev;
544         mmc_detect_change(host->mmc, msecs_to_jiffies(100));
545         return IRQ_HANDLED;
546 }
547
548 static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
549 {
550         struct mvsd_host *host = mmc_priv(mmc);
551         void __iomem *iobase = host->base;
552         unsigned long flags;
553
554         spin_lock_irqsave(&host->lock, flags);
555         if (enable) {
556                 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
557                 host->intr_en |= MVSD_NOR_CARD_INT;
558         } else {
559                 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
560                 host->intr_en &= ~MVSD_NOR_CARD_INT;
561         }
562         mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
563         mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
564         spin_unlock_irqrestore(&host->lock, flags);
565 }
566
567 static int mvsd_get_ro(struct mmc_host *mmc)
568 {
569         struct mvsd_host *host = mmc_priv(mmc);
570
571         if (host->gpio_write_protect)
572                 return gpio_get_value(host->gpio_write_protect);
573
574         /*
575          * Board doesn't support read only detection; let the mmc core
576          * decide what to do.
577          */
578         return -ENOSYS;
579 }
580
581 static void mvsd_power_up(struct mvsd_host *host)
582 {
583         void __iomem *iobase = host->base;
584         dev_dbg(host->dev, "power up\n");
585         mvsd_write(MVSD_NOR_INTR_EN, 0);
586         mvsd_write(MVSD_ERR_INTR_EN, 0);
587         mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
588         mvsd_write(MVSD_XFER_MODE, 0);
589         mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
590         mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
591         mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
592         mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
593 }
594
595 static void mvsd_power_down(struct mvsd_host *host)
596 {
597         void __iomem *iobase = host->base;
598         dev_dbg(host->dev, "power down\n");
599         mvsd_write(MVSD_NOR_INTR_EN, 0);
600         mvsd_write(MVSD_ERR_INTR_EN, 0);
601         mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
602         mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
603         mvsd_write(MVSD_NOR_STATUS_EN, 0);
604         mvsd_write(MVSD_ERR_STATUS_EN, 0);
605         mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
606         mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
607 }
608
609 static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
610 {
611         struct mvsd_host *host = mmc_priv(mmc);
612         void __iomem *iobase = host->base;
613         u32 ctrl_reg = 0;
614
615         if (ios->power_mode == MMC_POWER_UP)
616                 mvsd_power_up(host);
617
618         if (ios->clock == 0) {
619                 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
620                 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
621                 host->clock = 0;
622                 dev_dbg(host->dev, "clock off\n");
623         } else if (ios->clock != host->clock) {
624                 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
625                 if (m > MVSD_BASE_DIV_MAX)
626                         m = MVSD_BASE_DIV_MAX;
627                 mvsd_write(MVSD_CLK_DIV, m);
628                 host->clock = ios->clock;
629                 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
630                 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
631                         ios->clock, host->base_clock / (m+1), m);
632         }
633
634         /* default transfer mode */
635         ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
636         ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
637
638         /* default to maximum timeout */
639         ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
640         ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
641
642         if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
643                 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
644
645         if (ios->bus_width == MMC_BUS_WIDTH_4)
646                 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
647
648         /*
649          * The HI_SPEED_EN bit is causing trouble with many (but not all)
650          * high speed SD, SDHC and SDIO cards.  Not enabling that bit
651          * makes all cards work.  So let's just ignore that bit for now
652          * and revisit this issue if problems for not enabling this bit
653          * are ever reported.
654          */
655 #if 0
656         if (ios->timing == MMC_TIMING_MMC_HS ||
657             ios->timing == MMC_TIMING_SD_HS)
658                 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
659 #endif
660
661         host->ctrl = ctrl_reg;
662         mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
663         dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
664                 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
665                         "push-pull" : "open-drain",
666                 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
667                         "4bit-width" : "1bit-width",
668                 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
669                         "high-speed" : "");
670
671         if (ios->power_mode == MMC_POWER_OFF)
672                 mvsd_power_down(host);
673 }
674
675 static const struct mmc_host_ops mvsd_ops = {
676         .request                = mvsd_request,
677         .get_ro                 = mvsd_get_ro,
678         .set_ios                = mvsd_set_ios,
679         .enable_sdio_irq        = mvsd_enable_sdio_irq,
680 };
681
682 static void __init
683 mv_conf_mbus_windows(struct mvsd_host *host,
684                      const struct mbus_dram_target_info *dram)
685 {
686         void __iomem *iobase = host->base;
687         int i;
688
689         for (i = 0; i < 4; i++) {
690                 writel(0, iobase + MVSD_WINDOW_CTRL(i));
691                 writel(0, iobase + MVSD_WINDOW_BASE(i));
692         }
693
694         for (i = 0; i < dram->num_cs; i++) {
695                 const struct mbus_dram_window *cs = dram->cs + i;
696                 writel(((cs->size - 1) & 0xffff0000) |
697                        (cs->mbus_attr << 8) |
698                        (dram->mbus_dram_target_id << 4) | 1,
699                        iobase + MVSD_WINDOW_CTRL(i));
700                 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
701         }
702 }
703
704 static int __init mvsd_probe(struct platform_device *pdev)
705 {
706         struct mmc_host *mmc = NULL;
707         struct mvsd_host *host = NULL;
708         const struct mvsdio_platform_data *mvsd_data;
709         const struct mbus_dram_target_info *dram;
710         struct resource *r;
711         int ret, irq;
712
713         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
714         irq = platform_get_irq(pdev, 0);
715         mvsd_data = pdev->dev.platform_data;
716         if (!r || irq < 0 || !mvsd_data)
717                 return -ENXIO;
718
719         mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
720         if (!mmc) {
721                 ret = -ENOMEM;
722                 goto out;
723         }
724
725         host = mmc_priv(mmc);
726         host->mmc = mmc;
727         host->dev = &pdev->dev;
728         host->base_clock = mvsd_data->clock / 2;
729         host->clk = ERR_PTR(-EINVAL);
730
731         mmc->ops = &mvsd_ops;
732
733         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
734         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
735                     MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
736
737         mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
738         mmc->f_max = maxfreq;
739
740         mmc->max_blk_size = 2048;
741         mmc->max_blk_count = 65535;
742
743         mmc->max_segs = 1;
744         mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
745         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
746
747         spin_lock_init(&host->lock);
748
749         host->base = devm_request_and_ioremap(&pdev->dev, r);
750         if (!host->base) {
751                 ret = -ENOMEM;
752                 goto out;
753         }
754
755         /* (Re-)program MBUS remapping windows if we are asked to. */
756         dram = mv_mbus_dram_info();
757         if (dram)
758                 mv_conf_mbus_windows(host, dram);
759
760         mvsd_power_down(host);
761
762         ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
763         if (ret) {
764                 pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq);
765                 goto out;
766         }
767
768         /* Not all platforms can gate the clock, so it is not
769            an error if the clock does not exists. */
770         host->clk = devm_clk_get(&pdev->dev, NULL);
771         if (!IS_ERR(host->clk))
772                 clk_prepare_enable(host->clk);
773
774         if (mvsd_data->gpio_card_detect) {
775                 ret = devm_gpio_request_one(&pdev->dev,
776                                             mvsd_data->gpio_card_detect,
777                                             GPIOF_IN, DRIVER_NAME " cd");
778                 if (ret == 0) {
779                         irq = gpio_to_irq(mvsd_data->gpio_card_detect);
780                         ret = devm_request_irq(&pdev->dev, irq,
781                                                mvsd_card_detect_irq,
782                                                IRQ_TYPE_EDGE_RISING |
783                                                IRQ_TYPE_EDGE_FALLING,
784                                                DRIVER_NAME " cd", host);
785                         if (ret == 0)
786                                 host->gpio_card_detect =
787                                         mvsd_data->gpio_card_detect;
788                         else
789                                 devm_gpio_free(&pdev->dev,
790                                                mvsd_data->gpio_card_detect);
791                 }
792         }
793         if (!host->gpio_card_detect)
794                 mmc->caps |= MMC_CAP_NEEDS_POLL;
795
796         if (mvsd_data->gpio_write_protect) {
797                 ret = devm_gpio_request_one(&pdev->dev,
798                                             mvsd_data->gpio_write_protect,
799                                             GPIOF_IN, DRIVER_NAME " wp");
800                 if (ret == 0) {
801                         host->gpio_write_protect =
802                                 mvsd_data->gpio_write_protect;
803                 }
804         }
805
806         setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
807         platform_set_drvdata(pdev, mmc);
808         ret = mmc_add_host(mmc);
809         if (ret)
810                 goto out;
811
812         pr_notice("%s: %s driver initialized, ",
813                            mmc_hostname(mmc), DRIVER_NAME);
814         if (host->gpio_card_detect)
815                 printk("using GPIO %d for card detection\n",
816                        host->gpio_card_detect);
817         else
818                 printk("lacking card detect (fall back to polling)\n");
819         return 0;
820
821 out:
822         if (mmc) {
823                 if (!IS_ERR(host->clk))
824                         clk_disable_unprepare(host->clk);
825                 mmc_free_host(mmc);
826         }
827
828         return ret;
829 }
830
831 static int __exit mvsd_remove(struct platform_device *pdev)
832 {
833         struct mmc_host *mmc = platform_get_drvdata(pdev);
834
835         struct mvsd_host *host = mmc_priv(mmc);
836
837         mmc_remove_host(mmc);
838         del_timer_sync(&host->timer);
839         mvsd_power_down(host);
840
841         if (!IS_ERR(host->clk))
842                 clk_disable_unprepare(host->clk);
843         mmc_free_host(mmc);
844
845         platform_set_drvdata(pdev, NULL);
846         return 0;
847 }
848
849 #ifdef CONFIG_PM
850 static int mvsd_suspend(struct platform_device *dev, pm_message_t state)
851 {
852         struct mmc_host *mmc = platform_get_drvdata(dev);
853         int ret = 0;
854
855         if (mmc)
856                 ret = mmc_suspend_host(mmc);
857
858         return ret;
859 }
860
861 static int mvsd_resume(struct platform_device *dev)
862 {
863         struct mmc_host *mmc = platform_get_drvdata(dev);
864         int ret = 0;
865
866         if (mmc)
867                 ret = mmc_resume_host(mmc);
868
869         return ret;
870 }
871 #else
872 #define mvsd_suspend    NULL
873 #define mvsd_resume     NULL
874 #endif
875
876 static struct platform_driver mvsd_driver = {
877         .remove         = __exit_p(mvsd_remove),
878         .suspend        = mvsd_suspend,
879         .resume         = mvsd_resume,
880         .driver         = {
881                 .name   = DRIVER_NAME,
882         },
883 };
884
885 static int __init mvsd_init(void)
886 {
887         return platform_driver_probe(&mvsd_driver, mvsd_probe);
888 }
889
890 static void __exit mvsd_exit(void)
891 {
892         platform_driver_unregister(&mvsd_driver);
893 }
894
895 module_init(mvsd_init);
896 module_exit(mvsd_exit);
897
898 /* maximum card clock frequency (default 50MHz) */
899 module_param(maxfreq, int, 0);
900
901 /* force PIO transfers all the time */
902 module_param(nodma, int, 0);
903
904 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
905 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
906 MODULE_LICENSE("GPL");
907 MODULE_ALIAS("platform:mvsdio");