Merge tag 'mmc-updates-for-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel...
[~shefty/rdma-dev.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
1 /* Realtek PCI-Express SD/MMC Card Interface driver
2  *
3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2, or (at your option) any
8  * later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  *
18  * Author:
19  *   Wei WANG <wei_wang@realsil.com.cn>
20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21  */
22
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/sd.h>
31 #include <linux/mmc/card.h>
32 #include <linux/mfd/rtsx_pci.h>
33 #include <asm/unaligned.h>
34
35 /* SD Tuning Data Structure
36  * Record continuous timing phase path
37  */
38 struct timing_phase_path {
39         int start;
40         int end;
41         int mid;
42         int len;
43 };
44
45 struct realtek_pci_sdmmc {
46         struct platform_device  *pdev;
47         struct rtsx_pcr         *pcr;
48         struct mmc_host         *mmc;
49         struct mmc_request      *mrq;
50
51         struct mutex            host_mutex;
52
53         u8                      ssc_depth;
54         unsigned int            clock;
55         bool                    vpclk;
56         bool                    double_clk;
57         bool                    eject;
58         bool                    initial_mode;
59         bool                    ddr_mode;
60 };
61
62 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
63 {
64         return &(host->pdev->dev);
65 }
66
67 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
68 {
69         rtsx_pci_write_register(host->pcr, CARD_STOP,
70                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
71 }
72
73 #ifdef DEBUG
74 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
75 {
76         struct rtsx_pcr *pcr = host->pcr;
77         u16 i;
78         u8 *ptr;
79
80         /* Print SD host internal registers */
81         rtsx_pci_init_cmd(pcr);
82         for (i = 0xFDA0; i <= 0xFDAE; i++)
83                 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
84         for (i = 0xFD52; i <= 0xFD69; i++)
85                 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
86         rtsx_pci_send_cmd(pcr, 100);
87
88         ptr = rtsx_pci_get_cmd_data(pcr);
89         for (i = 0xFDA0; i <= 0xFDAE; i++)
90                 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
91         for (i = 0xFD52; i <= 0xFD69; i++)
92                 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
93 }
94 #else
95 #define sd_print_debug_regs(host)
96 #endif /* DEBUG */
97
98 static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
99                 u8 *buf, int buf_len, int timeout)
100 {
101         struct rtsx_pcr *pcr = host->pcr;
102         int err, i;
103         u8 trans_mode;
104
105         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
106
107         if (!buf)
108                 buf_len = 0;
109
110         if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
111                 trans_mode = SD_TM_AUTO_TUNING;
112         else
113                 trans_mode = SD_TM_NORMAL_READ;
114
115         rtsx_pci_init_cmd(pcr);
116
117         for (i = 0; i < 5; i++)
118                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
119
120         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
121         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
122                         0xFF, (u8)(byte_cnt >> 8));
123         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
124         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
125
126         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
127                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
128                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
129         if (trans_mode != SD_TM_AUTO_TUNING)
130                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
131                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
132
133         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
134                         0xFF, trans_mode | SD_TRANSFER_START);
135         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
136                         SD_TRANSFER_END, SD_TRANSFER_END);
137
138         err = rtsx_pci_send_cmd(pcr, timeout);
139         if (err < 0) {
140                 sd_print_debug_regs(host);
141                 dev_dbg(sdmmc_dev(host),
142                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
143                 return err;
144         }
145
146         if (buf && buf_len) {
147                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
148                 if (err < 0) {
149                         dev_dbg(sdmmc_dev(host),
150                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
151                         return err;
152                 }
153         }
154
155         return 0;
156 }
157
158 static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
159                 u8 *buf, int buf_len, int timeout)
160 {
161         struct rtsx_pcr *pcr = host->pcr;
162         int err, i;
163         u8 trans_mode;
164
165         if (!buf)
166                 buf_len = 0;
167
168         if (buf && buf_len) {
169                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
170                 if (err < 0) {
171                         dev_dbg(sdmmc_dev(host),
172                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
173                         return err;
174                 }
175         }
176
177         trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
178         rtsx_pci_init_cmd(pcr);
179
180         if (cmd) {
181                 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
182                                 cmd[0] - 0x40);
183
184                 for (i = 0; i < 5; i++)
185                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
186                                         SD_CMD0 + i, 0xFF, cmd[i]);
187         }
188
189         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
190         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
191                         0xFF, (u8)(byte_cnt >> 8));
192         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
193         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
194
195         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
196                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
197                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
198
199         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
200                         trans_mode | SD_TRANSFER_START);
201         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
202                         SD_TRANSFER_END, SD_TRANSFER_END);
203
204         err = rtsx_pci_send_cmd(pcr, timeout);
205         if (err < 0) {
206                 sd_print_debug_regs(host);
207                 dev_dbg(sdmmc_dev(host),
208                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
209                 return err;
210         }
211
212         return 0;
213 }
214
215 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
216                 struct mmc_command *cmd)
217 {
218         struct rtsx_pcr *pcr = host->pcr;
219         u8 cmd_idx = (u8)cmd->opcode;
220         u32 arg = cmd->arg;
221         int err = 0;
222         int timeout = 100;
223         int i;
224         u8 *ptr;
225         int stat_idx = 0;
226         u8 rsp_type;
227         int rsp_len = 5;
228
229         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
230                         __func__, cmd_idx, arg);
231
232         /* Response type:
233          * R0
234          * R1, R5, R6, R7
235          * R1b
236          * R2
237          * R3, R4
238          */
239         switch (mmc_resp_type(cmd)) {
240         case MMC_RSP_NONE:
241                 rsp_type = SD_RSP_TYPE_R0;
242                 rsp_len = 0;
243                 break;
244         case MMC_RSP_R1:
245                 rsp_type = SD_RSP_TYPE_R1;
246                 break;
247         case MMC_RSP_R1B:
248                 rsp_type = SD_RSP_TYPE_R1b;
249                 break;
250         case MMC_RSP_R2:
251                 rsp_type = SD_RSP_TYPE_R2;
252                 rsp_len = 16;
253                 break;
254         case MMC_RSP_R3:
255                 rsp_type = SD_RSP_TYPE_R3;
256                 break;
257         default:
258                 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
259                 err = -EINVAL;
260                 goto out;
261         }
262
263         if (rsp_type == SD_RSP_TYPE_R1b)
264                 timeout = 3000;
265
266         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
267                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
268                                 0xFF, SD_CLK_TOGGLE_EN);
269                 if (err < 0)
270                         goto out;
271         }
272
273         rtsx_pci_init_cmd(pcr);
274
275         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
276         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
277         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
278         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
279         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
280
281         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
282         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
283                         0x01, PINGPONG_BUFFER);
284         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
285                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
286         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
287                      SD_TRANSFER_END | SD_STAT_IDLE,
288                      SD_TRANSFER_END | SD_STAT_IDLE);
289
290         if (rsp_type == SD_RSP_TYPE_R2) {
291                 /* Read data from ping-pong buffer */
292                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
293                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
294                 stat_idx = 16;
295         } else if (rsp_type != SD_RSP_TYPE_R0) {
296                 /* Read data from SD_CMDx registers */
297                 for (i = SD_CMD0; i <= SD_CMD4; i++)
298                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
299                 stat_idx = 5;
300         }
301
302         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
303
304         err = rtsx_pci_send_cmd(pcr, timeout);
305         if (err < 0) {
306                 sd_print_debug_regs(host);
307                 sd_clear_error(host);
308                 dev_dbg(sdmmc_dev(host),
309                         "rtsx_pci_send_cmd error (err = %d)\n", err);
310                 goto out;
311         }
312
313         if (rsp_type == SD_RSP_TYPE_R0) {
314                 err = 0;
315                 goto out;
316         }
317
318         /* Eliminate returned value of CHECK_REG_CMD */
319         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
320
321         /* Check (Start,Transmission) bit of Response */
322         if ((ptr[0] & 0xC0) != 0) {
323                 err = -EILSEQ;
324                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
325                 goto out;
326         }
327
328         /* Check CRC7 */
329         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
330                 if (ptr[stat_idx] & SD_CRC7_ERR) {
331                         err = -EILSEQ;
332                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
333                         goto out;
334                 }
335         }
336
337         if (rsp_type == SD_RSP_TYPE_R2) {
338                 for (i = 0; i < 4; i++) {
339                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
340                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
341                                         i, cmd->resp[i]);
342                 }
343         } else {
344                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
345                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
346                                 cmd->resp[0]);
347         }
348
349 out:
350         cmd->error = err;
351 }
352
353 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
354 {
355         struct rtsx_pcr *pcr = host->pcr;
356         struct mmc_host *mmc = host->mmc;
357         struct mmc_card *card = mmc->card;
358         struct mmc_data *data = mrq->data;
359         int uhs = mmc_sd_card_uhs(card);
360         int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
361         u8 cfg2, trans_mode;
362         int err;
363         size_t data_len = data->blksz * data->blocks;
364
365         if (read) {
366                 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
367                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
368                 trans_mode = SD_TM_AUTO_READ_3;
369         } else {
370                 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
371                         SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
372                 trans_mode = SD_TM_AUTO_WRITE_3;
373         }
374
375         if (!uhs)
376                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
377
378         rtsx_pci_init_cmd(pcr);
379
380         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
381         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
382         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
383                         0xFF, (u8)data->blocks);
384         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
385                         0xFF, (u8)(data->blocks >> 8));
386
387         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
388                         DMA_DONE_INT, DMA_DONE_INT);
389         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
390                         0xFF, (u8)(data_len >> 24));
391         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
392                         0xFF, (u8)(data_len >> 16));
393         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
394                         0xFF, (u8)(data_len >> 8));
395         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
396         if (read) {
397                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
398                                 0x03 | DMA_PACK_SIZE_MASK,
399                                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
400         } else {
401                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
402                                 0x03 | DMA_PACK_SIZE_MASK,
403                                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
404         }
405
406         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
407                         0x01, RING_BUFFER);
408
409         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
410         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
411                         trans_mode | SD_TRANSFER_START);
412         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
413                         SD_TRANSFER_END, SD_TRANSFER_END);
414
415         rtsx_pci_send_cmd_no_wait(pcr);
416
417         err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
418         if (err < 0) {
419                 sd_clear_error(host);
420                 return err;
421         }
422
423         return 0;
424 }
425
426 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
427 {
428         rtsx_pci_write_register(host->pcr, SD_CFG1,
429                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
430 }
431
432 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
433 {
434         rtsx_pci_write_register(host->pcr, SD_CFG1,
435                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
436 }
437
438 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
439                 struct mmc_request *mrq)
440 {
441         struct mmc_command *cmd = mrq->cmd;
442         struct mmc_data *data = mrq->data;
443         u8 _cmd[5], *buf;
444
445         _cmd[0] = 0x40 | (u8)cmd->opcode;
446         put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
447
448         buf = kzalloc(data->blksz, GFP_NOIO);
449         if (!buf) {
450                 cmd->error = -ENOMEM;
451                 return;
452         }
453
454         if (data->flags & MMC_DATA_READ) {
455                 if (host->initial_mode)
456                         sd_disable_initial_mode(host);
457
458                 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
459                                 data->blksz, 200);
460
461                 if (host->initial_mode)
462                         sd_enable_initial_mode(host);
463
464                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
465         } else {
466                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
467
468                 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
469                                 data->blksz, 200);
470         }
471
472         kfree(buf);
473 }
474
475 static int sd_change_phase(struct realtek_pci_sdmmc *host, u8 sample_point)
476 {
477         struct rtsx_pcr *pcr = host->pcr;
478         int err;
479
480         dev_dbg(sdmmc_dev(host), "%s: sample_point = %d\n",
481                         __func__, sample_point);
482
483         rtsx_pci_init_cmd(pcr);
484
485         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
486         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPRX_CTL, 0x1F, sample_point);
487         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
488         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
489                         PHASE_NOT_RESET, PHASE_NOT_RESET);
490         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
491         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
492
493         err = rtsx_pci_send_cmd(pcr, 100);
494         if (err < 0)
495                 return err;
496
497         return 0;
498 }
499
500 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
501 {
502         struct timing_phase_path path[MAX_PHASE + 1];
503         int i, j, cont_path_cnt;
504         int new_block, max_len, final_path_idx;
505         u8 final_phase = 0xFF;
506
507         /* Parse phase_map, take it as a bit-ring */
508         cont_path_cnt = 0;
509         new_block = 1;
510         j = 0;
511         for (i = 0; i < MAX_PHASE + 1; i++) {
512                 if (phase_map & (1 << i)) {
513                         if (new_block) {
514                                 new_block = 0;
515                                 j = cont_path_cnt++;
516                                 path[j].start = i;
517                                 path[j].end = i;
518                         } else {
519                                 path[j].end = i;
520                         }
521                 } else {
522                         new_block = 1;
523                         if (cont_path_cnt) {
524                                 /* Calculate path length and middle point */
525                                 int idx = cont_path_cnt - 1;
526                                 path[idx].len =
527                                         path[idx].end - path[idx].start + 1;
528                                 path[idx].mid =
529                                         path[idx].start + path[idx].len / 2;
530                         }
531                 }
532         }
533
534         if (cont_path_cnt == 0) {
535                 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
536                 goto finish;
537         } else {
538                 /* Calculate last continuous path length and middle point */
539                 int idx = cont_path_cnt - 1;
540                 path[idx].len = path[idx].end - path[idx].start + 1;
541                 path[idx].mid = path[idx].start + path[idx].len / 2;
542         }
543
544         /* Connect the first and last continuous paths if they are adjacent */
545         if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
546                 /* Using negative index */
547                 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
548                 path[0].len += path[cont_path_cnt - 1].len;
549                 path[0].mid = path[0].start + path[0].len / 2;
550                 /* Convert negative middle point index to positive one */
551                 if (path[0].mid < 0)
552                         path[0].mid += MAX_PHASE + 1;
553                 cont_path_cnt--;
554         }
555
556         /* Choose the longest continuous phase path */
557         max_len = 0;
558         final_phase = 0;
559         final_path_idx = 0;
560         for (i = 0; i < cont_path_cnt; i++) {
561                 if (path[i].len > max_len) {
562                         max_len = path[i].len;
563                         final_phase = (u8)path[i].mid;
564                         final_path_idx = i;
565                 }
566
567                 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
568                                 i, path[i].start);
569                 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
570                                 i, path[i].end);
571                 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
572                                 i, path[i].len);
573                 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
574                                 i, path[i].mid);
575         }
576
577 finish:
578         dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
579         return final_phase;
580 }
581
582 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
583 {
584         int err, i;
585         u8 val = 0;
586
587         for (i = 0; i < 100; i++) {
588                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
589                 if (val & SD_DATA_IDLE)
590                         return;
591
592                 udelay(100);
593         }
594 }
595
596 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
597                 u8 opcode, u8 sample_point)
598 {
599         int err;
600         u8 cmd[5] = {0};
601
602         err = sd_change_phase(host, sample_point);
603         if (err < 0)
604                 return err;
605
606         cmd[0] = 0x40 | opcode;
607         err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
608         if (err < 0) {
609                 /* Wait till SD DATA IDLE */
610                 sd_wait_data_idle(host);
611                 sd_clear_error(host);
612                 return err;
613         }
614
615         return 0;
616 }
617
618 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
619                 u8 opcode, u32 *phase_map)
620 {
621         int err, i;
622         u32 raw_phase_map = 0;
623
624         for (i = MAX_PHASE; i >= 0; i--) {
625                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
626                 if (err == 0)
627                         raw_phase_map |= 1 << i;
628         }
629
630         if (phase_map)
631                 *phase_map = raw_phase_map;
632
633         return 0;
634 }
635
636 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
637 {
638         int err, i;
639         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
640         u8 final_phase;
641
642         for (i = 0; i < RX_TUNING_CNT; i++) {
643                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
644                 if (err < 0)
645                         return err;
646
647                 if (raw_phase_map[i] == 0)
648                         break;
649         }
650
651         phase_map = 0xFFFFFFFF;
652         for (i = 0; i < RX_TUNING_CNT; i++) {
653                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
654                                 i, raw_phase_map[i]);
655                 phase_map &= raw_phase_map[i];
656         }
657         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
658
659         if (phase_map) {
660                 final_phase = sd_search_final_phase(host, phase_map);
661                 if (final_phase == 0xFF)
662                         return -EINVAL;
663
664                 err = sd_change_phase(host, final_phase);
665                 if (err < 0)
666                         return err;
667         } else {
668                 return -EINVAL;
669         }
670
671         return 0;
672 }
673
674 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
675 {
676         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
677         struct rtsx_pcr *pcr = host->pcr;
678         struct mmc_command *cmd = mrq->cmd;
679         struct mmc_data *data = mrq->data;
680         unsigned int data_size = 0;
681         int err;
682
683         if (host->eject) {
684                 cmd->error = -ENOMEDIUM;
685                 goto finish;
686         }
687
688         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
689         if (err) {
690                 cmd->error = err;
691                 goto finish;
692         }
693
694         mutex_lock(&pcr->pcr_mutex);
695
696         rtsx_pci_start_run(pcr);
697
698         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
699                         host->initial_mode, host->double_clk, host->vpclk);
700         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
701         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
702                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
703
704         mutex_lock(&host->host_mutex);
705         host->mrq = mrq;
706         mutex_unlock(&host->host_mutex);
707
708         if (mrq->data)
709                 data_size = data->blocks * data->blksz;
710
711         if (!data_size || mmc_op_multi(cmd->opcode) ||
712                         (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
713                         (cmd->opcode == MMC_WRITE_BLOCK)) {
714                 sd_send_cmd_get_rsp(host, cmd);
715
716                 if (!cmd->error && data_size) {
717                         sd_rw_multi(host, mrq);
718
719                         if (mmc_op_multi(cmd->opcode) && mrq->stop)
720                                 sd_send_cmd_get_rsp(host, mrq->stop);
721                 }
722         } else {
723                 sd_normal_rw(host, mrq);
724         }
725
726         if (mrq->data) {
727                 if (cmd->error || data->error)
728                         data->bytes_xfered = 0;
729                 else
730                         data->bytes_xfered = data->blocks * data->blksz;
731         }
732
733         mutex_unlock(&pcr->pcr_mutex);
734
735 finish:
736         if (cmd->error)
737                 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
738
739         mutex_lock(&host->host_mutex);
740         host->mrq = NULL;
741         mutex_unlock(&host->host_mutex);
742
743         mmc_request_done(mmc, mrq);
744 }
745
746 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
747                 unsigned char bus_width)
748 {
749         int err = 0;
750         u8 width[] = {
751                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
752                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
753                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
754         };
755
756         if (bus_width <= MMC_BUS_WIDTH_8)
757                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
758                                 0x03, width[bus_width]);
759
760         return err;
761 }
762
763 static int sd_power_on(struct realtek_pci_sdmmc *host)
764 {
765         struct rtsx_pcr *pcr = host->pcr;
766         int err;
767
768         rtsx_pci_init_cmd(pcr);
769         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
770         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
771                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
772         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
773                         SD_CLK_EN, SD_CLK_EN);
774         err = rtsx_pci_send_cmd(pcr, 100);
775         if (err < 0)
776                 return err;
777
778         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
779         if (err < 0)
780                 return err;
781
782         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
783         if (err < 0)
784                 return err;
785
786         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
787         if (err < 0)
788                 return err;
789
790         return 0;
791 }
792
793 static int sd_power_off(struct realtek_pci_sdmmc *host)
794 {
795         struct rtsx_pcr *pcr = host->pcr;
796         int err;
797
798         rtsx_pci_init_cmd(pcr);
799
800         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
801         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
802
803         err = rtsx_pci_send_cmd(pcr, 100);
804         if (err < 0)
805                 return err;
806
807         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
808         if (err < 0)
809                 return err;
810
811         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
812 }
813
814 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
815                 unsigned char power_mode)
816 {
817         int err;
818
819         if (power_mode == MMC_POWER_OFF)
820                 err = sd_power_off(host);
821         else
822                 err = sd_power_on(host);
823
824         return err;
825 }
826
827 static int sd_set_timing(struct realtek_pci_sdmmc *host,
828                 unsigned char timing, bool *ddr_mode)
829 {
830         struct rtsx_pcr *pcr = host->pcr;
831         int err = 0;
832
833         *ddr_mode = false;
834
835         rtsx_pci_init_cmd(pcr);
836
837         switch (timing) {
838         case MMC_TIMING_UHS_SDR104:
839         case MMC_TIMING_UHS_SDR50:
840                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
841                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
842                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
843                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
844                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
845                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
846                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
847                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
848                 break;
849
850         case MMC_TIMING_UHS_DDR50:
851                 *ddr_mode = true;
852
853                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
854                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
855                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
856                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
857                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
858                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
859                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
860                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
861                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
862                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
863                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
864                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
865                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
866                 break;
867
868         case MMC_TIMING_MMC_HS:
869         case MMC_TIMING_SD_HS:
870                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
871                                 0x0C, SD_20_MODE);
872                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
873                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
874                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
875                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
876                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
877                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
878                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
879                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
880                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
881                 break;
882
883         default:
884                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
885                                 SD_CFG1, 0x0C, SD_20_MODE);
886                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
887                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
888                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
889                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
890                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
891                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
892                                 SD_PUSH_POINT_CTL, 0xFF, 0);
893                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
894                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
895                 break;
896         }
897
898         err = rtsx_pci_send_cmd(pcr, 100);
899
900         return err;
901 }
902
903 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
904 {
905         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
906         struct rtsx_pcr *pcr = host->pcr;
907
908         if (host->eject)
909                 return;
910
911         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
912                 return;
913
914         mutex_lock(&pcr->pcr_mutex);
915
916         rtsx_pci_start_run(pcr);
917
918         sd_set_bus_width(host, ios->bus_width);
919         sd_set_power_mode(host, ios->power_mode);
920         sd_set_timing(host, ios->timing, &host->ddr_mode);
921
922         host->vpclk = false;
923         host->double_clk = true;
924
925         switch (ios->timing) {
926         case MMC_TIMING_UHS_SDR104:
927         case MMC_TIMING_UHS_SDR50:
928                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
929                 host->vpclk = true;
930                 host->double_clk = false;
931                 break;
932         case MMC_TIMING_UHS_DDR50:
933         case MMC_TIMING_UHS_SDR25:
934                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
935                 break;
936         default:
937                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
938                 break;
939         }
940
941         host->initial_mode = (ios->clock <= 1000000) ? true : false;
942
943         host->clock = ios->clock;
944         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
945                         host->initial_mode, host->double_clk, host->vpclk);
946
947         mutex_unlock(&pcr->pcr_mutex);
948 }
949
950 static int sdmmc_get_ro(struct mmc_host *mmc)
951 {
952         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
953         struct rtsx_pcr *pcr = host->pcr;
954         int ro = 0;
955         u32 val;
956
957         if (host->eject)
958                 return -ENOMEDIUM;
959
960         mutex_lock(&pcr->pcr_mutex);
961
962         rtsx_pci_start_run(pcr);
963
964         /* Check SD mechanical write-protect switch */
965         val = rtsx_pci_readl(pcr, RTSX_BIPR);
966         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
967         if (val & SD_WRITE_PROTECT)
968                 ro = 1;
969
970         mutex_unlock(&pcr->pcr_mutex);
971
972         return ro;
973 }
974
975 static int sdmmc_get_cd(struct mmc_host *mmc)
976 {
977         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
978         struct rtsx_pcr *pcr = host->pcr;
979         int cd = 0;
980         u32 val;
981
982         if (host->eject)
983                 return -ENOMEDIUM;
984
985         mutex_lock(&pcr->pcr_mutex);
986
987         rtsx_pci_start_run(pcr);
988
989         /* Check SD card detect */
990         val = rtsx_pci_card_exist(pcr);
991         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
992         if (val & SD_EXIST)
993                 cd = 1;
994
995         mutex_unlock(&pcr->pcr_mutex);
996
997         return cd;
998 }
999
1000 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1001 {
1002         struct rtsx_pcr *pcr = host->pcr;
1003         int err;
1004         u8 stat;
1005
1006         /* Reference to Signal Voltage Switch Sequence in SD spec.
1007          * Wait for a period of time so that the card can drive SD_CMD and
1008          * SD_DAT[3:0] to low after sending back CMD11 response.
1009          */
1010         mdelay(1);
1011
1012         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1013          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1014          * abort the voltage switch sequence;
1015          */
1016         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1017         if (err < 0)
1018                 return err;
1019
1020         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1021                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1022                 return -EINVAL;
1023
1024         /* Stop toggle SD clock */
1025         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1026                         0xFF, SD_CLK_FORCE_STOP);
1027         if (err < 0)
1028                 return err;
1029
1030         return 0;
1031 }
1032
1033 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1034 {
1035         struct rtsx_pcr *pcr = host->pcr;
1036         int err;
1037         u8 stat, mask, val;
1038
1039         /* Wait 1.8V output of voltage regulator in card stable */
1040         msleep(50);
1041
1042         /* Toggle SD clock again */
1043         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1044         if (err < 0)
1045                 return err;
1046
1047         /* Wait for a period of time so that the card can drive
1048          * SD_DAT[3:0] to high at 1.8V
1049          */
1050         msleep(20);
1051
1052         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1053         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1054         if (err < 0)
1055                 return err;
1056
1057         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1058                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1059         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1060                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1061         if ((stat & mask) != val) {
1062                 dev_dbg(sdmmc_dev(host),
1063                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1064                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1065                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1066                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1067                 return -EINVAL;
1068         }
1069
1070         return 0;
1071 }
1072
1073 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1074 {
1075         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1076         struct rtsx_pcr *pcr = host->pcr;
1077         int err = 0;
1078         u8 voltage;
1079
1080         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1081                         __func__, ios->signal_voltage);
1082
1083         if (host->eject)
1084                 return -ENOMEDIUM;
1085
1086         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1087         if (err)
1088                 return err;
1089
1090         mutex_lock(&pcr->pcr_mutex);
1091
1092         rtsx_pci_start_run(pcr);
1093
1094         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1095                 voltage = OUTPUT_3V3;
1096         else
1097                 voltage = OUTPUT_1V8;
1098
1099         if (voltage == OUTPUT_1V8) {
1100                 err = sd_wait_voltage_stable_1(host);
1101                 if (err < 0)
1102                         goto out;
1103         }
1104
1105         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1106         if (err < 0)
1107                 goto out;
1108
1109         if (voltage == OUTPUT_1V8) {
1110                 err = sd_wait_voltage_stable_2(host);
1111                 if (err < 0)
1112                         goto out;
1113         }
1114
1115         /* Stop toggle SD clock in idle */
1116         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1117                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1118
1119 out:
1120         mutex_unlock(&pcr->pcr_mutex);
1121
1122         return err;
1123 }
1124
1125 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1126 {
1127         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1128         struct rtsx_pcr *pcr = host->pcr;
1129         int err = 0;
1130
1131         if (host->eject)
1132                 return -ENOMEDIUM;
1133
1134         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1135         if (err)
1136                 return err;
1137
1138         mutex_lock(&pcr->pcr_mutex);
1139
1140         rtsx_pci_start_run(pcr);
1141
1142         if (!host->ddr_mode)
1143                 err = sd_tuning_rx(host, MMC_SEND_TUNING_BLOCK);
1144
1145         mutex_unlock(&pcr->pcr_mutex);
1146
1147         return err;
1148 }
1149
1150 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1151         .request = sdmmc_request,
1152         .set_ios = sdmmc_set_ios,
1153         .get_ro = sdmmc_get_ro,
1154         .get_cd = sdmmc_get_cd,
1155         .start_signal_voltage_switch = sdmmc_switch_voltage,
1156         .execute_tuning = sdmmc_execute_tuning,
1157 };
1158
1159 #ifdef CONFIG_PM
1160 static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1161                 pm_message_t state)
1162 {
1163         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1164         struct mmc_host *mmc = host->mmc;
1165         int err;
1166
1167         dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1168
1169         err = mmc_suspend_host(mmc);
1170         if (err)
1171                 return err;
1172
1173         return 0;
1174 }
1175
1176 static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1177 {
1178         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1179         struct mmc_host *mmc = host->mmc;
1180
1181         dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1182
1183         return mmc_resume_host(mmc);
1184 }
1185 #else /* CONFIG_PM */
1186 #define rtsx_pci_sdmmc_suspend NULL
1187 #define rtsx_pci_sdmmc_resume NULL
1188 #endif /* CONFIG_PM */
1189
1190 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1191 {
1192         struct mmc_host *mmc = host->mmc;
1193         struct rtsx_pcr *pcr = host->pcr;
1194
1195         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1196
1197         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1198                 mmc->caps |= MMC_CAP_UHS_SDR50;
1199         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1200                 mmc->caps |= MMC_CAP_UHS_SDR104;
1201         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1202                 mmc->caps |= MMC_CAP_UHS_DDR50;
1203         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1204                 mmc->caps |= MMC_CAP_1_8V_DDR;
1205         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1206                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1207 }
1208
1209 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1210 {
1211         struct mmc_host *mmc = host->mmc;
1212
1213         mmc->f_min = 250000;
1214         mmc->f_max = 208000000;
1215         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1216         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1217                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1218                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1219         mmc->max_current_330 = 400;
1220         mmc->max_current_180 = 800;
1221         mmc->ops = &realtek_pci_sdmmc_ops;
1222
1223         init_extra_caps(host);
1224
1225         mmc->max_segs = 256;
1226         mmc->max_seg_size = 65536;
1227         mmc->max_blk_size = 512;
1228         mmc->max_blk_count = 65535;
1229         mmc->max_req_size = 524288;
1230 }
1231
1232 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1233 {
1234         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1235
1236         mmc_detect_change(host->mmc, 0);
1237 }
1238
1239 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1240 {
1241         struct mmc_host *mmc;
1242         struct realtek_pci_sdmmc *host;
1243         struct rtsx_pcr *pcr;
1244         struct pcr_handle *handle = pdev->dev.platform_data;
1245
1246         if (!handle)
1247                 return -ENXIO;
1248
1249         pcr = handle->pcr;
1250         if (!pcr)
1251                 return -ENXIO;
1252
1253         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1254
1255         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1256         if (!mmc)
1257                 return -ENOMEM;
1258
1259         host = mmc_priv(mmc);
1260         host->pcr = pcr;
1261         host->mmc = mmc;
1262         host->pdev = pdev;
1263         platform_set_drvdata(pdev, host);
1264         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1265         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1266
1267         mutex_init(&host->host_mutex);
1268
1269         realtek_init_host(host);
1270
1271         mmc_add_host(mmc);
1272
1273         return 0;
1274 }
1275
1276 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1277 {
1278         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1279         struct rtsx_pcr *pcr;
1280         struct mmc_host *mmc;
1281
1282         if (!host)
1283                 return 0;
1284
1285         pcr = host->pcr;
1286         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1287         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1288         mmc = host->mmc;
1289         host->eject = true;
1290
1291         mutex_lock(&host->host_mutex);
1292         if (host->mrq) {
1293                 dev_dbg(&(pdev->dev),
1294                         "%s: Controller removed during transfer\n",
1295                         mmc_hostname(mmc));
1296
1297                 rtsx_pci_complete_unfinished_transfer(pcr);
1298
1299                 host->mrq->cmd->error = -ENOMEDIUM;
1300                 if (host->mrq->stop)
1301                         host->mrq->stop->error = -ENOMEDIUM;
1302                 mmc_request_done(mmc, host->mrq);
1303         }
1304         mutex_unlock(&host->host_mutex);
1305
1306         mmc_remove_host(mmc);
1307         mmc_free_host(mmc);
1308
1309         platform_set_drvdata(pdev, NULL);
1310
1311         dev_dbg(&(pdev->dev),
1312                 ": Realtek PCI-E SDMMC controller has been removed\n");
1313
1314         return 0;
1315 }
1316
1317 static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1318         {
1319                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1320         }, {
1321                 /* sentinel */
1322         }
1323 };
1324 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1325
1326 static struct platform_driver rtsx_pci_sdmmc_driver = {
1327         .probe          = rtsx_pci_sdmmc_drv_probe,
1328         .remove         = rtsx_pci_sdmmc_drv_remove,
1329         .id_table       = rtsx_pci_sdmmc_ids,
1330         .suspend        = rtsx_pci_sdmmc_suspend,
1331         .resume         = rtsx_pci_sdmmc_resume,
1332         .driver         = {
1333                 .owner  = THIS_MODULE,
1334                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1335         },
1336 };
1337 module_platform_driver(rtsx_pci_sdmmc_driver);
1338
1339 MODULE_LICENSE("GPL");
1340 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1341 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");