mmc: sdhci: R1B command handling + MMC_CAP_ERASE.
[~shefty/rdma-dev.git] / drivers / mmc / host / sdhci.c
1 /*
2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3  *
4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or (at
9  * your option) any later version.
10  *
11  * Thanks to the following companies for their support:
12  *
13  *     - JMicron (hardware and technical support)
14  */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <linux/leds.h>
25
26 #include <linux/mmc/mmc.h>
27 #include <linux/mmc/host.h>
28
29 #include "sdhci.h"
30
31 #define DRIVER_NAME "sdhci"
32
33 #define DBG(f, x...) \
34         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
35
36 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37         defined(CONFIG_MMC_SDHCI_MODULE))
38 #define SDHCI_USE_LEDS_CLASS
39 #endif
40
41 static unsigned int debug_quirks = 0;
42
43 static void sdhci_finish_data(struct sdhci_host *);
44
45 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
46 static void sdhci_finish_command(struct sdhci_host *);
47
48 static void sdhci_dumpregs(struct sdhci_host *host)
49 {
50         printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
51                 mmc_hostname(host->mmc));
52
53         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
54                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
55                 sdhci_readw(host, SDHCI_HOST_VERSION));
56         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
57                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
58                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
59         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
60                 sdhci_readl(host, SDHCI_ARGUMENT),
61                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
62         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
63                 sdhci_readl(host, SDHCI_PRESENT_STATE),
64                 sdhci_readb(host, SDHCI_HOST_CONTROL));
65         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
66                 sdhci_readb(host, SDHCI_POWER_CONTROL),
67                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
68         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
69                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
70                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
71         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
72                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
73                 sdhci_readl(host, SDHCI_INT_STATUS));
74         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
75                 sdhci_readl(host, SDHCI_INT_ENABLE),
76                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
77         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
78                 sdhci_readw(host, SDHCI_ACMD12_ERR),
79                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
80         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
81                 sdhci_readl(host, SDHCI_CAPABILITIES),
82                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
83         printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
84                 sdhci_readw(host, SDHCI_COMMAND),
85                 sdhci_readl(host, SDHCI_MAX_CURRENT));
86
87         if (host->flags & SDHCI_USE_ADMA)
88                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
89                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
90                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
91
92         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
93 }
94
95 /*****************************************************************************\
96  *                                                                           *
97  * Low level functions                                                       *
98  *                                                                           *
99 \*****************************************************************************/
100
101 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
102 {
103         u32 ier;
104
105         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
106         ier &= ~clear;
107         ier |= set;
108         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
109         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
110 }
111
112 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
113 {
114         sdhci_clear_set_irqs(host, 0, irqs);
115 }
116
117 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
118 {
119         sdhci_clear_set_irqs(host, irqs, 0);
120 }
121
122 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
123 {
124         u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
125
126         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
127                 return;
128
129         if (enable)
130                 sdhci_unmask_irqs(host, irqs);
131         else
132                 sdhci_mask_irqs(host, irqs);
133 }
134
135 static void sdhci_enable_card_detection(struct sdhci_host *host)
136 {
137         sdhci_set_card_detection(host, true);
138 }
139
140 static void sdhci_disable_card_detection(struct sdhci_host *host)
141 {
142         sdhci_set_card_detection(host, false);
143 }
144
145 static void sdhci_reset(struct sdhci_host *host, u8 mask)
146 {
147         unsigned long timeout;
148         u32 uninitialized_var(ier);
149
150         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
151                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
152                         SDHCI_CARD_PRESENT))
153                         return;
154         }
155
156         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
157                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
158
159         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
160
161         if (mask & SDHCI_RESET_ALL)
162                 host->clock = 0;
163
164         /* Wait max 100 ms */
165         timeout = 100;
166
167         /* hw clears the bit when it's done */
168         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
169                 if (timeout == 0) {
170                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
171                                 mmc_hostname(host->mmc), (int)mask);
172                         sdhci_dumpregs(host);
173                         return;
174                 }
175                 timeout--;
176                 mdelay(1);
177         }
178
179         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
180                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
181 }
182
183 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
184
185 static void sdhci_init(struct sdhci_host *host, int soft)
186 {
187         if (soft)
188                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
189         else
190                 sdhci_reset(host, SDHCI_RESET_ALL);
191
192         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
193                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
194                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
195                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
196                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
197
198         if (soft) {
199                 /* force clock reconfiguration */
200                 host->clock = 0;
201                 sdhci_set_ios(host->mmc, &host->mmc->ios);
202         }
203 }
204
205 static void sdhci_reinit(struct sdhci_host *host)
206 {
207         sdhci_init(host, 0);
208         sdhci_enable_card_detection(host);
209 }
210
211 static void sdhci_activate_led(struct sdhci_host *host)
212 {
213         u8 ctrl;
214
215         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
216         ctrl |= SDHCI_CTRL_LED;
217         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
218 }
219
220 static void sdhci_deactivate_led(struct sdhci_host *host)
221 {
222         u8 ctrl;
223
224         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
225         ctrl &= ~SDHCI_CTRL_LED;
226         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
227 }
228
229 #ifdef SDHCI_USE_LEDS_CLASS
230 static void sdhci_led_control(struct led_classdev *led,
231         enum led_brightness brightness)
232 {
233         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
234         unsigned long flags;
235
236         spin_lock_irqsave(&host->lock, flags);
237
238         if (brightness == LED_OFF)
239                 sdhci_deactivate_led(host);
240         else
241                 sdhci_activate_led(host);
242
243         spin_unlock_irqrestore(&host->lock, flags);
244 }
245 #endif
246
247 /*****************************************************************************\
248  *                                                                           *
249  * Core functions                                                            *
250  *                                                                           *
251 \*****************************************************************************/
252
253 static void sdhci_read_block_pio(struct sdhci_host *host)
254 {
255         unsigned long flags;
256         size_t blksize, len, chunk;
257         u32 uninitialized_var(scratch);
258         u8 *buf;
259
260         DBG("PIO reading\n");
261
262         blksize = host->data->blksz;
263         chunk = 0;
264
265         local_irq_save(flags);
266
267         while (blksize) {
268                 if (!sg_miter_next(&host->sg_miter))
269                         BUG();
270
271                 len = min(host->sg_miter.length, blksize);
272
273                 blksize -= len;
274                 host->sg_miter.consumed = len;
275
276                 buf = host->sg_miter.addr;
277
278                 while (len) {
279                         if (chunk == 0) {
280                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
281                                 chunk = 4;
282                         }
283
284                         *buf = scratch & 0xFF;
285
286                         buf++;
287                         scratch >>= 8;
288                         chunk--;
289                         len--;
290                 }
291         }
292
293         sg_miter_stop(&host->sg_miter);
294
295         local_irq_restore(flags);
296 }
297
298 static void sdhci_write_block_pio(struct sdhci_host *host)
299 {
300         unsigned long flags;
301         size_t blksize, len, chunk;
302         u32 scratch;
303         u8 *buf;
304
305         DBG("PIO writing\n");
306
307         blksize = host->data->blksz;
308         chunk = 0;
309         scratch = 0;
310
311         local_irq_save(flags);
312
313         while (blksize) {
314                 if (!sg_miter_next(&host->sg_miter))
315                         BUG();
316
317                 len = min(host->sg_miter.length, blksize);
318
319                 blksize -= len;
320                 host->sg_miter.consumed = len;
321
322                 buf = host->sg_miter.addr;
323
324                 while (len) {
325                         scratch |= (u32)*buf << (chunk * 8);
326
327                         buf++;
328                         chunk++;
329                         len--;
330
331                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
332                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
333                                 chunk = 0;
334                                 scratch = 0;
335                         }
336                 }
337         }
338
339         sg_miter_stop(&host->sg_miter);
340
341         local_irq_restore(flags);
342 }
343
344 static void sdhci_transfer_pio(struct sdhci_host *host)
345 {
346         u32 mask;
347
348         BUG_ON(!host->data);
349
350         if (host->blocks == 0)
351                 return;
352
353         if (host->data->flags & MMC_DATA_READ)
354                 mask = SDHCI_DATA_AVAILABLE;
355         else
356                 mask = SDHCI_SPACE_AVAILABLE;
357
358         /*
359          * Some controllers (JMicron JMB38x) mess up the buffer bits
360          * for transfers < 4 bytes. As long as it is just one block,
361          * we can ignore the bits.
362          */
363         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
364                 (host->data->blocks == 1))
365                 mask = ~0;
366
367         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
368                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
369                         udelay(100);
370
371                 if (host->data->flags & MMC_DATA_READ)
372                         sdhci_read_block_pio(host);
373                 else
374                         sdhci_write_block_pio(host);
375
376                 host->blocks--;
377                 if (host->blocks == 0)
378                         break;
379         }
380
381         DBG("PIO transfer complete.\n");
382 }
383
384 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
385 {
386         local_irq_save(*flags);
387         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
388 }
389
390 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
391 {
392         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
393         local_irq_restore(*flags);
394 }
395
396 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
397 {
398         __le32 *dataddr = (__le32 __force *)(desc + 4);
399         __le16 *cmdlen = (__le16 __force *)desc;
400
401         /* SDHCI specification says ADMA descriptors should be 4 byte
402          * aligned, so using 16 or 32bit operations should be safe. */
403
404         cmdlen[0] = cpu_to_le16(cmd);
405         cmdlen[1] = cpu_to_le16(len);
406
407         dataddr[0] = cpu_to_le32(addr);
408 }
409
410 static int sdhci_adma_table_pre(struct sdhci_host *host,
411         struct mmc_data *data)
412 {
413         int direction;
414
415         u8 *desc;
416         u8 *align;
417         dma_addr_t addr;
418         dma_addr_t align_addr;
419         int len, offset;
420
421         struct scatterlist *sg;
422         int i;
423         char *buffer;
424         unsigned long flags;
425
426         /*
427          * The spec does not specify endianness of descriptor table.
428          * We currently guess that it is LE.
429          */
430
431         if (data->flags & MMC_DATA_READ)
432                 direction = DMA_FROM_DEVICE;
433         else
434                 direction = DMA_TO_DEVICE;
435
436         /*
437          * The ADMA descriptor table is mapped further down as we
438          * need to fill it with data first.
439          */
440
441         host->align_addr = dma_map_single(mmc_dev(host->mmc),
442                 host->align_buffer, 128 * 4, direction);
443         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
444                 goto fail;
445         BUG_ON(host->align_addr & 0x3);
446
447         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
448                 data->sg, data->sg_len, direction);
449         if (host->sg_count == 0)
450                 goto unmap_align;
451
452         desc = host->adma_desc;
453         align = host->align_buffer;
454
455         align_addr = host->align_addr;
456
457         for_each_sg(data->sg, sg, host->sg_count, i) {
458                 addr = sg_dma_address(sg);
459                 len = sg_dma_len(sg);
460
461                 /*
462                  * The SDHCI specification states that ADMA
463                  * addresses must be 32-bit aligned. If they
464                  * aren't, then we use a bounce buffer for
465                  * the (up to three) bytes that screw up the
466                  * alignment.
467                  */
468                 offset = (4 - (addr & 0x3)) & 0x3;
469                 if (offset) {
470                         if (data->flags & MMC_DATA_WRITE) {
471                                 buffer = sdhci_kmap_atomic(sg, &flags);
472                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
473                                 memcpy(align, buffer, offset);
474                                 sdhci_kunmap_atomic(buffer, &flags);
475                         }
476
477                         /* tran, valid */
478                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
479
480                         BUG_ON(offset > 65536);
481
482                         align += 4;
483                         align_addr += 4;
484
485                         desc += 8;
486
487                         addr += offset;
488                         len -= offset;
489                 }
490
491                 BUG_ON(len > 65536);
492
493                 /* tran, valid */
494                 sdhci_set_adma_desc(desc, addr, len, 0x21);
495                 desc += 8;
496
497                 /*
498                  * If this triggers then we have a calculation bug
499                  * somewhere. :/
500                  */
501                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
502         }
503
504         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
505                 /*
506                 * Mark the last descriptor as the terminating descriptor
507                 */
508                 if (desc != host->adma_desc) {
509                         desc -= 8;
510                         desc[0] |= 0x2; /* end */
511                 }
512         } else {
513                 /*
514                 * Add a terminating entry.
515                 */
516
517                 /* nop, end, valid */
518                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
519         }
520
521         /*
522          * Resync align buffer as we might have changed it.
523          */
524         if (data->flags & MMC_DATA_WRITE) {
525                 dma_sync_single_for_device(mmc_dev(host->mmc),
526                         host->align_addr, 128 * 4, direction);
527         }
528
529         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
530                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
531         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
532                 goto unmap_entries;
533         BUG_ON(host->adma_addr & 0x3);
534
535         return 0;
536
537 unmap_entries:
538         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
539                 data->sg_len, direction);
540 unmap_align:
541         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
542                 128 * 4, direction);
543 fail:
544         return -EINVAL;
545 }
546
547 static void sdhci_adma_table_post(struct sdhci_host *host,
548         struct mmc_data *data)
549 {
550         int direction;
551
552         struct scatterlist *sg;
553         int i, size;
554         u8 *align;
555         char *buffer;
556         unsigned long flags;
557
558         if (data->flags & MMC_DATA_READ)
559                 direction = DMA_FROM_DEVICE;
560         else
561                 direction = DMA_TO_DEVICE;
562
563         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
564                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
565
566         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
567                 128 * 4, direction);
568
569         if (data->flags & MMC_DATA_READ) {
570                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
571                         data->sg_len, direction);
572
573                 align = host->align_buffer;
574
575                 for_each_sg(data->sg, sg, host->sg_count, i) {
576                         if (sg_dma_address(sg) & 0x3) {
577                                 size = 4 - (sg_dma_address(sg) & 0x3);
578
579                                 buffer = sdhci_kmap_atomic(sg, &flags);
580                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
581                                 memcpy(buffer, align, size);
582                                 sdhci_kunmap_atomic(buffer, &flags);
583
584                                 align += 4;
585                         }
586                 }
587         }
588
589         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
590                 data->sg_len, direction);
591 }
592
593 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
594 {
595         u8 count;
596         struct mmc_data *data = cmd->data;
597         unsigned target_timeout, current_timeout;
598
599         /*
600          * If the host controller provides us with an incorrect timeout
601          * value, just skip the check and use 0xE.  The hardware may take
602          * longer to time out, but that's much better than having a too-short
603          * timeout value.
604          */
605         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
606                 return 0xE;
607
608         /* Unspecified timeout, assume max */
609         if (!data && !cmd->cmd_timeout_ms)
610                 return 0xE;
611
612         /* timeout in us */
613         if (!data)
614                 target_timeout = cmd->cmd_timeout_ms * 1000;
615         else
616                 target_timeout = data->timeout_ns / 1000 +
617                         data->timeout_clks / host->clock;
618
619         /*
620          * Figure out needed cycles.
621          * We do this in steps in order to fit inside a 32 bit int.
622          * The first step is the minimum timeout, which will have a
623          * minimum resolution of 6 bits:
624          * (1) 2^13*1000 > 2^22,
625          * (2) host->timeout_clk < 2^16
626          *     =>
627          *     (1) / (2) > 2^6
628          */
629         count = 0;
630         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
631         while (current_timeout < target_timeout) {
632                 count++;
633                 current_timeout <<= 1;
634                 if (count >= 0xF)
635                         break;
636         }
637
638         if (count >= 0xF) {
639                 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
640                        mmc_hostname(host->mmc), cmd->opcode);
641                 count = 0xE;
642         }
643
644         return count;
645 }
646
647 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
648 {
649         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
650         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
651
652         if (host->flags & SDHCI_REQ_USE_DMA)
653                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
654         else
655                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
656 }
657
658 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
659 {
660         u8 count;
661         u8 ctrl;
662         struct mmc_data *data = cmd->data;
663         int ret;
664
665         WARN_ON(host->data);
666
667         if (data || (cmd->flags & MMC_RSP_BUSY)) {
668                 count = sdhci_calc_timeout(host, cmd);
669                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
670         }
671
672         if (!data)
673                 return;
674
675         /* Sanity checks */
676         BUG_ON(data->blksz * data->blocks > 524288);
677         BUG_ON(data->blksz > host->mmc->max_blk_size);
678         BUG_ON(data->blocks > 65535);
679
680         host->data = data;
681         host->data_early = 0;
682
683         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
684                 host->flags |= SDHCI_REQ_USE_DMA;
685
686         /*
687          * FIXME: This doesn't account for merging when mapping the
688          * scatterlist.
689          */
690         if (host->flags & SDHCI_REQ_USE_DMA) {
691                 int broken, i;
692                 struct scatterlist *sg;
693
694                 broken = 0;
695                 if (host->flags & SDHCI_USE_ADMA) {
696                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
697                                 broken = 1;
698                 } else {
699                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
700                                 broken = 1;
701                 }
702
703                 if (unlikely(broken)) {
704                         for_each_sg(data->sg, sg, data->sg_len, i) {
705                                 if (sg->length & 0x3) {
706                                         DBG("Reverting to PIO because of "
707                                                 "transfer size (%d)\n",
708                                                 sg->length);
709                                         host->flags &= ~SDHCI_REQ_USE_DMA;
710                                         break;
711                                 }
712                         }
713                 }
714         }
715
716         /*
717          * The assumption here being that alignment is the same after
718          * translation to device address space.
719          */
720         if (host->flags & SDHCI_REQ_USE_DMA) {
721                 int broken, i;
722                 struct scatterlist *sg;
723
724                 broken = 0;
725                 if (host->flags & SDHCI_USE_ADMA) {
726                         /*
727                          * As we use 3 byte chunks to work around
728                          * alignment problems, we need to check this
729                          * quirk.
730                          */
731                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
732                                 broken = 1;
733                 } else {
734                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
735                                 broken = 1;
736                 }
737
738                 if (unlikely(broken)) {
739                         for_each_sg(data->sg, sg, data->sg_len, i) {
740                                 if (sg->offset & 0x3) {
741                                         DBG("Reverting to PIO because of "
742                                                 "bad alignment\n");
743                                         host->flags &= ~SDHCI_REQ_USE_DMA;
744                                         break;
745                                 }
746                         }
747                 }
748         }
749
750         if (host->flags & SDHCI_REQ_USE_DMA) {
751                 if (host->flags & SDHCI_USE_ADMA) {
752                         ret = sdhci_adma_table_pre(host, data);
753                         if (ret) {
754                                 /*
755                                  * This only happens when someone fed
756                                  * us an invalid request.
757                                  */
758                                 WARN_ON(1);
759                                 host->flags &= ~SDHCI_REQ_USE_DMA;
760                         } else {
761                                 sdhci_writel(host, host->adma_addr,
762                                         SDHCI_ADMA_ADDRESS);
763                         }
764                 } else {
765                         int sg_cnt;
766
767                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
768                                         data->sg, data->sg_len,
769                                         (data->flags & MMC_DATA_READ) ?
770                                                 DMA_FROM_DEVICE :
771                                                 DMA_TO_DEVICE);
772                         if (sg_cnt == 0) {
773                                 /*
774                                  * This only happens when someone fed
775                                  * us an invalid request.
776                                  */
777                                 WARN_ON(1);
778                                 host->flags &= ~SDHCI_REQ_USE_DMA;
779                         } else {
780                                 WARN_ON(sg_cnt != 1);
781                                 sdhci_writel(host, sg_dma_address(data->sg),
782                                         SDHCI_DMA_ADDRESS);
783                         }
784                 }
785         }
786
787         /*
788          * Always adjust the DMA selection as some controllers
789          * (e.g. JMicron) can't do PIO properly when the selection
790          * is ADMA.
791          */
792         if (host->version >= SDHCI_SPEC_200) {
793                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
794                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
795                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
796                         (host->flags & SDHCI_USE_ADMA))
797                         ctrl |= SDHCI_CTRL_ADMA32;
798                 else
799                         ctrl |= SDHCI_CTRL_SDMA;
800                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
801         }
802
803         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
804                 int flags;
805
806                 flags = SG_MITER_ATOMIC;
807                 if (host->data->flags & MMC_DATA_READ)
808                         flags |= SG_MITER_TO_SG;
809                 else
810                         flags |= SG_MITER_FROM_SG;
811                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
812                 host->blocks = data->blocks;
813         }
814
815         sdhci_set_transfer_irqs(host);
816
817         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
818         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
819         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
820 }
821
822 static void sdhci_set_transfer_mode(struct sdhci_host *host,
823         struct mmc_data *data)
824 {
825         u16 mode;
826
827         if (data == NULL)
828                 return;
829
830         WARN_ON(!host->data);
831
832         mode = SDHCI_TRNS_BLK_CNT_EN;
833         if (data->blocks > 1) {
834                 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
835                         mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
836                 else
837                         mode |= SDHCI_TRNS_MULTI;
838         }
839         if (data->flags & MMC_DATA_READ)
840                 mode |= SDHCI_TRNS_READ;
841         if (host->flags & SDHCI_REQ_USE_DMA)
842                 mode |= SDHCI_TRNS_DMA;
843
844         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
845 }
846
847 static void sdhci_finish_data(struct sdhci_host *host)
848 {
849         struct mmc_data *data;
850
851         BUG_ON(!host->data);
852
853         data = host->data;
854         host->data = NULL;
855
856         if (host->flags & SDHCI_REQ_USE_DMA) {
857                 if (host->flags & SDHCI_USE_ADMA)
858                         sdhci_adma_table_post(host, data);
859                 else {
860                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
861                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
862                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
863                 }
864         }
865
866         /*
867          * The specification states that the block count register must
868          * be updated, but it does not specify at what point in the
869          * data flow. That makes the register entirely useless to read
870          * back so we have to assume that nothing made it to the card
871          * in the event of an error.
872          */
873         if (data->error)
874                 data->bytes_xfered = 0;
875         else
876                 data->bytes_xfered = data->blksz * data->blocks;
877
878         if (data->stop) {
879                 /*
880                  * The controller needs a reset of internal state machines
881                  * upon error conditions.
882                  */
883                 if (data->error) {
884                         sdhci_reset(host, SDHCI_RESET_CMD);
885                         sdhci_reset(host, SDHCI_RESET_DATA);
886                 }
887
888                 sdhci_send_command(host, data->stop);
889         } else
890                 tasklet_schedule(&host->finish_tasklet);
891 }
892
893 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
894 {
895         int flags;
896         u32 mask;
897         unsigned long timeout;
898
899         WARN_ON(host->cmd);
900
901         /* Wait max 10 ms */
902         timeout = 10;
903
904         mask = SDHCI_CMD_INHIBIT;
905         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
906                 mask |= SDHCI_DATA_INHIBIT;
907
908         /* We shouldn't wait for data inihibit for stop commands, even
909            though they might use busy signaling */
910         if (host->mrq->data && (cmd == host->mrq->data->stop))
911                 mask &= ~SDHCI_DATA_INHIBIT;
912
913         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
914                 if (timeout == 0) {
915                         printk(KERN_ERR "%s: Controller never released "
916                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
917                         sdhci_dumpregs(host);
918                         cmd->error = -EIO;
919                         tasklet_schedule(&host->finish_tasklet);
920                         return;
921                 }
922                 timeout--;
923                 mdelay(1);
924         }
925
926         mod_timer(&host->timer, jiffies + 10 * HZ);
927
928         host->cmd = cmd;
929
930         sdhci_prepare_data(host, cmd);
931
932         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
933
934         sdhci_set_transfer_mode(host, cmd->data);
935
936         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
937                 printk(KERN_ERR "%s: Unsupported response type!\n",
938                         mmc_hostname(host->mmc));
939                 cmd->error = -EINVAL;
940                 tasklet_schedule(&host->finish_tasklet);
941                 return;
942         }
943
944         if (!(cmd->flags & MMC_RSP_PRESENT))
945                 flags = SDHCI_CMD_RESP_NONE;
946         else if (cmd->flags & MMC_RSP_136)
947                 flags = SDHCI_CMD_RESP_LONG;
948         else if (cmd->flags & MMC_RSP_BUSY)
949                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
950         else
951                 flags = SDHCI_CMD_RESP_SHORT;
952
953         if (cmd->flags & MMC_RSP_CRC)
954                 flags |= SDHCI_CMD_CRC;
955         if (cmd->flags & MMC_RSP_OPCODE)
956                 flags |= SDHCI_CMD_INDEX;
957         if (cmd->data)
958                 flags |= SDHCI_CMD_DATA;
959
960         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
961 }
962
963 static void sdhci_finish_command(struct sdhci_host *host)
964 {
965         int i;
966
967         BUG_ON(host->cmd == NULL);
968
969         if (host->cmd->flags & MMC_RSP_PRESENT) {
970                 if (host->cmd->flags & MMC_RSP_136) {
971                         /* CRC is stripped so we need to do some shifting. */
972                         for (i = 0;i < 4;i++) {
973                                 host->cmd->resp[i] = sdhci_readl(host,
974                                         SDHCI_RESPONSE + (3-i)*4) << 8;
975                                 if (i != 3)
976                                         host->cmd->resp[i] |=
977                                                 sdhci_readb(host,
978                                                 SDHCI_RESPONSE + (3-i)*4-1);
979                         }
980                 } else {
981                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
982                 }
983         }
984
985         host->cmd->error = 0;
986
987         if (host->data && host->data_early)
988                 sdhci_finish_data(host);
989
990         if (!host->cmd->data)
991                 tasklet_schedule(&host->finish_tasklet);
992
993         host->cmd = NULL;
994 }
995
996 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
997 {
998         int div;
999         u16 clk;
1000         unsigned long timeout;
1001
1002         if (clock == host->clock)
1003                 return;
1004
1005         if (host->ops->set_clock) {
1006                 host->ops->set_clock(host, clock);
1007                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1008                         return;
1009         }
1010
1011         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1012
1013         if (clock == 0)
1014                 goto out;
1015
1016         if (host->version >= SDHCI_SPEC_300) {
1017                 /* Version 3.00 divisors must be a multiple of 2. */
1018                 if (host->max_clk <= clock)
1019                         div = 1;
1020                 else {
1021                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
1022                                 if ((host->max_clk / div) <= clock)
1023                                         break;
1024                         }
1025                 }
1026         } else {
1027                 /* Version 2.00 divisors must be a power of 2. */
1028                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1029                         if ((host->max_clk / div) <= clock)
1030                                 break;
1031                 }
1032         }
1033         div >>= 1;
1034
1035         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1036         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1037                 << SDHCI_DIVIDER_HI_SHIFT;
1038         clk |= SDHCI_CLOCK_INT_EN;
1039         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1040
1041         /* Wait max 20 ms */
1042         timeout = 20;
1043         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1044                 & SDHCI_CLOCK_INT_STABLE)) {
1045                 if (timeout == 0) {
1046                         printk(KERN_ERR "%s: Internal clock never "
1047                                 "stabilised.\n", mmc_hostname(host->mmc));
1048                         sdhci_dumpregs(host);
1049                         return;
1050                 }
1051                 timeout--;
1052                 mdelay(1);
1053         }
1054
1055         clk |= SDHCI_CLOCK_CARD_EN;
1056         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1057
1058 out:
1059         host->clock = clock;
1060 }
1061
1062 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1063 {
1064         u8 pwr = 0;
1065
1066         if (power != (unsigned short)-1) {
1067                 switch (1 << power) {
1068                 case MMC_VDD_165_195:
1069                         pwr = SDHCI_POWER_180;
1070                         break;
1071                 case MMC_VDD_29_30:
1072                 case MMC_VDD_30_31:
1073                         pwr = SDHCI_POWER_300;
1074                         break;
1075                 case MMC_VDD_32_33:
1076                 case MMC_VDD_33_34:
1077                         pwr = SDHCI_POWER_330;
1078                         break;
1079                 default:
1080                         BUG();
1081                 }
1082         }
1083
1084         if (host->pwr == pwr)
1085                 return;
1086
1087         host->pwr = pwr;
1088
1089         if (pwr == 0) {
1090                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1091                 return;
1092         }
1093
1094         /*
1095          * Spec says that we should clear the power reg before setting
1096          * a new value. Some controllers don't seem to like this though.
1097          */
1098         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1099                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1100
1101         /*
1102          * At least the Marvell CaFe chip gets confused if we set the voltage
1103          * and set turn on power at the same time, so set the voltage first.
1104          */
1105         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1106                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1107
1108         pwr |= SDHCI_POWER_ON;
1109
1110         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1111
1112         /*
1113          * Some controllers need an extra 10ms delay of 10ms before they
1114          * can apply clock after applying power
1115          */
1116         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1117                 mdelay(10);
1118 }
1119
1120 /*****************************************************************************\
1121  *                                                                           *
1122  * MMC callbacks                                                             *
1123  *                                                                           *
1124 \*****************************************************************************/
1125
1126 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1127 {
1128         struct sdhci_host *host;
1129         bool present;
1130         unsigned long flags;
1131
1132         host = mmc_priv(mmc);
1133
1134         spin_lock_irqsave(&host->lock, flags);
1135
1136         WARN_ON(host->mrq != NULL);
1137
1138 #ifndef SDHCI_USE_LEDS_CLASS
1139         sdhci_activate_led(host);
1140 #endif
1141         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1142                 if (mrq->stop) {
1143                         mrq->data->stop = NULL;
1144                         mrq->stop = NULL;
1145                 }
1146         }
1147
1148         host->mrq = mrq;
1149
1150         /* If polling, assume that the card is always present. */
1151         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1152                 present = true;
1153         else
1154                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1155                                 SDHCI_CARD_PRESENT;
1156
1157         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1158                 host->mrq->cmd->error = -ENOMEDIUM;
1159                 tasklet_schedule(&host->finish_tasklet);
1160         } else
1161                 sdhci_send_command(host, mrq->cmd);
1162
1163         mmiowb();
1164         spin_unlock_irqrestore(&host->lock, flags);
1165 }
1166
1167 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1168 {
1169         struct sdhci_host *host;
1170         unsigned long flags;
1171         u8 ctrl;
1172
1173         host = mmc_priv(mmc);
1174
1175         spin_lock_irqsave(&host->lock, flags);
1176
1177         if (host->flags & SDHCI_DEVICE_DEAD)
1178                 goto out;
1179
1180         /*
1181          * Reset the chip on each power off.
1182          * Should clear out any weird states.
1183          */
1184         if (ios->power_mode == MMC_POWER_OFF) {
1185                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1186                 sdhci_reinit(host);
1187         }
1188
1189         sdhci_set_clock(host, ios->clock);
1190
1191         if (ios->power_mode == MMC_POWER_OFF)
1192                 sdhci_set_power(host, -1);
1193         else
1194                 sdhci_set_power(host, ios->vdd);
1195
1196         if (host->ops->platform_send_init_74_clocks)
1197                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1198
1199         /*
1200          * If your platform has 8-bit width support but is not a v3 controller,
1201          * or if it requires special setup code, you should implement that in
1202          * platform_8bit_width().
1203          */
1204         if (host->ops->platform_8bit_width)
1205                 host->ops->platform_8bit_width(host, ios->bus_width);
1206         else {
1207                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1208                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1209                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1210                         if (host->version >= SDHCI_SPEC_300)
1211                                 ctrl |= SDHCI_CTRL_8BITBUS;
1212                 } else {
1213                         if (host->version >= SDHCI_SPEC_300)
1214                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1215                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1216                                 ctrl |= SDHCI_CTRL_4BITBUS;
1217                         else
1218                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1219                 }
1220                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1221         }
1222
1223         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1224
1225         if ((ios->timing == MMC_TIMING_SD_HS ||
1226              ios->timing == MMC_TIMING_MMC_HS)
1227             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1228                 ctrl |= SDHCI_CTRL_HISPD;
1229         else
1230                 ctrl &= ~SDHCI_CTRL_HISPD;
1231
1232         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1233
1234         /*
1235          * Some (ENE) controllers go apeshit on some ios operation,
1236          * signalling timeout and CRC errors even on CMD0. Resetting
1237          * it on each ios seems to solve the problem.
1238          */
1239         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1240                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1241
1242 out:
1243         mmiowb();
1244         spin_unlock_irqrestore(&host->lock, flags);
1245 }
1246
1247 static int sdhci_get_ro(struct mmc_host *mmc)
1248 {
1249         struct sdhci_host *host;
1250         unsigned long flags;
1251         int is_readonly;
1252
1253         host = mmc_priv(mmc);
1254
1255         spin_lock_irqsave(&host->lock, flags);
1256
1257         if (host->flags & SDHCI_DEVICE_DEAD)
1258                 is_readonly = 0;
1259         else if (host->ops->get_ro)
1260                 is_readonly = host->ops->get_ro(host);
1261         else
1262                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1263                                 & SDHCI_WRITE_PROTECT);
1264
1265         spin_unlock_irqrestore(&host->lock, flags);
1266
1267         /* This quirk needs to be replaced by a callback-function later */
1268         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1269                 !is_readonly : is_readonly;
1270 }
1271
1272 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1273 {
1274         struct sdhci_host *host;
1275         unsigned long flags;
1276
1277         host = mmc_priv(mmc);
1278
1279         spin_lock_irqsave(&host->lock, flags);
1280
1281         if (host->flags & SDHCI_DEVICE_DEAD)
1282                 goto out;
1283
1284         if (enable)
1285                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1286         else
1287                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1288 out:
1289         mmiowb();
1290
1291         spin_unlock_irqrestore(&host->lock, flags);
1292 }
1293
1294 static const struct mmc_host_ops sdhci_ops = {
1295         .request        = sdhci_request,
1296         .set_ios        = sdhci_set_ios,
1297         .get_ro         = sdhci_get_ro,
1298         .enable_sdio_irq = sdhci_enable_sdio_irq,
1299 };
1300
1301 /*****************************************************************************\
1302  *                                                                           *
1303  * Tasklets                                                                  *
1304  *                                                                           *
1305 \*****************************************************************************/
1306
1307 static void sdhci_tasklet_card(unsigned long param)
1308 {
1309         struct sdhci_host *host;
1310         unsigned long flags;
1311
1312         host = (struct sdhci_host*)param;
1313
1314         spin_lock_irqsave(&host->lock, flags);
1315
1316         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1317                 if (host->mrq) {
1318                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1319                                 mmc_hostname(host->mmc));
1320                         printk(KERN_ERR "%s: Resetting controller.\n",
1321                                 mmc_hostname(host->mmc));
1322
1323                         sdhci_reset(host, SDHCI_RESET_CMD);
1324                         sdhci_reset(host, SDHCI_RESET_DATA);
1325
1326                         host->mrq->cmd->error = -ENOMEDIUM;
1327                         tasklet_schedule(&host->finish_tasklet);
1328                 }
1329         }
1330
1331         spin_unlock_irqrestore(&host->lock, flags);
1332
1333         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1334 }
1335
1336 static void sdhci_tasklet_finish(unsigned long param)
1337 {
1338         struct sdhci_host *host;
1339         unsigned long flags;
1340         struct mmc_request *mrq;
1341
1342         host = (struct sdhci_host*)param;
1343
1344         /*
1345          * If this tasklet gets rescheduled while running, it will
1346          * be run again afterwards but without any active request.
1347          */
1348         if (!host->mrq)
1349                 return;
1350
1351         spin_lock_irqsave(&host->lock, flags);
1352
1353         del_timer(&host->timer);
1354
1355         mrq = host->mrq;
1356
1357         /*
1358          * The controller needs a reset of internal state machines
1359          * upon error conditions.
1360          */
1361         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1362             ((mrq->cmd && mrq->cmd->error) ||
1363                  (mrq->data && (mrq->data->error ||
1364                   (mrq->data->stop && mrq->data->stop->error))) ||
1365                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1366
1367                 /* Some controllers need this kick or reset won't work here */
1368                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1369                         unsigned int clock;
1370
1371                         /* This is to force an update */
1372                         clock = host->clock;
1373                         host->clock = 0;
1374                         sdhci_set_clock(host, clock);
1375                 }
1376
1377                 /* Spec says we should do both at the same time, but Ricoh
1378                    controllers do not like that. */
1379                 sdhci_reset(host, SDHCI_RESET_CMD);
1380                 sdhci_reset(host, SDHCI_RESET_DATA);
1381         }
1382
1383         host->mrq = NULL;
1384         host->cmd = NULL;
1385         host->data = NULL;
1386
1387 #ifndef SDHCI_USE_LEDS_CLASS
1388         sdhci_deactivate_led(host);
1389 #endif
1390
1391         mmiowb();
1392         spin_unlock_irqrestore(&host->lock, flags);
1393
1394         mmc_request_done(host->mmc, mrq);
1395 }
1396
1397 static void sdhci_timeout_timer(unsigned long data)
1398 {
1399         struct sdhci_host *host;
1400         unsigned long flags;
1401
1402         host = (struct sdhci_host*)data;
1403
1404         spin_lock_irqsave(&host->lock, flags);
1405
1406         if (host->mrq) {
1407                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1408                         "interrupt.\n", mmc_hostname(host->mmc));
1409                 sdhci_dumpregs(host);
1410
1411                 if (host->data) {
1412                         host->data->error = -ETIMEDOUT;
1413                         sdhci_finish_data(host);
1414                 } else {
1415                         if (host->cmd)
1416                                 host->cmd->error = -ETIMEDOUT;
1417                         else
1418                                 host->mrq->cmd->error = -ETIMEDOUT;
1419
1420                         tasklet_schedule(&host->finish_tasklet);
1421                 }
1422         }
1423
1424         mmiowb();
1425         spin_unlock_irqrestore(&host->lock, flags);
1426 }
1427
1428 /*****************************************************************************\
1429  *                                                                           *
1430  * Interrupt handling                                                        *
1431  *                                                                           *
1432 \*****************************************************************************/
1433
1434 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1435 {
1436         BUG_ON(intmask == 0);
1437
1438         if (!host->cmd) {
1439                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1440                         "though no command operation was in progress.\n",
1441                         mmc_hostname(host->mmc), (unsigned)intmask);
1442                 sdhci_dumpregs(host);
1443                 return;
1444         }
1445
1446         if (intmask & SDHCI_INT_TIMEOUT)
1447                 host->cmd->error = -ETIMEDOUT;
1448         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1449                         SDHCI_INT_INDEX))
1450                 host->cmd->error = -EILSEQ;
1451
1452         if (host->cmd->error) {
1453                 tasklet_schedule(&host->finish_tasklet);
1454                 return;
1455         }
1456
1457         /*
1458          * The host can send and interrupt when the busy state has
1459          * ended, allowing us to wait without wasting CPU cycles.
1460          * Unfortunately this is overloaded on the "data complete"
1461          * interrupt, so we need to take some care when handling
1462          * it.
1463          *
1464          * Note: The 1.0 specification is a bit ambiguous about this
1465          *       feature so there might be some problems with older
1466          *       controllers.
1467          */
1468         if (host->cmd->flags & MMC_RSP_BUSY) {
1469                 if (host->cmd->data)
1470                         DBG("Cannot wait for busy signal when also "
1471                                 "doing a data transfer");
1472                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1473                         return;
1474
1475                 /* The controller does not support the end-of-busy IRQ,
1476                  * fall through and take the SDHCI_INT_RESPONSE */
1477         }
1478
1479         if (intmask & SDHCI_INT_RESPONSE)
1480                 sdhci_finish_command(host);
1481 }
1482
1483 #ifdef CONFIG_MMC_DEBUG
1484 static void sdhci_show_adma_error(struct sdhci_host *host)
1485 {
1486         const char *name = mmc_hostname(host->mmc);
1487         u8 *desc = host->adma_desc;
1488         __le32 *dma;
1489         __le16 *len;
1490         u8 attr;
1491
1492         sdhci_dumpregs(host);
1493
1494         while (true) {
1495                 dma = (__le32 *)(desc + 4);
1496                 len = (__le16 *)(desc + 2);
1497                 attr = *desc;
1498
1499                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1500                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1501
1502                 desc += 8;
1503
1504                 if (attr & 2)
1505                         break;
1506         }
1507 }
1508 #else
1509 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1510 #endif
1511
1512 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1513 {
1514         BUG_ON(intmask == 0);
1515
1516         if (!host->data) {
1517                 /*
1518                  * The "data complete" interrupt is also used to
1519                  * indicate that a busy state has ended. See comment
1520                  * above in sdhci_cmd_irq().
1521                  */
1522                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1523                         if (intmask & SDHCI_INT_DATA_END) {
1524                                 sdhci_finish_command(host);
1525                                 return;
1526                         }
1527                 }
1528
1529                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1530                         "though no data operation was in progress.\n",
1531                         mmc_hostname(host->mmc), (unsigned)intmask);
1532                 sdhci_dumpregs(host);
1533
1534                 return;
1535         }
1536
1537         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1538                 host->data->error = -ETIMEDOUT;
1539         else if (intmask & SDHCI_INT_DATA_END_BIT)
1540                 host->data->error = -EILSEQ;
1541         else if ((intmask & SDHCI_INT_DATA_CRC) &&
1542                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
1543                         != MMC_BUS_TEST_R)
1544                 host->data->error = -EILSEQ;
1545         else if (intmask & SDHCI_INT_ADMA_ERROR) {
1546                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1547                 sdhci_show_adma_error(host);
1548                 host->data->error = -EIO;
1549         }
1550
1551         if (host->data->error)
1552                 sdhci_finish_data(host);
1553         else {
1554                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1555                         sdhci_transfer_pio(host);
1556
1557                 /*
1558                  * We currently don't do anything fancy with DMA
1559                  * boundaries, but as we can't disable the feature
1560                  * we need to at least restart the transfer.
1561                  */
1562                 if (intmask & SDHCI_INT_DMA_END)
1563                         sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1564                                 SDHCI_DMA_ADDRESS);
1565
1566                 if (intmask & SDHCI_INT_DATA_END) {
1567                         if (host->cmd) {
1568                                 /*
1569                                  * Data managed to finish before the
1570                                  * command completed. Make sure we do
1571                                  * things in the proper order.
1572                                  */
1573                                 host->data_early = 1;
1574                         } else {
1575                                 sdhci_finish_data(host);
1576                         }
1577                 }
1578         }
1579 }
1580
1581 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1582 {
1583         irqreturn_t result;
1584         struct sdhci_host* host = dev_id;
1585         u32 intmask;
1586         int cardint = 0;
1587
1588         spin_lock(&host->lock);
1589
1590         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1591
1592         if (!intmask || intmask == 0xffffffff) {
1593                 result = IRQ_NONE;
1594                 goto out;
1595         }
1596
1597         DBG("*** %s got interrupt: 0x%08x\n",
1598                 mmc_hostname(host->mmc), intmask);
1599
1600         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1601                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1602                         SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1603                 tasklet_schedule(&host->card_tasklet);
1604         }
1605
1606         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1607
1608         if (intmask & SDHCI_INT_CMD_MASK) {
1609                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1610                         SDHCI_INT_STATUS);
1611                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1612         }
1613
1614         if (intmask & SDHCI_INT_DATA_MASK) {
1615                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1616                         SDHCI_INT_STATUS);
1617                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1618         }
1619
1620         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1621
1622         intmask &= ~SDHCI_INT_ERROR;
1623
1624         if (intmask & SDHCI_INT_BUS_POWER) {
1625                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1626                         mmc_hostname(host->mmc));
1627                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1628         }
1629
1630         intmask &= ~SDHCI_INT_BUS_POWER;
1631
1632         if (intmask & SDHCI_INT_CARD_INT)
1633                 cardint = 1;
1634
1635         intmask &= ~SDHCI_INT_CARD_INT;
1636
1637         if (intmask) {
1638                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1639                         mmc_hostname(host->mmc), intmask);
1640                 sdhci_dumpregs(host);
1641
1642                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1643         }
1644
1645         result = IRQ_HANDLED;
1646
1647         mmiowb();
1648 out:
1649         spin_unlock(&host->lock);
1650
1651         /*
1652          * We have to delay this as it calls back into the driver.
1653          */
1654         if (cardint)
1655                 mmc_signal_sdio_irq(host->mmc);
1656
1657         return result;
1658 }
1659
1660 /*****************************************************************************\
1661  *                                                                           *
1662  * Suspend/resume                                                            *
1663  *                                                                           *
1664 \*****************************************************************************/
1665
1666 #ifdef CONFIG_PM
1667
1668 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1669 {
1670         int ret;
1671
1672         sdhci_disable_card_detection(host);
1673
1674         ret = mmc_suspend_host(host->mmc);
1675         if (ret)
1676                 return ret;
1677
1678         free_irq(host->irq, host);
1679
1680         if (host->vmmc)
1681                 ret = regulator_disable(host->vmmc);
1682
1683         return ret;
1684 }
1685
1686 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1687
1688 int sdhci_resume_host(struct sdhci_host *host)
1689 {
1690         int ret;
1691
1692         if (host->vmmc) {
1693                 int ret = regulator_enable(host->vmmc);
1694                 if (ret)
1695                         return ret;
1696         }
1697
1698
1699         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1700                 if (host->ops->enable_dma)
1701                         host->ops->enable_dma(host);
1702         }
1703
1704         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1705                           mmc_hostname(host->mmc), host);
1706         if (ret)
1707                 return ret;
1708
1709         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1710         mmiowb();
1711
1712         ret = mmc_resume_host(host->mmc);
1713         sdhci_enable_card_detection(host);
1714
1715         return ret;
1716 }
1717
1718 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1719
1720 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
1721 {
1722         u8 val;
1723         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
1724         val |= SDHCI_WAKE_ON_INT;
1725         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
1726 }
1727
1728 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
1729
1730 #endif /* CONFIG_PM */
1731
1732 /*****************************************************************************\
1733  *                                                                           *
1734  * Device allocation/registration                                            *
1735  *                                                                           *
1736 \*****************************************************************************/
1737
1738 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1739         size_t priv_size)
1740 {
1741         struct mmc_host *mmc;
1742         struct sdhci_host *host;
1743
1744         WARN_ON(dev == NULL);
1745
1746         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1747         if (!mmc)
1748                 return ERR_PTR(-ENOMEM);
1749
1750         host = mmc_priv(mmc);
1751         host->mmc = mmc;
1752
1753         return host;
1754 }
1755
1756 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1757
1758 int sdhci_add_host(struct sdhci_host *host)
1759 {
1760         struct mmc_host *mmc;
1761         unsigned int caps, ocr_avail;
1762         int ret;
1763
1764         WARN_ON(host == NULL);
1765         if (host == NULL)
1766                 return -EINVAL;
1767
1768         mmc = host->mmc;
1769
1770         if (debug_quirks)
1771                 host->quirks = debug_quirks;
1772
1773         sdhci_reset(host, SDHCI_RESET_ALL);
1774
1775         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1776         host->version = (host->version & SDHCI_SPEC_VER_MASK)
1777                                 >> SDHCI_SPEC_VER_SHIFT;
1778         if (host->version > SDHCI_SPEC_300) {
1779                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1780                         "You may experience problems.\n", mmc_hostname(mmc),
1781                         host->version);
1782         }
1783
1784         caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1785                 sdhci_readl(host, SDHCI_CAPABILITIES);
1786
1787         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1788                 host->flags |= SDHCI_USE_SDMA;
1789         else if (!(caps & SDHCI_CAN_DO_SDMA))
1790                 DBG("Controller doesn't have SDMA capability\n");
1791         else
1792                 host->flags |= SDHCI_USE_SDMA;
1793
1794         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1795                 (host->flags & SDHCI_USE_SDMA)) {
1796                 DBG("Disabling DMA as it is marked broken\n");
1797                 host->flags &= ~SDHCI_USE_SDMA;
1798         }
1799
1800         if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1801                 host->flags |= SDHCI_USE_ADMA;
1802
1803         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1804                 (host->flags & SDHCI_USE_ADMA)) {
1805                 DBG("Disabling ADMA as it is marked broken\n");
1806                 host->flags &= ~SDHCI_USE_ADMA;
1807         }
1808
1809         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1810                 if (host->ops->enable_dma) {
1811                         if (host->ops->enable_dma(host)) {
1812                                 printk(KERN_WARNING "%s: No suitable DMA "
1813                                         "available. Falling back to PIO.\n",
1814                                         mmc_hostname(mmc));
1815                                 host->flags &=
1816                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1817                         }
1818                 }
1819         }
1820
1821         if (host->flags & SDHCI_USE_ADMA) {
1822                 /*
1823                  * We need to allocate descriptors for all sg entries
1824                  * (128) and potentially one alignment transfer for
1825                  * each of those entries.
1826                  */
1827                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1828                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1829                 if (!host->adma_desc || !host->align_buffer) {
1830                         kfree(host->adma_desc);
1831                         kfree(host->align_buffer);
1832                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
1833                                 "buffers. Falling back to standard DMA.\n",
1834                                 mmc_hostname(mmc));
1835                         host->flags &= ~SDHCI_USE_ADMA;
1836                 }
1837         }
1838
1839         /*
1840          * If we use DMA, then it's up to the caller to set the DMA
1841          * mask, but PIO does not need the hw shim so we set a new
1842          * mask here in that case.
1843          */
1844         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1845                 host->dma_mask = DMA_BIT_MASK(64);
1846                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1847         }
1848
1849         if (host->version >= SDHCI_SPEC_300)
1850                 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
1851                         >> SDHCI_CLOCK_BASE_SHIFT;
1852         else
1853                 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
1854                         >> SDHCI_CLOCK_BASE_SHIFT;
1855
1856         host->max_clk *= 1000000;
1857         if (host->max_clk == 0 || host->quirks &
1858                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
1859                 if (!host->ops->get_max_clock) {
1860                         printk(KERN_ERR
1861                                "%s: Hardware doesn't specify base clock "
1862                                "frequency.\n", mmc_hostname(mmc));
1863                         return -ENODEV;
1864                 }
1865                 host->max_clk = host->ops->get_max_clock(host);
1866         }
1867
1868         host->timeout_clk =
1869                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1870         if (host->timeout_clk == 0) {
1871                 if (host->ops->get_timeout_clock) {
1872                         host->timeout_clk = host->ops->get_timeout_clock(host);
1873                 } else if (!(host->quirks &
1874                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1875                         printk(KERN_ERR
1876                                "%s: Hardware doesn't specify timeout clock "
1877                                "frequency.\n", mmc_hostname(mmc));
1878                         return -ENODEV;
1879                 }
1880         }
1881         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1882                 host->timeout_clk *= 1000;
1883
1884         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
1885                 host->timeout_clk = host->clock / 1000;
1886
1887         /*
1888          * Set host parameters.
1889          */
1890         mmc->ops = &sdhci_ops;
1891         if (host->ops->get_min_clock)
1892                 mmc->f_min = host->ops->get_min_clock(host);
1893         else if (host->version >= SDHCI_SPEC_300)
1894                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
1895         else
1896                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
1897
1898         mmc->f_max = host->max_clk;
1899         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE;
1900
1901         /*
1902          * A controller may support 8-bit width, but the board itself
1903          * might not have the pins brought out.  Boards that support
1904          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
1905          * their platform code before calling sdhci_add_host(), and we
1906          * won't assume 8-bit width for hosts without that CAP.
1907          */
1908         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1909                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1910
1911         if (caps & SDHCI_CAN_DO_HISPD)
1912                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1913
1914         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
1915             mmc_card_is_removable(mmc))
1916                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1917
1918         ocr_avail = 0;
1919         if (caps & SDHCI_CAN_VDD_330)
1920                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
1921         if (caps & SDHCI_CAN_VDD_300)
1922                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
1923         if (caps & SDHCI_CAN_VDD_180)
1924                 ocr_avail |= MMC_VDD_165_195;
1925
1926         mmc->ocr_avail = ocr_avail;
1927         mmc->ocr_avail_sdio = ocr_avail;
1928         if (host->ocr_avail_sdio)
1929                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
1930         mmc->ocr_avail_sd = ocr_avail;
1931         if (host->ocr_avail_sd)
1932                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
1933         else /* normal SD controllers don't support 1.8V */
1934                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
1935         mmc->ocr_avail_mmc = ocr_avail;
1936         if (host->ocr_avail_mmc)
1937                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
1938
1939         if (mmc->ocr_avail == 0) {
1940                 printk(KERN_ERR "%s: Hardware doesn't report any "
1941                         "support voltages.\n", mmc_hostname(mmc));
1942                 return -ENODEV;
1943         }
1944
1945         spin_lock_init(&host->lock);
1946
1947         /*
1948          * Maximum number of segments. Depends on if the hardware
1949          * can do scatter/gather or not.
1950          */
1951         if (host->flags & SDHCI_USE_ADMA)
1952                 mmc->max_segs = 128;
1953         else if (host->flags & SDHCI_USE_SDMA)
1954                 mmc->max_segs = 1;
1955         else /* PIO */
1956                 mmc->max_segs = 128;
1957
1958         /*
1959          * Maximum number of sectors in one transfer. Limited by DMA boundary
1960          * size (512KiB).
1961          */
1962         mmc->max_req_size = 524288;
1963
1964         /*
1965          * Maximum segment size. Could be one segment with the maximum number
1966          * of bytes. When doing hardware scatter/gather, each entry cannot
1967          * be larger than 64 KiB though.
1968          */
1969         if (host->flags & SDHCI_USE_ADMA) {
1970                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
1971                         mmc->max_seg_size = 65535;
1972                 else
1973                         mmc->max_seg_size = 65536;
1974         } else {
1975                 mmc->max_seg_size = mmc->max_req_size;
1976         }
1977
1978         /*
1979          * Maximum block size. This varies from controller to controller and
1980          * is specified in the capabilities register.
1981          */
1982         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1983                 mmc->max_blk_size = 2;
1984         } else {
1985                 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1986                                 SDHCI_MAX_BLOCK_SHIFT;
1987                 if (mmc->max_blk_size >= 3) {
1988                         printk(KERN_WARNING "%s: Invalid maximum block size, "
1989                                 "assuming 512 bytes\n", mmc_hostname(mmc));
1990                         mmc->max_blk_size = 0;
1991                 }
1992         }
1993
1994         mmc->max_blk_size = 512 << mmc->max_blk_size;
1995
1996         /*
1997          * Maximum block count.
1998          */
1999         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2000
2001         /*
2002          * Init tasklets.
2003          */
2004         tasklet_init(&host->card_tasklet,
2005                 sdhci_tasklet_card, (unsigned long)host);
2006         tasklet_init(&host->finish_tasklet,
2007                 sdhci_tasklet_finish, (unsigned long)host);
2008
2009         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2010
2011         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2012                 mmc_hostname(mmc), host);
2013         if (ret)
2014                 goto untasklet;
2015
2016         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2017         if (IS_ERR(host->vmmc)) {
2018                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2019                 host->vmmc = NULL;
2020         } else {
2021                 regulator_enable(host->vmmc);
2022         }
2023
2024         sdhci_init(host, 0);
2025
2026 #ifdef CONFIG_MMC_DEBUG
2027         sdhci_dumpregs(host);
2028 #endif
2029
2030 #ifdef SDHCI_USE_LEDS_CLASS
2031         snprintf(host->led_name, sizeof(host->led_name),
2032                 "%s::", mmc_hostname(mmc));
2033         host->led.name = host->led_name;
2034         host->led.brightness = LED_OFF;
2035         host->led.default_trigger = mmc_hostname(mmc);
2036         host->led.brightness_set = sdhci_led_control;
2037
2038         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2039         if (ret)
2040                 goto reset;
2041 #endif
2042
2043         mmiowb();
2044
2045         mmc_add_host(mmc);
2046
2047         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2048                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2049                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2050                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2051
2052         sdhci_enable_card_detection(host);
2053
2054         return 0;
2055
2056 #ifdef SDHCI_USE_LEDS_CLASS
2057 reset:
2058         sdhci_reset(host, SDHCI_RESET_ALL);
2059         free_irq(host->irq, host);
2060 #endif
2061 untasklet:
2062         tasklet_kill(&host->card_tasklet);
2063         tasklet_kill(&host->finish_tasklet);
2064
2065         return ret;
2066 }
2067
2068 EXPORT_SYMBOL_GPL(sdhci_add_host);
2069
2070 void sdhci_remove_host(struct sdhci_host *host, int dead)
2071 {
2072         unsigned long flags;
2073
2074         if (dead) {
2075                 spin_lock_irqsave(&host->lock, flags);
2076
2077                 host->flags |= SDHCI_DEVICE_DEAD;
2078
2079                 if (host->mrq) {
2080                         printk(KERN_ERR "%s: Controller removed during "
2081                                 " transfer!\n", mmc_hostname(host->mmc));
2082
2083                         host->mrq->cmd->error = -ENOMEDIUM;
2084                         tasklet_schedule(&host->finish_tasklet);
2085                 }
2086
2087                 spin_unlock_irqrestore(&host->lock, flags);
2088         }
2089
2090         sdhci_disable_card_detection(host);
2091
2092         mmc_remove_host(host->mmc);
2093
2094 #ifdef SDHCI_USE_LEDS_CLASS
2095         led_classdev_unregister(&host->led);
2096 #endif
2097
2098         if (!dead)
2099                 sdhci_reset(host, SDHCI_RESET_ALL);
2100
2101         free_irq(host->irq, host);
2102
2103         del_timer_sync(&host->timer);
2104
2105         tasklet_kill(&host->card_tasklet);
2106         tasklet_kill(&host->finish_tasklet);
2107
2108         if (host->vmmc) {
2109                 regulator_disable(host->vmmc);
2110                 regulator_put(host->vmmc);
2111         }
2112
2113         kfree(host->adma_desc);
2114         kfree(host->align_buffer);
2115
2116         host->adma_desc = NULL;
2117         host->align_buffer = NULL;
2118 }
2119
2120 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2121
2122 void sdhci_free_host(struct sdhci_host *host)
2123 {
2124         mmc_free_host(host->mmc);
2125 }
2126
2127 EXPORT_SYMBOL_GPL(sdhci_free_host);
2128
2129 /*****************************************************************************\
2130  *                                                                           *
2131  * Driver init/exit                                                          *
2132  *                                                                           *
2133 \*****************************************************************************/
2134
2135 static int __init sdhci_drv_init(void)
2136 {
2137         printk(KERN_INFO DRIVER_NAME
2138                 ": Secure Digital Host Controller Interface driver\n");
2139         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2140
2141         return 0;
2142 }
2143
2144 static void __exit sdhci_drv_exit(void)
2145 {
2146 }
2147
2148 module_init(sdhci_drv_init);
2149 module_exit(sdhci_drv_exit);
2150
2151 module_param(debug_quirks, uint, 0444);
2152
2153 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2154 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2155 MODULE_LICENSE("GPL");
2156
2157 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");